diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/.cyignore b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/.cyignore new file mode 100644 index 0000000000..468d1f565e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/.cyignore @@ -0,0 +1,3 @@ +docs +personalities +udd diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/EULA.txt b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/EULA.txt new file mode 100644 index 0000000000..91c81ad20b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/EULA.txt @@ -0,0 +1,210 @@ +CYPRESS END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE +DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING +DOCUMENTATION. BY DOWNLOADING, INSTALLING, COPYING OR USING THE SOFTWARE, +YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT. 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Any notice to Cypress +will be deemed effective when actually received and must be sent to Cypress +Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San +Jose, CA 95134 USA. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_common_tables.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_common_tables.h new file mode 100644 index 0000000000..721b18dd2d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_common_tables.h @@ -0,0 +1,517 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_const_structs.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_const_structs.h new file mode 100644 index 0000000000..83984c40cd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_const_structs.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_helium_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_helium_utils.h new file mode 100644 index 0000000000..7609d329f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_helium_utils.h @@ -0,0 +1,348 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * $Date: 09. September 2019 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) + + +#include "arm_common_tables.h" + +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_math.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_math.h new file mode 100644 index 0000000000..48bee62cd9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_math.h @@ -0,0 +1,8970 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * + * Here is the list of pre-built libraries : + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M7, A5 are tested. + * + * + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * There is also a work in progress cmake build. The README file is giving more details. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_FLOAT16: + * + * Float16 implementations of some algorithms (Requires MVE extension). + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) + +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static __attribute__((inline)) +#define __STATIC_INLINE static __attribute__((inline)) +#pragma GCC diagnostic ignored "-Wunused-function" +#pragma GCC diagnostic ignored "-Wattributes" + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MAX ((float16_t)FLT_MAX) +#endif + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MIN (-(float16_t)FLT_MAX) +#endif + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMAX ((float16_t)FLT_MAX) +#endif + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMIN ((float16_t)0.0) +#endif + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) +#include +#endif + +#if defined (ARM_MATH_HELIUM) + #define ARM_MATH_MVEF + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_MVEF) + #define ARM_MATH_MVEI + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) +#include +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macros for complex numbers + */ + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; +#endif + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; +#endif + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; +#endif + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +#define STEP(x) (x) <= 0 ? 0 : 1 +#define SQ(x) ((x) * (x)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (val & 0x0FFFF); + (*pQ15)[1] = (val >> 16) & 0x0FFFF; +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = val & 0x0FFFF; + pQ15[1] = val >> 16; +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = val & 0x0FF; + (*pQ7)[1] = (val >> 8) & 0x0FF; + (*pQ7)[2] = (val >> 16) & 0x0FF; + (*pQ7)[3] = (val >> 24) & 0x0FF; + +#endif + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independant constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[in] pBuffer points to a buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pBuffer); + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_mve_tables.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_mve_tables.h new file mode 100644 index 0000000000..4d2c135ac6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_mve_tables.h @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 08. January 2020 + * $Revision: V1.7.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + + #include "arm_math.h" + + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_vec_math.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_vec_math.h new file mode 100644 index 0000000000..0ce9464bcb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/arm_vec_math.h @@ -0,0 +1,372 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 15. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cachel1_armv7.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cachel1_armv7.h new file mode 100644 index 0000000000..d2c3e2291f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armcc.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armcc.h new file mode 100644 index 0000000000..237ff6ec3e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armclang.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armclang.h new file mode 100644 index 0000000000..90de9dbf8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armclang.h @@ -0,0 +1,1467 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armclang_ltm.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..0e5c7349d3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_compiler.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_gcc.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_gcc.h new file mode 100644 index 0000000000..a2778f58e8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_iccarm.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_iccarm.h new file mode 100644 index 0000000000..7eeffca5c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_version.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_version.h new file mode 100644 index 0000000000..2f048e4552 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv81mml.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv81mml.h new file mode 100644 index 0000000000..1ad19e215a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv81mml.h @@ -0,0 +1,4191 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.3.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv8mbl.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv8mbl.h new file mode 100644 index 0000000000..932d3d188b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv8mml.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv8mml.h new file mode 100644 index 0000000000..71f000bcad --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_armv8mml.h @@ -0,0 +1,3196 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm0.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm0.h new file mode 100644 index 0000000000..6441ff3419 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm0plus.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm0plus.h new file mode 100644 index 0000000000..4e7179a614 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm1.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm23.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm23.h new file mode 100644 index 0000000000..55fff99509 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm3.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm3.h new file mode 100644 index 0000000000..24453a8863 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm33.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm33.h new file mode 100644 index 0000000000..13359be3ed --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm33.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm35p.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm35p.h new file mode 100644 index 0000000000..6a5f6ad147 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm35p.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm4.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm4.h new file mode 100644 index 0000000000..4e0e886697 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm55.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm55.h new file mode 100644 index 0000000000..6efaa3f842 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm55.h @@ -0,0 +1,4215 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm7.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm7.h new file mode 100644 index 0000000000..e1c31c275d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_cm7.h @@ -0,0 +1,2362 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_sc000.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_sc000.h new file mode 100644 index 0000000000..dbc755fff3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_sc300.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_sc300.h new file mode 100644 index 0000000000..e8914ba601 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/mpu_armv7.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/mpu_armv7.h new file mode 100644 index 0000000000..791a8dae65 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/mpu_armv8.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/mpu_armv8.h new file mode 100644 index 0000000000..ef44ad01df --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/pmu_armv8.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/pmu_armv8.h new file mode 100644 index 0000000000..dbd39d20c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.0 + * @date 24. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/tz_context.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/cmsis/include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_01.svd b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_01.svd new file mode 100644 index 0000000000..ee04d21458 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_01.svd @@ -0,0 +1,44555 @@ + + + + Cypress Semiconductor + Cypress + psoc6_01 + PSoC6_01 + 1.0 + PSoC6_01 + Copyright 2016-2021 Cypress Semiconductor Corporation\n + SPDX-License-Identifier: Apache-2.0\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + CM4 + r0p1 + little + true + true + 1 + 3 + 0 + + 8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERI + Peripheral interconnect + 0x40010000 + + 0 + 65536 + registers + + + + 11 + 64 + GR[%s] + Peripheral group structure + 0x00000000 + + CLOCK_CTL + Clock control + 0x0 + 32 + read-write + 0x0 + 0xFF00 + + + INT8_DIV + Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + SL_CTL + Slave control + 0x20 + 32 + read-write + 0xFFFF + 0xFFFF + + + ENABLED_0 + Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. + [0:0] + read-only + + + ENABLED_1 + Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [1:1] + read-write + + + ENABLED_2 + Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [2:2] + read-write + + + ENABLED_3 + N/A + [3:3] + read-write + + + ENABLED_4 + N/A + [4:4] + read-write + + + ENABLED_5 + N/A + [5:5] + read-write + + + ENABLED_6 + N/A + [6:6] + read-write + + + ENABLED_7 + N/A + [7:7] + read-write + + + ENABLED_8 + N/A + [8:8] + read-write + + + ENABLED_9 + N/A + [9:9] + read-write + + + ENABLED_10 + N/A + [10:10] + read-write + + + ENABLED_11 + N/A + [11:11] + read-write + + + ENABLED_12 + N/A + [12:12] + read-write + + + ENABLED_13 + N/A + [13:13] + read-write + + + ENABLED_14 + N/A + [14:14] + read-write + + + ENABLED_15 + N/A + [15:15] + read-write + + + + + TIMEOUT_CTL + Timeout control + 0x24 + 32 + read-write + 0xFFFF + 0xFFFF + + + TIMEOUT + This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). +'0x0000'-'0xfffe': Number of peripheral group clock cycles. +'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. + [15:0] + read-write + + + + + + DIV_CMD + Divider command register + 0x400 + 32 + read-write + 0xFFFF + 0xC000FFFF + + + DIV_SEL + (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. + +If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. + [5:0] + read-write + + + TYPE_SEL + Specifies the divider type of the divider on which the command is performed: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [7:6] + read-write + + + PA_DIV_SEL + (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. + +If PA_DIV_SEL is '63' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. + [13:8] + read-write + + + PA_TYPE_SEL + Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [15:14] + read-write + + + DISABLE + Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. + +The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. + [30:30] + read-write + + + ENABLE + Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the DIV_CMD.DISABLE field. +1: Configure the divider's DIV_XXX_CTL register. +2: Enable the divider using the DIV_CMD_ENABLE field. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. + +The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. + +The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. + [31:31] + read-write + + + + + 64 + 4 + DIV_8_CTL[%s] + Divider control register (for 8.0 divider) + 0x800 + 32 + read-write + 0x0 + 0xFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT8_DIV + Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 256]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + 64 + 4 + DIV_16_CTL[%s] + Divider control register (for 16.0 divider) + 0x900 + 32 + read-write + 0x0 + 0xFFFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 64 + 4 + DIV_16_5_CTL[%s] + Divider control register (for 16.5 divider) + 0xA00 + 32 + read-write + 0x0 + 0xFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. + +For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 63 + 4 + DIV_24_5_CTL[%s] + Divider control register (for 24.5 divider) + 0xB00 + 32 + read-write + 0x0 + 0xFFFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT24_DIV + Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. + +For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [31:8] + read-write + + + + + 128 + 4 + CLOCK_CTL[%s] + Clock control register + 0xC00 + 32 + read-write + 0xFF + 0xFF + + + DIV_SEL + Specifies one of the dividers of the divider type specified by TYPE_SEL. + +If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. + +When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. + [5:0] + read-write + + + TYPE_SEL + Specifies divider type: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [7:6] + read-write + + + + + TR_CMD + Trigger command register + 0x1000 + 32 + read-write + 0x0 + 0xC0FF0FFF + + + TR_SEL + Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect. + [7:0] + read-write + + + GROUP_SEL + Specifies the trigger group. + [11:8] + read-write + + + COUNT + Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVATE is '1'), HW decrements this field to '0' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to '0' and trigger activation is under direct control of ACTIVATE when ACTIVATE is '1' the trigger is activated and when ACTIVATE is '0' the trigger is deactivated. + [23:16] + read-write + + + OUT_SEL + Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. +'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. +'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. + [30:30] + read-write + + + ACTIVATE + SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented). + [31:31] + read-write + + + + + 15 + 512 + TR_GR[%s] + Trigger group + 0x00002000 + + 128 + 4 + TR_OUT_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x3FF + + + TR_SEL + Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. + [7:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + + + + 16 + 64 + PPU_PR[%s] + PPU structure with programmable address + 0x00004000 + + ADDR0 + PPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + PPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x124 + 0x80000124 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + PPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + See corresponding field for PPU structure with programmable address. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + See corresponding field for PPU structure with programmable address. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + PPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + See corresponding field for PPU structure with programmable address. + [1:1] + read-write + + + UX + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + See corresponding field for PPU structure with programmable address. + [4:4] + read-write + + + PX + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + See corresponding field for PPU structure with programmable address. + [6:6] + read-write + + + PC_MASK_0 + See corresponding field for PPU structure with programmable address. + [8:8] + read-only + + + PC_MASK_15_TO_1 + See corresponding field for PPU structure with programmable address. + [23:9] + read-write + + + REGION_SIZE + See corresponding field for PPU structure with programmable address. + +'7': 256 B region + [28:24] + read-only + + + PC_MATCH + See corresponding field for PPU structure with programmable address. + [30:30] + read-write + + + ENABLED + See corresponding field for PPU structure with programmable address. + [31:31] + read-write + + + + + + 11 + 64 + PPU_GR[%s] + PPU structure with fixed/constant address for a peripheral group + 0x00005000 + + ADDR0 + PPU region address 0 (slave structure) + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + See corresponding field for PPU structure with programmable address. + +Note: this field is read-only. Its value is chip specific. + [7:0] + read-only + + + ADDR24 + See corresponding field for PPU structure with programmable address. + +'ADDR_DEF1': address of protected region. + +Note: this field is read-only. Its value is chip specific. + [31:8] + read-only + + + + + ATT0 + PPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x124 + 0x9F000124 + + + UR + See corresponding field for PPU structure with programmable address. + [0:0] + read-write + + + UW + See corresponding field for PPU structure with programmable address. + [1:1] + read-write + + + UX + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. + [2:2] + read-only + + + PR + See corresponding field for PPU structure with programmable address. + [3:3] + read-write + + + PW + See corresponding field for PPU structure with programmable address. + [4:4] + read-write + + + PX + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. + [5:5] + read-only + + + NS + See corresponding field for PPU structure with programmable address. + [6:6] + read-write + + + PC_MASK_0 + See corresponding field for PPU structure with programmable address. + [8:8] + read-only + + + PC_MASK_15_TO_1 + See corresponding field for PPU structure with programmable address. + [23:9] + read-write + + + REGION_SIZE + See corresponding field for PPU structure with programmable address. + +Note: this field is read-only. Its value is chip specific. + [28:24] + read-only + + + PC_MATCH + See corresponding field for PPU structure with programmable address. + [30:30] + read-write + + + ENABLED + See corresponding field for PPU structure with programmable address. + [31:31] + read-write + + + + + ADDR1 + PPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + See corresponding field for PPU structure with programmable address. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + See corresponding field for PPU structure with programmable address. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + PPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + See corresponding field for PPU structure with programmable address. + [1:1] + read-write + + + UX + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + See corresponding field for PPU structure with programmable address. + [4:4] + read-write + + + PX + See corresponding field for PPU structure with programmable address. + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + See corresponding field for PPU structure with programmable address. + [6:6] + read-write + + + PC_MASK_0 + See corresponding field for PPU structure with programmable address. + [8:8] + read-only + + + PC_MASK_15_TO_1 + See corresponding field for PPU structure with programmable address. + [23:9] + read-write + + + REGION_SIZE + See corresponding field for PPU structure with programmable address. + +'7': 256 B region + [28:24] + read-only + + + PC_MATCH + See corresponding field for PPU structure with programmable address. + [30:30] + read-write + + + ENABLED + See corresponding field for PPU structure with programmable address. + [31:31] + read-write + + + + + + + + CPUSS + CPU subsystem (CPUSS) + 0x40210000 + + 0 + 65536 + registers + + + ioss_interrupts_gpio_0 + GPIO Port Interrupt #0 + 0 + + + ioss_interrupts_gpio_1 + GPIO Port Interrupt #1 + 1 + + + ioss_interrupts_gpio_2 + GPIO Port Interrupt #2 + 2 + + + ioss_interrupts_gpio_3 + GPIO Port Interrupt #3 + 3 + + + ioss_interrupts_gpio_4 + GPIO Port Interrupt #4 + 4 + + + ioss_interrupts_gpio_5 + GPIO Port Interrupt #5 + 5 + + + ioss_interrupts_gpio_6 + GPIO Port Interrupt #6 + 6 + + + ioss_interrupts_gpio_7 + GPIO Port Interrupt #7 + 7 + + + ioss_interrupts_gpio_8 + GPIO Port Interrupt #8 + 8 + + + ioss_interrupts_gpio_9 + GPIO Port Interrupt #9 + 9 + + + ioss_interrupts_gpio_10 + GPIO Port Interrupt #10 + 10 + + + ioss_interrupts_gpio_11 + GPIO Port Interrupt #11 + 11 + + + ioss_interrupts_gpio_12 + GPIO Port Interrupt #12 + 12 + + + ioss_interrupts_gpio_13 + GPIO Port Interrupt #13 + 13 + + + ioss_interrupts_gpio_14 + GPIO Port Interrupt #14 + 14 + + + ioss_interrupt_gpio + GPIO All Ports + 15 + + + ioss_interrupt_vdd + GPIO Supply Detect Interrupt + 16 + + + lpcomp_interrupt + Low Power Comparator Interrupt + 17 + + + scb_8_interrupt + Serial Communication Block #8 (DeepSleep capable) + 18 + + + srss_interrupt_mcwdt_0 + Multi Counter Watchdog Timer interrupt + 19 + + + srss_interrupt_mcwdt_1 + Multi Counter Watchdog Timer interrupt + 20 + + + srss_interrupt_backup + Backup domain interrupt + 21 + + + srss_interrupt + Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + 22 + + + pass_interrupt_ctbs + CTBm Interrupt (all CTBms) + 23 + + + bless_interrupt + Bluetooth Radio interrupt + 24 + + + cpuss_interrupts_ipc_0 + CPUSS Inter Process Communication Interrupt #0 + 25 + + + cpuss_interrupts_ipc_1 + CPUSS Inter Process Communication Interrupt #1 + 26 + + + cpuss_interrupts_ipc_2 + CPUSS Inter Process Communication Interrupt #2 + 27 + + + cpuss_interrupts_ipc_3 + CPUSS Inter Process Communication Interrupt #3 + 28 + + + cpuss_interrupts_ipc_4 + CPUSS Inter Process Communication Interrupt #4 + 29 + + + cpuss_interrupts_ipc_5 + CPUSS Inter Process Communication Interrupt #5 + 30 + + + cpuss_interrupts_ipc_6 + CPUSS Inter Process Communication Interrupt #6 + 31 + + + cpuss_interrupts_ipc_7 + CPUSS Inter Process Communication Interrupt #7 + 32 + + + cpuss_interrupts_ipc_8 + CPUSS Inter Process Communication Interrupt #8 + 33 + + + cpuss_interrupts_ipc_9 + CPUSS Inter Process Communication Interrupt #9 + 34 + + + cpuss_interrupts_ipc_10 + CPUSS Inter Process Communication Interrupt #10 + 35 + + + cpuss_interrupts_ipc_11 + CPUSS Inter Process Communication Interrupt #11 + 36 + + + cpuss_interrupts_ipc_12 + CPUSS Inter Process Communication Interrupt #12 + 37 + + + cpuss_interrupts_ipc_13 + CPUSS Inter Process Communication Interrupt #13 + 38 + + + cpuss_interrupts_ipc_14 + CPUSS Inter Process Communication Interrupt #14 + 39 + + + cpuss_interrupts_ipc_15 + CPUSS Inter Process Communication Interrupt #15 + 40 + + + scb_0_interrupt + Serial Communication Block #0 + 41 + + + scb_1_interrupt + Serial Communication Block #1 + 42 + + + scb_2_interrupt + Serial Communication Block #2 + 43 + + + scb_3_interrupt + Serial Communication Block #3 + 44 + + + scb_4_interrupt + Serial Communication Block #4 + 45 + + + scb_5_interrupt + Serial Communication Block #5 + 46 + + + scb_6_interrupt + Serial Communication Block #6 + 47 + + + scb_7_interrupt + Serial Communication Block #7 + 48 + + + csd_interrupt + CSD (Capsense) interrupt + 49 + + + cpuss_interrupts_dw0_0 + CPUSS DataWire #0, Channel #0 + 50 + + + cpuss_interrupts_dw0_1 + CPUSS DataWire #0, Channel #1 + 51 + + + cpuss_interrupts_dw0_2 + CPUSS DataWire #0, Channel #2 + 52 + + + cpuss_interrupts_dw0_3 + CPUSS DataWire #0, Channel #3 + 53 + + + cpuss_interrupts_dw0_4 + CPUSS DataWire #0, Channel #4 + 54 + + + cpuss_interrupts_dw0_5 + CPUSS DataWire #0, Channel #5 + 55 + + + cpuss_interrupts_dw0_6 + CPUSS DataWire #0, Channel #6 + 56 + + + cpuss_interrupts_dw0_7 + CPUSS DataWire #0, Channel #7 + 57 + + + cpuss_interrupts_dw0_8 + CPUSS DataWire #0, Channel #8 + 58 + + + cpuss_interrupts_dw0_9 + CPUSS DataWire #0, Channel #9 + 59 + + + cpuss_interrupts_dw0_10 + CPUSS DataWire #0, Channel #10 + 60 + + + cpuss_interrupts_dw0_11 + CPUSS DataWire #0, Channel #11 + 61 + + + cpuss_interrupts_dw0_12 + CPUSS DataWire #0, Channel #12 + 62 + + + cpuss_interrupts_dw0_13 + CPUSS DataWire #0, Channel #13 + 63 + + + cpuss_interrupts_dw0_14 + CPUSS DataWire #0, Channel #14 + 64 + + + cpuss_interrupts_dw0_15 + CPUSS DataWire #0, Channel #15 + 65 + + + cpuss_interrupts_dw1_0 + CPUSS DataWire #1, Channel #0 + 66 + + + cpuss_interrupts_dw1_1 + CPUSS DataWire #1, Channel #1 + 67 + + + cpuss_interrupts_dw1_2 + CPUSS DataWire #1, Channel #2 + 68 + + + cpuss_interrupts_dw1_3 + CPUSS DataWire #1, Channel #3 + 69 + + + cpuss_interrupts_dw1_4 + CPUSS DataWire #1, Channel #4 + 70 + + + cpuss_interrupts_dw1_5 + CPUSS DataWire #1, Channel #5 + 71 + + + cpuss_interrupts_dw1_6 + CPUSS DataWire #1, Channel #6 + 72 + + + cpuss_interrupts_dw1_7 + CPUSS DataWire #1, Channel #7 + 73 + + + cpuss_interrupts_dw1_8 + CPUSS DataWire #1, Channel #8 + 74 + + + cpuss_interrupts_dw1_9 + CPUSS DataWire #1, Channel #9 + 75 + + + cpuss_interrupts_dw1_10 + CPUSS DataWire #1, Channel #10 + 76 + + + cpuss_interrupts_dw1_11 + CPUSS DataWire #1, Channel #11 + 77 + + + cpuss_interrupts_dw1_12 + CPUSS DataWire #1, Channel #12 + 78 + + + cpuss_interrupts_dw1_13 + CPUSS DataWire #1, Channel #13 + 79 + + + cpuss_interrupts_dw1_14 + CPUSS DataWire #1, Channel #14 + 80 + + + cpuss_interrupts_dw1_15 + CPUSS DataWire #1, Channel #15 + 81 + + + cpuss_interrupts_fault_0 + CPUSS Fault Structure Interrupt #0 + 82 + + + cpuss_interrupts_fault_1 + CPUSS Fault Structure Interrupt #1 + 83 + + + cpuss_interrupt_crypto + CRYPTO Accelerator Interrupt + 84 + + + cpuss_interrupt_fm + FLASH Macro Interrupt + 85 + + + cpuss_interrupts_cm0_cti_0 + CM0+ CTI #0 + 86 + + + cpuss_interrupts_cm0_cti_1 + CM0+ CTI #1 + 87 + + + cpuss_interrupts_cm4_cti_0 + CM4 CTI #0 + 88 + + + cpuss_interrupts_cm4_cti_1 + CM4 CTI #1 + 89 + + + tcpwm_0_interrupts_0 + TCPWM #0, Counter #0 + 90 + + + tcpwm_0_interrupts_1 + TCPWM #0, Counter #1 + 91 + + + tcpwm_0_interrupts_2 + TCPWM #0, Counter #2 + 92 + + + tcpwm_0_interrupts_3 + TCPWM #0, Counter #3 + 93 + + + tcpwm_0_interrupts_4 + TCPWM #0, Counter #4 + 94 + + + tcpwm_0_interrupts_5 + TCPWM #0, Counter #5 + 95 + + + tcpwm_0_interrupts_6 + TCPWM #0, Counter #6 + 96 + + + tcpwm_0_interrupts_7 + TCPWM #0, Counter #7 + 97 + + + tcpwm_1_interrupts_0 + TCPWM #1, Counter #0 + 98 + + + tcpwm_1_interrupts_1 + TCPWM #1, Counter #1 + 99 + + + tcpwm_1_interrupts_2 + TCPWM #1, Counter #2 + 100 + + + tcpwm_1_interrupts_3 + TCPWM #1, Counter #3 + 101 + + + tcpwm_1_interrupts_4 + TCPWM #1, Counter #4 + 102 + + + tcpwm_1_interrupts_5 + TCPWM #1, Counter #5 + 103 + + + tcpwm_1_interrupts_6 + TCPWM #1, Counter #6 + 104 + + + tcpwm_1_interrupts_7 + TCPWM #1, Counter #7 + 105 + + + tcpwm_1_interrupts_8 + TCPWM #1, Counter #8 + 106 + + + tcpwm_1_interrupts_9 + TCPWM #1, Counter #9 + 107 + + + tcpwm_1_interrupts_10 + TCPWM #1, Counter #10 + 108 + + + tcpwm_1_interrupts_11 + TCPWM #1, Counter #11 + 109 + + + tcpwm_1_interrupts_12 + TCPWM #1, Counter #12 + 110 + + + tcpwm_1_interrupts_13 + TCPWM #1, Counter #13 + 111 + + + tcpwm_1_interrupts_14 + TCPWM #1, Counter #14 + 112 + + + tcpwm_1_interrupts_15 + TCPWM #1, Counter #15 + 113 + + + tcpwm_1_interrupts_16 + TCPWM #1, Counter #16 + 114 + + + tcpwm_1_interrupts_17 + TCPWM #1, Counter #17 + 115 + + + tcpwm_1_interrupts_18 + TCPWM #1, Counter #18 + 116 + + + tcpwm_1_interrupts_19 + TCPWM #1, Counter #19 + 117 + + + tcpwm_1_interrupts_20 + TCPWM #1, Counter #20 + 118 + + + tcpwm_1_interrupts_21 + TCPWM #1, Counter #21 + 119 + + + tcpwm_1_interrupts_22 + TCPWM #1, Counter #22 + 120 + + + tcpwm_1_interrupts_23 + TCPWM #1, Counter #23 + 121 + + + udb_interrupts_0 + UDB Interrupt #0 + 122 + + + udb_interrupts_1 + UDB Interrupt #1 + 123 + + + udb_interrupts_2 + UDB Interrupt #2 + 124 + + + udb_interrupts_3 + UDB Interrupt #3 + 125 + + + udb_interrupts_4 + UDB Interrupt #4 + 126 + + + udb_interrupts_5 + UDB Interrupt #5 + 127 + + + udb_interrupts_6 + UDB Interrupt #6 + 128 + + + udb_interrupts_7 + UDB Interrupt #7 + 129 + + + udb_interrupts_8 + UDB Interrupt #8 + 130 + + + udb_interrupts_9 + UDB Interrupt #9 + 131 + + + udb_interrupts_10 + UDB Interrupt #10 + 132 + + + udb_interrupts_11 + UDB Interrupt #11 + 133 + + + udb_interrupts_12 + UDB Interrupt #12 + 134 + + + udb_interrupts_13 + UDB Interrupt #13 + 135 + + + udb_interrupts_14 + UDB Interrupt #14 + 136 + + + udb_interrupts_15 + UDB Interrupt #15 + 137 + + + pass_interrupt_sar + SAR ADC interrupt + 138 + + + audioss_interrupt_i2s + I2S Audio interrupt + 139 + + + audioss_interrupt_pdm + PDM/PCM Audio interrupt + 140 + + + profile_interrupt + Energy Profiler interrupt + 141 + + + smif_interrupt + Serial Memory Interface interrupt + 142 + + + usb_interrupt_hi + USB Interrupt + 143 + + + usb_interrupt_med + USB Interrupt + 144 + + + usb_interrupt_lo + USB Interrupt + 145 + + + pass_interrupt_dacs + Consolidated interrrupt for all DACs + 146 + + + + CM0_CTL + CM0+ control + 0x0 + 32 + read-write + 0xFA050002 + 0xFFFF0003 + + + SLV_STALL + Processor debug access control: +'0': Access. +'1': Stall access. + +This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. + [0:0] + read-write + + + ENABLED + Processor enable: +'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. +'1': Enabled. +Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). + +Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). + [1:1] + read-write + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM0_STATUS + CM0+ status + 0x8 + 32 + read-only + 0x0 + 0x3 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + + + CM0_CLOCK_CTL + CM0+ clock control + 0x10 + 32 + read-write + 0x1000000 + 0xFF00FF00 + + + SLOW_INT_DIV + Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + PERI_INT_DIV + Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + +Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. + [31:24] + read-write + + + + + CM0_INT_CTL0 + CM0+ interrupt control 0 + 0x20 + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 1. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 2. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 3. + [31:24] + read-write + + + + + CM0_INT_CTL1 + CM0+ interrupt control 1 + 0x24 + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 4. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 5. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 6. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 7. + [31:24] + read-write + + + + + CM0_INT_CTL2 + CM0+ interrupt control 2 + 0x28 + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 8. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 9. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 10. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 11. + [31:24] + read-write + + + + + CM0_INT_CTL3 + CM0+ interrupt control 3 + 0x2C + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 12. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 13. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 14. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 15. + [31:24] + read-write + + + + + CM0_INT_CTL4 + CM0+ interrupt control 4 + 0x30 + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 16. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 17. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 18. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 19. + [31:24] + read-write + + + + + CM0_INT_CTL5 + CM0+ interrupt control 5 + 0x34 + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 20. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 21. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 22. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 23. + [31:24] + read-write + + + + + CM0_INT_CTL6 + CM0+ interrupt control 6 + 0x38 + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 24. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 25. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 26. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 27. + [31:24] + read-write + + + + + CM0_INT_CTL7 + CM0+ interrupt control 7 + 0x3C + 32 + read-write + 0xF0F0F0F0 + 0xFFFFFFFF + + + MUX0_SEL + System interrupt select for CPU interrupt source 28. + [7:0] + read-write + + + MUX1_SEL + System interrupt select for CPU interrupt source 29. + [15:8] + read-write + + + MUX2_SEL + System interrupt select for CPU interrupt source 30. + [23:16] + read-write + + + MUX3_SEL + System interrupt select for CPU interrupt source 31. + [31:24] + read-write + + + + + CM4_PWR_CTL + CM4 power control + 0x80 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for CM4 + [1:0] + read-write + + + OFF + Switch CM4 off +Power off, clock off, isolate, reset and no retain. + 0 + + + RESET + Reset CM4 +Clock off, no isolated, no retain and reset. + +Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. + 1 + + + RETAINED + Put CM4 in Retained mode +This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. +Power off, clock off, isolate, no reset and retain. + 2 + + + ENABLED + Switch CM4 on. +Power on, clock on, no isolate, no reset and no retain. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM4_PWR_DELAY_CTL + CM4 power control + 0x84 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM4_STATUS + CM4 status + 0x88 + 32 + read-only + 0x13 + 0x13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + + + CM4_CLOCK_CTL + CM4 clock control + 0x90 + 32 + read-write + 0x0 + 0xFF00 + + + FAST_INT_DIV + Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM4_NMI_CTL + CM4 NMI control + 0xA0 + 32 + read-write + 0xF0 + 0xFF + + + MUX0_SEL + System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [7:0] + read-write + + + + + RAM0_CTL0 + RAM 0 control 0 + 0x100 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + + + 16 + 4 + RAM0_PWR_MACRO_CTL[%s] + RAM 0 power control + 0x140 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for 1 SRAM0 Macro + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + RAM1_CTL0 + RAM 1 control 0 + 0x180 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + + + RAM1_PWR_CTL + RAM1 power control + 0x190 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for SRAM1 + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + RAM2_CTL0 + RAM 2 control 0 + 0x1A0 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + + + RAM2_PWR_CTL + RAM2 power control + 0x1B0 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for SRAM2 + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + RAM_PWR_DELAY_CTL + Power up delay used for all SRAM power domains + 0x1C0 + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + ROM_CTL + ROM control + 0x1D0 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + +Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + + + UDB_PWR_CTL + UDB power control + 0x1F0 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for UDBs + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RESET + See CM4_PWR_CTL + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + UDB_PWR_DELAY_CTL + UDB power control + 0x1F4 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + DP_STATUS + Debug port status + 0x208 + 32 + read-only + 0x4 + 0x7 + + + SWJ_CONNECTED + Specifies if the SWJ debug port is connected; i.e. debug host interface is active: +'0': Not connected/not active. +'1': Connected/active. + [0:0] + read-only + + + SWJ_DEBUG_EN + Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: +'0': Disabled. +'1': Enabled. + [1:1] + read-only + + + SWJ_JTAG_SEL + Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). +'0': SWD selected. +'1': JTAG selected. + [2:2] + read-only + + + + + BUFF_CTL + Buffer control + 0x220 + 32 + read-write + 0x1 + 0x1 + + + WRITE_BUFF + Specifies if write transfer can be buffered in the bus infrastructure bridges: +'0': Write transfers are not buffered, independent of the transfer's bufferable attribute. +'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. + [0:0] + read-write + + + + + DDFT_CTL + DDFT control + 0x230 + 32 + read-write + 0x0 + 0x1F1F + + + DDFT_OUT0_SEL + Select signal for CPUSS DDFT[0] +0: clk_r of the Main flash (which is clk_hf for SONOS Flash) +1: Flash data output bit '0' (r_q[0]) +2: Flash data output bit '32' (r_q[32]) +3: Flash data output bit '64' (r_q[64]) +4: Flash data output bit '127' (r_q[127]) +5: bist_fm_enabled +6: bist_fail +7: cm0_sleeping +8: cm0_sleepdeep +9: cm0_sleep_hold_ack_n +10: cm4_sleeping +11: cm4_sleepdeep +12: cm4_sleep_hold_ack_n +13: cm4_power +14: cm4_act_retain_n +15: cm4_act_isolate_n +16: cm4_enabled +17: cm4_reset_n +18: cm4_pwr_done +19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) +20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) +21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0) + [4:0] + read-write + + + DDFT_OUT1_SEL + Select signal for CPUSS DDFT[0] +0: clk_r of the Main flash (which is clk_hf for SONOS Flash) +1: Flash data output bit '0' (r_q[0]) +2: Flash data output bit '32' (r_q[32]) +3: Flash data output bit '64' (r_q[64]) +4: Flash data output bit '127' (r_q[127]) +5: bist_fm_enabled +6: bist_fail +7: cm0_sleeping +8: cm0_sleepdeep +9: cm0_sleep_hold_ack_n +10: cm4_sleeping +11: cm4_sleepdeep +12: cm4_sleep_hold_ack_n +13: cm4_power +14: cm4_act_retain_n +15: cm4_act_isolate_n +16: cm4_enabled +17: cm4_reset_n +18: cm4_pwr_done +19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) +20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) +21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0) + [12:8] + read-write + + + + + SYSTICK_CTL + SysTick timer control + 0x240 + 32 + read-write + 0x40000147 + 0xC3FFFFFF + + + TENMS + Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. + [23:0] + read-write + + + CLOCK_SOURCE + Specifies an external clock source: +'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). +'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. +o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. +'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). + +Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. +Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. + [25:24] + read-write + + + SKEW + Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: +'0': Precise. +'1': Imprecise. + [30:30] + read-write + + + NOREF + Specifies if an external clock source is provided: +'0': An external clock source is provided. +'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. + [31:31] + read-write + + + + + CM0_VECTOR_TABLE_BASE + CM0+ vector table base + 0x2B0 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + Address of CM0+ vector table. + +Note: the CM0+ vector table is at an address that is a 256 B multiple. + [31:8] + read-write + + + + + CM4_VECTOR_TABLE_BASE + CM4 vector table base + 0x2C0 + 32 + read-write + 0x0 + 0xFFFFFC00 + + + ADDR22 + Address of CM4 vector table. + +Note: the CM4 vector table is at an address that is a 1024 B multiple. + [31:10] + read-write + + + + + CM0_PC0_HANDLER + CM0+ protection context 0 handler + 0x320 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. + [31:0] + read-write + + + + + IDENTITY + Identity + 0x400 + 32 + read-only + 0x0 + 0x0 + + + P + This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. + [0:0] + read-only + + + NS + This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. + [1:1] + read-only + + + PC + This field specifies the protection context of the transfer that reads the register. + [7:4] + read-only + + + MS + This field specifies the bus master identifier of the transfer that reads the register. + [11:8] + read-only + + + + + PROTECTION + Protection status + 0x500 + 32 + read-write + 0x0 + 0x7 + + + STATE + Protection state: +'0': UNKNOWN. +'1': VIRGIN. +'2': NORMAL. +'3': SECURE. +'4': DEAD. + +The following state transitions are allowed (and enforced by HW): +- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD +- NORMAL => DEAD +- SECURE => DEAD +An attempt to make a NOT allowed state transition will NOT affect this register field. + [2:0] + read-write + + + + + CM0_NMI_CTL + CM0+ NMI control + 0x520 + 32 + read-write + 0xF0 + 0xFF + + + MUX0_SEL + System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [7:0] + read-write + + + + + AP_CTL + Access port control + 0x540 + 32 + read-write + 0x0 + 0x70007 + + + CM0_ENABLE + Enables the CM0 AP interface: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + CM4_ENABLE + Enables the CM4 AP interface: +'0': Disabled. +'1': Enabled. + [1:1] + read-write + + + SYS_ENABLE + Enables the system AP interface: +'0': Disabled. +'1': Enabled. + [2:2] + read-write + + + CM0_DISABLE + Disables the CM0 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. + [16:16] + read-write + + + CM4_DISABLE + Disables the CM4 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. + [17:17] + read-write + + + SYS_DISABLE + Disables the system AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. + [18:18] + read-write + + + + + MBIST_STAT + Memory BIST status + 0x5A0 + 32 + read-only + 0x0 + 0x3 + + + SFP_READY + Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. + [0:0] + read-only + + + SFP_FAIL + Report status of the BIST run, only valid if SFP_READY=1 + [1:1] + read-only + + + + + TRIM_ROM_CTL + ROM trim control + 0xF000 + 32 + read-write + 0x2 + 0x1F + + + RM + N/A + [3:0] + read-write + + + RME + Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin setting. + [4:4] + read-write + + + + + TRIM_RAM_CTL + RAM trim control + 0xF004 + 32 + read-write + 0x6002 + 0x73FF + + + RM + N/A + [3:0] + read-write + + + RME + Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin setting. + [4:4] + read-write + + + WPULSE + Write Assist Pulse to control pulse width of negative voltage on SRAM bitline. + [7:5] + read-write + + + RA + Read Assist control for WL under-drive. + [9:8] + read-write + + + WA + Write assist enable control (Active High). +- WA[1:0] Write Assist pins to control negative voltage on SRAM bitline. + [14:12] + read-write + + + + + + + FAULT + Fault structures + 0x40220000 + + 0 + 65536 + registers + + + + 2 + 256 + STRUCT[%s] + Fault structure + 0x00000000 + + CTL + Fault control + 0x0 + 32 + read-write + 0x0 + 0x7 + + + TR_EN + Trigger output enable: +'0': Disabled. The trigger output 'tr_fault' is '0'. +'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). + [0:0] + read-write + + + OUT_EN + IO output signal enable: +'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. +'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. + [1:1] + read-write + + + RESET_REQ_EN + Reset request enable: +'0': Disabled. +'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). + +The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. + [2:2] + read-write + + + + + STATUS + Fault status + 0xC + 32 + read-write + 0x0 + 0x80000000 + + + IDX + The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. + +Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. + [6:0] + read-only + + + VALID + Valid indication: +'0': Invalid. +'1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW). + [31:31] + read-write + + + + + 4 + 4 + DATA[%s] + Fault data + 0x10 + 32 + read-only + 0x0 + 0x0 + + + DATA + Captured fault source data. + +Note: the fault source index STATUS.IDX specifies the format of the DATA registers. + [31:0] + read-only + + + + + PENDING0 + Fault pending 0 + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: CM0 MPU. +Bit 1: CRYPTO MPU. +Bit 2: DW 0 MPU. +Bit 3: DW 1 MPU. +... +Bit 14: CM4 code bus MPU. +Bit 15: DAP MPU. +Bit 16: CM4 s+G92ystem bus MPU. + + +Bit 28: Peripheral master interface 0 PPU. +Bit 29: Peripheral master interface 1 PPU. +Bit 30: Peripheral master interface 2 PPU. +Bit 31: Peripheral master interface 3 PPU. + [31:0] + read-only + + + + + PENDING1 + Fault pending 1 + 0x44 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: Peripheral group 0 PPU. +Bit 1: Peripheral group 1 PPU. +Bit 2: Peripheral group 2 PPU. +Bit 3: Peripheral group 3 PPU. +Bit 4: Peripheral group 4 PPU. +Bit 5: Peripheral group 5 PPU. +Bit 6: Peripheral group 6 PPU. +Bit 7: Peripheral group 7 PPU. +... +Bit 15: Peripheral group 15 PPU. + +Bit 18: Flash controller, main interface, bus error. + [31:0] + read-only + + + + + PENDING2 + Fault pending 2 + 0x48 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0 - 31: TBD. + [31:0] + read-only + + + + + MASK0 + Fault mask 0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 31 to 0. + [31:0] + read-write + + + + + MASK1 + Fault mask 1 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 63 to 32. + [31:0] + read-write + + + + + MASK2 + Fault mask 2 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 95 to 64. + [31:0] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1 + + + FAULT + This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: +- STATUS.VALID is set to '1'. +- STATUS.IDX specifies the fault source index. +- DATA0 through DATA3 captures the fault source data. + +SW writes a '1' to these field to clear the interrupt cause to '0'. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1 + + + FAULT + SW writes a '1' to this field to set the corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1 + + + FAULT + Mask bit for corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1 + + + FAULT + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + IPC + IPC + 0x40230000 + + 0 + 65536 + registers + + + + 16 + 32 + STRUCT[%s] + IPC structure + 0x00000000 + + ACQUIRE + IPC acquire + 0x0 + 32 + read-only + 0x0 + 0x80000000 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the access that successfully acquired the lock. + [0:0] + read-only + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the access that successfully acquired the lock. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + SUCCESS + Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): +'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. +'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. + +Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). + [31:31] + read-only + + + + + RELEASE + IPC release + 0x4 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_RELEASE + This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. + +SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. + +As a side effect, a write to this register will always set LOCK_STATUS.ACQUIRED to '0' (even when no release event is generated; i.e. the written data is '0'). + [15:0] + write-only + + + + + NOTIFY + IPC notification + 0x8 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_NOTIFY + This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. + +SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + DATA + IPC data + 0xC + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + LOCK_STATUS + IPC lock status + 0x10 + 32 + read-only + 0x0 + 0x80000000 + + + P + This field specifies the user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + This field specifies the cecure/on-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + ACQUIRED + Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). + [31:31] + read-only + + + + + + 16 + 32 + INTR_STRUCT[%s] + IPC interrupt structure + 0x00001000 + + INTR + Interrupt + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [15:0] + read-write + + + NOTIFY + These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [31:16] + read-write + + + + + INTR_SET + Interrupt set + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + SW writes a '1' to this field to set the corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASK + Interrupt mask + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + Mask bit for corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RELEASE + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + NOTIFY + Logical and of corresponding INTR and INTR_MASK fields. + [31:16] + read-only + + + + + + + + PROT + Protection + 0x40240000 + + 0 + 65536 + registers + + + + SMPU + SMPU + 0x00000000 + + MS0_CTL + Master 0 protection context control + 0x0 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + Privileged setting ('0': user mode; '1': privileged mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. +The default/reset field value provides privileged mode access capabilities. + [0:0] + read-write + + + NS + Security setting ('0': secure mode; '1': non-secure mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. +Note that the default/reset field value provides non-secure mode access capabilities to all masters. + [1:1] + read-write + + + PRIO + Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). + +Notes: +The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). +The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). +Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. + [9:8] + read-write + + + PC_MASK_0 + Protection context mask for protection context '0'. This field is a constant '0': +- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. + [16:16] + read-only + + + PC_MASK_15_TO_1 + Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': +- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. +- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. + +Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). + [31:17] + read-write + + + + + MS1_CTL + Master 1 protection context control + 0x4 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS2_CTL + Master 2 protection context control + 0x8 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS3_CTL + Master 3 protection context control + 0xC + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS4_CTL + Master 4 protection context control + 0x10 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS5_CTL + Master 5 protection context control + 0x14 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS6_CTL + Master 6 protection context control + 0x18 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS7_CTL + Master 7 protection context control + 0x1C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS8_CTL + Master 8 protection context control + 0x20 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS9_CTL + Master 9 protection context control + 0x24 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS10_CTL + Master 10 protection context control + 0x28 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS11_CTL + Master 11 protection context control + 0x2C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS12_CTL + Master 12 protection context control + 0x30 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS13_CTL + Master 13 protection context control + 0x34 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS14_CTL + Master 14 protection context control + 0x38 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS15_CTL + Master 15 protection context control + 0x3C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + 16 + 64 + SMPU_STRUCT[%s] + SMPU structure + 0x00002000 + + ADDR0 + SMPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + SMPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x100 + 0x80000100 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + SMPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + SMPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'7': 256 B region (8 32 B subregions) + +Note: this field is read-only. + [28:24] + read-only + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + [31:31] + read-write + + + + + + + 16 + 1024 + MPU[%s] + MPU + 0x00004000 + + MS_CTL + Master control + 0x0 + 32 + read-write + 0x0 + 0xF000F + + + PC + N/A + [3:0] + read-write + + + PC_SAVED + Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. + [19:16] + read-write + + + + + 127 + 4 + MS_CTL_READ_MIR[%s] + Master control read mirror + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + PC + Read-only mirror of MS_CTL.PC + [3:0] + read-only + + + PC_SAVED + Read-only mirror of MS_CTL.PC_SAVED + [19:16] + read-only + + + + + 8 + 32 + MPU_STRUCT[%s] + MPU structure + 0x00000200 + + ADDR + MPU region address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT + MPU region attrributes + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + + + + + FLASHC + Flash controller + 0x40250000 + + 0 + 65536 + registers + + + + FLASH_CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x10F + + + MAIN_WS + FLASH macro main interface wait states: +0: 0 wait states. +... +15: 15 wait states + [3:0] + read-write + + + REMAP + Specifies remapping of FLASH macro main region. +0: No remapping. +1: Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors. + +Note: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface). + +E.g., for a 512 KB / 4 Mb main region, the logical address space ranges from [0x1000:0000, 0x1007:ffff] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is '0', the physical regions logical addresses are as follows: +- The physical region 0: [0x1000:0000, 0x1001:ffff]. +- The physical region 1: [0x1002:0000, 0x1003:ffff]. +- The physical region 2: [0x1004:0000, 0x1005:ffff]. +- The physical region 3: [0x1006:0000, 0x1007:ffff]. +If REMAP is '1', the physical regions logical addresses are as follows: +- The physical region 0: [0x1004:0000, 0x1005:ffff]. +- The physical region 1: [0x1006:0000, 0x1007:ffff]. +- The physical region 2: [0x1000:0000, 0x1001:ffff]. +- The physical region 3: [0x1002:0000, 0x1003:ffff]. + +Note: when the REMAP is changed, SW should invalidate the caches and buffers. + [8:8] + read-write + + + + + FLASH_PWR_CTL + Flash power control + 0x4 + 32 + read-write + 0x3 + 0x3 + + + ENABLE + Controls 'enable' pin of the Flash memory. + [0:0] + read-write + + + ENABLE_HV + Controls 'enable_hv' pin of the Flash memory. + [1:1] + read-write + + + + + FLASH_CMD + Command + 0x8 + 32 + read-write + 0x0 + 0x1 + + + INV + FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. + [0:0] + read-write + + + + + BIST_CTL + BIST control + 0x100 + 32 + read-write + 0x0 + 0xFF + + + OPCODE + This field specifies how the data check should be performed after reading the data from Flash memory. +0: Read the Flash and compare the output to BIST_DATA (R0). +1: Read the Flash and compare the output to the binary complement of BIST_DATA (R1). +3: Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on. + [1:0] + read-write + + + UP + Specifies direction in which Flash BIST steps through addresses: +0: BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configuration parameter when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the minimum row and column addresses. +1: BIST steps through the Flash from the minimum row and column addresses ('0' when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1'' to the maximum row and column addresses. + [2:2] + read-write + + + ROW_FIRST + Specifies how the Flash BIST addresses are generated: +'0': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the row address incremented/decremented. +'1': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the column address incremented/decremented. + [3:3] + read-write + + + ADDR_START_ENABLED + Specifies Flash BIST start addresses: +'0': Row and column addresses start with their maximum/minimum values. +'1': Row and column addresses start with their values as specified by BIST_ADDR_START. + +This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read. + [4:4] + read-write + + + ADDR_COMPLIMENT_ENABLED + Specifies to generate address compliment patterns. +0: Generate normal increment/decrement patterns. +1: Generate address patterns which interleaves compliment of previous address in between. +Example: The following is an example pattern, With UP=1 and ROW_FIRST =0 +00_00 +11_11 +00_01 +11_10 +00_10 +11_01 +... + [5:5] + read-write + + + INCR_DECR_BOTH + Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously. +0: Generate normal increment/decrement patterns. +1: Generate address patterns with both row and column address changing. +Example: With UP = 1 and ROW_FIRST = 0 +00_00 +01_01 +10_10 +11_11 +00_01 +01_10 +10_11 +11_00 +00_10 +... + [6:6] + read-write + + + STOP_ON_ERROR + Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not. +0: BIST controller doesn't stop on the data failures, it continues regardless of the errors. +1: BIST controller stops on when the first data failure is encountered. + [7:7] + read-write + + + + + BIST_CMD + BIST command + 0x104 + 32 + read-write + 0x0 + 0x1 + + + START + 1: Start FLASH BIST. Hardware set this field to '0' when BIST is completed. + [0:0] + read-write + + + + + BIST_ADDR_START + BIST address start register + 0x108 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COL_ADDR_START + Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is [0, n-1]. + [15:0] + read-write + + + ROW_ADDR_START + Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is [0, m-1]. + [31:16] + read-write + + + + + 8 + 4 + BIST_DATA[%s] + BIST data register(s) + 0x10C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + BIST data register to store the expected value for data comparison. +For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value. + [31:0] + read-write + + + + + 8 + 4 + BIST_DATA_ACT[%s] + BIST data actual register(s) + 0x12C + 32 + read-only + 0x0 + 0x0 + + + DATA + This field specified the actual Flash data output that caused the BIST failure. + [31:0] + read-only + + + + + 8 + 4 + BIST_DATA_EXP[%s] + BIST data expected register(s) + 0x14C + 32 + read-only + 0x0 + 0x0 + + + DATA + This field specified the expected Flash data output. + [31:0] + read-only + + + + + BIST_ADDR + BIST address register + 0x16C + 32 + read-only + 0x0 + 0x0 + + + COL_ADDR + Current column address. + [15:0] + read-only + + + ROW_ADDR + Current row address. + [31:16] + read-only + + + + + BIST_STATUS + BIST status register + 0x170 + 32 + read-write + 0x0 + 0x1 + + + FAIL + 0: BIST passed. +1: BIST failed. + [0:0] + read-write + + + + + CM0_CA_CTL0 + CM0+ cache control + 0x400 + 32 + read-write + 0xC0000000 + 0xC7030000 + + + WAY + Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. + [26:24] + read-write + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + ENABLED + Cache enable: +0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). +1: Enabled. + [31:31] + read-write + + + + + CM0_CA_CTL1 + CM0+ cache control + 0x404 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for CM0 cache + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM0_CA_CTL2 + CM0+ cache control + 0x408 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CA_CMD + CM0+ cache command + 0x40C + 32 + read-write + 0x0 + 0x1 + + + INV + FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure is also reset to its default state. + [0:0] + read-write + + + + + CM0_CA_STATUS0 + CM0+ cache status 0 + 0x440 + 32 + read-only + 0x0 + 0xFFFF + + + VALID16 + Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [15:0] + read-only + + + + + CM0_CA_STATUS1 + CM0+ cache status 1 + 0x444 + 32 + read-only + 0x0 + 0x0 + + + TAG + Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS2 + CM0+ cache status 2 + 0x448 + 32 + read-only + 0x0 + 0x0 + + + LRU + Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): +Bit 5: 0_LRU_1: way 0 less recently used than way 1. +Bit 4: 0_LRU_2. +Bit 3: 0_LRU_3. +Bit 2: 1_LRU_2. +Bit 1: 1_LRU_3. +Bit 0: 2_LRU_3. + [5:0] + read-only + + + + + CM4_CA_CTL0 + CM4 cache control + 0x480 + 32 + read-write + 0xC0000000 + 0xC7030000 + + + WAY + See CM0_CA_CTL. + [17:16] + read-write + + + SET_ADDR + See CM0_CA_CTL. + [26:24] + read-write + + + PREF_EN + See CM0_CA_CTL. + [30:30] + read-write + + + ENABLED + See CM0_CA_CTL. + [31:31] + read-write + + + + + CM4_CA_CTL1 + CM4 cache control + 0x484 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for CM4 cache + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM4_CA_CTL2 + CM4 cache control + 0x488 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM4_CA_CMD + CM4 cache command + 0x48C + 32 + read-write + 0x0 + 0x1 + + + INV + See CM0_CA_CMD. + [0:0] + read-write + + + + + CM4_CA_STATUS0 + CM4 cache status 0 + 0x4C0 + 32 + read-only + 0x0 + 0xFFFF + + + VALID16 + See CM0_CA_STATUS0. + [15:0] + read-only + + + + + CM4_CA_STATUS1 + CM4 cache status 1 + 0x4C4 + 32 + read-only + 0x0 + 0x0 + + + TAG + See CM0_CA_STATUS1. + [31:0] + read-only + + + + + CM4_CA_STATUS2 + CM4 cache status 2 + 0x4C8 + 32 + read-only + 0x0 + 0x0 + + + LRU + See CM0_CA_STATUS2. + [5:0] + read-only + + + + + CRYPTO_BUFF_CTL + Cryptography buffer control + 0x500 + 32 + read-write + 0xC0000000 + 0xC0000000 + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the buffer to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + ENABLED + Cache enable: +0: Disabled. +1: Enabled. + [31:31] + read-write + + + + + CRYPTO_BUFF_CMD + Cryptography buffer command + 0x508 + 32 + read-write + 0x0 + 0x1 + + + INV + FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to '0' when the operation is completed. + [0:0] + read-write + + + + + DW0_BUFF_CTL + Datawire 0 buffer control + 0x580 + 32 + read-write + 0xC0000000 + 0xC0000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + ENABLED + See CRYPTO_BUFF_CTL. + [31:31] + read-write + + + + + DW0_BUFF_CMD + Datawire 0 buffer command + 0x588 + 32 + read-write + 0x0 + 0x1 + + + INV + See CRYPTO_BUFF_CMD. + [0:0] + read-write + + + + + DW1_BUFF_CTL + Datawire 1 buffer control + 0x600 + 32 + read-write + 0xC0000000 + 0xC0000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + ENABLED + See CRYPTO_BUFF_CTL. + [31:31] + read-write + + + + + DW1_BUFF_CMD + Datawire 1 buffer command + 0x608 + 32 + read-write + 0x0 + 0x1 + + + INV + See CRYPTO_BUFF_CMD. + [0:0] + read-write + + + + + DAP_BUFF_CTL + Debug access port buffer control + 0x680 + 32 + read-write + 0xC0000000 + 0xC0000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + ENABLED + See CRYPTO_BUFF_CTL. + [31:31] + read-write + + + + + DAP_BUFF_CMD + Debug access port buffer command + 0x688 + 32 + read-write + 0x0 + 0x1 + + + INV + See CRYPTO_BUFF_CMD. + [0:0] + read-write + + + + + EXT_MS0_BUFF_CTL + External master 0 buffer control + 0x700 + 32 + read-write + 0xC0000000 + 0xC0000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + ENABLED + See CRYPTO_BUFF_CTL. + [31:31] + read-write + + + + + EXT_MS0_BUFF_CMD + External master 0 buffer command + 0x708 + 32 + read-write + 0x0 + 0x1 + + + INV + See CRYPTO_BUFF_CMD. + [0:0] + read-write + + + + + EXT_MS1_BUFF_CTL + External master 1 buffer control + 0x780 + 32 + read-write + 0xC0000000 + 0xC0000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + ENABLED + See CRYPTO_BUFF_CTL. + [31:31] + read-write + + + + + EXT_MS1_BUFF_CMD + External master 1 buffer command + 0x788 + 32 + read-write + 0x0 + 0x1 + + + INV + See CRYPTO_BUFF_CMD. + [0:0] + read-write + + + + + FM_CTL + Flash Macro Registers + 0x0000F000 + + FM_CTL + Flash macro control + 0x0 + 32 + read-write + 0x0 + 0x37F030F + + + FM_MODE + Flash macro mode selection: +'0': Normal functional mode. +'1': Sets 'pre-program control bit' for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation. +'2': Sets +... +'15': TBD + [3:0] + read-write + + + FM_SEQ + Flash macro sequence select: +'0': TBD +'1': TBD +'2': TBD +'3': TBD + [9:8] + read-write + + + DAA_MUX_SEL + Direct memory cell access address. + [22:16] + read-write + + + IF_SEL + Interface selection. Specifies the interface that is used for flash memory read operations: +'0': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. +'1': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. + [24:24] + read-write + + + WR_EN + '0': normal mode +'1': Fm Write Enable + [25:25] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x3F + + + HV_TIMER_RUNNING + Indicates if the high voltage timer is running: +'0': not running +'1': running + [0:0] + read-only + + + HV_REGS_ISOLATED + Indicates the isolation status at HV trim and redundancy registers inputs +'0' - Not isolated, writing permitted +'1' - isolated writing disabled + [1:1] + read-only + + + ILLEGAL_HVOP + Indicates a bulk, sector erase, program has been requested when axa=1 +'0' - no error +'1' - illegal HV operation error + [2:2] + read-only + + + TURBO_N + After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. +Used in the testchip boot only as an 'FM READY' flag. +'0' - turbo mode +'1' - normal mode + [3:3] + read-only + + + WR_EN_MON + FM_CTL.WR_EN bit after being synchronized in clk_r domain + [4:4] + read-only + + + IF_SEL_MON + FM_CTL.IF_SEL bit after being synchronized in clk_r domain + [5:5] + read-only + + + + + FM_ADDR + Flash macro address + 0x8 + 32 + read-write + 0x0 + 0x1FFFFFF + + + RA + Row address. + [15:0] + read-write + + + BA + Bank address. + [23:16] + read-write + + + AXA + Auxiliary address field: +'0': regular flash memory. +'1': supervisory flash memory. + [24:24] + read-write + + + + + GEOMETRY + Regular flash geometry + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: +'0': 1 Byte +'1': 2 Bytes +'2': 4 Bytes +... +'7': 128 Bytes + +The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. + [3:0] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2): +'0': 1 Byte +'1': 2 Bytes +'2': 4 Bytes +... +'15': 32768 Bytes + +The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. + [7:4] + read-only + + + ROW_COUNT + Number of rows (minus 1): +'0': 1 row +'1': 2 rows +'2': 3 rows +... +'65535': 65536 rows + [23:8] + read-only + + + BANK_COUNT + Number of banks (minus 1): +'0': 1 bank +'1': 2 banks +... +'255': 256 banks + [31:24] + read-only + + + + + GEOMETRY_SUPERVISORY + Supervisory flash geometry + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. + [3:0] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. + [7:4] + read-only + + + ROW_COUNT + Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT + [23:8] + read-only + + + BANK_COUNT + Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. + [31:24] + read-only + + + + + TIMER_CTL + Timer control + 0x14 + 32 + read-write + 0x4000000 + 0xE701FFFF + + + PERIOD + Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. + [15:0] + read-write + + + SCALE + Timer tick scale: +'0': 1 microsecond. +'1': 100 microseconds. + [16:16] + read-write + + + PUMP_CLOCK_SEL + Pump clock select: +'0': internal clock. +'1': external clock. + [24:24] + read-write + + + PRE_PROG + '1' during pre-program operation + [25:25] + read-write + + + PRE_PROG_CSL + '0' CSL lines driven by CSL_DAC +'1' CSL lines driven by VNEG_G + [26:26] + read-write + + + PUMP_EN + Pump enable: +'0': disabled +'1': enabled (also requires FM_CTL.IF_SEL to be '1', this additional restriction is required to prevent non intentional clearing of the FM). +SW sets this field to '1' to generate a single PE pulse. +HW clears this field when timer is expired. + [29:29] + read-write + + + ACLK_EN + ACLK enable (generates a single cycle pulse for the FM): +'0': disabled +'1': enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. + [30:30] + read-write + + + TIMER_EN + Timer enable: +'0': disabled +'1': enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. + [31:31] + read-write + + + + + ANA_CTL0 + Analog control 0 + 0x18 + 32 + read-write + 0x400 + 0x9000700 + + + CSLDAC + Trimming of common source line DAC. + [10:8] + read-write + + + VCC_SEL + Vcc select: +'0': 1.2 V : LP reset value +'1': 0.95 V: ULP reset value +Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field. + [24:24] + read-write + + + FLIP_AMUXBUS_AB + Flips amuxbusa and amuxbusb +'0': amuxbusa, amuxbusb +'1': amuxbusb, amuxbusb + [27:27] + read-write + + + + + ANA_CTL1 + Analog control 1 + 0x1C + 32 + read-write + 0x6060000 + 0x7F0F00FF + + + MDAC + Trimming of the output margin Voltage as a function of Vpos and Vneg. + [7:0] + read-write + + + PDAC + Trimming of positive pump output Voltage: + [19:16] + read-write + + + NDAC + Trimming of negative pump output Voltage: + [27:24] + read-write + + + VPROT_OVERRIDE + '0': vprot = BG.vprot. + '1': vprot = vcc + [28:28] + read-write + + + R_GRANT_CTL + r_grant control: +'0': r_grant normal functionality +'1': forces r_grant LO synchronized on clk_r + [29:29] + read-write + + + RST_SFT_HVPL + '1': Page Latches Soft Reset + [30:30] + read-write + + + + + GEOMETRY_GEN + N/A, DNU + 0x20 + 32 + read-only + 0x0 + 0xE + + + DNU_0X20_1 + N/A + [1:1] + read-only + + + DNU_0X20_2 + N/A + [2:2] + read-only + + + DNU_0X20_3 + N/A + [3:3] + read-only + + + + + TEST_CTL + Test mode control + 0x24 + 32 + read-write + 0x0 + 0x80070F1F + + + TEST_MODE + Test mode control: +'0'-'31': TBD + [4:0] + read-write + + + PN_CTL + Positive/negative margin mode control: +'0': negative margin control +'1': positive margin control + [8:8] + read-write + + + TM_PE + PUMP_EN override: Pump Enable =PUMP_EN | PE_TM + [9:9] + read-write + + + TM_DISPOS + Test mode positive pump disable + [10:10] + read-write + + + TM_DISNEG + Test mode negative pump disable + [11:11] + read-write + + + EN_CLK_MON + 1: enables the oscillator output monitor + [16:16] + read-write + + + CSL_DEBUG + Engineering Debug Register + [17:17] + read-write + + + ENABLE_OSC + 0': the oscillator enable logic has control over the internal oscillator +'1': forces oscillator enable HI + [18:18] + read-write + + + UNSCRAMBLE_WA + See BSN-242 memo +'0': normal +'1': disables the Word Address scrambling + [31:31] + read-write + + + + + WAIT_CTL + Wiat State control + 0x28 + 32 + read-write + 0x30B09 + 0x70F0F + + + WAIT_FM_MEM_RD + Number of C interface wait cycles (on 'clk_c') for a read from the memory + [3:0] + read-write + + + WAIT_FM_HV_RD + Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. +Common for reading HV Page Latches and the DATA_COMP_RESULT bit + [11:8] + read-write + + + WAIT_FM_HV_WR + Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. + [18:16] + read-write + + + + + MONITOR_STATUS + Monitor Status + 0x2C + 32 + read-only + 0x4 + 0x6 + + + POS_PUMP_VLO + POS pump VLO + [1:1] + read-only + + + NEG_PUMP_VHI + NEG pump VHI + [2:2] + read-only + + + + + SCRATCH_CTL + Scratch Control + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DUMMY32 + Scratchpad register fields. Provided for test purposes. + [31:0] + read-write + + + + + HV_CTL + High voltage control + 0x34 + 32 + read-write + 0x32 + 0xFF + + + TIMER_CLOCK_FREQ + Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macro. E.g., if '4', the timer clock 'clk_t' has a frequency of 4 MHz. + [7:0] + read-write + + + + + ACLK_CTL + Aclk control + 0x38 + 32 + write-only + 0x0 + 0x1 + + + ACLK_GEN + A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1'). + [0:0] + write-only + + + + + INTR + Interrupt + 0x3C + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x40 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x44 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x48 + 32 + read-only + 0x0 + 0x1 + + + TIMER_EXPIRED + Logical and of corresponding request and mask fields. + [0:0] + read-only + + + + + FM_HV_DATA_ALL + Flash macro high Voltage page latches data (for all page latches) + 0x4C + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Write all high Voltage page latches with the same 32-bit data in a single write cycle + [31:0] + write-only + + + + + CAL_CTL0 + Cal control BG LO trim bits + 0x50 + 32 + read-write + 0x88F8F + 0xFFFFF + + + VCT_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_LO_HV + LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_LO_HV + LO Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control + [15:13] + read-write + + + IPREF_TRIM_LO_HV + LO Bandgap IPTAT trim control. + [19:16] + read-write + + + + + CAL_CTL1 + Cal control BG HI trim bits + 0x54 + 32 + read-write + 0x88F8F + 0xFFFFF + + + VCT_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_HI_HV + HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_HI_HV + HI Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [15:13] + read-write + + + IPREF_TRIM_HI_HV + HI Bandgap IPTAT trim control. + [19:16] + read-write + + + + + CAL_CTL2 + Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext + 0x58 + 32 + read-write + 0x7070 + 0xFFFFF + + + ICREF_TRIM_LO_HV + LO Bandgap Current trim control. + [4:0] + read-write + + + ICREF_TC_TRIM_LO_HV + LO Bandgap Current Temperature Compensation trim control + [7:5] + read-write + + + ICREF_TRIM_HI_HV + HI Bandgap Current trim control. + [12:8] + read-write + + + ICREF_TC_TRIM_HI_HV + HI Bandgap Current Temperature Compensation trim control. + [15:13] + read-write + + + VREF_SEL_HV + Voltage reference: +'0': internal bandgap reference +'1': external voltage reference + [16:16] + read-write + + + IREF_SEL_HV + Current reference: +'0': internal current reference +'1': external current reference + [17:17] + read-write + + + FM_ACTIVE_HV + 0: No Action +1: Forces FM SYS in active mode + [18:18] + read-write + + + TURBO_EXT_HV + 0: turbo signal generated internally +1: turbo cleared by clk_pump_ext HI + [19:19] + read-write + + + + + CAL_CTL3 + Cal control osc trim bits, idac, sdac, itim, bdac. + 0x5C + 32 + read-write + 0xA504 + 0xFFFFF + + + OSC_TRIM_HV + Flash macro pump clock trim control. + [3:0] + read-write + + + OSC_RANGE_TRIM_HV + 0: Oscillator High Frequency Range +1: Oscillator Low Frequency range + [4:4] + read-write + + + IDAC_HV + N/A + [8:5] + read-write + + + SDAC_HV + N/A + [10:9] + read-write + + + ITIM_HV + Trimming of timing current + [14:11] + read-write + + + VDDHI_HV + 0': vdd<2.3V +'1': vdd>=2.3V + [15:15] + read-write + + + TURBO_PULSEW_HV + Turbo pulse width trim + [17:16] + read-write + + + BGLO_EN_HV + LO Bandgap Enable + [18:18] + read-write + + + BGHI_EN_HV + HI Bandgap Enable + [19:19] + read-write + + + + + BOOKMARK + Bookmark register - keeps the current FW HV seq + 0x60 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + BOOKMARK + Used by FW. Keeps the Current HV cycle sequence + [31:0] + write-only + + + + + RED_CTL01 + Redundancy Control normal sectors 0,1 + 0x80 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_0 + Bad Row Pair Address for Sector 0 + [7:0] + read-write + + + RED_EN_0 + '1': Redundancy Enable for Sector 0 + [8:8] + read-write + + + RED_ADDR_1 + Bad Row Pair Address for Sector 1 + [23:16] + read-write + + + RED_EN_1 + '1': Redundancy Enable for Sector 1 + [24:24] + read-write + + + + + RED_CTL23 + Redundancy Controll normal sectors 2,3 + 0x84 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_2 + Bad Row Pair Address for Sector 2 + [7:0] + read-write + + + RED_EN_2 + 1': Redundancy Enable for Sector 2 + [8:8] + read-write + + + RED_ADDR_3 + Bad Row Pair Address for Sector 3 + [23:16] + read-write + + + RED_EN_3 + 1': Redundancy Enable for Sector 3 + [24:24] + read-write + + + + + RED_CTL45 + Redundancy Controll normal sectors 4,5 + 0x88 + 32 + read-write + 0x0 + 0xFF01FF + + + DNU_45_1 + Not Used + [0:0] + read-write + + + REG_ACT_HV + Forces the VBST regulator in active mode all the time + [1:1] + read-write + + + DNU_45_3 + Not Used + [2:2] + read-write + + + FDIV_TRIM_HV_0 + '2b00' F = 1MHz see fdiv_trim_hv<1> value as well +'2b01' F = 0.5MHz +'2b10' F = 2MHz +'2b11' F = 4Mhz + [3:3] + read-write + + + DNU_45_5 + Not Used + [4:4] + read-write + + + FDIV_TRIM_HV_1 + '2b00' F = 1MHz see fdiv_trim_hv<0> value as well +'2b01' F = 0.5MHz +'2b10' F = 2MHz +'2b11' F = 4Mhz + [5:5] + read-write + + + DNU_45_6 + Not Used + [6:6] + read-write + + + VLIM_TRIM_HV_0 + '2b00' V2 = 650mV see vlim_trim_hv<1> value as well +'2b01' V2 = 600mV +'2b10' V2 = 750mV +'2b11' V2 = 700mV + [7:7] + read-write + + + DNU_45_8 + Not Used + [8:8] + read-write + + + DNU_45_23_16 + Not Used + [23:16] + read-write + + + + + RED_CTL67 + Redundancy Controll normal sectors 6,7 + 0x8C + 32 + read-write + 0x0 + 0xFF01FF + + + VLIM_TRIM_HV_1 + '2b00' V2 = 650mV see vlim_trim_hv<0> value as well +'2b01' V2 = 600mV +'2b10' V2 = 750mV +'2b11' V2 = 700mV + [0:0] + read-write + + + DNU_67_1 + Not Used + [1:1] + read-write + + + VPROT_ACT_HV + Forces VPROT in active mode all the time + [2:2] + read-write + + + DNU_67_3 + Not Used + [3:3] + read-write + + + IPREF_TC_HV + Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA + [4:4] + read-write + + + DNU_67_5 + Not Used + [5:5] + read-write + + + IPREF_TRIMA_HI_HV + Adds 200-300nA boost on IPREF_HI + [6:6] + read-write + + + DNU_67_7 + Not Used + [7:7] + read-write + + + IPREF_TRIMA_LO_HV + Adds 200-300nA boost on IPREF_LO + [8:8] + read-write + + + DNU_67_23_16 + Not Used + [23:16] + read-write + + + + + RED_CTL_SM01 + Redundancy Controll special sectors 0,1 + 0x90 + 32 + read-write + 0x0 + 0xC1FF01FF + + + RED_ADDR_SM0 + Bad Row Pair Address for Special Sector 0 + [7:0] + read-write + + + RED_EN_SM0 + Redundancy Enable for Special Sector 0 + [8:8] + read-write + + + RED_ADDR_SM1 + Bad Row Pair Address for Special Sector 1 + [23:16] + read-write + + + RED_EN_SM1 + Redundancy Enable for Special Sector 1 + [24:24] + read-write + + + TRKD + Sense Amp Control tracking delay + [30:30] + read-write + + + R_GRANT_EN + '0': r_grant handshake disabled, r_grant always 1. + '1': r_grand handshake enabled + [31:31] + read-write + + + + + 32 + 4 + TM_CMPR[%s] + Do Not Use + 0x100 + 32 + read-only + 0x0 + 0x1 + + + DATA_COMP_RESULT + The result of a comparison between the flash macro data output and the content of the high voltage page latches. +The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. +The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. +'0': FALSE (not equal) + +'1': TRUE (equal) + [0:0] + read-only + + + + + 256 + 4 + FM_HV_DATA[%s] + Flash macro high Voltage page latches data + 0x800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). + +Note: the high Voltage page latches are readable for test mode functionality. + [31:0] + read-write + + + + + 256 + 4 + FM_MEM_DATA[%s] + Flash macro memory sense amplifier and column decoder data + 0xC00 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: +- IF_SEL is '0': data as specified by the R interface address +- IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. + [31:0] + read-only + + + + + + + + SRSS + SRSS Core Registers + 0x40260000 + + 0 + 65536 + registers + + + + PWR_CTL + Power Mode Control + 0x0 + 32 + read-write + 0x0 + 0xFFFC0033 + + + POWER_MODE + Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. + [1:0] + read-only + + + RESET + System is resetting. + 0 + + + ACTIVE + At least one CPU is running. + 1 + + + SLEEP + No CPUs are running. Peripherals may be running. + 2 + + + DEEPSLEEP + Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. + 3 + + + + + DEBUG_SESSION + Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) + [4:4] + read-only + + + NO_SESSION + No debug session active + 0 + + + SESSION_ACTIVE + Debug session is active. Power modes behave differently to keep the debug session active. + 1 + + + + + LPM_READY + Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. +1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. + [5:5] + read-only + + + IREF_LPMODE + Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. +1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. + [18:18] + read-write + + + VREFBUF_OK + Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. + [19:19] + read-only + + + DPSLP_REG_DIS + Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: DeepSleep Regulator is on. +1: DeepSleep Regulator is off. + [20:20] + read-write + + + RET_REG_DIS + Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Retention Regulator is on. +1: Retention Regulator is off. + [21:21] + read-write + + + NWELL_REG_DIS + Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Nwell Regulator is on. +1: Nwell Regulator is off. + [22:22] + read-write + + + LINREG_DIS + Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear regulator is on. +1: Linear regulator is off. + [23:23] + read-write + + + LINREG_LPMODE + Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. +1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. + [24:24] + read-write + + + PORBOD_LPMODE + Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [25:25] + read-write + + + BGREF_LPMODE + Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0. + [26:26] + read-write + + + PLL_LS_BYPASS + Bypass level shifter inside the PLL. +0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. +1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. + [27:27] + read-write + + + VREFBUF_LPMODE + Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. +0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/HIBERNATE. +1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [28:28] + read-write + + + VREFBUF_DIS + Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. + [29:29] + read-write + + + ACT_REF_DIS + Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Reference is enabled +1: Active Reference is disabled + [30:30] + read-write + + + ACT_REF_OK + Indicates that the normal mode of the Active Reference is ready. + [31:31] + read-only + + + + + PWR_HIBERNATE + HIBERNATE Mode Register + 0x4 + 32 + read-write + 0x0 + 0xCFFEFFFF + + + TOKEN + Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. + [7:0] + read-write + + + UNLOCK + This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. + [15:8] + read-write + + + FREEZE + Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. + [17:17] + read-write + + + MASK_HIBALARM + When set, HIBERNATE will wakeup for a RTC interrupt + [18:18] + read-write + + + MASK_HIBWDT + When set, HIBERNATE will wakeup if WDT matches + [19:19] + read-write + + + POLARITY_HIBPIN + Each bit sets the active polarity of the corresponding wakeup pin. +0: Pin input of 0 will wakeup the part from HIBERNATE +1: Pin input of 1 will wakeup the part from HIBERNATE + [23:20] + read-write + + + MASK_HIBPIN + When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. + [27:24] + read-write + + + HIBERNATE_DISABLE + Hibernate disable bit. +0: Normal operation, HIBERNATE works as described +1: Further writes to this register are ignored +Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. + [30:30] + read-write + + + HIBERNATE + Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. + [31:31] + read-write + + + + + PWR_LVD_CTL + Low Voltage Detector (LVD) Configuration Register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + HVLVD1_TRIPSEL + Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. +0: rise=1.225V (nom), fall=1.2V (nom) +1: rise=1.425V (nom), fall=1.4V (nom) +2: rise=1.625V (nom), fall=1.6V (nom) +3: rise=1.825V (nom), fall=1.8V (nom) +4: rise=2.025V (nom), fall=2V (nom) +5: rise=2.125V (nom), fall=2.1V (nom) +6: rise=2.225V (nom), fall=2.2V (nom) +7: rise=2.325V (nom), fall=2.3V (nom) +8: rise=2.425V (nom), fall=2.4V (nom) +9: rise=2.525V (nom), fall=2.5V (nom) +10: rise=2.625V (nom), fall=2.6V (nom) +11: rise=2.725V (nom), fall=2.7V (nom) +12: rise=2.825V (nom), fall=2.8V (nom) +13: rise=2.925V (nom), fall=2.9V (nom) +14: rise=3.025V (nom), fall=3.0V (nom) +15: rise=3.125V (nom), fall=3.1V (nom) + [3:0] + read-write + + + HVLVD1_SRCSEL + Source selection for HVLVD1 + [6:4] + read-write + + + VDDD + Select VDDD + 0 + + + AMUXBUSA + Select AMUXBUSA (VDDD branch) + 1 + + + RSVD + N/A + 2 + + + VDDIO + N/A + 3 + + + AMUXBUSB + Select AMUXBUSB (VDDD branch) + 4 + + + + + HVLVD1_EN + Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. + [7:7] + read-write + + + + + PWR_BUCK_CTL + Buck Control Register + 0x14 + 32 + read-write + 0x5 + 0xC0000007 + + + BUCK_OUT1_SEL + Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 0.85V +1: 0.875V +2: 0.90V +3: 0.95V +4: 1.05V +5: 1.10V +6: 1.15V +7: 1.20V + [2:0] + read-write + + + BUCK_EN + Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. + [30:30] + read-write + + + BUCK_OUT1_EN + Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. TRM must follow the SAS. + [31:31] + read-write + + + + + PWR_BUCK_CTL2 + Buck Control Register 2 + 0x18 + 32 + read-write + 0x0 + 0xC0000007 + + + BUCK_OUT2_SEL + Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 1.15V +1: 1.20V +2: 1.25V +3: 1.30V +4: 1.35V +5: 1.40V +6: 1.45V +7: 1.50V + [2:0] + read-write + + + BUCK_OUT2_HW_SEL + Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. + [30:30] + read-write + + + BUCK_OUT2_EN + Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. + [31:31] + read-write + + + + + PWR_LVD_STATUS + Low Voltage Detector (LVD) Status Register + 0x1C + 32 + read-only + 0x0 + 0x1 + + + HVLVD1_OK + HVLVD1 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + 16 + 4 + PWR_HIB_DATA[%s] + HIBERNATE Data Register + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HIB_DATA + Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. + [31:0] + read-write + + + + + WDT_CTL + Watchdog Counter Control Register + 0x180 + 32 + read-write + 0xC0000001 + 0xC0000001 + + + WDT_EN + Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. + [0:0] + read-write + + + WDT_LOCK + Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. +Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + WDT_CNT + Watchdog Counter Count Register + 0x184 + 32 + read-write + 0x0 + 0xFFFF + + + COUNTER + Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. + [15:0] + read-write + + + + + WDT_MATCH + Watchdog Counter Match Register + 0x188 + 32 + read-write + 0x1000 + 0xFFFFF + + + MATCH + Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). + [15:0] + read-write + + + IGNORE_BITS + The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. + [19:16] + read-write + + + + + 2 + 64 + MCWDT_STRUCT[%s] + Multi-Counter Watchdog Timer + MCWDT_STRUCT + 0x00000200 + + MCWDT_CNTLOW + Multi-Counter Watchdog Sub-counters 0/1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR0 + Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. + [15:0] + read-write + + + WDT_CTR1 + Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:16] + read-write + + + + + MCWDT_CNTHIGH + Multi-Counter Watchdog Sub-counter 2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR2 + Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:0] + read-write + + + + + MCWDT_MATCH + Multi-Counter Watchdog Counter Match Register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_MATCH0 + Match value for sub-counter 0 of this MCWDT + [15:0] + read-write + + + WDT_MATCH1 + Match value for sub-counter 1 of this MCWDT + [31:16] + read-write + + + + + MCWDT_CONFIG + Multi-Counter Watchdog Counter Configuration + 0x10 + 32 + read-write + 0x0 + 0x1F010F0F + + + WDT_MODE0 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). + [1:0] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR0 + Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. + [2:2] + read-write + + + WDT_CASCADE0_1 + Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. +0: Independent counters +1: Cascaded counters + [3:3] + read-write + + + WDT_MODE1 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). + [9:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR1 + Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. + [10:10] + read-write + + + WDT_CASCADE1_2 + Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. +0: Independent counters +1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. + [11:11] + read-write + + + WDT_MODE2 + Watchdog Counter 2 Mode. + [16:16] + read-write + + + NOTHING + Free running counter with no interrupt requests + 0 + + + INT + Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). + 1 + + + + + WDT_BITS2 + Bit to observe for WDT_INT2: +0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) +... +31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) + [28:24] + read-write + + + + + MCWDT_CTL + Multi-Counter Watchdog Counter Control + 0x14 + 32 + read-write + 0x0 + 0xB0B0B + + + WDT_ENABLE0 + Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [0:0] + read-write + + + WDT_ENABLED0 + Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. + [1:1] + read-only + + + WDT_RESET0 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [3:3] + read-write + + + WDT_ENABLE1 + Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [8:8] + read-write + + + WDT_ENABLED1 + Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. + [9:9] + read-only + + + WDT_RESET1 + Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [11:11] + read-write + + + WDT_ENABLE2 + Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [16:16] + read-write + + + WDT_ENABLED2 + Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. + [17:17] + read-only + + + WDT_RESET2 + Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [19:19] + read-write + + + + + MCWDT_INTR + Multi-Counter Watchdog Counter Interrupt Register + 0x18 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. + [0:0] + read-write + + + MCWDT_INT1 + MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. + [1:1] + read-write + + + MCWDT_INT2 + MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. + [2:2] + read-write + + + + + MCWDT_INTR_SET + Multi-Counter Watchdog Counter Interrupt Set Register + 0x1C + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Set interrupt for MCWDT_INT0 + [0:0] + read-write + + + MCWDT_INT1 + Set interrupt for MCWDT_INT1 + [1:1] + read-write + + + MCWDT_INT2 + Set interrupt for MCWDT_INT2 + [2:2] + read-write + + + + + MCWDT_INTR_MASK + Multi-Counter Watchdog Counter Interrupt Mask Register + 0x20 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Mask for sub-counter 0 + [0:0] + read-write + + + MCWDT_INT1 + Mask for sub-counter 1 + [1:1] + read-write + + + MCWDT_INT2 + Mask for sub-counter 2 + [2:2] + read-write + + + + + MCWDT_INTR_MASKED + Multi-Counter Watchdog Counter Interrupt Masked Register + 0x24 + 32 + read-only + 0x0 + 0x7 + + + MCWDT_INT0 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + MCWDT_INT1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + MCWDT_INT2 + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + MCWDT_LOCK + Multi-Counter Watchdog Counter Lock Register + 0x28 + 32 + read-write + 0x0 + 0xC0000000 + + + MCWDT_LOCK + Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + + 16 + 4 + CLK_DSI_SELECT[%s] + Clock DSI Select Register + 0x300 + 32 + read-write + 0x0 + 0x1F + + + DSI_MUX + Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. + [4:0] + read-write + + + DSI_OUT0 + DSI0 - dsi_out[0] + 0 + + + DSI_OUT1 + DSI1 - dsi_out[1] + 1 + + + DSI_OUT2 + DSI2 - dsi_out[2] + 2 + + + DSI_OUT3 + DSI3 - dsi_out[3] + 3 + + + DSI_OUT4 + DSI4 - dsi_out[4] + 4 + + + DSI_OUT5 + DSI5 - dsi_out[5] + 5 + + + DSI_OUT6 + DSI6 - dsi_out[6] + 6 + + + DSI_OUT7 + DSI7 - dsi_out[7] + 7 + + + DSI_OUT8 + DSI8 - dsi_out[8] + 8 + + + DSI_OUT9 + DSI9 - dsi_out[9] + 9 + + + DSI_OUT10 + DSI10 - dsi_out[10] + 10 + + + DSI_OUT11 + DSI11 - dsi_out[11] + 11 + + + DSI_OUT12 + DSI12 - dsi_out[12] + 12 + + + DSI_OUT13 + DSI13 - dsi_out[13] + 13 + + + DSI_OUT14 + DSI14 - dsi_out[14] + 14 + + + DSI_OUT15 + DSI15 - dsi_out[15] + 15 + + + ILO + ILO - Internal Low-speed Oscillator + 16 + + + WCO + WCO - Watch-Crystal Oscillator + 17 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock + 18 + + + PILO + PILO - Precision Internal Low-speed Oscillator + 19 + + + + + + + 16 + 4 + CLK_PATH_SELECT[%s] + Clock Path Select Register + 0x340 + 32 + read-write + 0x0 + 0x7 + + + PATH_MUX + Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + DSI_MUX + DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. + 4 + + + + + + + 16 + 4 + CLK_ROOT_SELECT[%s] + Clock Root Select Register + 0x380 + 32 + read-write + 0x0 + 0x8000003F + + + ROOT_MUX + Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [3:0] + read-write + + + PATH0 + Select PATH0 (can be configured for FLL) + 0 + + + PATH1 + Select PATH1 (can be configured for PLL0, if available in the product) + 1 + + + PATH2 + Select PATH2 (can be configured for PLL1, if available in the product) + 2 + + + PATH3 + Select PATH3 (can be configured for PLL2, if available in the product) + 3 + + + PATH4 + Select PATH4 (can be configured for PLL3, if available in the product) + 4 + + + PATH5 + Select PATH5 (can be configured for PLL4, if available in the product) + 5 + + + PATH6 + Select PATH6 (can be configured for PLL5, if available in the product) + 6 + + + PATH7 + Select PATH7 (can be configured for PLL6, if available in the product) + 7 + + + PATH8 + Select PATH8 (can be configured for PLL7, if available in the product) + 8 + + + PATH9 + Select PATH9 (can be configured for PLL8, if available in the product) + 9 + + + PATH10 + Select PATH10 (can be configured for PLL9, if available in the product) + 10 + + + PATH11 + Select PATH11 (can be configured for PLL10, if available in the product) + 11 + + + PATH12 + Select PATH12 (can be configured for PLL11, if available in the product) + 12 + + + PATH13 + Select PATH13 (can be configured for PLL12, if available in the product) + 13 + + + PATH14 + Select PATH14 (can be configured for PLL13, if available in the product) + 14 + + + PATH15 + Select PATH15 (can be configured for PLL14, if available in the product) + 15 + + + + + ROOT_DIV + Selects predivider value for this clock root and DSI input. + [5:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + + + ENABLE + Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. + [31:31] + read-write + + + + + CLK_SELECT + Clock selection register + 0x500 + 32 + read-write + 0x0 + 0xFF03 + + + LFCLK_SEL + Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. + [1:0] + read-write + + + ILO + ILO - Internal Low-speed Oscillator + 0 + + + WCO + WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). + 1 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock. Capability is product-specific + 2 + + + PILO + PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. + 3 + + + + + PUMP_SEL + Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. + [11:8] + read-write + + + PUMP_DIV + Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. + [14:12] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + + + PUMP_ENABLE + Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: +1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. +2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. +3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. + [15:15] + read-write + + + + + CLK_TIMER_CTL + Timer Clock Control Register + 0x504 + 32 + read-write + 0x70000 + 0x80FF0301 + + + TIMER_SEL + Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. + [0:0] + read-write + + + IMO + IMO - Internal Main Oscillator + 0 + + + HF0_DIV + Select the output of the predivider configured by TIMER_HF0_DIV. + 1 + + + + + TIMER_HF0_DIV + Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. + [9:8] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. + 0 + + + DIV_BY_2 + Divide HFCLK0 by 2. + 1 + + + DIV_BY_4 + Divide HFCLK0 by 4. + 2 + + + DIV_BY_8 + Divide HFCLK0 by 8. + 3 + + + + + TIMER_DIV + Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. + [23:16] + read-write + + + ENABLE + Enable for TIMERCLK. +0: TIMERCLK is off +1: TIMERCLK is enabled + [31:31] + read-write + + + + + CLK_ILO_CONFIG + ILO Configuration + 0x50C + 32 + read-write + 0x80000000 + 0x80000001 + + + ILO_BACKUP + If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. +0: ILO turns off at XRES/BOD event or HIBERNATE entry. +1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. + [0:0] + read-write + + + ENABLE + Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. + [31:31] + read-write + + + + + CLK_IMO_CONFIG + IMO Configuration + 0x510 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLE + Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0. + [31:31] + read-write + + + + + CLK_OUTPUT_FAST + Fast Clock Output Select Register + 0x514 + 32 + read-write + 0x0 + 0xFFF0FFF + + + FAST_SEL0 + Select signal for fast clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL0 + Selects the clock path chosen by PATH_SEL0 field + 5 + + + HFCLK_SEL0 + Selects the output of the HFCLK_SEL0 mux + 6 + + + SLOW_SEL0 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 + 7 + + + + + PATH_SEL0 + Selects a clock path to use in fast clock output #0 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [7:4] + read-write + + + HFCLK_SEL0 + Selects a HFCLK tree for use in fast clock output #0 + [11:8] + read-write + + + FAST_SEL1 + Select signal for fast clock output #1 + [19:16] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL1 + Selects the clock path chosen by PATH_SEL1 field + 5 + + + HFCLK_SEL1 + Selects the output of the HFCLK_SEL1 mux + 6 + + + SLOW_SEL1 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 + 7 + + + + + PATH_SEL1 + Selects a clock path to use in fast clock output #1 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [23:20] + read-write + + + HFCLK_SEL1 + Selects a HFCLK tree for use in fast clock output #1 logic + [27:24] + read-write + + + + + CLK_OUTPUT_SLOW + Slow Clock Output Select Register + 0x518 + 32 + read-write + 0x0 + 0xFF + + + SLOW_SEL0 + Select signal for slow clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + SLOW_SEL1 + Select signal for slow clock output #1 + [7:4] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + + + CLK_CAL_CNT1 + Clock Calibration Counter 1 + 0x51C + 32 + read-write + 0x80000000 + 0x80FFFFFF + + + CAL_COUNTER1 + Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. + [23:0] + read-write + + + CAL_COUNTER_DONE + Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up + [31:31] + read-only + + + + + CLK_CAL_CNT2 + Clock Calibration Counter 2 + 0x520 + 32 + read-only + 0x0 + 0xFFFFFF + + + CAL_COUNTER2 + Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) + [23:0] + read-only + + + + + CLK_ECO_CONFIG + ECO Configuration Register + 0x52C + 32 + read-write + 0x2 + 0x80000002 + + + AGC_EN + Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. + [1:1] + read-write + + + ECO_EN + Master enable for ECO oscillator. + [31:31] + read-write + + + + + CLK_ECO_STATUS + ECO Status Register + 0x530 + 32 + read-only + 0x0 + 0x3 + + + ECO_OK + Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. + [0:0] + read-only + + + ECO_READY + Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. + [1:1] + read-only + + + + + CLK_PILO_CONFIG + Precision ILO Configuration Register + 0x53C + 32 + read-write + 0x80 + 0xE00003FF + + + PILO_FFREQ + Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. + [9:0] + read-write + + + PILO_CLK_EN + Enable the PILO clock output. See PILO_EN field for required sequencing. + [29:29] + read-write + + + PILO_RESET_N + Reset the PILO. See PILO_EN field for required sequencing. + [30:30] + read-write + + + PILO_EN + Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. + [31:31] + read-write + + + + + CLK_FLL_CONFIG + FLL Configuration Register + 0x580 + 32 + read-write + 0x1000000 + 0x8103FFFF + + + FLL_MULT + Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). + +Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) + [17:0] + read-write + + + FLL_OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: no division +1: divide by 2 + [24:24] + read-write + + + FLL_ENABLE + Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. + +To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. + +To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. + +Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. + +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_CONFIG2 + FLL Configuration Register 2 + 0x584 + 32 + read-write + 0x20001 + 0x1FF1FFF + + + FLL_REF_DIV + Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +8191: divide by 8191 + [12:0] + read-write + + + LOCK_TOL + Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. +0: tolerate error of 1 count value +1: tolerate error of 2 count values +... +511: tolerate error of 512 count values + [24:16] + read-write + + + + + CLK_FLL_CONFIG3 + FLL Configuration Register 3 + 0x588 + 32 + read-write + 0x2800 + 0x301FFFFF + + + FLL_LF_IGAIN + FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [3:0] + read-write + + + FLL_LF_PGAIN + FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [7:4] + read-write + + + SETTLING_COUNT + Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. +0: no settling time +1: wait one reference clock cycle +... +8191: wait 8191 reference clock cycles + [20:8] + read-write + + + BYPASS_SEL + Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. + [29:28] + read-write + + + AUTO + N/A + 0 + + + AUTO1 + N/A + 1 + + + FLL_REF + Select FLL reference input (bypass mode). Ignores lock indicator + 2 + + + FLL_OUT + Select FLL output. Ignores lock indicator. + 3 + + + + + + + CLK_FLL_CONFIG4 + FLL Configuration Register 4 + 0x58C + 32 + read-write + 0xFF + 0xC1FF07FF + + + CCO_LIMIT + Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) + [7:0] + read-write + + + CCO_RANGE + Frequency range of CCO + [10:8] + read-write + + + RANGE0 + Target frequency is in range [48, 64) MHz + 0 + + + RANGE1 + Target frequency is in range [64, 85) MHz + 1 + + + RANGE2 + Target frequency is in range [85, 113) MHz + 2 + + + RANGE3 + Target frequency is in range [113, 150) MHz + 3 + + + RANGE4 + Target frequency is in range [150, 200] MHz + 4 + + + + + CCO_FREQ + CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. + [24:16] + read-write + + + CCO_HW_UPDATE_DIS + Disable CCO frequency update by FLL hardware +0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. +1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. + [30:30] + read-write + + + CCO_ENABLE + Enable the CCO. It is required to enable the CCO before using the FLL. +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_STATUS + FLL Status Register + 0x590 + 32 + read-write + 0x0 + 0x7 + + + LOCKED + FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. + [0:0] + read-only + + + UNLOCK_OCCURRED + N/A + [1:1] + read-write + + + CCO_READY + This indicates that the CCO is internally settled and ready to use. + [2:2] + read-only + + + + + 15 + 4 + CLK_PLL_CONFIG[%s] + PLL Configuration Register + 0x600 + 32 + read-write + 0x20116 + 0xB81F1F7F + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-21: illegal (undefined behavior) +22: divide by 22 +... +112: divide by 112 +>112: illegal (undefined behavior) + [6:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +20: divide by 20 +others: illegal (undefined behavior) + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + PLL_LF_MODE + VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. +0: VCO frequency is [200MHz, 400MHz] +1: VCO frequency is [170MHz, 200MHz) + [27:27] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. + 0 + + + AUTO1 + Same as AUTO + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. + +Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled +1: Block is enabled + [31:31] + read-write + + + + + 15 + 4 + CLK_PLL_STATUS[%s] + PLL Status Register + 0x640 + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + SRSS_INTR + SRSS Interrupt Register + 0x700 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. + [0:0] + read-write + + + HVLVD1 + Interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Clock calibration counter is done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_SET + SRSS Interrupt Set Register + 0x704 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Set interrupt for low voltage detector WDT_MATCH + [0:0] + read-write + + + HVLVD1 + Set interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_MASK + SRSS Interrupt Mask Register + 0x708 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. + [0:0] + read-write + + + HVLVD1 + Mask for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Mask for clock calibration done + [5:5] + read-write + + + + + SRSS_INTR_MASKED + SRSS Interrupt Masked Register + 0x70C + 32 + read-only + 0x0 + 0x23 + + + WDT_MATCH + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + HVLVD1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CLK_CAL + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + SRSS_INTR_CFG + SRSS Interrupt Configuration Register + 0x710 + 32 + read-write + 0x0 + 0x3 + + + HVLVD1_EDGE_SEL + Sets which edge(s) will trigger an IRQ for HVLVD1 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + + + RES_CAUSE + Reset Cause Observation Register + 0x800 + 32 + read-write + 0x0 + 0x1FF + + + RESET_WDT + A basic WatchDog Timer (WDT) reset has occurred since last power cycle. + [0:0] + read-write + + + RESET_ACT_FAULT + Fault logging system requested a reset from its Active logic. + [1:1] + read-write + + + RESET_DPSLP_FAULT + Fault logging system requested a reset from its DeepSleep logic. + [2:2] + read-write + + + RESET_CSV_WCO_LOSS + Clock supervision logic requested a reset due to loss of a watch-crystal clock. + [3:3] + read-write + + + RESET_SOFT + A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. + [4:4] + read-write + + + RESET_MCWDT0 + Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. + [5:5] + read-write + + + RESET_MCWDT1 + Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. + [6:6] + read-write + + + RESET_MCWDT2 + Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. + [7:7] + read-write + + + RESET_MCWDT3 + Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. + [8:8] + read-write + + + + + RES_CAUSE2 + Reset Cause Observation Register 2 + 0x804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESET_CSV_HF_LOSS + Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [15:0] + read-write + + + RESET_CSV_HF_FREQ + Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [31:16] + read-write + + + + + PWR_TRIM_REF_CTL + Reference Trim Register + 0x7F00 + 32 + read-write + 0x70F00000 + 0xF1FF5FFF + + + ACT_REF_TCTRIM + Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [3:0] + read-write + + + ACT_REF_ITRIM + Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [7:4] + read-write + + + ACT_REF_ABSTRIM + Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [12:8] + read-write + + + ACT_REF_IBOOST + Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: normal operation +others: risk mitigation + [14:14] + read-write + + + DPSLP_REF_TCTRIM + DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [19:16] + read-write + + + DPSLP_REF_ABSTRIM + DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [24:20] + read-write + + + DPSLP_REF_ITRIM + DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:28] + read-write + + + + + PWR_TRIM_BODOVP_CTL + BOD/OVP Trim Register + 0x7F04 + 32 + read-write + 0x40D04 + 0xFDFF7 + + + HVPORBOD_TRIPSEL + HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [2:0] + read-write + + + HVPORBOD_OFSTRIM + HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [6:4] + read-write + + + HVPORBOD_ITRIM + HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [9:7] + read-write + + + LVPORBOD_TRIPSEL + LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [12:10] + read-write + + + LVPORBOD_OFSTRIM + LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [16:14] + read-write + + + LVPORBOD_ITRIM + LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [19:17] + read-write + + + + + CLK_TRIM_CCO_CTL + CCO Trim Register + 0x7F08 + 32 + read-write + 0xA7000020 + 0xBF00003F + + + CCO_RCSTRIM + CCO reference current source trim. + [5:0] + read-write + + + CCO_STABLE_CNT + Terminal count for the stabilization counter from CCO_ENABLE until stable. + [29:24] + read-write + + + ENABLE_CNT + Enables the automatic stabilization counter. + [31:31] + read-write + + + + + CLK_TRIM_CCO_CTL2 + CCO Trim Register 2 + 0x7F0C + 32 + read-write + 0x884110 + 0x1FFFFFF + + + CCO_FCTRIM1 + CCO frequency 1st range calibration + [4:0] + read-write + + + CCO_FCTRIM2 + CCO frequency 2nd range calibration + [9:5] + read-write + + + CCO_FCTRIM3 + CCO frequency 3rd range calibration + [14:10] + read-write + + + CCO_FCTRIM4 + CCO frequency 4th range calibration + [19:15] + read-write + + + CCO_FCTRIM5 + CCO frequency 5th range calibration + [24:20] + read-write + + + + + PWR_TRIM_WAKE_CTL + Wakeup Trim Register + 0x7F30 + 32 + read-write + 0x0 + 0xFF + + + WAKE_DELAY + Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. + [7:0] + read-write + + + + + PWR_TRIM_LVD_CTL + LVD Trim Register + 0xFF10 + 32 + read-write + 0x20 + 0x77 + + + HVLVD1_OFSTRIM + HVLVD1 offset trim + [2:0] + read-write + + + HVLVD1_ITRIM + HVLVD1 current trim + [6:4] + read-write + + + + + CLK_TRIM_ILO_CTL + ILO Trim Register + 0xFF18 + 32 + read-write + 0x2C + 0x3F + + + ILO_FTRIM + ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + + + PWR_TRIM_PWRSYS_CTL + Power System Trim Register + 0xFF1C + 32 + read-write + 0x17 + 0x1F + + + ACT_REG_TRIM + Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively. + [4:0] + read-write + + + ACT_REG_BOOST + Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: +2'b00: 50uA +2'b01: 100uA +2'b10: 150uA +2'b11: 200uA + +The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. +50mA chip: 2'b00 (default); +100mA chip: 2'b00 (default); +150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); +200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); +250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); +300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); + +This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:30] + read-write + + + + + CLK_TRIM_ECO_CTL + ECO Trim Register + 0xFF20 + 32 + read-write + 0x1F0003 + 0x3F3FF7 + + + WDTRIM + Watch Dog Trim - Delta voltage below steady state level +0x0 - 50mV +0x1 - 75mV +0x2 - 100mV +0x3 - 125mV +0x4 - 150mV +0x5 - 175mV +0x6 - 200mV +0x7 - 225mV + [2:0] + read-write + + + ATRIM + Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. +0x0 - 150mV +0x1 - 175mV +0x2 - 200mV +0x3 - 225mV +0x4 - 250mV +0x5 - 275mV +0x6 - 300mV +0x7 - 325mV +0x8 - 350mV +0x9 - 375mV +0xA - 400mV +0xB - 425mV +0xC - 450mV +0xD - 475mV +0xE - 500mV +0xF - 525mV + [7:4] + read-write + + + FTRIM + Filter Trim - 3rd harmonic oscillation + [9:8] + read-write + + + RTRIM + Feedback resistor Trim + [11:10] + read-write + + + GTRIM + Gain Trim - Startup time + [13:12] + read-write + + + ITRIM + Current Trim + [21:16] + read-write + + + + + CLK_TRIM_PILO_CTL + PILO Trim Register + 0xFF24 + 32 + read-write + 0x108500F + 0x7DFF703F + + + PILO_CFREQ + Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. + [5:0] + read-write + + + PILO_OSC_TRIM + Trim for current in oscillator block. + [14:12] + read-write + + + PILO_COMP_TRIM + Trim for comparator bias current. + [17:16] + read-write + + + PILO_NBIAS_TRIM + Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier + [19:18] + read-write + + + PILO_RES_TRIM + Trim for beta-multiplier branch current + [24:20] + read-write + + + PILO_ISLOPE_TRIM + Trim for beta-multiplier current slope + [27:26] + read-write + + + PILO_VTDIFF_TRIM + Trim for VT-DIFF output (internal power supply) + [30:28] + read-write + + + + + CLK_TRIM_PILO_CTL2 + PILO Trim Register 2 + 0xFF28 + 32 + read-write + 0xDA10E0 + 0xFF1FFF + + + PILO_VREF_TRIM + Trim for voltage reference + [7:0] + read-write + + + PILO_IREFBM_TRIM + Trim for beta-multiplier current reference + [12:8] + read-write + + + PILO_IREF_TRIM + Trim for current reference + [23:16] + read-write + + + + + CLK_TRIM_PILO_CTL3 + PILO Trim Register 3 + 0xFF2C + 32 + read-write + 0x4800 + 0xFFFF + + + PILO_ENGOPT + Engineering options for PILO circuits +0: Short vdda to vpwr +1: Beta:mult current change +2: Iref generation Ptat current addition +3: Disable current path in secondary Beta:mult startup circuit +4: Double oscillator current +5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block +6: Spare +7: Ptat component increase in Iref +8: vpwr_rc and vpwr_dig_rc shorting testmode +9: Switch b/w psub connection for cascode nfet for vref generation +10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. +15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. + [15:0] + read-write + + + + + + + BACKUP + SRSS Backup Domain + 0x40270000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFF0F3308 + + + WCO_EN + Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. +After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. + [3:3] + read-write + + + CLK_SEL + Clock select for BAK clock + [9:8] + read-write + + + WCO + Watch-crystal oscillator input. + 0 + + + ALTBAK + This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. + 1 + + + + + PRESCALER + N/A + [13:12] + read-write + + + WCO_BYPASS + Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. +0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. +1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. + [16:16] + read-write + + + VDDBAK_CTL + Controls the behavior of the switch that generates vddbak from vbackup or vddd. +0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. +1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. + [18:17] + read-write + + + VBACKUP_MEAS + Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. + [19:19] + read-write + + + EN_CHARGE_KEY + When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. + [31:24] + read-write + + + + + RTC_RW + RTC Read Write register + 0x8 + 32 + read-write + 0x0 + 0x3 + + + READ + Read bit +When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. +Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. + [0:0] + read-write + + + WRITE + Write bit +Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. +The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. +Only user RTC registers that were written to will get copied, others will not be affected. +When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). +When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. +Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. + [1:1] + read-write + + + + + CAL_CTL + Oscillator calibration for absolute frequency + 0xC + 32 + read-write + 0x0 + 0x8000007F + + + CALIB_VAL + Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). +Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) + +Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. + [5:0] + read-write + + + CALIB_SIGN + Calibration sign: +0= Negative sign: remove pulses (it takes more clock ticks to count one second) +1= Positive sign: add pulses (it takes less clock ticks to count one second) + [6:6] + read-write + + + CAL_OUT + Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. + [31:31] + read-write + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x0 + 0x5 + + + RTC_BUSY + pending RTC write + [0:0] + read-only + + + WCO_OK + Indicates that output has transitioned. + [2:2] + read-only + + + + + RTC_TIME + Calendar Seconds, Minutes, Hours, Day of Week + 0x14 + 32 + read-write + 0x0 + 0x77F7F7F + + + RTC_SEC + Calendar seconds in BCD, 0-59 + [6:0] + read-write + + + RTC_MIN + Calendar minutes in BCD, 0-59 + [14:8] + read-write + + + RTC_HOUR + Calendar hours in BCD, value depending on 12/24HR mode +0=24HR: [21:16]=0-23 +1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 + [21:16] + read-write + + + CTRL_12HR + Select 12/24HR mode: 1=12HR, 0=24HR + [22:22] + read-write + + + RTC_DAY + Calendar Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + + + RTC_DATE + Calendar Day of Month, Month, Year + 0x18 + 32 + read-write + 0x0 + 0xFF1F3F + + + RTC_DATE + Calendar Day of the Month in BCD, 1-31 +Automatic Leap Year Correction + [5:0] + read-write + + + RTC_MON + Calendar Month in BCD, 1-12 + [12:8] + read-write + + + RTC_YEAR + Calendar year in BCD, 0-99 + [23:16] + read-write + + + + + ALM1_TIME + Alarm 1 Seconds, Minute, Hours, Day of Week + 0x1C + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM1_DATE + Alarm 1 Day of Month, Month + 0x20 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 1. +0: Alarm 1 is disabled. Fields for date and time are ignored. +1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + ALM2_TIME + Alarm 2 Seconds, Minute, Hours, Day of Week + 0x24 + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM2_DATE + Alarm 2 Day of Month, Month + 0x28 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 2. +0: Alarm 2 is disabled. Fields for date and time are ignored. +1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x2C + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Alarm 1 Interrupt + [0:0] + read-write + + + ALARM2 + Alarm 2 Interrupt + [1:1] + read-write + + + CENTURY + Century overflow interrupt + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x30 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x34 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x38 + 32 + read-only + 0x0 + 0x7 + + + ALARM1 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + ALARM2 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CENTURY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + OSCCNT + 32kHz oscillator counter + 0x3C + 32 + read-only + 0x0 + 0xFF + + + CNT32KHZ + 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. + [7:0] + read-only + + + + + TICKS + 128Hz tick counter + 0x40 + 32 + read-only + 0x0 + 0x3F + + + CNT128HZ + 128Hz counter (msb=2Hz) +When SECONDS is written this field will be reset. + [5:0] + read-only + + + + + PMIC_CTL + PMIC control register + 0x44 + 32 + read-write + 0xA0000000 + 0xE001FF00 + + + UNLOCK + This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. + [15:8] + read-write + + + POLARITY + N/A + [16:16] + read-write + + + PMIC_EN_OUTEN + Output enable for the output driver in the PMIC_EN pad. +0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present +1: Output pad is enabled for PMIC_EN pin. + [29:29] + read-write + + + PMIC_ALWAYSEN + Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. +0: Normal operation, PMIC_EN and PMIC_OUTEN work as described +1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. +Note: This bit is a write-once bit until the next backup reset. + [30:30] + read-write + + + PMIC_EN + Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. + [31:31] + read-write + + + + + RESET + Backup reset register + 0x48 + 32 + read-write + 0x0 + 0x80000000 + + + RESET + Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. + [31:31] + read-write + + + + + 64 + 4 + BREG[%s] + Backup register region + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BREG + Backup memory that contains application-specific data. Memory is retained on vbackup supply. + [31:0] + read-write + + + + + TRIM + Trim Register + 0xFF00 + 32 + read-write + 0x0 + 0x3F + + + TRIM + WCO trim + [5:0] + read-write + + + + + + + DW0 + Datawire Controller + DW + 0x40280000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80700000 + + + P + Active channel, user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + Active channel, secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + B + Active channel, non-bufferable/bufferable access control: +'0': non-bufferable +'1': bufferable. + [2:2] + read-only + + + PC + Active channel protection context. + [7:4] + read-only + + + CH_IDX + Active channel index. + [12:8] + read-only + + + PRIO + Active channel priority. + [17:16] + read-only + + + PREEMPTABLE + Active channel preemptable. + [18:18] + read-only + + + STATE + State of the DW controller. +'0': Default/inactive state. +'1': Loading descriptor. +'2': Loading data element from source location. +'3': Storing data element to destination location. +'4': Update of active control information (e.g. source and destination addresses). +'5': Wait for trigger de-activation. + [22:20] + read-only + + + ACTIVE + Active channel present: +'0': No. +'1': Yes. + [31:31] + read-only + + + + + PENDING + Pending channels + 0x8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CH_PENDING + Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). + [31:0] + read-only + + + + + STATUS_INTR + System interrupt control + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CH + Reflects the INTR.CH bit fields of all channels. + [31:0] + read-only + + + + + STATUS_INTR_MASKED + Status of interrupts masked + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CH + Reflects the INTR_MASKED.CH bit fields of all channels. + [31:0] + read-only + + + + + ACT_DESCR_CTL + Active descriptor control + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_CTL of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_SRC + Active descriptor source + 0x24 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_SRC of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_DST + Active descriptor destination + 0x28 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_DST of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_X_CTL + Active descriptor X loop control + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_X_CTL of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_Y_CTL + Active descriptor Y loop control + 0x34 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_Y_CTL of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_NEXT_PTR + Active descriptor next pointer + 0x38 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Copy of DESCR_NEXT_PTR of the currently active descriptor. + [31:2] + read-only + + + + + ACT_SRC + Active source + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SRC_ADDR + Current address of source location. + [31:0] + read-only + + + + + ACT_DST + Active destination + 0x44 + 32 + read-only + 0x0 + 0x0 + + + DST_ADDR + Current address of destination location. + [31:0] + read-only + + + + + 16 + 32 + CH_STRUCT[%s] + DW channel structure + 0x00000800 + + CH_CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x800700F7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). + [17:16] + read-write + + + PREEMPTABLE + Specifies if the channel is preemptable. +'0': Not preemptable. +'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. + [18:18] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). + [31:31] + read-write + + + + + CH_STATUS + Channel status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + INTR_CAUSE + Specifies the source of the interrupt cause: +'0': NO_INTR +'1': COMPLETION +'2': SRC_BUS_ERROR +'3': DST_BUS_ERROR +'4': SRC_MISAL +'5': DST_MISAL +'6': CURR_PTR_NULL +'7': ACTIVE_CH_DISABLED +'8': DESCR_BUS_ERROR +'9'-'15': Not used. + +For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). + [3:0] + read-only + + + + + CH_IDX + Channel current indices + 0x8 + 32 + read-write + 0x0 + 0x0 + + + X_IDX + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [7:0] + read-write + + + Y_IDX + Specifies the Y loop index, with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [15:8] + read-write + + + + + CH_CURR_PTR + Channel current descriptor pointer + 0xC + 32 + read-write + 0x0 + 0x0 + + + ADDR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. + [31:2] + read-write + + + + + INTR + Interrupt + 0x10 + 32 + read-write + 0x0 + 0x1 + + + CH + Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x14 + 32 + read-write + 0x0 + 0x1 + + + CH + Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x18 + 32 + read-write + 0x0 + 0x1 + + + CH + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x1C + 32 + read-only + 0x0 + 0x1 + + + CH + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + DW1 + 0x40281000 + + + EFUSE + EFUSE MXS40 registers + 0x402C0000 + + 0 + 128 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + + + CMD + Command + 0x10 + 32 + read-write + 0x1 + 0x800F1F71 + + + BIT_DATA + Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. + [0:0] + read-write + + + BIT_ADDR + Bit address. This field specifies a bit within a Byte. + [6:4] + read-write + + + BYTE_ADDR + Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). + [12:8] + read-write + + + MACRO_ADDR + Macro address. This field specifies an eFUSE macro. + [19:16] + read-write + + + START + FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. + +Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. + +Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. + +Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. + [31:31] + read-write + + + + + SEQ_DEFAULT + Sequencer Default value + 0x20 + 32 + read-write + 0x1D0000 + 0x7F0000 + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + + + SEQ_READ_CTL_0 + Sequencer read control 0 + 0x40 + 32 + read-write + 0x80560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_1 + Sequencer read control 1 + 0x44 + 32 + read-write + 0x540004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_2 + Sequencer read control 2 + 0x48 + 32 + read-write + 0x560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_3 + Sequencer read control 3 + 0x4C + 32 + read-write + 0x540003 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_4 + Sequencer read control 4 + 0x50 + 32 + read-write + 0x80150001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_5 + Sequencer read control 5 + 0x54 + 32 + read-write + 0x310004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_0 + Sequencer program control 0 + 0x60 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_1 + Sequencer program control 1 + 0x64 + 32 + read-write + 0x220020 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_2 + Sequencer program control 2 + 0x68 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_3 + Sequencer program control 3 + 0x6C + 32 + read-write + 0x310005 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_4 + Sequencer program control 4 + 0x70 + 32 + read-write + 0x80350006 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_5 + Sequencer program control 5 + 0x74 + 32 + read-write + 0x803D0019 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + + + PROFILE + Energy Profiler IP + 0x402D0000 + + 0 + 65536 + registers + + + + CTL + Profile control + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + WIN_MODE + Specifies the profiling time window mode: +'0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs. +In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped. +'1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect. + [0:0] + read-write + + + ENABLED + Enables the profiling block: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Profile status + 0x4 + 32 + read-only + 0x0 + 0x1 + + + WIN_ACTIVE + Indicates if the profiling time window is active. +'0': Not active. +'1': Active. + [0:0] + read-only + + + + + CMD + Profile command + 0x10 + 32 + read-write + 0x0 + 0x103 + + + START_TR + Software start trigger for the profiling time window. When written with '1', the profiling time window is started. +Can only be used in start / stop mode (PROFILE_WIN_MODE=0). +Has no effect in enable mode (PROFILE_WIN_MODE=1). + [0:0] + read-write + + + STOP_TR + Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped. +Can only be used in start / stop mode (PROFILE_WIN_MODE=0). +Has no effect in enable mode (PROFILE_WIN_MODE=1). + [1:1] + read-write + + + CLR_ALL_CNT + Counter clear. When written with '1', all profiling counter registers are cleared to 0x00. + [8:8] + read-write + + + + + INTR + Profile interrupt + 0x7C0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter. + +SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0'). + [31:0] + read-write + + + + + INTR_SET + Profile interrupt set + 0x7C4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register. + [31:0] + read-write + + + + + INTR_MASK + Profile interrupt mask + 0x7C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + Mask bit for corresponding field in the INTR register. + [31:0] + read-write + + + + + INTR_MASKED + Profile interrupt masked + 0x7CC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + Logical and of corresponding INTR and INTR_MASK fields. + [31:0] + read-only + + + + + 8 + 16 + CNT_STRUCT[%s] + Profile counter structure + 0x00000800 + + CTL + Profile counter configuration + 0x0 + 32 + read-write + 0x0 + 0x807F0071 + + + CNT_DURATION + This field specifies if events (edges) or a duration of the monitor signal is counted. +'0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. +'1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. + +Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results. + [0:0] + read-write + + + REF_CLK_SEL + This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0. + [6:4] + read-write + + + CLK_TIMER + Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL. + 0 + + + CLK_IMO + IMO - Internal Main Oscillator + 1 + + + CLK_ECO + ECO - External-Crystal Oscillator + 2 + + + CLK_LF + Low frequency clock (ILO, WCO or ALTLF). +Selection is done in SRSS register CLK_SELECT.LFCLK_SEL. + 3 + + + CLK_HF + High frequuency clock ('clk_hfx'). + 4 + + + CLK_PERI + Peripheral clock ('clk_peri'). + 5 + + + RSVD_6 + N/A + 6 + + + RSVD_7 + N/A + 7 + + + + + MON_SEL + This field specifies the montior input signal to be observed by the profiling counter. +The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details. + [22:16] + read-write + + + ENABLED + Enables the profiling counter: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CNT + Profile counter value + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT + This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter. + [31:0] + read-write + + + + + + + + HSIOM + High Speed IO Matrix (HSIOM) + 0x40310000 + + 0 + 16384 + registers + + + + 15 + 16 + PRT[%s] + HSIOM port registers + 0x00000000 + + PORT_SEL0 + Port selection 0 + 0x0 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO0_SEL + Selects connection for IO pin 0 route. + [4:0] + read-write + + + GPIO + GPIO controls 'out' + 0 + + + GPIO_DSI + GPIO controls 'out', DSI controls 'output enable' + 1 + + + DSI_DSI + DSI controls 'out' and 'output enable' + 2 + + + DSI_GPIO + DSI controls 'out', GPIO controls 'output enable' + 3 + + + AMUXA + Analog mux bus A + 4 + + + AMUXB + Analog mux bus B + 5 + + + AMUXA_DSI + Analog mux bus A, DSI control + 6 + + + AMUXB_DSI + Analog mux bus B, DSI control + 7 + + + ACT_0 + Active functionality 0 + 8 + + + ACT_1 + Active functionality 1 + 9 + + + ACT_2 + Active functionality 2 + 10 + + + ACT_3 + Active functionality 3 + 11 + + + DS_0 + DeepSleep functionality 0 + 12 + + + DS_1 + DeepSleep functionality 1 + 13 + + + DS_2 + DeepSleep functionality 2 + 14 + + + DS_3 + DeepSleep functionality 3 + 15 + + + ACT_4 + Active functionality 4 + 16 + + + ACT_5 + Active functionality 5 + 17 + + + ACT_6 + Active functionality 6 + 18 + + + ACT_7 + Active functionality 7 + 19 + + + ACT_8 + Active functionality 8 + 20 + + + ACT_9 + Active functionality 9 + 21 + + + ACT_10 + Active functionality 10 + 22 + + + ACT_11 + Active functionality 11 + 23 + + + ACT_12 + Active functionality 12 + 24 + + + ACT_13 + Active functionality 13 + 25 + + + ACT_14 + Active functionality 14 + 26 + + + ACT_15 + Active functionality 15 + 27 + + + DS_4 + DeepSleep functionality 4 + 28 + + + DS_5 + DeepSleep functionality 5 + 29 + + + DS_6 + DeepSleep functionality 6 + 30 + + + DS_7 + DeepSleep functionality 7 + 31 + + + + + IO1_SEL + Selects connection for IO pin 1 route. + [12:8] + read-write + + + IO2_SEL + Selects connection for IO pin 2 route. + [20:16] + read-write + + + IO3_SEL + Selects connection for IO pin 3 route. + [28:24] + read-write + + + + + PORT_SEL1 + Port selection 1 + 0x4 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO4_SEL + Selects connection for IO pin 4 route. +See PORT_SEL0 for connection details. + [4:0] + read-write + + + IO5_SEL + Selects connection for IO pin 5 route. + [12:8] + read-write + + + IO6_SEL + Selects connection for IO pin 6 route. + [20:16] + read-write + + + IO7_SEL + Selects connection for IO pin 7 route. + [28:24] + read-write + + + + + + 64 + 4 + AMUX_SPLIT_CTL[%s] + AMUX splitter cell control + 0x2000 + 32 + read-write + 0x0 + 0x77 + + + SWITCH_AA_SL + T-switch control for Left AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [0:0] + read-write + + + SWITCH_AA_SR + T-switch control for Right AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [1:1] + read-write + + + SWITCH_AA_S0 + T-switch control for AMUXBUSA vssa/ground switch: +'0': switch open. +'1': switch closed. + [2:2] + read-write + + + SWITCH_BB_SL + T-switch control for Left AMUXBUSB switch. + [4:4] + read-write + + + SWITCH_BB_SR + T-switch control for Right AMUXBUSB switch. + [5:5] + read-write + + + SWITCH_BB_S0 + T-switch control for AMUXBUSB vssa/ground switch. + [6:6] + read-write + + + + + + + GPIO + GPIO port control/configuration + 0x40320000 + + 0 + 65536 + registers + + + + 15 + 128 + PRT[%s] + GPIO port registers + 0x00000000 + + OUT + Port output data register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO output data for pin 0 +'0': Output state set to '0' +'1': Output state set to '1' + [0:0] + read-write + + + OUT1 + IO output data for pin 1 + [1:1] + read-write + + + OUT2 + IO output data for pin 2 + [2:2] + read-write + + + OUT3 + IO output data for pin 3 + [3:3] + read-write + + + OUT4 + IO output data for pin 4 + [4:4] + read-write + + + OUT5 + IO output data for pin 5 + [5:5] + read-write + + + OUT6 + IO output data for pin 6 + [6:6] + read-write + + + OUT7 + IO output data for pin 7 + [7:7] + read-write + + + + + OUT_CLR + Port output data clear register + 0x4 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO clear output for pin 0: +'0': Output state not affected. +'1': Output state set to '0'. + [0:0] + read-write + + + OUT1 + IO clear output for pin 1 + [1:1] + read-write + + + OUT2 + IO clear output for pin 2 + [2:2] + read-write + + + OUT3 + IO clear output for pin 3 + [3:3] + read-write + + + OUT4 + IO clear output for pin 4 + [4:4] + read-write + + + OUT5 + IO clear output for pin 5 + [5:5] + read-write + + + OUT6 + IO clear output for pin 6 + [6:6] + read-write + + + OUT7 + IO clear output for pin 7 + [7:7] + read-write + + + + + OUT_SET + Port output data set register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO set output for pin 0: +'0': Output state not affected. +'1': Output state set to '1'. + [0:0] + read-write + + + OUT1 + IO set output for pin 1 + [1:1] + read-write + + + OUT2 + IO set output for pin 2 + [2:2] + read-write + + + OUT3 + IO set output for pin 3 + [3:3] + read-write + + + OUT4 + IO set output for pin 4 + [4:4] + read-write + + + OUT5 + IO set output for pin 5 + [5:5] + read-write + + + OUT6 + IO set output for pin 6 + [6:6] + read-write + + + OUT7 + IO set output for pin 7 + [7:7] + read-write + + + + + OUT_INV + Port output data invert register + 0xC + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO invert output for pin 0: +'0': Output state not affected. +'1': Output state inverted ('0' => '1', '1' => '0'). + [0:0] + read-write + + + OUT1 + IO invert output for pin 1 + [1:1] + read-write + + + OUT2 + IO invert output for pin 2 + [2:2] + read-write + + + OUT3 + IO invert output for pin 3 + [3:3] + read-write + + + OUT4 + IO invert output for pin 4 + [4:4] + read-write + + + OUT5 + IO invert output for pin 5 + [5:5] + read-write + + + OUT6 + IO invert output for pin 6 + [6:6] + read-write + + + OUT7 + IO invert output for pin 7 + [7:7] + read-write + + + + + IN + Port input state register + 0x10 + 32 + read-only + 0x0 + 0x1FF + + + IN0 + IO pin state for pin 0 +'0': Low logic level present on pin. +'1': High logic level present on pin. +On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. + [0:0] + read-only + + + IN1 + IO pin state for pin 1 + [1:1] + read-only + + + IN2 + IO pin state for pin 2 + [2:2] + read-only + + + IN3 + IO pin state for pin 3 + [3:3] + read-only + + + IN4 + IO pin state for pin 4 + [4:4] + read-only + + + IN5 + IO pin state for pin 5 + [5:5] + read-only + + + IN6 + IO pin state for pin 6 + [6:6] + read-only + + + IN7 + IO pin state for pin 7 + [7:7] + read-only + + + FLT_IN + Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. + [8:8] + read-only + + + + + INTR + Port interrupt status register + 0x14 + 32 + read-write + 0x0 + 0x1FF01FF + + + EDGE0 + Edge detect for IO pin 0 +'0': No edge was detected on pin. +'1': An edge was detected on pin. + [0:0] + read-write + + + EDGE1 + Edge detect for IO pin 1 + [1:1] + read-write + + + EDGE2 + Edge detect for IO pin 2 + [2:2] + read-write + + + EDGE3 + Edge detect for IO pin 3 + [3:3] + read-write + + + EDGE4 + Edge detect for IO pin 4 + [4:4] + read-write + + + EDGE5 + Edge detect for IO pin 5 + [5:5] + read-write + + + EDGE6 + Edge detect for IO pin 6 + [6:6] + read-write + + + EDGE7 + Edge detect for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Edge detected on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + IN_IN0 + IO pin state for pin 0 + [16:16] + read-only + + + IN_IN1 + IO pin state for pin 1 + [17:17] + read-only + + + IN_IN2 + IO pin state for pin 2 + [18:18] + read-only + + + IN_IN3 + IO pin state for pin 3 + [19:19] + read-only + + + IN_IN4 + IO pin state for pin 4 + [20:20] + read-only + + + IN_IN5 + IO pin state for pin 5 + [21:21] + read-only + + + IN_IN6 + IO pin state for pin 6 + [22:22] + read-only + + + IN_IN7 + IO pin state for pin 7 + [23:23] + read-only + + + FLT_IN_IN + Filtered pin state for pin selected by INTR_CFG.FLT_SEL + [24:24] + read-only + + + + + INTR_MASK + Port interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Masks edge interrupt on IO pin 0 +'0': Pin interrupt forwarding disabled +'1': Pin interrupt forwarding enabled + [0:0] + read-write + + + EDGE1 + Masks edge interrupt on IO pin 1 + [1:1] + read-write + + + EDGE2 + Masks edge interrupt on IO pin 2 + [2:2] + read-write + + + EDGE3 + Masks edge interrupt on IO pin 3 + [3:3] + read-write + + + EDGE4 + Masks edge interrupt on IO pin 4 + [4:4] + read-write + + + EDGE5 + Masks edge interrupt on IO pin 5 + [5:5] + read-write + + + EDGE6 + Masks edge interrupt on IO pin 6 + [6:6] + read-write + + + EDGE7 + Masks edge interrupt on IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_MASKED + Port interrupt masked status register + 0x1C + 32 + read-only + 0x0 + 0x1FF + + + EDGE0 + Edge detected AND masked on IO pin 0 +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [0:0] + read-only + + + EDGE1 + Edge detected and masked on IO pin 1 + [1:1] + read-only + + + EDGE2 + Edge detected and masked on IO pin 2 + [2:2] + read-only + + + EDGE3 + Edge detected and masked on IO pin 3 + [3:3] + read-only + + + EDGE4 + Edge detected and masked on IO pin 4 + [4:4] + read-only + + + EDGE5 + Edge detected and masked on IO pin 5 + [5:5] + read-only + + + EDGE6 + Edge detected and masked on IO pin 6 + [6:6] + read-only + + + EDGE7 + Edge detected and masked on IO pin 7 + [7:7] + read-only + + + FLT_EDGE + Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-only + + + + + INTR_SET + Port interrupt set register + 0x20 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Sets edge detect interrupt for IO pin 0 +'0': Interrupt state not affected +'1': Interrupt set + [0:0] + read-write + + + EDGE1 + Sets edge detect interrupt for IO pin 1 + [1:1] + read-write + + + EDGE2 + Sets edge detect interrupt for IO pin 2 + [2:2] + read-write + + + EDGE3 + Sets edge detect interrupt for IO pin 3 + [3:3] + read-write + + + EDGE4 + Sets edge detect interrupt for IO pin 4 + [4:4] + read-write + + + EDGE5 + Sets edge detect interrupt for IO pin 5 + [5:5] + read-write + + + EDGE6 + Sets edge detect interrupt for IO pin 6 + [6:6] + read-write + + + EDGE7 + Sets edge detect interrupt for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_CFG + Port interrupt configuration register + 0x24 + 32 + read-write + 0x0 + 0x1FFFFF + + + EDGE0_SEL + Sets which edge will trigger an IRQ for IO pin 0 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + EDGE1_SEL + Sets which edge will trigger an IRQ for IO pin 1 + [3:2] + read-write + + + EDGE2_SEL + Sets which edge will trigger an IRQ for IO pin 2 + [5:4] + read-write + + + EDGE3_SEL + Sets which edge will trigger an IRQ for IO pin 3 + [7:6] + read-write + + + EDGE4_SEL + Sets which edge will trigger an IRQ for IO pin 4 + [9:8] + read-write + + + EDGE5_SEL + Sets which edge will trigger an IRQ for IO pin 5 + [11:10] + read-write + + + EDGE6_SEL + Sets which edge will trigger an IRQ for IO pin 6 + [13:12] + read-write + + + EDGE7_SEL + Sets which edge will trigger an IRQ for IO pin 7 + [15:14] + read-write + + + FLT_EDGE_SEL + Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + FLT_SEL + Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. + [20:18] + read-write + + + + + CFG + Port configuration register + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DRIVE_MODE0 + The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [2:0] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Weak/resistive pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull up + D_OUT = '1': Weak/resistive pull up + 2 + + + PULLDOWN + Resistive pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': High Impedance +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 4 + + + OD_DRIVESHIGH + Open drain, drives high + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': High Impedance + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 5 + + + STRONG + Strong D_OUTput buffer + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 6 + + + PULLUP_DOWN + Pull up or pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = '0': + GPIO_DSI_OUT = '0': Weak/resistive pull down + GPIO_DSI_OUT = '1': Weak/resistive pull up +where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull up + 7 + + + + + IN_EN0 + Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. +'0': Input buffer disabled +'1': Input buffer enabled + [3:3] + read-write + + + DRIVE_MODE1 + The GPIO drive mode for IO pin 1 + [6:4] + read-write + + + IN_EN1 + Enables the input buffer for IO pin 1 + [7:7] + read-write + + + DRIVE_MODE2 + The GPIO drive mode for IO pin 2 + [10:8] + read-write + + + IN_EN2 + Enables the input buffer for IO pin 2 + [11:11] + read-write + + + DRIVE_MODE3 + The GPIO drive mode for IO pin 3 + [14:12] + read-write + + + IN_EN3 + Enables the input buffer for IO pin 3 + [15:15] + read-write + + + DRIVE_MODE4 + The GPIO drive mode for IO pin4 + [18:16] + read-write + + + IN_EN4 + Enables the input buffer for IO pin 4 + [19:19] + read-write + + + DRIVE_MODE5 + The GPIO drive mode for IO pin 5 + [22:20] + read-write + + + IN_EN5 + Enables the input buffer for IO pin 5 + [23:23] + read-write + + + DRIVE_MODE6 + The GPIO drive mode for IO pin 6 + [26:24] + read-write + + + IN_EN6 + Enables the input buffer for IO pin 6 + [27:27] + read-write + + + DRIVE_MODE7 + The GPIO drive mode for IO pin 7 + [30:28] + read-write + + + IN_EN7 + Enables the input buffer for IO pin 7 + [31:31] + read-write + + + + + CFG_IN + Port input buffer configuration register + 0x2C + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_0 + Configures the pin 0 input buffer mode (trip points and hysteresis) + [0:0] + read-write + + + CMOS + S40S: Input buffer compatible with CMOS and I2C interfaces + 0 + + + TTL + S40S: Input buffer compatible with TTL and MediaLB interfaces + 1 + + + + + VTRIP_SEL1_0 + Configures the pin 1 input buffer mode (trip points and hysteresis) + [1:1] + read-write + + + VTRIP_SEL2_0 + Configures the pin 2 input buffer mode (trip points and hysteresis) + [2:2] + read-write + + + VTRIP_SEL3_0 + Configures the pin 3 input buffer mode (trip points and hysteresis) + [3:3] + read-write + + + VTRIP_SEL4_0 + Configures the pin 4 input buffer mode (trip points and hysteresis) + [4:4] + read-write + + + VTRIP_SEL5_0 + Configures the pin 5 input buffer mode (trip points and hysteresis) + [5:5] + read-write + + + VTRIP_SEL6_0 + Configures the pin 6 input buffer mode (trip points and hysteresis) + [6:6] + read-write + + + VTRIP_SEL7_0 + Configures the pin 7 input buffer mode (trip points and hysteresis) + [7:7] + read-write + + + + + CFG_OUT + Port output buffer configuration register + 0x30 + 32 + read-write + 0x0 + 0xFFFF00FF + + + SLOW0 + Enables slow slew rate for IO pin 0 +'0': Fast slew rate +'1': Slow slew rate + [0:0] + read-write + + + SLOW1 + Enables slow slew rate for IO pin 1 + [1:1] + read-write + + + SLOW2 + Enables slow slew rate for IO pin 2 + [2:2] + read-write + + + SLOW3 + Enables slow slew rate for IO pin 3 + [3:3] + read-write + + + SLOW4 + Enables slow slew rate for IO pin 4 + [4:4] + read-write + + + SLOW5 + Enables slow slew rate for IO pin 5 + [5:5] + read-write + + + SLOW6 + Enables slow slew rate for IO pin 6 + [6:6] + read-write + + + SLOW7 + Enables slow slew rate for IO pin 7 + [7:7] + read-write + + + DRIVE_SEL0 + Sets the GPIO drive strength for IO pin 0 + [17:16] + read-write + + + FULL_DRIVE + Full drive strength: GPIO drives current at its max rated spec. + 0 + + + ONE_HALF_DRIVE + 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec + 1 + + + ONE_QUARTER_DRIVE + 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec. + 2 + + + ONE_EIGHTH_DRIVE + 1/8 drive strength: GPIO drives current at 1/8 of its max rated spec. + 3 + + + + + DRIVE_SEL1 + Sets the GPIO drive strength for IO pin 1 + [19:18] + read-write + + + DRIVE_SEL2 + Sets the GPIO drive strength for IO pin 2 + [21:20] + read-write + + + DRIVE_SEL3 + Sets the GPIO drive strength for IO pin 3 + [23:22] + read-write + + + DRIVE_SEL4 + Sets the GPIO drive strength for IO pin 4 + [25:24] + read-write + + + DRIVE_SEL5 + Sets the GPIO drive strength for IO pin 5 + [27:26] + read-write + + + DRIVE_SEL6 + Sets the GPIO drive strength for IO pin 6 + [29:28] + read-write + + + DRIVE_SEL7 + Sets the GPIO drive strength for IO pin 7 + [31:30] + read-write + + + + + CFG_SIO + Port SIO configuration register + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VREG_EN01 + Selects the output buffer mode: +'0': Unregulated output buffer +'1': Regulated output buffer +The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. + [0:0] + read-write + + + IBUF_SEL01 + Selects the input buffer mode: +0: Singled ended input buffer +1: Differential input buffer + [1:1] + read-write + + + VTRIP_SEL01 + Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): +'0': Input buffer functions as a CMOS input buffer. +'1': Input buffer functions as a TTL input buffer. +In differential input buffer mode (IBUF_SEL = '1') +'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) +'1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) + [2:2] + read-write + + + VREF_SEL01 + Selects reference voltage (Vref) trip-point of the input buffer: +'0': Trip-point reference from pin_ref +'1': Trip-point reference of SRSS internal reference Vref (1.2 V) +'2': Trip-point reference of AMUXBUS_A +'3': Trip-point reference of AMUXBUS_B + [4:3] + read-write + + + VOH_SEL01 + Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). +'0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V +'1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V +'2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V +'3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V +'4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V +'5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V +'6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V +'7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V +Note: The upper value on Voh is limited to Vddio - 400mV + [7:5] + read-write + + + VREG_EN23 + See corresponding definition for IO pins 0 and 1 + [8:8] + read-write + + + IBUF_SEL23 + See corresponding definition for IO pins 0 and 1 + [9:9] + read-write + + + VTRIP_SEL23 + See corresponding definition for IO pins 0 and 1 + [10:10] + read-write + + + VREF_SEL23 + See corresponding definition for IO pins 0 and 1 + [12:11] + read-write + + + VOH_SEL23 + See corresponding definition for IO pins 0 and 1 + [15:13] + read-write + + + VREG_EN45 + See corresponding definition for IO pins 0 and 1 + [16:16] + read-write + + + IBUF_SEL45 + See corresponding definition for IO pins 0 and 1 + [17:17] + read-write + + + VTRIP_SEL45 + See corresponding definition for IO pins 0 and 1 + [18:18] + read-write + + + VREF_SEL45 + See corresponding definition for IO pins 0 and 1 + [20:19] + read-write + + + VOH_SEL45 + See corresponding definition for IO pins 0 and 1 + [23:21] + read-write + + + VREG_EN67 + See corresponding definition for IO pins 0 and 1 + [24:24] + read-write + + + IBUF_SEL67 + See corresponding definition for IO pins 0 and 1 + [25:25] + read-write + + + VTRIP_SEL67 + See corresponding definition for IO pins 0 and 1 + [26:26] + read-write + + + VREF_SEL67 + See corresponding definition for IO pins 0 and 1 + [28:27] + read-write + + + VOH_SEL67 + See corresponding definition for IO pins 0 and 1 + [31:29] + read-write + + + + + CFG_IN_GPIO5V + Port GPIO5V input buffer configuration register + 0x3C + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_1 + Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. +0: input buffer is not compatible with automotive. +1: input buffer is compatible with automotive. + +Use CFG_IN.VTRIP_SEL0_0 fields set as CMOS only when this bit needs to be set. + [0:0] + read-write + + + DISABLE + Input buffer not compatible with automotive (elevated Vil) interfaces. + 0 + + + AUTO + Input buffer compatible with automotive (elevated Vil) interfaces. + 1 + + + + + VTRIP_SEL1_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [1:1] + read-write + + + VTRIP_SEL2_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [2:2] + read-write + + + VTRIP_SEL3_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [3:3] + read-write + + + VTRIP_SEL4_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [4:4] + read-write + + + VTRIP_SEL5_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [5:5] + read-write + + + VTRIP_SEL6_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [6:6] + read-write + + + VTRIP_SEL7_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [7:7] + read-write + + + + + + INTR_CAUSE0 + Interrupt port cause register 0 + 0x4000 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE1 + Interrupt port cause register 1 + 0x4004 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE2 + Interrupt port cause register 2 + 0x4008 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE3 + Interrupt port cause register 3 + 0x400C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + VDD_ACTIVE + Extern power supply detection register + 0x4010 + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. +'0': Supply is not present +'1': Supply is present + +When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. +For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: +0: vbackup, +1: vddio_0, +2: vddio_1, +3: vddio_a, +4: vddio_r, +5: vddusb' + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) + [31:31] + read-only + + + + + VDD_INTR + Supply detection interrupt register + 0x4014 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply state change detected. +'0': No change to supply detected +'1': Change to supply detected + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. + [31:31] + read-write + + + + + VDD_INTR_MASK + Supply detection interrupt mask register + 0x4018 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Masks supply interrupt on VDDIO. +'0': VDDIO interrupt forwarding disabled +'1': VDDIO interrupt forwarding enabled + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + VDD_INTR_MASKED + Supply detection interrupt masked register + 0x401C + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply transition detected AND masked +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-only + + + + + VDD_INTR_SET + Supply detection interrupt set register + 0x4020 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Sets supply interrupt. +'0': Interrupt state not affected +'1': Interrupt set + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + + + SMARTIO + Programmable IO configuration + 0x40330000 + + 0 + 65536 + registers + + + + 10 + 256 + PRT[%s] + Programmable IO port registers + 0x00000000 + + CTL + Control register + 0x0 + 32 + read-write + 0x2001400 + 0x82001F00 + + + BYPASS + Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. +'0': No bypass (programmable SMARTIO fabric is exposed). +'1': Bypass (programmable SMARTIOIO fabric is hidden). + [7:0] + read-write + + + CLOCK_SRC + Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: +'0': io_data_in[0]/'1'. +... +'7': io_data_in[7]/'1'. +'8': chip_data[0]/'1'. +... +'15': chip_data[7]/'1'. +'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. +'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. +'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. +'31': asynchronous mode/'1'. Select this when clockless operation is configured. + +NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. + [12:8] + read-write + + + HLD_OVR + IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: +'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). +'1': The SMARTIO controls the IO cel hold override functionality: +- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. +- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). + [24:24] + read-write + + + PIPELINE_EN + Enable for pipeline register: +'0': Disabled (register is bypassed). +'1': Enabled. + [25:25] + read-write + + + ENABLED + Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: +'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. + +If the IP is disabled: +- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. +- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. + +'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. + [31:31] + read-write + + + + + SYNC_CTL + Synchronization control register + 0x10 + 32 + read-write + 0x0 + 0x0 + + + IO_SYNC_EN + Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. +'0': No synchronization. +'1': Synchronization. + [7:0] + read-write + + + CHIP_SYNC_EN + Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. +'0': No synchronization. +'1': Synchronization. + [15:8] + read-write + + + + + 8 + 4 + LUT_SEL[%s] + LUT component input selection + 0x20 + 32 + read-write + 0x0 + 0x0 + + + LUT_TR0_SEL + LUT input signal 'tr0_in' source selection: +'0': Data unit output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [3:0] + read-write + + + LUT_TR1_SEL + LUT input signal 'tr1_in' source selection: +'0': LUT 0 output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [11:8] + read-write + + + LUT_TR2_SEL + LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. + [19:16] + read-write + + + + + 8 + 4 + LUT_CTL[%s] + LUT component control register + 0x40 + 32 + read-write + 0x0 + 0x0 + + + LUT + LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). + [7:0] + read-write + + + LUT_OPC + LUT opcode specifies the LUT operation: +'0': Combinatoral output, no feedback. + tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. +'1': Combinatorial output, feedback. + tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. +On clock: + lut_reg <= tr_in2. +'2': Sequential output, no feedback. + temp = LUT[{tr2_in, tr1_in, tr0_in}]. + tr_out = lut_reg. +On clock: + lut_reg <= temp. +'3': Register with asynchronous set and reset. + tr_out = lut_reg. + enable = (tr2_in ^ LUT[4]) | LUT[5]. + set = enable & (tr1_in ^ LUT[2]) & LUT[3]. + clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. +Asynchronously (no clock required): + lut_reg <= if (clr) '0' else if (set) '1' + [9:8] + read-write + + + + + DU_SEL + Data unit component input selection + 0xC0 + 32 + read-write + 0x0 + 0x0 + + + DU_TR0_SEL + Data unit input signal 'tr0_in' source selection: +'0': Constant '0'. +'1': Constant '1'. +'2': Data unit output. +'10-3': LUT 7 - 0 outputs. +Otherwise: Undefined. + [3:0] + read-write + + + DU_TR1_SEL + Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. + [11:8] + read-write + + + DU_TR2_SEL + Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. + [19:16] + read-write + + + DU_DATA0_SEL + Data unit input data 'data0_in' source selection: +'0': Constant '0'. +'1': chip_data[7:0]. +'2': io_data_in[7:0]. +'3': DATA.DATA MMIO register field. + [25:24] + read-write + + + DU_DATA1_SEL + Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. + [29:28] + read-write + + + + + DU_CTL + Data unit component control register + 0xC4 + 32 + read-write + 0x0 + 0x0 + + + DU_SIZE + Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. + [2:0] + read-write + + + DU_OPC + Data unit opcode specifies the data unit operation: +'1': INCR +'2': DECR +'3': INCR_WRAP +'4': DECR_WRAP +'5': INCR_DECR +'6': INCR_DECR_WRAP +'7': ROR +'8': SHR +'9': AND_OR +'10': SHR_MAJ3 +'11': SHR_EQL. +Otherwise: Undefined. + [11:8] + read-write + + + + + DATA + Data register + 0xF0 + 32 + read-write + 0x0 + 0x0 + + + DATA + Data unit input data source. + [7:0] + read-write + + + + + + + + LPCOMP + Low Power Comparators + 0x40350000 + + 0 + 65536 + registers + + + + CONFIG + LPCOMP Configuration Register + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + LPREF_EN + Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. + [30:30] + read-write + + + ENABLED + - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) +- 1: IP enabled + [31:31] + read-write + + + + + STATUS + LPCOMP Status Register + 0x4 + 32 + read-only + 0x0 + 0x10001 + + + OUT0 + Current output value of the comparator 0. + [0:0] + read-only + + + OUT1 + Current output value of the comparator 1. + [16:16] + read-only + + + + + INTR + LPCOMP Interrupt request register + 0x10 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + LPCOMP Interrupt set register + 0x14 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + LPCOMP Interrupt request mask + 0x18 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + LPCOMP Interrupt request masked + 0x1C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + CMP0_CTRL + Comparator 0 control Register + 0x40 + 32 + read-write + 0x0 + 0xCE3 + + + MODE0 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST0 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE0 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS0 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL0 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP0_SW + Comparator 0 switch control + 0x50 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + Comparator 0 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP0_AP0 + Comparator 0 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP0_BP0 + Comparator 0 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP0_IN0 + Comparator 0 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP0_AN0 + Comparator 0 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP0_BN0 + Comparator 0 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP0_VN0 + Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP0_SW_CLEAR + Comparator 0 switch control clear + 0x54 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + see corresponding bit in CMP0_SW + [0:0] + read-write + + + CMP0_AP0 + see corresponding bit in CMP0_SW + [1:1] + read-write + + + CMP0_BP0 + see corresponding bit in CMP0_SW + [2:2] + read-write + + + CMP0_IN0 + see corresponding bit in CMP0_SW + [4:4] + read-write + + + CMP0_AN0 + see corresponding bit in CMP0_SW + [5:5] + read-write + + + CMP0_BN0 + see corresponding bit in CMP0_SW + [6:6] + read-write + + + CMP0_VN0 + see corresponding bit in CMP0_SW + [7:7] + read-write + + + + + CMP1_CTRL + Comparator 1 control Register + 0x80 + 32 + read-write + 0x0 + 0xCE3 + + + MODE1 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST1 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE1 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS1 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL1 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP1_SW + Comparator 1 switch control + 0x90 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + Comparator 1 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP1_AP1 + Comparator 1 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP1_BP1 + Comparator 1 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP1_IN1 + Comparator 1 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP1_AN1 + Comparator 1 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP1_BN1 + Comparator 1 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP1_VN1 + Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP1_SW_CLEAR + Comparator 1 switch control clear + 0x94 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + see corresponding bit in CMP1_SW + [0:0] + read-write + + + CMP1_AP1 + see corresponding bit in CMP1_SW + [1:1] + read-write + + + CMP1_BP1 + see corresponding bit in CMP1_SW + [2:2] + read-write + + + CMP1_IN1 + see corresponding bit in CMP1_SW + [4:4] + read-write + + + CMP1_AN1 + see corresponding bit in CMP1_SW + [5:5] + read-write + + + CMP1_BN1 + see corresponding bit in CMP1_SW + [6:6] + read-write + + + CMP1_VN1 + see corresponding bit in CMP1_SW + [7:7] + read-write + + + + + + + CSD0 + Capsense Controller + CSD + 0x40360000 + + 0 + 4096 + registers + + + + CONFIG + Configuration and Control + 0x0 + 32 + read-write + 0x4000000 + 0xCF0E1DF1 + + + IREF_SEL + Select Iref supply. + [0:0] + read-write + + + IREF_SRSS + select SRSS Iref (default) + 0 + + + IREF_PASS + select PASS.AREF Iref, only available if PASS IP is on the chip. + 1 + + + + + FILTER_DELAY + This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on. +When set to 0 the digital filter is off. When set to any other value the ignoring will last for FILTER_DELAY clk_csd cycles after the start of each measurement and from the first comparator trip to the end of each measurement. + [8:4] + read-write + + + SHIELD_DELAY + Selects the delay by which csd_shield is delayed relative to csd_sense. + [11:10] + read-write + + + OFF + Delay line is off, csd_shield=csd_sense + 0 + + + D5NS + Introduces a 5ns delay (typ) + 1 + + + D10NS + Introduces a 10ns delay (typ) + 2 + + + D20NS + Introduces a 20ns delay (typ) + 3 + + + + + SENSE_EN + Enables the sense modulator output. +0: all switches, static or dynamic, are open and IDAC in CSD mode is off +1: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer. + [12:12] + read-write + + + FULL_WAVE + Enables full wave cap sensing mode + [17:17] + read-write + + + HALFWAVE + Half Wave mode (normal). +In this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change. + 0 + + + FULLWAVE + Full Wave mode. +In this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips. + 1 + + + + + MUTUAL_CAP + Enables mutual cap sensing mode + [18:18] + read-write + + + SELFCAP + Self-cap mode (configure sense line as CSD_SENSE) + 0 + + + MUTUALCAP + Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense. + 1 + + + + + CSX_DUAL_CNT + Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUTUAL_CAP=0 + [19:19] + read-write + + + ONE + Use one counter for both phases (source and sink). + 0 + + + TWO + Use two counters, separate count for when csd_sense is high and when csd_sense is low. + 1 + + + + + DSI_COUNT_SEL + Select what to output on the dsi_count bus. + [24:24] + read-write + + + CSD_RESULT + depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially. + 0 + + + ADC_RESULT + output ADC_RES.VIN_CNT on the dsi_count bus + 1 + + + + + DSI_SAMPLE_EN + Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER. + [25:25] + read-write + + + SAMPLE_SYNC + Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1). + [26:26] + read-write + + + DSI_SENSE_EN + Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals. + [27:27] + read-write + + + LP_MODE + Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP): +0: High Power mode +1: Low Power mode + [30:30] + read-write + + + ENABLE + Master enable of the CSDv2 IP. Must be set to 1 for any CSDv2, ADC or IDAC operation to function. +When 0 all analog components will be off and all switches will be open. + [31:31] + read-write + + + + + SPARE + Spare MMIO + 0x4 + 32 + read-write + 0x0 + 0xF + + + SPARE + Spare MMIO + [3:0] + read-write + + + + + STATUS + Status Register + 0x80 + 32 + read-only + 0x0 + 0xE + + + CSD_SENSE + Signal used to drive the Cs switches. + [1:1] + read-only + + + HSCMP_OUT + Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized) + [2:2] + read-only + + + C_LT_VREF + Vin < Vref + 0 + + + C_GT_VREF + Vin > Vref + 1 + + + + + CSDCMP_OUT + Output of main sensing comparator (synchronized) + [3:3] + read-only + + + + + STAT_SEQ + Current Sequencer status + 0x84 + 32 + read-only + 0x0 + 0x70007 + + + SEQ_STATE + CSD sequencer state + [2:0] + read-only + + + ADC_STATE + ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) + [18:16] + read-only + + + + + STAT_CNTS + Current status counts + 0x88 + 32 + read-only + 0x0 + 0xFFFF + + + NUM_CONV + Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) + [15:0] + read-only + + + + + STAT_HCNT + Current count of the HSCMP counter + 0x8C + 32 + read-only + 0x0 + 0xFFFF + + + CNT + Current value of HSCMP counter + [15:0] + read-only + + + + + RESULT_VAL1 + Result CSD/CSX accumulation counter value 1 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFF + + + VALUE + Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. + [15:0] + read-only + + + BAD_CONVS + Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. + [23:16] + read-only + + + + + RESULT_VAL2 + Result CSX accumulation counter value 2 + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + VALUE + Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. + [15:0] + read-only + + + + + ADC_RES + ADC measurement + 0xE0 + 32 + read-only + 0x0 + 0xC001FFFF + + + VIN_CNT + Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. + [15:0] + read-only + + + HSCMP_POL + Polarity used for IDACB for this last ADC result, 0= source, 1= sink + [16:16] + read-only + + + ADC_OVERFLOW + This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. + [30:30] + read-only + + + ADC_ABORT + This flag is set when the ADC sequencer was aborted before tripping HSCMP. + [31:31] + read-only + + + + + INTR + CSD Interrupt Request Register + 0xF0 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + A normal sample is complete + [1:1] + read-write + + + INIT + Coarse initialization complete or Sample initialization complete (the latter is typically ignored) + [2:2] + read-write + + + ADC_RES + ADC Result ready + [8:8] + read-write + + + + + INTR_SET + CSD Interrupt set register + 0xF4 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASK + CSD Interrupt mask register + 0xF8 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASKED + CSD Interrupt masked register + 0xFC + 32 + read-only + 0x0 + 0x106 + + + SAMPLE + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + INIT + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + ADC_RES + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + + + HSCMP + High Speed Comparator configuration + 0x180 + 32 + read-write + 0x0 + 0x80000011 + + + HSCMP_EN + High Speed Comparator enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + HSCMP_INVERT + Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT + [4:4] + read-write + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + AMBUF + Reference Generator configuration + 0x184 + 32 + read-write + 0x0 + 0x3 + + + PWR_MODE + Amux buffer power level + [1:0] + read-write + + + OFF + Disable buffer + 0 + + + NORM + On, normal or low power level depending on CONFIG.LP_MODE. + 1 + + + HI + On, high or low power level depending on CONFIG.LP_MODE. + 2 + + + + + + + REFGEN + Reference Generator configuration + 0x188 + 32 + read-write + 0x0 + 0x9F1F71 + + + REFGEN_EN + Reference Generator Enable + [0:0] + read-write + + + OFF + Disable Reference Generator + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + BYPASS + Bypass selected input reference unbuffered to Vrefhi + [4:4] + read-write + + + VDDA_EN + Close Vdda switch to top of resistor string (or Vrefhi?) + [5:5] + read-write + + + RES_EN + Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) + [6:6] + read-write + + + GAIN + Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) + [12:8] + read-write + + + VREFLO_SEL + Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) + [20:16] + read-write + + + VREFLO_INT + Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). + [23:23] + read-write + + + + + CSDCMP + CSD Comparator configuration + 0x18C + 32 + read-write + 0x0 + 0xB0000331 + + + CSDCMP_EN + CSD Comparator Enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + POLARITY_SEL + Select which IDAC polarity to use to detect CSDCMP triggering + [5:4] + read-write + + + IDACA_POL + Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX + 0 + + + IDACB_POL + Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) + 1 + + + DUAL_POL + Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case + 2 + + + + + CMP_PHASE + Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). + [9:8] + read-write + + + FULL + Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + Comparator is active during Phi1 only. Currently no known use-case. + 1 + + + PHI2 + Comparator is active during Phi2 only. Intended usage: CSD Low EMI. + 2 + + + PHI1_2 + Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. + 3 + + + + + CMP_MODE + Select which signal to output on dsi_sample_out. + [28:28] + read-write + + + CSD + CSD mode: output the filtered sample signal on dsi_sample_out + 0 + + + GP + General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. + 1 + + + + + FEEDBACK_MODE + This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. + [29:29] + read-write + + + FLOP + Use feedback from sampling flip-flop (used in most modes). + 0 + + + COMP + Use feedback from comparator directly (used in single Cmod mutual cap sensing only) + 1 + + + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + SW_RES + Switch Resistance configuration + 0x1F0 + 32 + read-write + 0x0 + 0xF00FF + + + RES_HCAV + Select resistance or low EMI (slow ramp) for the HCAV switch + [1:0] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + LOWEMI + Low EMI (slow ramp: 3 switches closed by fixed delay line) + 3 + + + + + RES_HCAG + Select resistance or low EMI for the corresponding switch + [3:2] + read-write + + + RES_HCBV + Select resistance or low EMI for the corresponding switch + [5:4] + read-write + + + RES_HCBG + Select resistance or low EMI for the corresponding switch + [7:6] + read-write + + + RES_F1PM + Select resistance for the corresponding switch + [17:16] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + RSVD + N/A + 3 + + + + + RES_F2PT + Select resistance for the corresponding switch + [19:18] + read-write + + + + + SENSE_PERIOD + Sense clock period + 0x200 + 32 + read-write + 0xC000000 + 0xFF70FFF + + + SENSE_DIV + The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . +Note this is the base divider, clock dithering may change the actual period length. +Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. +In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. + [11:0] + read-write + + + LFSR_SIZE + Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. + [18:16] + read-write + + + OFF + Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) + 0 + + + 6B + 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) + 1 + + + 7B + 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) + 2 + + + 9B + 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) + 3 + + + 10B + 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) + 4 + + + 8B + 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) + 5 + + + 12B + 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) + 6 + + + + + LFSR_SCALE + Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. +The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). +Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. + [23:20] + read-write + + + LFSR_CLEAR + When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. +Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. + [24:24] + read-write + + + SEL_LFSR_MSB + Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. + [25:25] + read-write + + + LFSR_BITS + Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. +Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. + [27:26] + read-write + + + 2B + use 2 bits: range = [-2,1] + 0 + + + 3B + use 3 bits: range = [-4,3] + 1 + + + 4B + use 4 bits: range = [-8,7] + 2 + + + 5B + use 5 bits: range = [-16,15] (default) + 3 + + + + + + + SENSE_DUTY + Sense clock duty cycle + 0x204 + 32 + read-write + 0x0 + 0xD0FFF + + + SENSE_WIDTH + Defines the length of the first phase of the sense clock in clk_csd cycles. +A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. +Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. + [11:0] + read-write + + + SENSE_POL + Polarity of the sense clock +0 = start with low phase (typical for regular negative transfer CSD) +1 = start with high phase + [16:16] + read-write + + + OVERLAP_PHI1 + NonOverlap or not for Phi1 (csd_sense=0). +0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. +1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. + [18:18] + read-write + + + OVERLAP_PHI2 + Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). + [19:19] + read-write + + + + + SW_HS_P_SEL + HSCMP Pos input switch Waveform selection + 0x280 + 32 + read-write + 0x0 + 0x11111111 + + + SW_HMPM + Set HMPM switch +0: static open +1: static closed + [0:0] + read-write + + + SW_HMPT + Set corresponding switch + [4:4] + read-write + + + SW_HMPS + Set corresponding switch + [8:8] + read-write + + + SW_HMMA + Set corresponding switch + [12:12] + read-write + + + SW_HMMB + Set corresponding switch + [16:16] + read-write + + + SW_HMCA + Set corresponding switch + [20:20] + read-write + + + SW_HMCB + Set corresponding switch + [24:24] + read-write + + + SW_HMRH + Set corresponding switch + [28:28] + read-write + + + + + SW_HS_N_SEL + HSCMP Neg input switch Waveform selection + 0x284 + 32 + read-write + 0x0 + 0x77110000 + + + SW_HCCC + Set corresponding switch + [16:16] + read-write + + + SW_HCCD + Set corresponding switch + [20:20] + read-write + + + SW_HCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_HCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_SHIELD_SEL + Shielding switches Waveform selection + 0x288 + 32 + read-write + 0x0 + 0x117777 + + + SW_HCAV + N/A + [2:0] + read-write + + + SW_HCAG + Select waveform for corresponding switch + [6:4] + read-write + + + SW_HCBV + N/A + [10:8] + read-write + + + SW_HCBG + Select waveform for corresponding switch, using csd_shield as base + [14:12] + read-write + + + SW_HCCV + Set corresponding switch + [16:16] + read-write + + + SW_HCCG + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_AMUXBUF_SEL + Amuxbuffer switches Waveform selection + 0x290 + 32 + read-write + 0x0 + 0x11171110 + + + SW_IRBY + Set corresponding switch + [4:4] + read-write + + + SW_IRLB + Set corresponding switch + [8:8] + read-write + + + SW_ICA + Set corresponding switch + [12:12] + read-write + + + SW_ICB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_IRLI + Set corresponding switch + [20:20] + read-write + + + SW_IRH + Set corresponding switch + [24:24] + read-write + + + SW_IRL + Set corresponding switch + [28:28] + read-write + + + + + SW_BYP_SEL + AMUXBUS bypass switches Waveform selection + 0x294 + 32 + read-write + 0x0 + 0x111000 + + + SW_BYA + Set corresponding switch + [12:12] + read-write + + + SW_BYB + Set corresponding switch + [16:16] + read-write + + + SW_CBCC + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_CMP_P_SEL + CSDCMP Pos Switch Waveform selection + 0x2A0 + 32 + read-write + 0x0 + 0x1111777 + + + SW_SFPM + Select waveform for corresponding switch + [2:0] + read-write + + + SW_SFPT + Select waveform for corresponding switch + [6:4] + read-write + + + SW_SFPS + Select waveform for corresponding switch + [10:8] + read-write + + + SW_SFMA + Set corresponding switch + [12:12] + read-write + + + SW_SFMB + Set corresponding switch + [16:16] + read-write + + + SW_SFCA + Set corresponding switch + [20:20] + read-write + + + SW_SFCB + Set corresponding switch + [24:24] + read-write + + + + + SW_CMP_N_SEL + CSDCMP Neg Switch Waveform selection + 0x2A4 + 32 + read-write + 0x0 + 0x77000000 + + + SW_SCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_SCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_REFGEN_SEL + Reference Generator Switch Waveform selection + 0x2A8 + 32 + read-write + 0x0 + 0x11110011 + + + SW_IAIB + Set corresponding switch + [0:0] + read-write + + + SW_IBCB + Set corresponding switch + [4:4] + read-write + + + SW_SGMB + Set corresponding switch + [16:16] + read-write + + + SW_SGRP + Set corresponding switch + [20:20] + read-write + + + SW_SGRE + Set corresponding switch + [24:24] + read-write + + + SW_SGR + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_MOD_SEL + Full Wave Cmod Switch Waveform selection + 0x2B0 + 32 + read-write + 0x0 + 0x11170701 + + + SW_F1PM + Set corresponding switch + [0:0] + read-write + + + SW_F1MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F1CA + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C1CC + Set corresponding switch + [20:20] + read-write + + + SW_C1CD + Set corresponding switch + [24:24] + read-write + + + SW_C1F1 + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_TANK_SEL + Full Wave Csh_tank Switch Waveform selection + 0x2B4 + 32 + read-write + 0x0 + 0x11177710 + + + SW_F2PT + Set corresponding switch + [4:4] + read-write + + + SW_F2MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F2CA + Select waveform for corresponding switch + [14:12] + read-write + + + SW_F2CB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C2CC + Set corresponding switch + [20:20] + read-write + + + SW_C2CD + Set corresponding switch + [24:24] + read-write + + + SW_C2F2 + Set corresponding switch + [28:28] + read-write + + + + + SW_DSI_SEL + DSI output switch control Waveform selection + 0x2C0 + 32 + read-write + 0x0 + 0xFF + + + DSI_CSH_TANK + Select waveform for dsi_csh_tank output signal +0: static open +1: static closed +2: phi1 +3: phi2 +4: phi1 & HSCMP +5: phi2 & HSCMP +6: HSCMP // ignores phi1/2 +7: !sense // = phi1 but ignores OVERLAP_PHI1 + +8: phi1_delay // phi1 delayed with shield delay +9: phi2_delay // phi2 delayed with shield delay + +10: !phi1 +11: !phi2 +12: !(phi1 & HSCMP) +13: !(phi2 & HSCMP) +14: !HSCMP // ignores phi1/2 +15: sense // = phi2 but ignores OVERLAP_PHI2 + [3:0] + read-write + + + DSI_CMOD + Select waveform for dsi_cmod output signal + [7:4] + read-write + + + + + IO_SEL + IO output control Waveform selection + 0x2D0 + 32 + read-write + 0x0 + 0xFFFF0FF + + + CSD_TX_OUT + Select waveform for csd_tx_out output signal + [3:0] + read-write + + + CSD_TX_OUT_EN + Select waveform for csd_tx_out_en output signal + [7:4] + read-write + + + CSD_TX_AMUXB_EN + Select waveform for csd_tx_amuxb_en output signal + [15:12] + read-write + + + CSD_TX_N_OUT + Select waveform for csd_tx_n_out output signal + [19:16] + read-write + + + CSD_TX_N_OUT_EN + Select waveform for csd_tx_n_out_en output signal + [23:20] + read-write + + + CSD_TX_N_AMUXA_EN + Select waveform for csd_tx_n_amuxa_en output signal + [27:24] + read-write + + + + + SEQ_TIME + Sequencer Timing + 0x300 + 32 + read-write + 0x0 + 0xFF + + + AZ_TIME + Define Auto-Zero time in csd_sense cycles -1. + [7:0] + read-write + + + + + SEQ_INIT_CNT + Sequencer Initial conversion and sample counts + 0x310 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. + [15:0] + read-write + + + + + SEQ_NORM_CNT + Sequencer Normal conversion and sample counts + 0x314 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. +Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). +Note for CSDv1 Sample window size = PERIOD + [15:0] + read-write + + + + + ADC_CTL + ADC Control + 0x320 + 32 + read-write + 0x0 + 0x300FF + + + ADC_TIME + ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 + [7:0] + read-write + + + ADC_MODE + Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state + [17:16] + read-write + + + OFF + No ADC measurement + 0 + + + VREF_CNT + Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB + 1 + + + VREF_BY2_CNT + Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) + 2 + + + VIN_CNT + Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. + 3 + + + + + + + SEQ_START + Sequencer start + 0x340 + 32 + read-write + 0x0 + 0x31B + + + START + Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). + [0:0] + read-write + + + SEQ_MODE + 0 = regular CSD scan + optional ADC +1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. + [1:1] + read-write + + + ABORT + When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. + [3:3] + read-write + + + DSI_START_EN + When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. + [4:4] + read-write + + + AZ0_SKIP + When set the AutoZero_0 state will be skipped + [8:8] + read-write + + + AZ1_SKIP + When set the AutoZero_1 state will be skipped + [9:9] + read-write + + + + + IDACA + IDACA Configuration + 0x400 + 32 + read-write + 0x0 + 0x3EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_MODE==CSD also mixed with the CSD configuration and operation. However in mutual cap mode with one IDAC (config.mutual_cap=1 & config.csx_dual_idac=0) the polarity of the IDAC is controlled by csd_sense. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + Balancing mode: only applies to legs configured as CSD. + [11:10] + read-write + + + FULL + enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking. + 1 + + + PHI2 + enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or dual IDAC CSX or Full-Wave. + 2 + + + PHI1_2 + enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave. + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled). +0: no DSI control + IDACA_POLARITY = IDACA.POLARITY + IDACA_LEG1_EN = IDACA.LEG1_EN + IDACA_LEG2_EN = IDACA.LEG2_EN +1: Mix MMIO with DSI control + IDACA_POLARITY = IDACA.POLARITY EXOR dsi_idaca_pol + IDACA_LEG1_EN = IDACA.LEG1_EN AND dsi_idaca_leg1_en + IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSA + [25:25] + read-write + + + + + IDACB + IDACB Configuration + 0x500 + 32 + read-write + 0x0 + 0x7EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_EN==1 and LEG1_MODE==CSD also mixed with the CSD configuration and operation. In mutual cap mode however (see config.mutual_cap) the polarity of the IDAC is controlled by csd_sense. If LEG3_EN=1 (the other two legs must be off) then the ADC sequencer controls the IDACB polarity, optionally mixed with DSI. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + same as corresponding IDACA Balancing mode + [11:10] + read-write + + + FULL + same as corresponding IDACA Balancing mode + 0 + + + PHI1 + same as corresponding IDACA Balancing mode + 1 + + + PHI2 + same as corresponding IDACA Balancing mode + 2 + + + PHI1_2 + same as corresponding IDACA Balancing mode + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG1_MODE + 0 + + + GP + same as corresponding IDACA.LEG1_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG1_MODE + 2 + + + CSD + same as corresponding IDACA.LEG1_MODE + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG2_MODE + 0 + + + GP + same as corresponding IDACA.LEG2_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG2_MODE + 2 + + + CSD + same as corresponding IDACA.LEG2_MODE + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled) +0: no DSI control + IDACB_POLARITY = IDACB.POLARITY + IDACB_LEG1_EN = IDACB.LEG1_EN + IDACB_LEG2_EN = IDACB.LEG2_EN + IDACB_LEG3_EN = IDACB.LEG3_EN +1: Mix MMIO with DSI control + IDACB_POLARITY = IDACB.POLARITY EXOR dsi_idacb_pol + IDACB_LEG1_EN = IDACB.LEG1_EN AND dsi_idacb_leg1_en + IDACB_LEG2_EN = IDACB.LEG2_EN AND dsi_idacb_leg2_en + IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSB or CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSB or CSDBUSA + [25:25] + read-write + + + LEG3_EN + output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit is set both other legs should be off. +Note that leg3 can only be used for ADC mode, not GP mode. Which means that leg3 can only be on when the ADC Sequencer is in the ADC_measure or Calib_measure state. In those states leg3 is controlled by the ADC configuration and the HSCMP output. In addition this leg3 enable bit can optionally be mixed with DSI (see DSI_CTRL_EN). +When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer. + [26:26] + read-write + + + + + + + TCPWM0 + Timer/Counter/PWM + TCPWM + 0x40380000 + + 0 + 65536 + registers + + + + CTRL + TCPWM control register + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Counter enables for counters 0 up to CNT_NR-1. +'0': counter disabled. +'1': counter enabled. +Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: +- the associated counter triggers in the CMD register are set to '0'. +- the counter's interrupt cause fields in counter's INTR register. +- the counter's status fields in counter's STATUS register.. +- the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). +- the counter's line outputs ('line_out' and 'line_compl_out'). +In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. + [31:0] + read-write + + + + + CTRL_CLR + TCPWM control clear register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Alias of CTRL that only allows disabling of counters. A write access: +'0': Does nothing. +'1': Clears respective COUNTER_ENABLED field. + +A read access returns CTRL.COUNTER_ENABLED. + [31:0] + read-write + + + + + CTRL_SET + TCPWM control set register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Alias of CTRL that only allows enabling of counters. A write access: +'0': Does nothing. +'1': Sets respective COUNTER_ENABLED field. + +A read access returns CTRL.COUNTER_ENABLED. + [31:0] + read-write + + + + + CMD_CAPTURE + TCPWM capture command register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_CAPTURE + Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. + [31:0] + read-write + + + + + CMD_RELOAD + TCPWM reload command register + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_RELOAD + Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + CMD_STOP + TCPWM stop command register + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_STOP + Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + CMD_START + TCPWM start command register + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_START + Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + INTR_CAUSE + TCPWM Counter interrupt cause register + 0x1C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNTER_INT + Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. + [31:0] + read-only + + + + + 24 + 64 + CNT[%s] + Timer/Counter/PWM Counter Module + 0x00000100 + + CTRL + Counter control register + 0x0 + 32 + read-write + 0x0 + 0x737FF0F + + + AUTO_RELOAD_CC + Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. +Timer mode: +'0': never switch. +'1': switch on a compare match event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [0:0] + read-write + + + AUTO_RELOAD_PERIOD + Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + [1:1] + read-write + + + PWM_SYNC_KILL + Specifies asynchronous/synchronous kill behavior: +'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. +'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. + +This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. + [2:2] + read-write + + + PWM_STOP_ON_KILL + Specifies whether the counter stops on a kill events: +'0': kill event does NOT stop counter. +'1': kill event stops counter. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [3:3] + read-write + + + GENERIC + Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. + [15:8] + read-write + + + UP_DOWN_MODE + Determines counter direction. + [17:16] + read-write + + + COUNT_UP + Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. + 0 + + + COUNT_DOWN + Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 1 + + + COUNT_UPDN1 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 2 + + + COUNT_UPDN2 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). + 3 + + + + + ONE_SHOT + When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. + [18:18] + read-write + + + QUADRATURE_MODE + In QUAD mode selects quadrature encoding mode (X1/X2/X4). +In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1]. + [21:20] + read-write + + + X1 + X1 encoding (QUAD mode) + 0 + + + X2 + X2 encoding (QUAD mode) + 1 + + + X4 + X4 encoding (QUAD mode) + 2 + + + + + MODE + Counter mode. + [26:24] + read-write + + + TIMER + Timer mode + 0 + + + CAPTURE + Capture mode + 2 + + + QUAD + Quadrature encoding mode + 3 + + + PWM + Pulse width modulation (PWM) mode + 4 + + + PWM_DT + PWM with deadtime insertion mode + 5 + + + PWM_PR + Pseudo random pulse width modulation + 6 + + + + + + + STATUS + Counter status register + 0x4 + 32 + read-only + 0x0 + 0x8000FF01 + + + DOWN + When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. + [0:0] + read-only + + + GENERIC + Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. + [15:8] + read-only + + + RUNNING + When '0', the counter is NOT running. When '1', the counter is running. + [31:31] + read-only + + + + + COUNTER + Counter count register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER + 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. + [31:0] + read-write + + + + + CC + Counter compare/capture register + 0xC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC_BUFF + Counter buffered compare/capture register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC register. + [31:0] + read-write + + + + + PERIOD + Counter period register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. + [31:0] + read-write + + + + + PERIOD_BUFF + Counter buffered period register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Additional buffer for counter PERIOD register. + [31:0] + read-write + + + + + TR_CTRL0 + Counter trigger control register 0 + 0x20 + 32 + read-write + 0x10 + 0xFFFFF + + + CAPTURE_SEL + Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. + [3:0] + read-write + + + COUNT_SEL + Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. + [7:4] + read-write + + + RELOAD_SEL + Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint). + [11:8] + read-write + + + STOP_SEL + Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. + [15:12] + read-write + + + START_SEL + Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). + [19:16] + read-write + + + + + TR_CTRL1 + Counter trigger control register 1 + 0x24 + 32 + read-write + 0x3FF + 0x3FF + + + CAPTURE_EDGE + A capture event will copy the counter value into the CC register. + [1:0] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + COUNT_EDGE + A counter event will increase or decrease the counter by '1'. + [3:2] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + RELOAD_EDGE + A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. + [5:4] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + STOP_EDGE + A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. + [7:6] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + START_EDGE + A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. + [9:8] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + + + TR_CTRL2 + Counter trigger control register 2 + 0x28 + 32 + read-write + 0x3F + 0x3F + + + CC_MATCH_MODE + Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. +To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. + [1:0] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + OVERFLOW_MODE + Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. + [3:2] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + UNDERFLOW_MODE + Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. + [5:4] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + + + INTR + Interrupt request register + 0x30 + 32 + read-write + 0x0 + 0x3 + + + TC + Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. + [0:0] + read-write + + + CC_MATCH + Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + Interrupt set request register + 0x34 + 32 + read-write + 0x0 + 0x3 + + + TC + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + CC_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x38 + 32 + read-write + 0x0 + 0x3 + + + TC + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + CC_MATCH + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x3C + 32 + read-only + 0x0 + 0x3 + + + TC + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CC_MATCH + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + + + + TCPWM1 + 0x40390000 + + + LCD0 + LCD Controller Block + LCD + 0x403B0000 + + 0 + 65536 + registers + + + + ID + ID & Revision + 0x0 + 32 + read-only + 0x1F0F0 + 0xFFFFFFFF + + + ID + the ID of LCD controller peripheral is 0xF0F0 + [15:0] + read-only + + + REVISION + the version number is 0x0001 + [31:16] + read-only + + + + + DIVIDER + LCD Divider Register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SUBFR_DIV + Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. + [15:0] + read-write + + + DEAD_DIV + Length of the dead time period in cycles. When set to zero, no dead time period exists. + [31:16] + read-write + + + + + CONTROL + LCD Configuration Register + 0x8 + 32 + read-write + 0x0 + 0x80000F7F + + + LS_EN + Low speed (LS) generator enable +1: enable +0: disable + [0:0] + read-write + + + HS_EN + High speed (HS) generator enable +1: enable +0: disable + [1:1] + read-write + + + LCD_MODE + HS/LS Mode selection + [2:2] + read-write + + + LS + Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes). + 0 + + + HS + Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). + 1 + + + + + TYPE + LCD driving waveform type configuration. + [3:3] + read-write + + + TYPE_A + Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. + 0 + + + TYPE_B + Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). + 1 + + + + + OP_MODE + Driving mode configuration + [4:4] + read-write + + + PWM + PWM Mode + 0 + + + CORRELATION + Digital Correlation Mode + 1 + + + + + BIAS + PWM bias selection + [6:5] + read-write + + + HALF + 1/2 Bias + 0 + + + THIRD + 1/3 Bias + 1 + + + FOURTH + 1/4 Bias (not supported by LS generator) + 2 + + + FIFTH + 1/5 Bias (not supported by LS generator) + 3 + + + + + COM_NUM + The number of COM connections minus 2. So: +0: 2 COM's +1: 3 COM's +... +13: 15 COM's +14: 16 COM's +15: undefined + [11:8] + read-write + + + LS_EN_STAT + LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. +The following procedure should be followed to disable the LS generator: +1. If LS_EN=0 we are done. Exit the procedure. +2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. +3. Set LS_EN=0. +4. Wait until LS_EN_STAT=0. + [31:31] + read-only + + + + + 8 + 4 + DATA0[%s] + LCD Pin Data Registers + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA1[%s] + LCD Pin Data Registers + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA2[%s] + LCD Pin Data Registers + 0x300 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA3[%s] + LCD Pin Data Registers + 0x400 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). + [31:0] + read-write + + + + + + + BLE + Bluetooth Low Energy Subsystem + 0x403C0000 + + 0 + 131072 + registers + + + + RCB + Radio Control Bus (RCB) controller + 0x00000000 + + CTRL + RCB control register. + 0x0 + 32 + read-write + 0xF80000 + 0x80FFFF3E + + + TX_CLK_EDGE + Clock edge used for transmitting (Transmision uses internal core clock) +0: Negative Edge (Default) +1: Positive Edge + [1:1] + read-write + + + RX_CLK_EDGE + Clock edge used for sampling the received data (Sampling uses clock selected by RX_CLK_SRC) +0: Negative Edge (Default) +1: Positive Edge +Note: For RX_CLK_SRC =1, when pad clock is used as sampling clock, this field is ignored + [2:2] + read-write + + + RX_CLK_SRC + Clock to be used for sampling the received data +0: Internal clock (Default) +1: Clock from the SCK pad + +When Clock from the SCK pad is used, sampling is always on negedge only + [3:3] + read-write + + + SCLK_CONTINUOUS + Controls the behaviour of the RCB clock +'0': SCLK is generated, only when the RCB controller is enabled and data is transmitted. +'1': SCLK is generated, when the RCB controller is enabled. + [4:4] + read-write + + + SSEL_POLARITY + Slave select polarity. SSEL_POLARITY applies to the outgoing slave select signal +'0': slave select is low/'0' active. +'1': slave select is high/'1' active. + [5:5] + read-write + + + LEAD + N/A + [9:8] + read-write + + + LAG + N/A + [11:10] + read-write + + + DIV_ENABLED + Enable for RCB Clock Divider. +The internal core clock divider is bypassed when DIV_ENABLED=0 + [12:12] + read-write + + + DIV + The internal core clock divider factor when DIV_ENABLED=1 +Divider factor: 2*DIV. Max DIV value supported is 31. +DIV value of zero is not supported. Make DIV_ENABLED=0 for undivided clock + [18:13] + read-write + + + ADDR_WIDTH + Width of Address phase (includes read/write mode bit) of the Dataframe width. ADDR_WIDTH + 1 is the amount of bits in a transmitted data frame. Allowed legal values are 'd8, 'd10 and 'd15 + [22:19] + read-write + + + DATA_WIDTH + Width of Data phase of the transmit Dataframe width. +0 - 8 bits +1 - 16 bits + [23:23] + read-write + + + ENABLED + IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: +- Program protocol specific information using CTRL except ENABLED field. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL to enable IP. +When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the edges, dividers. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + [31:31] + read-write + + + + + STATUS + RCB status register. + 0x4 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + RCB bus is busy. The bus is considered busy ('1') during an ongoing transaction. + [0:0] + read-only + + + + + TX_CTRL + Transmitter control register. + 0x10 + 32 + read-write + 0x21 + 0x7F + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). +This field also affects the Address field +When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address +When MSB_FIRST = 0, then [15:0] is for data. No address field + [0:0] + read-write + + + FIFO_RECONFIG + Setting this bit, clears the FIFO and resets the pointer + [1:1] + read-write + + + TX_ENTRIES + This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 only + [6:2] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control register. + 0x14 + 32 + read-write + 0x0 + 0x1001F + + + TX_TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated. + [4:0] + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status register. + 0x18 + 32 + read-only + 0x0 + 0xF0F801F + + + USED + Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to 16 + [4:0] + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + [19:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + [27:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write register. + 0x1C + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. +A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. + [31:0] + write-only + + + + + RX_CTRL + Receiver control register. + 0x20 + 32 + read-write + 0x1 + 0x1 + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). +This field also affects the Address field +When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address +When MSB_FIRST = 0, then [15:0] is for data. No address field + [0:0] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control register. + 0x24 + 32 + read-write + 0x0 + 0x1000F + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated. + [3:0] + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status register. + 0x28 + 32 + read-only + 0x0 + 0xF0F801F + + + USED + Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR. + [4:0] + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + [19:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + [27:24] + read-only + + + + + RX_FIFO_RD + Receiver FIFO read register. + 0x2C + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. +During debug it may be required to read the FIFO without a corresponding POP of the FIFO. This can be achieved by using the RX_FIFO_RD_SILENT register + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read register. + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [31:0] + read-only + + + + + INTR + Master interrupt request register. + 0x40 + 32 + read-write + 0x600 + 0x1F1F01 + + + RCB_DONE + RCB Controller transfer done event. On completion of every RCB transaction, this bit is set + [0:0] + read-write + + + TX_FIFO_TRIGGER + Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL. + [8:8] + read-write + + + TX_FIFO_NOT_FULL + TX FIFO is not full. entries != TX_ENTRIES + [9:9] + read-write + + + TX_FIFO_EMPTY + TX FIFO is empty; i.e. it has 0 entries. + [10:10] + read-write + + + TX_FIFO_OVERFLOW + Attempt to write to a full TX FIFO. + [11:11] + read-write + + + TX_FIFO_UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. + [12:12] + read-write + + + RX_FIFO_TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL. + [16:16] + read-write + + + RX_FIFO_NOT_EMPTY + RX FIFO is not empty. + [17:17] + read-write + + + RX_FIFO_FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. entries == (16-TX_ENTRIES_ + [18:18] + read-write + + + RX_FIFO_OVERFLOW + Attempt to write to a full RX FIFO. + [19:19] + read-write + + + RX_FIFO_UNDERFLOW + Attempt to read from an empty RX FIFO. + [20:20] + read-write + + + + + INTR_SET + Master interrupt set request register + 0x44 + 32 + read-write + 0x600 + 0x1F1F01 + + + RCB_DONE + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_FIFO_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + TX_FIFO_NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + TX_FIFO_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + TX_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + TX_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [12:12] + read-write + + + RX_FIFO_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_FIFO_NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [17:17] + read-write + + + RX_FIFO_FULL + Write with '1' to set corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [20:20] + read-write + + + + + INTR_MASK + Master interrupt mask register. + 0x48 + 32 + read-write + 0x0 + 0x1F1F01 + + + RCB_DONE + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_FIFO_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + TX_FIFO_NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + TX_FIFO_EMPTY + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + TX_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + TX_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [12:12] + read-write + + + RX_FIFO_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_FIFO_NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [17:17] + read-write + + + RX_FIFO_FULL + Mask bit for corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [20:20] + read-write + + + + + INTR_MASKED + Master interrupt masked request register + 0x4C + 32 + read-only + 0x0 + 0x1F1F01 + + + RCB_DONE + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TX_FIFO_TRIGGER + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + TX_FIFO_NOT_FULL + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + TX_FIFO_EMPTY + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + TX_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + TX_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [12:12] + read-only + + + RX_FIFO_TRIGGER + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + RX_FIFO_NOT_EMPTY + Logical and of corresponding request and mask bits. + [17:17] + read-only + + + RX_FIFO_FULL + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + RX_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [19:19] + read-only + + + RX_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [20:20] + read-only + + + + + RCBLL + Radio Control Bus (RCB) & Link Layer controller + 0x00000100 + + CTRL + RCB LL control register. + 0x0 + 32 + read-write + 0x0 + 0x3F + + + RCBLL_CTRL + RCB register access control +0: RCB registers can be accessed by CPU +1: RCB registers can be accessed by BLE Link Layer. + +FW sets this bit to give the access control to BLE link layer +HW clears this bit to 0 to give the access control to CPU (HW clears this when the RCB controller is free abd RCB?_LL_CPU_REQ is set to 1) + [0:0] + read-write + + + RCBLL_CPU_REQ + RCB register access control request by CPU +FW sets this bit to take the RCB register access control +Once the HW is done with the current transactions, it clears this bit to give control to CPU +And also indicates this by giving RCB_LL_DONE interrupt + [1:1] + read-write + + + CPU_SINGLE_WRITE + N/A + [2:2] + read-write + + + CPU_SINGLE_READ + N/A + [3:3] + read-write + + + ALLOW_CPU_ACCESS_TX_RX + This bit indicates if CPU Single Read/Single Write are allowed when Radio RX/TX is ongoing. By default this bit is 0 and no RCB access from CPU are allowed during BLE RX/TX. + [4:4] + read-write + + + ENABLE_RADIO_BOD + This bit indicates if the active logic in CYBLERD55 is reset on every TX/RX transaction. + [5:5] + read-write + + + + + INTR + Master interrupt request register. + 0x10 + 32 + read-write + 0x0 + 0xD + + + RCB_LL_DONE + RCB_LL is done and the access is given back to CPU + [0:0] + read-write + + + SINGLE_WRITE_DONE + N/A + [2:2] + read-write + + + SINGLE_READ_DONE + N/A + [3:3] + read-write + + + + + INTR_SET + Master interrupt set request register + 0x14 + 32 + read-write + 0x0 + 0xD + + + RCB_LL_DONE + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + SINGLE_WRITE_DONE + N/A + [2:2] + read-write + + + SINGLE_READ_DONE + N/A + [3:3] + read-write + + + + + INTR_MASK + Master interrupt mask register. + 0x18 + 32 + read-write + 0x0 + 0xD + + + RCB_LL_DONE + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + SINGLE_WRITE_DONE + N/A + [2:2] + read-write + + + SINGLE_READ_DONE + N/A + [3:3] + read-write + + + + + INTR_MASKED + Master interrupt masked request register + 0x1C + 32 + read-only + 0x0 + 0xD + + + RCB_LL_DONE + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + SINGLE_WRITE_DONE + N/A + [2:2] + read-only + + + SINGLE_READ_DONE + N/A + [3:3] + read-only + + + + + RADIO_REG1_ADDR + Address of Register#1 in Radio (MDON) + 0x20 + 32 + read-write + 0x1E02 + 0xFFFF + + + REG_ADDR + N/A + [15:0] + read-write + + + + + RADIO_REG2_ADDR + Address of Register#2 in Radio (RSSI) + 0x24 + 32 + read-write + 0xA03 + 0xFFFF + + + REG_ADDR + N/A + [15:0] + read-write + + + + + RADIO_REG3_ADDR + Address of Register#3 in Radio (ACCL) + 0x28 + 32 + read-write + 0x824 + 0xFFFF + + + REG_ADDR + N/A + [15:0] + read-write + + + + + RADIO_REG4_ADDR + Address of Register#4 in Radio (ACCH) + 0x2C + 32 + read-write + 0x823 + 0xFFFF + + + REG_ADDR + N/A + [15:0] + read-write + + + + + RADIO_REG5_ADDR + Address of Register#5 in Radio (RSSI ENERGY) + 0x30 + 32 + read-write + 0xA03 + 0xFFFF + + + REG_ADDR + N/A + [15:0] + read-write + + + + + CPU_WRITE_REG + N/A + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + N/A + [15:0] + read-write + + + WRITE_DATA + N/A + [31:16] + read-write + + + + + CPU_READ_REG + N/A + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + N/A + [15:0] + read-write + + + READ_DATA + N/A + [31:16] + read-only + + + + + + + BLELL + Bluetooth Low Energy Link Layer + 0x00001000 + + COMMAND_REGISTER + Instruction Register + 0x0 + 32 + write-only + 0x0 + 0xFF + + + COMMAND + N/A + [7:0] + write-only + + + + + EVENT_INTR + Event(Interrupt) status and Clear register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + ADV_INTR + Advertiser interrupt. If bit is set to 1, it indicates an event occurred in the advertising procedure. The source of the event needs to be read from the ADV_INTR register. +This bit is cleared, when firmware clears ALL interrupts by writing to the ADV_INTR register. + [0:0] + read-only + + + SCAN_INTR + Scanner interrupt. If bit is set to 1, it indicates an event occurred in the scanning procedure. The source of the event needs to be read from the SCAN_INTR register. +This bit is cleared, when firmware clears ALL interrupts by writing to the SCAN_INTR register. + [1:1] + read-only + + + INIT_INTR + Initiator interrupt. If bit is set to 1, it indicates an event occurred in the initiating procedure. The source of the event needs to be read from the INIT_INTR register. +This bit is cleared, when firmware clears ALL interrupts by writing to the INIT_INTR register. + [2:2] + read-only + + + CONN_INTR + Connection interrupt. If bit is set to 1, it indicates an event occurred in the connection operation. This interrupt is aggregation of interrupts for all the connections. The source of the event for the specific connection, needs to be read from the CONN_INTR register specific to the connection. This bit is cleared, when firmware clears ALL interrupts by writing to the CONN_INTR register. + [3:3] + read-only + + + SM_INTR + Read: Sleep-mode-exit interrupt. This bit is set, when link layer hardware exits from sleep mode. +Write: Clear sleep-mode-exit interrupt. Write to the register with this bit set to 1, clears the interrupt source. +This interrupt is deprecated and should not be used. + [4:4] + read-write + + + DSM_INTR + Read: Deep sleep mode exit interrupt. This bit is set, when link layer hardware exits from deep sleep mode. +Write: Clear deep sleep mode exit interrupt. Write to the register with this bit set to 1, clears the interrupt source. + [5:5] + read-write + + + ENC_INTR + Encryption module interrupt. +This interrupt id deprecated and should not be used + [6:6] + read-only + + + RSSI_RX_DONE_INTR + RSSI RX done interrupt. + [7:7] + read-only + + + + + EVENT_ENABLE + Event indications enable. + 0x10 + 32 + read-write + 0x0 + 0xFF + + + ADV_INT_EN + Advertiser interrupt enable. +1 - enable advertiser procedure to interrupt the firmware. +0 - disable advertiser procedure interrupt to firmware. + [0:0] + read-write + + + SCN_INT_EN + Scanner interrupt enable. +1 - enable scan procedure to interrupt the firmware. +0 - disable scan procedure interrupt to firmware. + [1:1] + read-write + + + INIT_INT_EN + Initiator interrupt enable. +1 - enable initiator procedure to interrupt the firmware. +0 - disable initiator procedure interrupt to firmware. + [2:2] + read-write + + + CONN_INT_EN + Connection interrupt enable. +1 - enable connection procedure to interrupt the firmware. +0 - disable connection procedure interrupt to firmware. + [3:3] + read-write + + + SM_INT_EN + Sleep-mode-exit interrupt enable. +1 - enable sleep mode exit event to interrupt the firmware. +0 - disable sleep mode exit interrupt to firmware. +This interrupt is deprecated and should not be used. + [4:4] + read-write + + + DSM_INT_EN + Deep Sleep-mode-exit interrupt enable. +1 - enable deep sleep mode exit event to interrupt the firmware. +0 - disable deep sleep mode exit interrupt to firmware. + [5:5] + read-write + + + ENC_INT_EN + Encryption module interrupt enable. +1 - Enable encryption module interrupt to firmware. +0 - disable encryption module interrupt to firmware. +This interrupt is deprecated and should not be used + [6:6] + read-write + + + RSSI_RX_DONE_INT_EN + RSSI Rx interrupt enable. +1 - Enable RSSI Rx done interrupt to firmware. +0 - Disable RSSI Rx done interrupt to firmware. + [7:7] + read-write + + + + + ADV_PARAMS + Advertising parameters register. + 0x18 + 32 + read-write + 0xE0 + 0xFFFF + + + TX_ADDR + Device own address type. +1 - Address type is random. +0 - Address type is public. + [0:0] + read-write + + + ADV_TYPE + The Advertising type is used to determine the packet type that is used for advertising when advertising is enabled. +0x0 - Connectable undirected advertising. (adv_ind) +0x1 - Connectable directed advertising (adv_direct_ind). +0x2 - Discoverable undirected advertising (adv_discover_ind) +0x3 - Non connectable undirected advertising (adv_nonconn_ind). + [2:1] + read-write + + + ADV_FILT_POLICY + Advertising filter policy. The set of devices that the advertising procedure uses for device filtering is called the White List. +0x0 - Allow scan request from any device, allow connect request from any device. +0x1 - Allow scan request from devices in white list only, allow connect request from any device. +0x2 - Allow scan request from any device, allow connect request from devices in white list only. +0x3 - Allow scan request from devices in white list only, allow connect request from devices in white list only. + [4:3] + read-write + + + ADV_CHANNEL_MAP + Advertising channel map indicates the advertising channels used for advertising. By setting the bit, corresponding channel is enabled for use. Atleast one channel bit should be set. +7 - enable channel 39. +6 - enable channel 38. +5 - enable channel 37. + [7:5] + read-write + + + RX_ADDR + Peer addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent. +1 - Rx addr type is random. +0 - Rx addr type is public + [8:8] + read-write + + + RX_SEC_ADDR + Peer secondary addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent. This address type corresponds to the PEER_SERC_ADDR register. Valid only if PRIV_1_2_ADV is set. +1 - Rx secondary addr type is random. +0 - Rx secondary addr type is public + [9:9] + read-write + + + ADV_LOW_DUTY_CYCLE + This bit field is used to specify to the Controller the Low Duty Cycle connectable directed advertising variant being used. +1 - Low Duty Cycle Connectable Directed Advertising. +0 - High Duty Cycle Connectable Directed Advertising. + [10:10] + read-write + + + INITA_RPA_CHECK + This bit field is used to specify the Advertiser behavior on receiving the same INITA in the connect_req as in the ADV_DIRECT_IND packet it sent. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. +0 - Accept the connect_req packet +1 - Reject the connect_req packet + [11:11] + read-write + + + TX_ADDR_PRIV + Device own address type subtype when Address type is random. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. +1 - Random Address type is private. +0 - Random Address type is static. + [12:12] + read-write + + + ADV_RCV_IA_IN_PRIV + Advertiser behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. +1 - Accept packets with peer identity address not in the Resolving list in privacy mode +0 - Reject packets with peer identity address not in the Resolving list in privacy mode + [13:13] + read-write + + + ADV_RPT_PEER_NRPA_ADDR_IN_PRIV + Advertiser behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. This is applicable when whitelist is disabled. +1 - Only report the packets with peer NRPA address in privacy mode +0 - Respond to packets with peer NRPA address in privacy mode + [14:14] + read-write + + + RCV_TX_ADDR + Transmit address field of the received packet extracted from the receive packet. This field is used by firmware to report peer_addr_type parameter in the connection complete event. + [15:15] + read-only + + + + + ADV_INTERVAL_TIMEOUT + Advertising interval register. + 0x1C + 32 + read-write + 0x20 + 0x7FFF + + + ADV_INTERVAL + Range: 0x0020 to 0x4000 (For ADV_IND) +0x00A0 to 0x4000 (For ADV_SCAN_IND and NONCONN_IND) +Invalid for ADV_DIRECT_IND +Time = N * 0.625 msec +Time Range: 20 ms to 10.24 sec. +For directed advertising, firmware programs the default value of 1.28 seconds. + +In MMMS mode, this register is used as ADV_NI_TIMER when the ADV_NI_VALID is set by firmware + [14:0] + read-write + + + + + ADV_INTR + Advertising interrupt status and Clear register + 0x20 + 32 + read-write + 0x0 + 0x1FFF + + + ADV_STRT_INTR + If this bit is set it indicates a new advertising event started after interval expiry. +Write to the register with this bit set to 1, clears the interrupt source. + [0:0] + read-write + + + ADV_CLOSE_INTR + If this bit is set it indicates current advertising event is closed. +Write to the register with this bit set to 1, clears the interrupt source. + [1:1] + read-write + + + ADV_TX_INTR + If this bit is set it indicates ADV packet is transmitted. +Write to the register with this bit set to 1, clears the interrupt source. + [2:2] + read-write + + + SCAN_RSP_TX_INTR + If this bit is set it indicates scan response packet transmitted in response to previous scan request packet received. +Write to the register with this bit set to 1, clears the interrupt source. + [3:3] + read-write + + + SCAN_REQ_RX_INTR + If this bit is set it indicates scan request packet received. +Write to the register with this bit set to 1, clears the interrupt source. + [4:4] + read-write + + + CONN_REQ_RX_INTR + If this bit is set it indicates connect request packet is received. +Write to the register with this bit set to 1, clears the interrupt source. + [5:5] + read-write + + + SLV_CONNECTED + If this bit is set it indicates that connection is created as slave. +Write to the register with this bit set to 1, clears the interrupt source. +Note: On a slave connection creation, the link layer cannot enter deepsleep mode in the same slot . It can enter deepsleep mode only in the subsequent slots. + [6:6] + read-write + + + ADV_TIMEOUT + If this bit is set it indicates that the directed advertising event has timed out after 1.28 seconds. Applicable in adv_direct_ind advertising. +Write to the register with this bit set to 1, clears the interrupt source. + [7:7] + read-write + + + ADV_ON + Advertiser procedure is ON in hardware. Indicates that advertiser procedure is ON in hardware. +1 - ON +0 - OFF + [8:8] + read-only + + + SLV_CONN_PEER_RPA_UNMCH_INTR + If this bit is set it indicates that connection is created as slave, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. If the address is not resolved prior to connection establishment, the connection will be terminated. +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. + [9:9] + read-write + + + SCAN_REQ_RX_PEER_RPA_UNMCH_INTR + If this bit is set it indicates scan request packet received, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. + [10:10] + read-write + + + INIT_ADDR_MATCH_PRIV_MISMATCH_INTR + If this bit is set it indicates that an Identity address is received from a Scanner and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the Scanner +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. + [11:11] + read-write + + + SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR + If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. + [12:12] + read-write + + + + + ADV_NEXT_INSTANT + Advertising next instant. + 0x24 + 32 + read-only + 0x0 + 0xFFFF + + + ADV_NEXT_INSTANT + Shows the next start of advertising event with reference to the internal reference clock. + [15:0] + read-only + + + + + SCAN_INTERVAL + Scan Interval Register + 0x28 + 32 + read-write + 0x10 + 0xFFFF + + + SCAN_INTERVAL + Scan interval register. Interval between two consecutive scanning events. Firmware sets the scanning interval value to this register before issuing start scan command. +Range: 0x0004 to 0x4000 +Default: 0x0010 (10 ms) +Time = N * 0.625 msec +Time Range: 2.5 msec to 10.24 sec. + +In MMMS mode, this register is used as SCAN_NI_TIMER when the SCAN_NI_VALID is set by firmware + [15:0] + read-write + + + + + SCAN_WINDOW + Scan window Register + 0x2C + 32 + read-write + 0x10 + 0xFFFF + + + SCAN_WINDOW + Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing start scan command. +Range: 0x0004 to 0x4000 +Default: 0x0010 (10 ms) +Time = N * 0.625 msec +Time Range: 2.5 msec to 10.24 sec. +(To prevent ADV RX - SCAN REQ TX - SCAN RSP RX spilling over across the scan window, when not in continuous scan, the scan window must be 2 slots less that the scan interval. + [15:0] + read-write + + + + + SCAN_PARAM + Scanning parameters register + 0x30 + 32 + read-write + 0x0 + 0x3FF + + + TX_ADDR + Device's own address type. +1 - addr type is random. +0 - addr type is public. + [0:0] + read-write + + + SCAN_TYPE + 0x00 - passive scanning.(default) +0x01 - active scanning. +0x10 - RFU +0x11 - RFU + [2:1] + read-write + + + SCAN_FILT_POLICY + The scanner filter policy determines how the scanner processes advertising packets. +0x00 - Accept advertising packets from any device. +0x01 - Accept advertising packets from only devices in the whitelist. +In the above 2 policies, the directed advertising packets which are not addressed to this device are ignored. +0x10 - Accept all undirected advertising packets and directed advertising packet addressed to this device. +0x11 - Accept undirected advertising packets from devices in the whitelist and directed advertising packet addressed to this device +In the above 2 policies, the directed advertising packets where the initiator address is a resolvable private address are accepted. The above 2 policies are extended scanner filter policies. + [4:3] + read-write + + + DUP_FILT_EN + Filter duplicate packets. +1- Duplicate filtering enabled. +0- Duplicate filtering not enabled. +This field is derived from the LE_set_scan_enable command. + [5:5] + read-write + + + DUP_FILT_CHK_ADV_DIR + This bit field is used to specify the Scanner duplicate filter behavior for ADV_DIRECT_IND packet when duplicate DUP_FILT_EN is set. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. +0 - Do not filter ADV_DIRECT_IND duplicate packets. +1 - Filter ADV_DIRECT_IND duplicate packets + [6:6] + read-write + + + SCAN_RSP_ADVA_CHECK + This bit field is used to specify the Scanner behavior with respect to ADVA while receiving a SCAN_RSP packet. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. +0 - The ADVA in SCAN_RSP packets are not verified +1 - The ADVA in SCAN_RSP packets are verified against ADVA received in ADV packet . If it fails, then abort the packet. + [7:7] + read-write + + + SCAN_RCV_IA_IN_PRIV + Scanner behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. +1 - Accept packets with peer identity address not in the Resolving list in privacy mode +0 - Reject packets with peer identity address not in the Resolving list in privacy mode + [8:8] + read-write + + + SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV + Scanner behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. This is applicable when whitelist is disabled. +1 - Only report packets with peer NRPA address in privacy mode +0 - Respond packets with peer NRPA address in privacy mode + [9:9] + read-write + + + + + SCAN_INTR + Scan interrupt status and Clear register + 0x38 + 32 + read-write + 0x0 + 0x7FF + + + SCAN_STRT_INTR + If this bit is set it indicates scan window is opened. +Write to the register with this bit set to 1, clears the interrupt source. + [0:0] + read-write + + + SCAN_CLOSE_INTR + If this bit is set it indicates scan window is closed. +Write to the register with this bit set to 1, clears the interrupt source. + [1:1] + read-write + + + SCAN_TX_INTR + If this bit is set it indicates scan request packet is transmitted. +Write to the register with this bit set to 1, clears the interrupt source. + [2:2] + read-write + + + ADV_RX_INTR + If this bit is set it indicates ADV packet received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. +Write to the register with this bit set to 1, clears the interrupt source. +This interrupt is generated while active/passive scanning upon receiving adv packets. +Note: Any ADV RX interrupt received after issuing SCAN_STOP command must be ignored and the ADVCH FIFO flushed. + [3:3] + read-write + + + SCAN_RSP_RX_INTR + If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. +Write to the register with this bit set to 1, clears the interrupt source. +NOTE: This interrupt is generated while active scanning upon receiving scan response packet. + [4:4] + read-write + + + ADV_RX_PEER_RPA_UNMCH_INTR + If this bit is set it indicates ADV packet received but the peer device Address is not match yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. +Write to the register with this bit set to 1, clears the interrupt source. +This interrupt is generated while active/passive scanning upon receiving adv packets. + [5:5] + read-write + + + ADV_RX_SELF_RPA_UNMCH_INTR + If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. +Write to the register with this bit set to 1, clears the interrupt source. +This interrupt is generated while active/passive scanning upon receiving adv_direct packets. + [6:6] + read-write + + + SCANA_TX_ADDR_NOT_SET_INTR + If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ packet in response to an ADV packet is not present in the resolving list +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. + [7:7] + read-write + + + SCAN_ON + Scan procedure status. +1 - scan procedure is active. +0 - scan procedure is not active. + [8:8] + read-only + + + PEER_ADDR_MATCH_PRIV_MISMATCH_INTR + If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. + [9:9] + read-write + + + SELF_ADDR_MATCH_PRIV_MISMATCH_INTR + If this bit is set it indicates that the self Identity address is received from an initiator and matches, but self IRK is set and hence a corresponding RPA is expected from the initiator +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. + [10:10] + read-write + + + + + SCAN_NEXT_INSTANT + Advertising next instant. + 0x3C + 32 + read-only + 0x0 + 0xFFFF + + + NEXT_SCAN_INSTANT + Shows the instant with respect to internal reference clock of resolution 625 us at which next scanning event begins. + [15:0] + read-only + + + + + INIT_INTERVAL + Initiator Interval Register + 0x40 + 32 + read-write + 0x0 + 0xFFFF + + + INIT_SCAN_INTERVAL + Initiator interval register. Firmware sets the initiator's scanning interval value to this regis-ter before issuing create connection command. Interval between two consecutive scanning events. +Range: 0x0004 to 0x4000 +Time = N * 0.625 msec +Time Range: 2.5 msec to 10.24 sec. + +In MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware + [15:0] + read-write + + + + + INIT_WINDOW + Initiator window Register + 0x44 + 32 + read-write + 0x0 + 0xFFFF + + + INIT_SCAN_WINDOW + Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing create connection command. +Range: 0x0004 to 0x4000 +Time = N * 0.625 msec +Time Range: 2.5 msec to 10.24 sec. + +In MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware + [15:0] + read-write + + + + + INIT_PARAM + Initiator parameters register + 0x48 + 32 + read-write + 0x0 + 0x1B + + + TX_ADDR + Device' own address type. +1 - addr type is random. +0 - addr type is public. + [0:0] + read-write + + + RX_ADDR__RX_TX_ADDR + Peer address type. +The rx_addr field is updated by the receiver with the address type of the received connectable advertising packet. +1 - addr type is random. +0 - addr type is public. + [1:1] + read-write + + + INIT_FILT_POLICY + The Initiator_Filter_Policy is used to determine whether the White List is used or not. +0 - White list is not used to determine which advertiser to connect to. Instead the Peer_Address_Type and Peer Address fields are used to specify the address type and address of the advertising device to connect to. +1 - White list is used to determine the advertising device to connect to. +Peer_Address_Type and Peer_Address fields are ignored when whitelist is used. + [3:3] + read-write + + + INIT_RCV_IA_IN_PRIV + Init behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. +1 - Accept packets with peer identity address not in the Resolving list in privacy mode +0 - Reject packets with peer identity address not in the Resolving list in privacy mode & HW_RSLV_LIST_FULL is not set + [4:4] + read-write + + + + + INIT_INTR + Scan interrupt status and Clear register + 0x50 + 32 + read-write + 0x0 + 0x3F7 + + + INIT_INTERVAL_EXPIRE_INTR + If this bit is set it indicates initiator scan window has started. +Write to the register with this bit set to 1, clears the interrupt source. + [0:0] + read-write + + + INIT_CLOSE_WINDOW_INR + If this bit is set it indicates initiator scan window has finished. +Write to the register with this bit set to 1, clears the interrupt source. + [1:1] + read-write + + + INIT_TX_START_INTR + If this bit is set it indicates initiator packet (CONREQ) transmission has started. +Write to the register with this bit set to 1, clears the interrupt source. + [2:2] + read-write + + + MASTER_CONN_CREATED + If this bit is set it indicates connection is created as master. +Write to the register with this bit set to 1, clears the interrupt source. + [4:4] + read-write + + + ADV_RX_SELF_ADDR_UNMCH_INTR + If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. +Write to the register with this bit set to 1, clears the interrupt source. +This interrupt is generated while active/passive scanning upon receiving adv packets. + [5:5] + read-write + + + ADV_RX_PEER_ADDR_UNMCH_INTR + If this bit is set it indicates ADV packet received but the peer device Address is not matched yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. +Write to the register with this bit set to 1, clears the interrupt source. +This interrupt is generated while active/passive scanning upon receiving adv packets. + [6:6] + read-write + + + INITA_TX_ADDR_NOT_SET_INTR + If this bit is set it indicates that a valid INITA RPA to be transmitted in CONN_REQ packet in response to an ADV packet is not present in the resolving list +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. + [7:7] + read-write + + + INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR + If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. + [8:8] + read-write + + + INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR + If this bit is set it indicates that +- an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator +- or an RPA is received from an initiator and matches an entry in the resolving list, but peer IRK is not set and hence a corresponding Identity address is expected from the initiator +Write to the register with this bit set to 1, clears the interrupt source. +This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. + [9:9] + read-write + + + + + INIT_NEXT_INSTANT + Initiator next instant. + 0x54 + 32 + read-only + 0x0 + 0xFFFF + + + INIT_NEXT_INSTANT + Shows the instant with respect to internal reference clock of resolution 625 us at which next initiator scanning event begins. + [15:0] + read-only + + + + + DEVICE_RAND_ADDR_L + Lower 16 bit random address of the device. + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + DEVICE_RAND_ADDR_L + Lower 16 bit of 48-bit random address of the device. + [15:0] + read-write + + + + + DEVICE_RAND_ADDR_M + Middle 16 bit random address of the device. + 0x5C + 32 + read-write + 0x0 + 0xFFFF + + + DEVICE_RAND_ADDR_M + Middle 16 bit of 48-bit random address of the device. + [15:0] + read-write + + + + + DEVICE_RAND_ADDR_H + Higher 16 bit random address of the device. + 0x60 + 32 + read-write + 0x0 + 0xFFFF + + + DEVICE_RAND_ADDR_H + Higher 16 bit of 48-bit random address of the device. + [15:0] + read-write + + + + + PEER_ADDR_L + Lower 16 bit address of the peer device. + 0x68 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_ADDR_L + Lower 16 bit of 48-bit address of the peer device. + [15:0] + read-write + + + + + PEER_ADDR_M + Middle 16 bit address of the peer device. + 0x6C + 32 + read-write + 0x0 + 0xFFFF + + + PEER_ADDR_M + Middle 16 bit of 48-bit address of the peer device. + [15:0] + read-write + + + + + PEER_ADDR_H + Higher 16 bit address of the peer device. + 0x70 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_ADDR_H + Higher 16 bit of 48-bit address of the peer device. +The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. + +While doing directed Advertising, the firmware writes the peer address of the device specified by the Di-rect_Address parameter of the LE_Set_Advertising_Parameters command. + +In non MMMS mode, While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. + +In non MMMS mode, While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. + +When a connection is created as a slave, the firmware can read this register to get the address of the peer de-vice to which connection is created. + [15:0] + read-write + + + + + WL_ADDR_TYPE + whitelist address type + 0x78 + 32 + read-write + 0x0 + 0xFFFF + + + WL_ADDR_TYPE + 8 address type bits corresponding to the device address stored. +1 - Address type is random. +0 - Address type is public. + [15:0] + read-write + + + + + WL_ENABLE + whitelist valid entry bit + 0x7C + 32 + read-write + 0x0 + 0xFFFF + + + WL_ENABLE + Stores the valid entry bit corresponding to each of the eight device address stored in the whitelist. +1 - White list entry is Valid +0 - White list entry is Invalid + [15:0] + read-write + + + + + TRANSMIT_WINDOW_OFFSET + Transmit window offset + 0x80 + 32 + read-write + 0x0 + 0xFFFF + + + TX_WINDOW_OFFSET + This is used to determine the first anchor point for the master transmission, from the time of connection creation. +Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value. + [15:0] + read-write + + + + + TRANSMIT_WINDOW_SIZE + Transmit window size + 0x84 + 32 + read-write + 0x0 + 0xFF + + + TX_WINDOW_SIZE + window_size along with the window_offset is used to calculate the first connection point anchor point for the master. +This shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms). +Values range from 0 to 10 ms. + [7:0] + read-write + + + + + DATA_CHANNELS_L0 + Data channel map 0 (lower word) + 0x88 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_CHANNELS_L0 + This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [15:0] + read-write + + + + + DATA_CHANNELS_M0 + Data channel map 0 (middle word) + 0x8C + 32 + read-write + 0x0 + 0xFFFF + + + DATA_CHANNELS_M0 + This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [15:0] + read-write + + + + + DATA_CHANNELS_H0 + Data channel map 0 (upper word) + 0x90 + 32 + read-write + 0x0 + 0x1F + + + DATA_CHANNELS_H0 + This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. +Note: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map. + [4:0] + read-write + + + + + DATA_CHANNELS_L1 + Data channel map 1 (lower word) + 0x98 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_CHANNELS_L1 + This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [15:0] + read-write + + + + + DATA_CHANNELS_M1 + Data channel map 1 (middle word) + 0x9C + 32 + read-write + 0x0 + 0xFFFF + + + DATA_CHANNELS_M1 + This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [15:0] + read-write + + + + + DATA_CHANNELS_H1 + Data channel map 1 (upper word) + 0xA0 + 32 + read-write + 0x0 + 0x1F + + + DATA_CHANNELS_H1 + This register field indicates which of the data channels are in use. This stores the information for the upper 5 data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. +Note: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map. + [4:0] + read-write + + + + + CONN_INTR + Connection interrupt status and Clear register + 0xA8 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_CLOSED + If this bit is set it indicates that the link is disconnected. +If this bit is written with 1, it clears the connection updated interrupt. + [0:0] + read-write + + + CONN_ESTB + If this bit is set it indicates that the connection has been established. The bit is also set when a connection update procedure is complet-ed, at the start of the first anchor point with the updated parameters. +If this bit is written with 1, it clears the connection established interrupt. + [1:1] + read-write + + + MAP_UPDT_DONE + If this bit is set it indicates that the channel map update is completed at the instant specified by the firmware. +If this bit is written with 1, it clears the map update done interrupt. + [2:2] + read-write + + + START_CE + If this bit is set it indicates that the connection event started interrupt has happened. +If this bit is written with 1, it clears the connection event started interrupt. + [3:3] + read-write + + + CLOSE_CE + If this bit is set it indicates that the connection event closed interrupt has happened. +If this bit is written with 1, it clears the connection event closed interrupt. + [4:4] + read-write + + + CE_TX_ACK + If this bit is set it indicates that the connection event transmission acknowledgement is received for the previous non-empty packet transmitted. +If this bit is written with 1, it clears the ce transmission acknowledgement interrupt. + [5:5] + read-write + + + CE_RX + If this bit is set it indicates that a packet is received in the connection event. +If this bit is written with 1, it clears the connection event received interrupt. + [6:6] + read-write + + + CON_UPDT_DONE + This bit is set when the last connection event with previous connec-tion parameters is reached. The bit is set immediately after the re-ceive operation at the anchor point of the last connection event. +If this bit is written with 1, it clears the connection updated interrupt. + [7:7] + read-write + + + DISCON_STATUS + Reason for disconnect - indicates the reason the link is disconnected by hardware. +001 - connection failed to be established +010 - supervision timeout +011 - kill connection by host +100 - kill connection after ACK transmitted +101 - PDU response timer expired + [10:8] + read-only + + + RX_PDU_STATUS + Status of PDU received. This information is valid along with receive interrupt. +xx1 - Bad Packet (packet with CRC error) +000 - empty PDU +010 - new data (non-empty) PDU +110 - Duplicate Packet + [13:11] + read-only + + + PING_TIMER_EXPIRD_INTR + If this is set, it indicates that ping timer has expired. +If this bit is written with 1, it clears the interrupt. + [14:14] + read-write + + + PING_NEARLY_EXPIRD_INTR + If this is set, it indicates that ping timer has nearly expired. +If this bit is written with 1, it clears the interrupt. + [15:15] + read-write + + + + + CONN_STATUS + Connection channel status + 0xAC + 32 + read-only + 0x0 + 0xF000 + + + RECEIVE_PACKET_COUNT + This field stores the count for the number of receive packets in the receive FIFO that are still not ready by firmware. +The counter value is incremented by hardware for every good packet it stores in the FIFO. +After firmware reads a packet, it decrements the counter by issuing the PACKET_RECEIVED command from the commander. + [15:12] + read-only + + + + + CONN_INDEX + Connection Index register + 0xB0 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_INDEX + This field is used to index the multiple connections existing. Range is 0 to maximum number of connections supported. +For a single connection device, conn_index is 0. + [15:0] + read-write + + + + + WAKEUP_CONFIG + Wakeup configuration + 0xB8 + 32 + read-write + 0x0 + 0xFCFF + + + OSC_STARTUP_DELAY + Oscillator stabilization/startup delay. This is in X.Y for-mat where X is in terms of number of BT slots (625 us) and Y is in terms of number of clock periods of 16KHz clock input, required for RF oscillator to stabilize the clock output to the controller on its output pin, after oscillator is turned ON. In this period the clock is as-sumed to be unstable, and so the controller does not turn on the clock to internal logic till this period is over. This means, the wake up from deep sleep mode must account for this delay before the wakeup instant. +Osc_startup_delay[7:5] is number of slots(625us) +Osc_startup_delay[4:0 is number of clock periods of 16KHz clock +(Warning: Min. value of Osc_startup_delay [4:0] sup-ported is 1 and Max. value is 9. Therefore programma-ble range is 1 to 9) + [7:0] + read-write + + + DSM_OFFSET_TO_WAKEUP_INSTANT + Number of 'slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The slot is of 0.625ms period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant. + [15:10] + read-write + + + + + WAKEUP_CONTROL + Wakeup control + 0xC0 + 32 + read-write + 0x0 + 0xFFFF + + + WAKEUP_INSTANT + Instant, with reference to the internal 16-bit clock reference, at which the hardware must wakeup from deep sleep mode. This is calculated by firmware based on the next closest instant where a controller operation is required (like advertiser/scanner). Firmware reads the next instant of the procedures in the corresponding *_NEXT_INSTANT registers. This value is used only when hardware auto wakeup from deep sleep mode is enabled in the clock control register. +Note: it is recommended to program wakeup_instant such a way that the actual instant to wakeup shall be at least two counts (two slots of 625 us) ahead of reference clock when entering DSM. The actual instant to wakeup is 'wakeup_instant - dsm_offset_to_wakeup_instant - osc_startup_delay, and it shall be greater than 'reference clock + 2' + [15:0] + read-write + + + + + CLOCK_CONFIG + Clock control + 0xC4 + 32 + read-write + 0x80 + 0xF7FF + + + ADV_CLK_GATE_EN + Advertiser block clock gate enable. 1 - enable, 0 - disable. +Enables gating of clock to the advertiser module (llh_adv) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON. + [0:0] + read-write + + + SCAN_CLK_GATE_EN + Scan block clock gate enable. 1 - enable, 0 - disable. +Enables gating of clock to the scanner module (llh_scan) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON. + [1:1] + read-write + + + INIT_CLK_GATE_EN + Initiator block clock gate enable. 1 - enable, 0 - disable. +Enables gating of clock to the initiator module (llh_init). If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON. + [2:2] + read-write + + + CONN_CLK_GATE_EN + Connection block clock gate enable. 1 - enable, 0 - disable. +Enables gating of clock to the connection module (llh_connch_top) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the engine. If 0, the logic has no control and clock to the module is always turned ON. + [3:3] + read-write + + + CORECLK_GATE_EN + Core clock gate enable. 1 - enable, 0 - disable. +Enables gating of clock to the llh_core module in hard-ware. If 1, the sleep mode/deep sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock is always turned ON. + [4:4] + read-write + + + SYSCLK_GATE_EN + Sysclk gate enable. 1- enable, 0 - disable. +Enables clock gating of system clock input to the link layer. If 1, it enables the DSM logic to control the clock gate for system clock input from pin. If 0, the DSM logic has no control and the system clock is always ON. + [5:5] + read-write + + + PHY_CLK_GATE_EN + Digital PHY clock enable. 1- enable, 0-disable. +Enable the Digital PHY to shutdown the clock. When 1, it indicates that controller has an upcoming activity so PHY clock must be turned ON. When 0, it indicates inactivity in the controller. + [6:6] + read-write + + + LLH_IDLE + Indicates if hardware is doing any transmit/receive operation. This information is used by firmware to decide to program the hardware into deep sleep mode. +1 - LL hardware is idle. +0 - LL hardware is busy. In this case LL hardware will not enter deep sleep mode, even if firmware gives an enter DSM command. (In this situation hardware generates dsm exit interrupt to inform firmware that DSM entry was not successful). + [7:7] + read-only + + + LPO_CLK_FREQ_SEL + Clock frequency select. 0 - 32KHz, 1 - 32.768KHz. +Base frequency of the sleep_clk input used for generat-ing the internal reference clock of approximate 16Khz frequency. + [8:8] + read-write + + + LPO_SEL_EXTERNAL + Select external sleep clock. 1 - External clock, 0 - inter-nal generated clock. +The field is used to select either the low power clock in-put on sleep_clk input pin(of frequency 16.384KHz) di-rectly to run the DSM logic or to use the internal gener-ated reference clock(of 16KHz) for the same. + [9:9] + read-write + + + SM_AUTO_WKUP_EN + Enable sleep mode auto wakeup enable. 1- enable, 0 - disable. +Enables hardware to automatically wakeup from sleep mode at the instant = wakeup_instant - sm_offset_to_wakeup_instant. The wakeup_insant is the field in the wakeup control register described earlier. The sm_offset_to_wakeup_instant value is the field described in the wakeup configuration register. + [10:10] + read-write + + + SM_INTR_EN + Enable SM exit interrupt. 1 - enable, 0 - disable. +Enables hardware to generate an interrupt while exiting sleep mode - irrespective of whether it is initiated by hardware or firmware. The interrupt is captured and stored till it gets cleared. Disabling this bit mask the sleep mode exit event from hardware & firmware. +This feature is not available. FW should never set this bit + [12:12] + read-write + + + DEEP_SLEEP_AUTO_WKUP_DISABLE + Disable Auto Wakeup in DEEP_SLEEP mode. +1 - Disable Auto Wakeup +0 - Auto Wakeup enabled + [13:13] + read-write + + + SLEEP_MODE_EN + Enable sleep mode. 1 - enable, 0 - disable. +Enables hardware to control sleep mode operation. +This feature is not available. FW should never set this bit + [14:14] + read-write + + + DEEP_SLEEP_MODE_EN + Enable deep sleep mode. 1 - enable, 0 - disable. +Enables hardware logic related to deep sleep mode to control the deep sleep mode operation. If disabled, the related logic is not executed and hardware cannot enter deep sleep mode. + [15:15] + read-write + + + + + TIM_COUNTER_L + Reference Clock + 0xC8 + 32 + read-only + 0x0 + 0xFFFF + + + TIM_REF_CLOCK + 16-bit internal reference clock. The clock is a free run-ning clock, incremented by a 0.625ms periodic pulse. It is used as a reference clock to derive all the timing required as per protocol. + [15:0] + read-only + + + + + WAKEUP_CONFIG_EXTD + Wakeup configuration extended + 0xCC + 32 + read-write + 0x0 + 0x1F + + + DSM_LF_OFFSET + Number of 'LF slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The LF slot is of 62.5us period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant. This is in addition to the LF slots calculated by HW window widening logic. + [4:0] + read-write + + + + + POC_REG__TIM_CONTROL + BLE Time Control + 0xD8 + 32 + read-write + 0x0 + 0xFF8 + + + BB_CLK_FREQ_MINUS_1 + LLH clock configuration. The clock frequency of the clock input to this design is configured in this register. This is used to derive a 1MHz clock. + [7:3] + read-write + + + START_SLOT_OFFSET + LLH clock configuration. The start of slot signal is offset by this value. If value is 0, the start of slot signal is generated at the 625us. The offset value is in terms of us. + [11:8] + read-write + + + + + ADV_TX_DATA_FIFO + Advertising data transmit FIFO. Access ADVCH_TX_FIFO. + 0xE0 + 32 + read-write + 0x0 + 0xFFFF + + + ADV_TX_DATA + IO mapped FIFO of depth 16 (2 byte wide), to store ADV data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same address location. +Note: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated. +Reading this location resets the FIFO pointer. + [15:0] + read-write + + + + + ADV_SCN_RSP_TX_FIFO + Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO. + 0xE8 + 32 + read-write + 0x0 + 0xFFFF + + + SCAN_RSP_DATA + IO mapped FIFO of depth 16 (2 byte wide), to store scan response data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same location. +Note: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated. +Reading this location resets the FIFO pointer. + [15:0] + read-write + + + + + INIT_SCN_ADV_RX_FIFO + advertising scan response data receive data FIFO. Access ADVRX_FIFO. + 0xF8 + 32 + read-only + 0x0 + 0xFFFF + + + ADV_SCAN_RSP_RX_DATA + IO mapped FIFO of depth 64, to store ADV and SCAN_RSP header and payload received by the scanner. The RSSI value at the time of reception of this packet is also stored. Firmware reads from the same address to read out consecutive words of data. +Note: The 16 bit header is first loaded to the advertise channel data receive FIFO followed by the payload data and then 16 bit RSSI. + [15:0] + read-only + + + + + CONN_INTERVAL + Connection Interval + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + CONNECTION_INTERVAL + The value configured in this register determines the spacing be-tween the connection events. +This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s. + [15:0] + read-write + + + + + SUP_TIMEOUT + Supervision timeout + 0x104 + 32 + read-write + 0x0 + 0xFFFF + + + SUPERVISION_TIMEOUT + This field defines the maximum time between two received Data packet PDUs before the connection is considered lost. +This shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval. + [15:0] + read-write + + + + + SLAVE_LATENCY + Slave Latency + 0x108 + 32 + read-write + 0x0 + 0xFFFF + + + SLAVE_LATENCY + The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. +The value of connSlaveLatency should not cause a Supervision Timeout. +This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500. + [15:0] + read-write + + + + + CE_LENGTH + Connection event length + 0x10C + 32 + read-write + 0x0 + 0xFFFF + + + CONNECTION_EVENT_LENGTH + N/A + [15:0] + read-write + + + + + PDU_ACCESS_ADDR_L_REGISTER + Access address (lower) + 0x110 + 32 + read-write + 0x0 + 0xFFFF + + + PDU_ACCESS_ADDRESS_LOWER_BITS + This field defines the lower 16 bits of the access address for each Link layer connection between any two devices. + [15:0] + read-write + + + + + PDU_ACCESS_ADDR_H_REGISTER + Access address (upper) + 0x114 + 32 + read-write + 0x0 + 0xFFFF + + + PDU_ACCESS_ADDRESS_HIGHER_BITS + This field defines the higher 16 bits of the access address for each Link layer connection between any two devices. + [15:0] + read-write + + + + + CONN_CE_INSTANT + Connection event instant + 0x118 + 32 + read-write + 0x0 + 0xFFFF + + + CE_INSTANT + This is the value of the free running Connection Event counter when the new parameters of 'connection update' and/or 'Channel map update' will be effective. +Range : 0x0000 to 0xFFFF + [15:0] + read-write + + + + + CE_CNFG_STS_REGISTER + connection configuration & status register + 0x11C + 32 + read-write + 0x0 + 0xF5FF + + + DATA_LIST_INDEX_LAST_ACK_INDEX + Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. +The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. +Hardware will start the next data transmission from the index indicated by this field. + [3:0] + read-write + + + DATA_LIST_HEAD_UP + Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. +The bit must be toggled every time the firmware needs to indicate the start/resume. This requires a read modify write operation. + [4:4] + read-write + + + SPARE + This bit is unused + [5:5] + read-write + + + MD + MD bit set to '1' indicates device has more data to be sent. + [6:6] + read-write + + + MAP_INDEX__CURR_INDEX + Written by firmware to select the map index to be used by hardware for this connection. +1 - use channel map register set 1. +0 - use channel map register set 0. +When firmware reads this field, it returns the current map index being used in hardware. + [7:7] + read-write + + + PAUSE_DATA + Pause data. +1 - pause data, +0 - do not pause. +The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. +But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out + [8:8] + read-write + + + CONN_ACTIVE + This bit is '1' whenever the connection is active. + [10:10] + read-only + + + CURRENT_PDU_INDEX + The index of the transmit packet buffer that is currently in transmission/waiting for transmission. + [15:12] + read-only + + + + + NEXT_CE_INSTANT + Next connection event instant + 0x120 + 32 + read-only + 0xFFFF + 0xFFFF + + + NEXT_CE_INSTANT + 16-bit internal reference clock value at which the next connection event will occur on a connection. The connection index register must be programmed with index of the connection, before reading the register. +The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF. + [15:0] + read-only + + + + + CONN_CE_COUNTER + connection event counter + 0x124 + 32 + read-only + 0x0 + 0xFFFF + + + CONNECTION_EVENT_COUNTER + This is the free running counter, connEventCounter as defined by Bluetooth spec. +Firmware will read the instantaneous Event counter from this register, during connection update and channel map update procedure. Firmware will use this value to calculate the instant from which the new parameters (for connection update and channel map update) will be effective. + [15:0] + read-only + + + + + DATA_LIST_SENT_UPDATE__STATUS + data list sent update and status + 0x128 + 32 + read-write + 0x0 + 0x8F + + + LIST_INDEX__TX_SENT_3_0 + Write:Indicates the buffer index for which the SENT bit is being updated by firmware. +The default number of buffers in the IP is 4. The index range is 0-3. + +Read: Reads TX_SENT[3:0]. +The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are +1 - queued +0 - no packet / packet ack received by hardware +Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. +NOTE: +The SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission. +SENT ACK Description +0 0 Buffer is empty. No packet is queued in the buffer +1 0 Packet is queued by firmware. +1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement. +0 1 Hardware has received ACK. Firmware has not yet processed the ACK. +0 0 Firmware has processed the ack. The buffer is again empty. + [3:0] + read-write + + + SET_CLEAR + Write: Used to set the SENT bit in hardware for the selected packet buffer. +1 - packet queued +When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. +The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. +Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. + [7:7] + write-only + + + + + DATA_LIST_ACK_UPDATE__STATUS + data list ack update and status + 0x12C + 32 + read-write + 0x0 + 0x8F + + + LIST_INDEX__TX_ACK_3_0 + Write: Indicates the buffer index for which the ACK bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-4. + +Read: Reads TX_ACK[3:0] +If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. +Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. +Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. +NOTE: +The SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission. +SENT ACK Description +0 0 Buffer is empty. No packet is queued in the buffer +1 0 Packet is queued by firmware. +1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement. +0 1 Hardware has received ACK. Firmware has not yet processed the ACK. +0 0 Firmware has processed the ack. The buffer is again empty. + [3:0] + read-write + + + SET_CLEAR + Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. +Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. +For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. +This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. +The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. + [7:7] + write-only + + + + + CE_CNFG_STS_REGISTER_EXT + connection configuration & status register + 0x130 + 32 + read-write + 0x0 + 0x3F0F + + + TX_2M + transmittion on 2M + [0:0] + read-write + + + RX_2M + receiving on 2M + [1:1] + read-write + + + SN + Sequence number for next scheduled connection index + [2:2] + read-write + + + NESN + Next Sequence number for next scheduled connection index + [3:3] + read-write + + + LAST_UNMAPPED_CHANNEL + Last unmapped channel for next scheduled connection index + [13:8] + read-write + + + + + CONN_EXT_INTR + Connection extended interrupt status and Clear register + 0x134 + 32 + read-write + 0x0 + 0x7 + + + DATARATE_UPDATE + If this bit is set it indicates that the data rate is updated +If this bit is written with 1, it clears the interrupt status bit + [0:0] + read-write + + + EARLY_INTR + For master this bit is set on start_ce +For Slave this bit is set on slave_timer_adj + [1:1] + read-write + + + GEN_TIMER_INTR + If this bit is set it indicates that the generic timer (PDU response timer reconfigured in MMMS mode) has expired +If this bit is written with 1, it clears the interrupt status bit + [2:2] + read-write + + + + + CONN_EXT_INTR_MASK + Connection Extended Interrupt mask + 0x138 + 32 + read-write + 0x0 + 0x7 + + + DATARATE_UPDATE + If this bit is set connection data rate update interrupt is enabled. + [0:0] + read-write + + + EARLY_INTR + If this bit is set connection early interrupt is enabled. + [1:1] + read-write + + + GEN_TIMER_INTR + Generic timer (PDU response timer reconfigured in MMMS mode) expiry interrupt + [2:2] + read-write + + + + + 5 + 4 + DATA_MEM_DESCRIPTOR[%s] + Data buffer descriptor 0 to 4 + 0x140 + 32 + read-write + 0x0 + 0x3FF + + + LLID + N/A + [1:0] + read-write + + + DATA_LENGTH + This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set. +Range 0x00 to 0xFF. + [9:2] + read-write + + + + + WINDOW_WIDEN_INTVL + Window widen for interval + 0x160 + 32 + read-write + 0xA + 0xFFF + + + WINDOW_WIDEN_INTVL + This value defines the increased listening time for the slave. +The window widening shall be smaller than ((connInterval/2)-T_IFS us) +This value is calculated by firmware based on the drift, the connec-tion interval value. The value is the unit widening value for one con-nection interval duration. In case of slave latency, this value is accu-mulated till the next anchor point at which the slave will listen. + [11:0] + read-write + + + + + WINDOW_WIDEN_WINOFF + Window widen for offset + 0x164 + 32 + read-write + 0xA + 0xFFF + + + WINDOW_WIDEN_WINOFF + This field stores the additional number of microseconds the slave must extend its listening window to listen for a master packet. This value is calculated based on the window offset value. This is used at connection setup directly. During connection setup, this value is added with window_widen_intvl register value to calculate the win-dow widening size. + [11:0] + read-write + + + + + LE_RF_TEST_MODE + Direct Test Mode control + 0x170 + 32 + read-write + 0x0 + 0xA3FF + + + TEST_FREQUENCY + N = (F - 2402) / 2 +Range: 0x00 - 0x27. Frequency Range : 2402 MHz to 2480 MHz + [5:0] + read-write + + + DTM_STATUS__DTM_CONT_RXEN + This bit is overloaded. +The read operation returns the staus of the DTM +1 - DTM test ON +0 - DTM test OFF +The write operation contrls the DTM RX mode +0: DTM run at normal DTMRX burst mode +1: DTM run at continuous RX DTM mode + [6:6] + read-write + + + PKT_PAYLOAD + N/A + [9:7] + read-write + + + DTM_CONT_TXEN + 0: DTM run at normal DTMTX burst mode +1: DTM run at continuous TX DTM mode + [13:13] + read-write + + + DTM_DATA_2MBPS + 0: DTM run at 1M bps data rate +1: DTM run at 2M bps data rate + [15:15] + read-write + + + + + DTM_RX_PKT_COUNT + Direct Test Mode receive packet count + 0x174 + 32 + read-only + 0x0 + 0xFFFF + + + RX_PACKET_COUNT + Number of packets received in receive test mode. + [15:0] + read-only + + + + + LE_RF_TEST_MODE_EXT + Direct Test Mode control + 0x178 + 32 + read-write + 0x0 + 0xFF + + + DTM_PACKET_LENGTH + DTM TX packet length. +Bits [7:6] are accessible onle when DLE is enabled + [7:0] + read-write + + + + + TXRX_HOP + Channel Address register + 0x188 + 32 + read-only + 0x0 + 0x7F7F + + + HOP_CH_TX + Transmit channel index. Channel index on which previous packet is transmitted. + [6:0] + read-only + + + HOP_CH_RX + Receive channel index. Channel index on which previous packet is received. + [14:8] + read-only + + + + + TX_RX_ON_DELAY + Transmit/Receive data delay + 0x190 + 32 + read-write + 0x0 + 0xFFFF + + + RXON_DELAY + Receive delay - Delay from start of receive to expected first bit of receive packet at the controller. Used to control the turn on time of radio to optimize on power. The delay is in resolution of 1 microsecond. + [7:0] + read-write + + + TXON_DELAY + Transmit delay - Delay from start of transmit to transmission of first bit on air. It is used to control the T_IFS. The delay is in resolution of 1 microsecond. + [15:8] + read-write + + + + + ADV_ACCADDR_L + ADV packet access code low word + 0x1A8 + 32 + read-write + 0xBED6 + 0xFFFF + + + ADV_ACCADDR_L + Lower 16 bit of ADV packet access code + [15:0] + read-write + + + + + ADV_ACCADDR_H + ADV packet access code high word + 0x1AC + 32 + read-write + 0x8E89 + 0xFFFF + + + ADV_ACCADDR_H + higher 16 bit of ADV packet access code + [15:0] + read-write + + + + + ADV_CH_TX_POWER_LVL_LS + Advertising channel transmit power setting + 0x1B0 + 32 + read-write + 0x0 + 0xFFFF + + + ADV_TRANSMIT_POWER_LVL_LS + When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Advertising channel transmit power setting Least Significant 16 bits. +When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Advertising channel transmit power code 4 bits. + [15:0] + read-write + + + + + ADV_CH_TX_POWER_LVL_MS + Advertising channel transmit power setting extension + 0x1B4 + 32 + read-write + 0x0 + 0x3 + + + ADV_TRANSMIT_POWER_LVL_MS + Advertising channel transmit power setting Most Significant 2 bits. + [1:0] + read-write + + + + + CONN_CH_TX_POWER_LVL_LS + Connection channel transmit power setting + 0x1B8 + 32 + read-write + 0x0 + 0xFFFF + + + CONNCH_TRANSMIT_POWER_LVL_LS + When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Connection channel transmit power setting Least Significant 16 bits. +When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Connection channel transmit power code 4 bits. + [15:0] + read-write + + + + + CONN_CH_TX_POWER_LVL_MS + Connection channel transmit power setting extension + 0x1BC + 32 + read-write + 0x0 + 0x3 + + + CONNCH_TRANSMIT_POWER_LVL_MS + Connection channel transmit power setting Most Significant 2 bits. + [1:0] + read-write + + + + + DEV_PUB_ADDR_L + Device public address lower register + 0x1C0 + 32 + read-write + 0x3412 + 0xFFFF + + + DEV_PUB_ADDR_L + Lower 16 bit of 48-bit public address of the device. + [15:0] + read-write + + + + + DEV_PUB_ADDR_M + Device public address middle register + 0x1C4 + 32 + read-write + 0x56 + 0xFFFF + + + DEV_PUB_ADDR_M + Middle 16 bit of 48-bit public address of the device. + [15:0] + read-write + + + + + DEV_PUB_ADDR_H + Device public address higher register + 0x1C8 + 32 + read-write + 0x0 + 0xFFFF + + + DEV_PUB_ADDR_H + Higher 16 bit of 48-bit public address of the device. + [15:0] + read-write + + + + + OFFSET_TO_FIRST_INSTANT + Offset to first instant + 0x1D0 + 32 + read-write + 0x6 + 0xFFFF + + + OFFSET_TO_FIRST_EVENT + The offset w.r.t the internal reference clock at which instant the first event occurs. +This register will give flexibility to the firmware to position the con-nection at a desired point with respect to the internal free running clock. It is optional to be updated by firmware. This is not updated in the current firmware. + [15:0] + read-write + + + + + ADV_CONFIG + Advertiser configuration register + 0x1D4 + 32 + read-write + 0x20FF + 0xFFFF + + + ADV_STRT_EN + Enable advertising event start interrupt. + [0:0] + read-write + + + ADV_CLS_EN + Enable advertising event stop interrupt. + [1:1] + read-write + + + ADV_TX_EN + Enable adv packet transmitted interrupt. + [2:2] + read-write + + + SCN_RSP_TX_EN + Enable scan response packet transmitted interrupt. + [3:3] + read-write + + + ADV_SCN_REQ_RX_EN + Enable scan request packet received interrupt. + [4:4] + read-write + + + ADV_CONN_REQ_RX_EN + Enable connect request packet received interrupt. + [5:5] + read-write + + + SLV_CONNECTED_EN + Enable slave connected interrupt. + [6:6] + read-write + + + ADV_TIMEOUT_EN + Enable adv_timeout interrupt. Applicable in adv_direct_ind advertising. + [7:7] + read-write + + + ADV_RAND_DISABLE + Disable randomization of adv interval. When disabled, interval is same as programmed in adv_interval register. + [8:8] + read-write + + + ADV_SCN_PEER_RPA_UNMCH_EN + Enable scan request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_ADV are set. + [9:9] + read-write + + + ADV_CONN_PEER_RPA_UNMCH_EN + Enable connect request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. + [10:10] + read-write + + + ADV_PKT_INTERVAL + Time between the beginning of two consecutive advertising PDU's. +Time = N * 0.625 msec +Time Range: <=10msec. + [15:11] + read-write + + + + + SCAN_CONFIG + Scan configuration register + 0x1D8 + 32 + read-write + 0xE01F + 0xE9FF + + + SCN_STRT_EN + Enable scan event start interrupt. + [0:0] + read-write + + + SCN_CLOSE_EN + Enable scan event close interrupt. + [1:1] + read-write + + + SCN_TX_EN + Enable scan request packet transmitted interrupt. + [2:2] + read-write + + + ADV_RX_EN + Enable adv packet received interrupt . + [3:3] + read-write + + + SCN_RSP_RX_EN + Enable scan_rsp packet received interrupt . + [4:4] + read-write + + + SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN + Enable ADV peer address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set. + [5:5] + read-write + + + SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN + Enable ADV self address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set. + [6:6] + read-write + + + SCANA_TX_ADDR_NOT_SET_INTR_EN + Enable SCANA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. + [7:7] + read-write + + + RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN + This bit controls the SCAN engine behavior when an self address match occurs but a privacy mismatch occurs +0 - The packet is aborted +1 - The packet is received and reported to the Link Layer firmware +This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. + [8:8] + read-write + + + BACKOFF_ENABLE + Enable random backoff feature in scanner. +1 - enable +0 - disable + [11:11] + read-write + + + SCAN_CHANNEL_MAP + Advertising channels that are enabled for scanning operation. +Bit 15: setting 1 - enables channel 39 for use. +Bit 14: setting 1 - enables channel 38 for use. +Bit 13: setting 1 - enables channel 37 for use. + [15:13] + read-write + + + + + INIT_CONFIG + Initiator configuration register + 0x1DC + 32 + read-write + 0x0 + 0xE0F7 + + + INIT_STRT_EN + Enable Initiator event start interrupt. + [0:0] + read-write + + + INIT_CLOSE_EN + Enable Initiator event close interrupt. + [1:1] + read-write + + + CONN_REQ_TX_EN + Enables connection request packet transmission start interrupt. + [2:2] + read-write + + + CONN_CREATED + Enable master connection created interrupt + [4:4] + read-write + + + INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN + Enable ADV self address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. + [5:5] + read-write + + + INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN + Enable ADV peer address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. + [6:6] + read-write + + + INITA_TX_ADDR_NOT_SET_INTR_EN + Enable INITA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set. + [7:7] + read-write + + + INIT_CHANNEL_MAP + Advertising channels that are enabled for initiator scanning operation. +Bit 15: setting 1 - enables channel 39 for use. +Bit 14: setting 1 - enables channel 38 for use. +Bit 13: setting 1 - enables channel 37 for use. + [15:13] + read-write + + + + + CONN_CONFIG + Connection configuration register + 0x1E0 + 32 + read-write + 0xE11F + 0xF9FF + + + RX_PKT_LIMIT + Defines a limit for the number of Rx packets that can be re-ceived by the LLH. Default maximum value is 0xF.Minimum value shall be '1' or no packet will be stored in the Rx FIFO. + [3:0] + read-write + + + RX_INTR_THRESHOLD + This register field allows setting a threshold for the packet received interrupt to the firmware. +For example if the value programmed is +0x2 - then HW will generate interrupt only on receiving the second packet. +In any case if the received number of packets in a conn event is less than the threshold or there are still packets (less than threshold) pending in the Rx FIFO, HW will generate the interrupt at the ce_close. +Min value possible is 1. Max value depends on the Rx FIFO capacity. + [7:4] + read-write + + + MD_BIT_CLEAR + This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and soft-ware logic combined'. +1 - MD bit is exclusively controlled by software, ie based on status of CE_CNFG_STS_REGISTER[6] - md bit. +0 - MD Bit in the transmitted pdu is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the md bit in CE_CNFG_STS_REGISTER[6] and either of the following conditions is true, +a) If there are packets queued for transmission. +b) If there is an acknowledgement awaited from the remote side for the packet transmitted. + [8:8] + read-write + + + DSM_SLOT_VARIANCE + This bit configures the DSM slot counting mode. +0 - The DSM slot count variance with respect to actual time is less than 1 slot +1 - The DSM slot count variance with respect to actual time is more than 1 slot &less that 2 slots + [11:11] + read-write + + + SLV_MD_CONFIG + This bit is set to configure the MD bit control when IUT is in slave role. +1 - MD bit will be decided on packet pending status +0 - MD bit will be decided on packet queued in next buffer status +This bit has effect only when 'CONN_CONFIG.md_bit_ctr' bit is not set . + [12:12] + read-write + + + EXTEND_CU_TX_WIN + This bit is used to enable/disable extending the additional rx window on slave side during connection update in event of packet miss at the update instant. +1 - Enable +0 - Disable + [13:13] + read-write + + + MASK_SUTO_AT_UPDT + This bit is used to enable/disable masking of internal hardware supervision timeout trigger when switching from old connection parameters to new parameters. +1 - Enable +0 - Disable + [14:14] + read-write + + + CONN_REQ_1SLOT_EARLY + This bit is used to enable extension of the Conn Request to arbiter to 1 slot early. When enabled the request length is 2 slots. +1 - Enable +0 - Disable + [15:15] + read-write + + + + + CONN_PARAM1 + Connection parameter 1 + 0x1E8 + 32 + read-write + 0x0 + 0xFFFF + + + SCA_PARAM + Sleep Clock Accuracy + [2:0] + read-write + + + HOP_INCREMENT_PARAM + Hop increment for connection channel. + [7:3] + read-write + + + CRC_INIT_L + This field defines the lower byte (7:0) of the CRC initialization vector. + [15:8] + read-write + + + + + CONN_PARAM2 + Connection parameter 2 + 0x1EC + 32 + read-write + 0x0 + 0xFFFF + + + CRC_INIT_H + This field defines the upper two bytes (23:8) of the CRC initialization vector. + [15:0] + read-write + + + + + CONN_INTR_MASK + Connection Interrupt mask + 0x1F0 + 32 + read-write + 0x2000 + 0xE3FF + + + CONN_CL_INT_EN + If this bit is set connection closed interrupt is enabled. + [0:0] + read-write + + + CONN_ESTB_INT_EN + If this bit is set connection establishment interrupt is enabled. + [1:1] + read-write + + + MAP_UPDT_INT_EN + If this bit is set, channel map update interrupt is enabled. + [2:2] + read-write + + + START_CE_INT_EN + If this bit is set connection event start interrupt is enabled + [3:3] + read-write + + + CLOSE_CE_INT_EN + If this bit is set connection event closed interrupt is enabled. + [4:4] + read-write + + + CE_TX_ACK_INT_EN + If this bit is set transmission acknowledgement interrupt is enabled: +This interrupt is generated to indicate to the firmware that a non-empty packet transmitted is successfully acknowledged by the remote device. +For negative acknowledgements from remote device, this interrupt indication is not generated. + [5:5] + read-write + + + CE_RX_INT_EN + If this bit is set interrupt is enabled for reception of packet in a connection event. + [6:6] + read-write + + + CONN_UPDATE_INTR_EN + If this bit is set connection update interrupt is enabled. + [7:7] + read-write + + + RX_GOOD_PDU_INT_EN + If this bit is set packet receive good pdu interrupt is enabled. Effective only when bit 6 is set. + [8:8] + read-write + + + RX_BAD_PDU_INT_EN + If this bit is set packet receive bad pdu interrupt is enabled. Effective only when bit 6 is set. + [9:9] + read-write + + + CE_CLOSE_NULL_RX_INT_EN + If this but us set, the RX interrupt is triggerred for an end of connection event with a null packet + [13:13] + read-write + + + PING_TIMER_EXPIRD_INTR + If this bit is set ping timer expired interrupt is enabled. + [14:14] + read-write + + + PING_NEARLY_EXPIRD_INTR + If this bit is set ping timer nearly expired interrupt is enabled + [15:15] + read-write + + + + + SLAVE_TIMING_CONTROL + slave timing control + 0x1F4 + 32 + read-write + 0xBE96 + 0xFFFF + + + SLAVE_TIME_SET_VAL + Programmable adjust value to the clock counter when slave is connected + [7:0] + read-write + + + SLAVE_TIME_ADJ_VAL + Timing adjust value. The internal micro second counter is adjusted to this value whenever slave receives a good access address match at connection anchor point. This will ensure the slave gets synchronized to master timing. + [15:8] + read-write + + + + + RECEIVE_TRIG_CTRL + Receive trigger control + 0x1F8 + 32 + read-write + 0x0 + 0xFF3F + + + ACC_TRIGGER_THRESHOLD + Access address match threshold value. Number of bits of ac-cess address that should match with the expected access ad-dress to trigger an access code match. + +Max value : 32 (for 32-bit access address) +Lower values may be programmed for bad radios or channels but care must be taken to ensure there are no 'false' matches due to reduced number of bits required to match. + [5:0] + read-write + + + ACC_TRIGGER_TIMEOUT + If access address match does not occur then within this time from the start of receive operation, the receive operation times out and stops. An internal counter value of 1usec resolution is continuously compared with the value programmed. +Max value :0xFF + [15:8] + read-write + + + + + LL_DBG_1 + LL debug register 1 + 0x200 + 32 + read-only + 0x0 + 0x3FF + + + CONN_RX_WR_PTR + Connection receive FIFO write pointer + [9:0] + read-only + + + + + LL_DBG_2 + LL debug register 2 + 0x204 + 32 + read-only + 0x0 + 0x3FF + + + CONN_RX_RD_PTR + Connection receive FIFO read pointer + [9:0] + read-only + + + + + LL_DBG_3 + LL debug register 3 + 0x208 + 32 + read-only + 0x0 + 0x3FF + + + CONN_RX_WR_PTR_STORE + Connection receive FIFO stored write pointer for pointer restore + [9:0] + read-only + + + + + LL_DBG_4 + LL debug register 4 + 0x20C + 32 + read-only + 0x0 + 0x7FF + + + CONNECTION_FSM_STATE + Connection FSM state + [3:0] + read-only + + + SLAVE_LATENCY_FSM_STATE + Slave Latency FSM state + [5:4] + read-only + + + ADVERTISER_FSM_STATE + Advertiser FSM state + [10:6] + read-only + + + + + LL_DBG_5 + LL debug register 5 + 0x210 + 32 + read-only + 0x0 + 0x3FF + + + INIT_FSM_STATE + Initiator FSM state + [4:0] + read-only + + + SCAN_FSM_STATE + Scanner FSM state + [9:5] + read-only + + + + + LL_DBG_6 + LL debug register 6 + 0x214 + 32 + read-only + 0x0 + 0x3FFF + + + ADV_TX_WR_PTR + Advertiser Transmit FIFO write pointer + [3:0] + read-only + + + SCAN_RSP_TX_WR_PTR + Scan Response Transmit FIFO write pointer + [7:4] + read-only + + + ADV_TX_RD_PTR + Advertiser/ Scan Response FIFO read pointer + [13:8] + read-only + + + + + LL_DBG_7 + LL debug register 7 + 0x218 + 32 + read-only + 0x0 + 0x3FFF + + + ADV_RX_WR_PTR + Advertiser Receive FIFO write pointer + [6:0] + read-only + + + ADV_RX_RD_PTR + Advertiser Receive FIFO read pointer + [13:7] + read-only + + + + + LL_DBG_8 + LL debug register 8 + 0x21C + 32 + read-only + 0x0 + 0x3FFF + + + ADV_RX_WR_PTR_STORE + Advertiser Receive FIFO stored write pointer for pointer restore + [6:0] + read-only + + + WLF_PTR + Whitelist FIFO pointer + [13:7] + read-only + + + + + LL_DBG_9 + LL debug register 9 + 0x220 + 32 + read-only + 0x10 + 0xFFFF + + + WINDOW_WIDEN + Window Widening value in us. The reset value of this register is 0x0000. After reset de-assertion, at the first clock cycle, the value 0x0010 is assigned to the register. + [15:0] + read-only + + + + + LL_DBG_10 + LL debug register 10 + 0x224 + 32 + read-only + 0x0 + 0x3F + + + RF_CHANNEL_NUM + Active channel number + [5:0] + read-only + + + + + PEER_ADDR_INIT_L + Lower 16 bit address of the peer device for INIT. + 0x230 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_ADDR_L + Lower 16 bit of 48-bit address of the peer device. This is used only in MMMS mode + +The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. + +While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. + +While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. + [15:0] + read-write + + + + + PEER_ADDR_INIT_M + Middle 16 bit address of the peer device for INIT. + 0x234 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_ADDR_M + Middle 16 bit of 48-bit address of the peer device. This is used only in MMMS mode + +The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. + +While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. + +While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. + [15:0] + read-write + + + + + PEER_ADDR_INIT_H + Higher 16 bit address of the peer device for INIT. + 0x238 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_ADDR_H + Higher 16 bit of 48-bit address of the peer device. This is used only in MMMS mode + +The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. + +While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures. + +While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. + [15:0] + read-write + + + + + PEER_SEC_ADDR_ADV_L + Lower 16 bits of the secondary address of the peer device for ADV_DIR. + 0x23C + 32 + read-write + 0x0 + 0xFFFF + + + PEER_SEC_ADDR_L + Lower 16 bit of 48-bit secondary address of the peer device for ADV_DIR. + [15:0] + read-write + + + + + PEER_SEC_ADDR_ADV_M + Middle 16 bits of the secondary address of the peer device for ADV_DIR. + 0x240 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_SEC_ADDR_M + Middle 16 bit of 48-bit secondary address of the peer device for ADV_DIR. + [15:0] + read-write + + + + + PEER_SEC_ADDR_ADV_H + Higher 16 bits of the secondary address of the peer device for ADV_DIR. + 0x244 + 32 + read-write + 0x0 + 0xFFFF + + + PEER_SEC_ADDR_H + Higher 16 bit of 48-bit secondary address of the peer device for ADV_DIR. + +While doing directed Advertising in device privacy mode, if the peer device has shared its IRK, then the peer device RPA is written into the PEER_ADDR registers and the peer device identity address is written into this register. If the peer device has not shared its IRK, then the peer identity address is written into the PEER_ADDR registers and this register must be cleared. + [15:0] + read-write + + + + + INIT_WINDOW_TIMER_CTRL + Initiator Window NI timer control + 0x248 + 32 + read-write + 0x0 + 0x1 + + + INIT_WINDOW_OFFSET_SEL + Controls the INIT Window offset source +1 - Pick INIT Window Offset from HW calculated INIT_WINDOW_OFFSET +0 - Pick INIT Window Offset from FW loaded register + [0:0] + read-write + + + + + CONN_CONFIG_EXT + Connection extended configuration register + 0x24C + 32 + read-write + 0xA000 + 0xFF7F + + + CONN_REQ_2SLOT_EARLY + This bit is used to enable extension of the Conn Request to arbiter to 2 slot early. When enabled the request length is 3 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY bit. +1 - Enable +0 - Disable + [0:0] + read-write + + + CONN_REQ_3SLOT_EARLY + This bit is used to enable extension of the Conn Request to arbiter to 3 slot early. When enabled the request length is 4 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY & CONN_REQ_2SLOT_EARLY bits. +1 - Enable +0 - Disable + [1:1] + read-write + + + FW_PKT_RCV_CONN_INDEX + Connection Index for which the FW generates Packet Received Command. In MMMS mode, FW should write this field before giving PKT_RECEIVE_COMMAND to HW. + [6:2] + read-write + + + MMMS_RX_PKT_LIMIT + Receive Packet Limit for MMMS mode. This is the RX_FIFO Limit and applies to all connections together + [13:8] + read-write + + + DEBUG_CE_EXPIRE + MMMS CE expire control bit + [14:14] + read-write + + + MT_PDU_CE_EXPIRE + MMMS empty PDU CE expire handling control bit + [15:15] + read-write + + + + + DPLL_CONFIG + DPLL & CY Correlator configuration register + 0x258 + 32 + read-write + 0x0 + 0xFFFF + + + DPLL_CORREL_CONFIG + If MXD_IF_OPTION is 0: +Not used + +If CY_CORREL_EN is 1: +[11:0] CY correl Access address compare mask for LSB 12 bits. Ideal value is 0xFFF +[15:12] CY correl maximum number of allowed mismatched bits in access address. Ideal value is 0x0. + [15:0] + read-write + + + + + INIT_NI_VAL + Initiator Window NI instant + 0x260 + 32 + read-write + 0x0 + 0xFFFF + + + INIT_NI_VAL + Initiator window Next Instant value used for spacing Master connections in time, to minimize connection contention. This value is in 625us slots. +The read value corresponds to the hardware updated Interval value + [15:0] + read-write + + + + + INIT_WINDOW_OFFSET + Initiator Window offset captured at conn request + 0x264 + 32 + read-only + 0x0 + 0xFFFF + + + INIT_WINDOW_NI + Initiator Window offset captured at conn request. This value is in 1.25ms slots + [15:0] + read-only + + + + + INIT_WINDOW_NI_ANCHOR_PT + Initiator Window NI anchor point captured at conn request + 0x268 + 32 + read-only + 0x0 + 0xFFFF + + + INIT_INT_OFF_CAPT + Initiator interval offset captured at conn request. The value indicates the master connection anchor point. This value is in 625us slots + [15:0] + read-only + + + + + CONN_UPDATE_NEW_INTERVAL + Connection update new interval + 0x3A4 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_UPDT_INTERVAL + This register will have the new connection interval that the hardware will use after the connection update instant. Before the instant, the connection interval in the register CONN_INTERVAL will be used by hardware. + [15:0] + read-write + + + + + CONN_UPDATE_NEW_LATENCY + Connection update new latency + 0x3A8 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_UPDT_SLV_LATENCY + This register will have the new slave latency parameter that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SLAVE_LATENCY will be used by hardware. + [15:0] + read-write + + + + + CONN_UPDATE_NEW_SUP_TO + Connection update new supervision timeout + 0x3AC + 32 + read-write + 0x0 + 0xFFFF + + + CONN_UPDT_SUP_TO + This register will have the new supervision timeout that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SUP_TIMEOUT will be used by hardware. + [15:0] + read-write + + + + + CONN_UPDATE_NEW_SL_INTERVAL + Connection update new Slave Latency X Conn interval Value + 0x3B0 + 32 + read-write + 0x0 + 0xFFFF + + + SL_CONN_INTERVAL_VAL + This register will have the new Slave Latency * Conn Interval value that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SL_CONN_INTERVAL will be used by hardware. + [15:0] + read-write + + + + + CONN_REQ_WORD0 + Connection request address word 0 + 0x3C0 + 32 + read-write + 0x0 + 0xFFFF + + + ACCESS_ADDR_LOWER + This field defines the lower 16 bits of the access address that is to be sent in the connect request packet of the initiator. + [15:0] + read-write + + + + + CONN_REQ_WORD1 + Connection request address word 1 + 0x3C4 + 32 + read-write + 0x0 + 0xFFFF + + + ACCESS_ADDR_UPPER + This field defines the upper16 bits of the access address that is to be sent in the connect request packet of the initiator. + [15:0] + read-write + + + + + CONN_REQ_WORD2 + Connection request address word 2 + 0x3C8 + 32 + read-write + 0x0 + 0xFFFF + + + TX_WINDOW_SIZE_VAL + window_size along with the window_offset is used to calculate the first connection point anchor point for the master. +This shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms). +Values range from 0 to 10 ms. + [7:0] + read-write + + + CRC_INIT_LOWER + This field defines the lower byte [7:0] of the CRC initialization value. + [15:8] + read-write + + + + + CONN_REQ_WORD3 + Connection request address word 3 + 0x3CC + 32 + read-write + 0x0 + 0xFFFF + + + CRC_INIT_UPPER + This field defines the upper byte [23:8] of the CRC initialization value that is to be sent in the connect request packet of the initiator. + [15:0] + read-write + + + + + CONN_REQ_WORD4 + Connection request address word 4 + 0x3D0 + 32 + read-write + 0x0 + 0xFFFF + + + TX_WINDOW_OFFSET + This is used to determine the anchor point for the master transmission. +Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value. + [15:0] + read-write + + + + + CONN_REQ_WORD5 + Connection request address word 5 + 0x3D4 + 32 + read-write + 0x0 + 0xFFFF + + + CONNECTION_INTERVAL_VAL + The value configured in this register determines the spacing between the connection events. +This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s. + [15:0] + read-write + + + + + CONN_REQ_WORD6 + Connection request address word 6 + 0x3D8 + 32 + read-write + 0x0 + 0xFFFF + + + SLAVE_LATENCY_VAL + The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. The value of connSlaveLatency should not cause a Supervision Timeout. This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500. + [15:0] + read-write + + + + + CONN_REQ_WORD7 + Connection request address word 7 + 0x3DC + 32 + read-write + 0x0 + 0xFFFF + + + SUPERVISION_TIMEOUT_VAL + This field defines the maximum time between two received Data packet PDUs before the connection is considered lost. +This shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval. + [15:0] + read-write + + + + + CONN_REQ_WORD8 + Connection request address word 8 + 0x3E0 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_CHANNELS_LOWER + This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices. +1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [15:0] + read-write + + + + + CONN_REQ_WORD9 + Connection request address word 9 + 0x3E4 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_CHANNELS_MID + This register field indicates which of the data channels are in use. This stores the information for the middle 16 (31:16) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [15:0] + read-write + + + + + CONN_REQ_WORD10 + Connection request address word 10 + 0x3E8 + 32 + read-write + 0x0 + 0x1F + + + DATA_CHANNELS_UPPER + This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices. +'1' indicates the corresponding data channel is used and '0' indicates the channel is unused. + [4:0] + read-write + + + + + CONN_REQ_WORD11 + Connection request address word 11 + 0x3EC + 32 + read-write + 0x0 + 0xFF + + + HOP_INCREMENT_2 + This field is used for the data channel selection process. + [4:0] + read-write + + + SCA_2 + This field defines the sleep clock accuracies given in ppm. + [7:5] + read-write + + + + + PDU_RESP_TIMER + PDU response timer/Generic Timer (MMMS mode) + 0xA04 + 32 + read-write + 0x0 + 0xFFFF + + + PDU_RESP_TIME_VAL + Non MMMS mode: This register is loaded with the count value to monitor the time to get a response for a PDU from peer device. +Firmware starts the timer by issuing the command, RESP_TIMER_ON, after it has queued a PDU for transmission, that requires a response. +If a response is received, firmware stops and clears the timer by issuing the command RESP_TIMER_OFF. +If this timer expires, it results in hardware closing the connection and triggering a conn_closed interrupt. +The discon_status field in the Connection status register is set with the appropriate reason. +Units : Milliseconds. +Resolution : 1.25 ms + +MMMS mode: This register is loaded with a count value, which when matched by the internal timer, triggers the GEN_TIMER_INTR. This is recommended to be used as a one shot timer and not as a periodic timer. +Firmware starts the timer by loading the expiry time and issuing the command, RESP_TIMER_ON. +Once the timer expiry is triggered with the interrupt GEN_TIMER_INTR, the firmware stops the timer by issuing the command RESP_TIMER_OFF. +Resolution : 625 us + [15:0] + read-write + + + + + NEXT_RESP_TIMER_EXP + Next response timeout instant + 0xA08 + 32 + read-only + 0x0 + 0xFFFF + + + NEXT_RESPONSE_INSTANT + This field defines the clock instant at which the next PDU response timeout event will occur on a connection. +This is with reference to the 16-bit internal reference clock. + [15:0] + read-only + + + + + NEXT_SUP_TO + Next supervision timeout instant + 0xA0C + 32 + read-only + 0x0 + 0xFFFF + + + NEXT_TIMEOUT_INSTANT + This field defines the clock instant at which the next connection supervision timeout event will occur on a connection +This is with reference to the 16-bit internal reference clock. + [15:0] + read-only + + + + + LLH_FEATURE_CONFIG + Feature enable + 0xA10 + 32 + read-write + 0x6 + 0x7 + + + QUICK_TRANSMIT + Quick transmit feature in slave latency is enabled by setting this bit. +When slave latency is enabled, this feature enables the slave to transmit in the immediate connection interval, in case required, instead of waiting till the end of slave latency + [0:0] + read-write + + + SL_DSM_EN + Enable/Disable Slave Latency Period DSM. + [1:1] + read-write + + + US_COUNTER_OFFSET_ADJ + Enable/Disable the connection US counter offset adjust. For non-MMMS mode, this bit must be tied to 1. + [2:2] + read-write + + + + + WIN_MIN_STEP_SIZE + Window minimum step size + 0xA14 + 32 + read-write + 0x2064 + 0xFFFF + + + STEPDN + After receiving 2 consecutive good packets the reference window is gradually decremented by step down size until it reaches window minimum. The unit is in microseconds + [3:0] + read-write + + + STEPUP + If packets are missed, the reference window is gradually increased by step up size, until it receives 2 consecutive good packets. The unit is in microseconds + [7:4] + read-write + + + WINDOW_MIN_FW + Minimum window interval value programmed by firmware. While the slave receive window is decremented, the windows_min_fw sets the lowest value of the window widen value to ensure packets are not missed. The unit is in microseconds. + [15:8] + read-write + + + + + SLV_WIN_ADJ + Slave window adjustment + 0xA18 + 32 + read-write + 0x10 + 0x7FF + + + SLV_WIN_ADJ + Window Adjust value. This value is added to the calculated slave window widening value to be used as final window widen value. + [10:0] + read-write + + + + + SL_CONN_INTERVAL + Slave Latency X Conn Interval Value + 0xA1C + 32 + read-write + 0x0 + 0xFFFF + + + SL_CONN_INTERVAL_VAL + This field defines the (SL*CI) product for the ongoing connection. This value is used in calculation of next connection instant during slave latency. + [15:0] + read-write + + + + + LE_PING_TIMER_ADDR + LE Ping connection timer address + 0xA20 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_PING_TIMER_ADDR + The register used to configure the LE Au-thenticated payload Timeout (LE APTO) which is the Maximum amount of time specified between packets authenticated by a MIC. +This value of ping timer is in the order of 10ms, valid range 0x1 ~ 0xFFFF + [15:0] + read-write + + + + + LE_PING_TIMER_OFFSET + LE Ping connection timer offset + 0xA24 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_PING_TIMER_OFFSET + The value of ping timer nearly expired offset in the order of 10ms, valid range 0x0 ~ 0xFFFF. This is the time period after which the ping timer nearly expired interrupt is generated. + [15:0] + read-write + + + + + LE_PING_TIMER_NEXT_EXP + LE Ping timer next expiry instant + 0xA28 + 32 + read-only + 0x0 + 0xFFFF + + + CONN_PING_TIMER_NEXT_EXP + The value of ping timer next expiry instant in the terms of native clock value (least 16 bit value of the 17 bit ping counter). + This together with CONN_PING_TIMER_NEXT_EXP_WRAP will provide the correct status of ping timer duration. + [15:0] + read-only + + + + + LE_PING_TIMER_WRAP_COUNT + LE Ping Timer wrap count + 0xA2C + 32 + read-only + 0x0 + 0xFFFF + + + CONN_SEC_CURRENT_WRAP + This register holds the current position of the Ping timer. + [15:0] + read-only + + + + + TX_EN_EXT_DELAY + Transmit enable extension delay + 0xE00 + 32 + read-write + 0x1345 + 0xFFFF + + + TXEN_EXT_DELAY + Transmit enable extension delay. This is to extend the active state (high) of rif_tx_en signal after the last bit is sent out from LLH. The unit is in microsecond and the supported range is 00 - 31 us. + [3:0] + read-write + + + RXEN_EXT_DELAY + receiver enable extension delay. This is to extend the active state (high) of dbus_rx_en signal after the last bit is received from demod. The unit is in microsecond and the supported range is 00 - 31 us. + [7:4] + read-write + + + DEMOD_2M_COMP_DLY + 2Mbps demod delay delta compare to 1Mbps demod delay. This data is 2's comp data. + [11:8] + read-write + + + MOD_2M_COMP_DLY + 2Mbps modulation delay delta compare to 1Mbps demod delay. This data is 2's comp data. + [15:12] + read-write + + + + + TX_RX_SYNTH_DELAY + Transmit/Receive enable delay + 0xE04 + 32 + read-write + 0x0 + 0xFFFF + + + RX_EN_DELAY + The delay used to assert rif_rx_en, Rx_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the Radio receiver. +The value to be programmed to the Rx_en_delay [7:0] = rx_on_delay - Rx_tRamp +rx_on_delay[7:0] = TX_RX_ON_DELAY[7:0]) +Rx_tRamp = Radio receiver rampup time + [7:0] + read-write + + + TX_EN_DELAY + The delay used to assert rif_tx_en exactly Tx_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the Radio transmitter. +The value to be programmed to the Tx_en_delay [7:0] = tx_on_delay - Tx_tRamp +tx_on_delay[7:0] = TX_RX_ON_DELAY[15:8]) +Tx_tRamp = Radio transmitter ramp_up + [15:8] + read-write + + + + + EXT_PA_LNA_DLY_CNFG + External TX PA and RX LNA delay configuration + 0xE08 + 32 + read-write + 0x0 + 0xFFFF + + + LNA_CTL_DELAY + The delay used to assert LNA_CTL, LNA_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the external Low Noise Amplifier. +The value to be programmed to the lna_ctl_delay [7:0] = rx_on_delay - LNA_tRamp +rx_on_delay[7:0] = TX_RX_ON_DELAY[7:0]) +LNA_tRamp = External Low Noise Amplifier startup time + [7:0] + read-write + + + PA_CTL_DELAY + The delay used to assert PA_CTL exactly PA_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the external power amplifier. +The value to be programmed to the pa_ctl_delay [7:0] = tx_on_delay - PA_tRamp +tx_on_delay[7:0] = TX_RX_ON_DELAY[15:8]) +PA_tRamp = External Power Amplifier ramp time + [15:8] + read-write + + + + + LL_CONFIG + Link Layer additional configuration + 0xE10 + 32 + read-write + 0x4C00 + 0x7FEF + + + RSSI_SEL + Controls the RSSI reads. When this bit is 1, the bit RSSI_INTR_SEL is don't care. +0 - RSSI read is initiated after the the packet is received +1 - RSSI read is completed before the packet is received. +When RCB Interface is operating 4Mhz are lower this bit should be set to 1'b0. + [0:0] + read-write + + + TX_RX_CTRL_SEL + Controls the mode of issueing TX_EN & RX_EN to the Radio +1 - TX_EN and RX_EN are issued through direct pins +0 - TX_EN and RX_EN are issued through RCB writes + [1:1] + read-write + + + TIFS_ENABLE + Setting this bit enables the tx 1MHz pulse to match the received bpktctl from CYBLERD55. This will result is reduced TIFS variation + [2:2] + read-write + + + TIMER_LF_SLOT_ENABLE + Controls the wakeup timer configuration +1 - Wakeup time is compensated with the LF_OFFSET +0 - Wakeup time is not compensated with the LF_OFFSET as in legacy mode + [3:3] + read-write + + + RSSI_INTR_SEL + Controls the engine interrupt generation based on RSSI reads. This is valid only if RSSI_SEL is 0. +0 - Receive interrupts are triggerred after the RSSI read is complete +1 - Receive interrupts are triggerred after the last bit of CRC + [5:5] + read-write + + + RSSI_EARLY_CNFG + Controls the early RSSI reads. This is applicable only when RSSI_SEL is 1. +1 - RSSI read is initiated during the first CRC byte reception. +0 - RSSI read is initiated during the third CRC byte reception. + [6:6] + read-write + + + TX_RX_PIN_DLY + Controls the delay from DBUS_TX, DBUS_RX assertion to the assertion on the pins. This is applicable only when TX_RX_CTRL_SEL is set. +0 - The pin assertion is delayed by 4 cycles. +1 - The pin assertion is delayed by 8 cycles. + [7:7] + read-write + + + TX_PA_PWR_LVL_TYPE + Controls the TX power level format given to the CYBLERD55 chip. +0 - The power level given to CYBLERD55 is in 4 bit code format from ADV_CH_TX_POWER for advertising channel and DTM packets & from CONN_CH_TX_POWER for connection channel packets. The power level setting is decoded and given to the PA. +1 - The power level given to CYBLERD55 is in 18 bit power level setting format from {ADV_CH_TX_POWER_LVL_MS, ADV_CH_TX_POWER_LVL_LS} channel and DTM packets & from {CONN_CH_TX_POWER_LVL_MS, CONN_CH_TX_POWER_LVL_LS} for connection channel packets. This setting is directly given to the PA. + [8:8] + read-write + + + RSSI_ENERGY_RD + Controls the RSSI reads. +0 - Channel Energy read is not initiated if no packet is received during a receive cycle +1 - Channel Energy read is initiated at the end of the receive cycle if no packet is received + [9:9] + read-write + + + RSSI_EACH_PKT + Controls the RSSI reads. +0 - RSSI read is not initiated for zero length and aborted packets +1 - RSSI read is initiated for zero length and aborted packets + [10:10] + read-write + + + FORCE_TRIG_RCB_UPDATE + Controls the RCB update to radio on TX/RX enable. Applicable only when TX_RX_CTRL_SEL is 1'b1 +0 - RCB update is triggerred only when the fields change on rising edge of TX/RX enable +1 - RCB update is force triggerred on rising edge of TX/RX enable +If TX_RX_CTRL_SEL is 1'b1 and ENABLE_RADIO_BOD is 1'b1, this bit needs to be set to 1'b1 + [11:11] + read-write + + + CHECK_DUP_CONN + Controls the duplicate connection checkin ADV and INIT +0 - Does not check if the peer is already connection before a new connection is created +1 - Checks if the peer is already connection before a new connection is created and aborts a duplicate connection creation + [12:12] + read-write + + + MULTI_ENGINE_LPM + Controls the LPM entry condition +0 - Legacy mode LPM entry check +1 - MMMS mode LPM entry check + [13:13] + read-write + + + ADV_DIR_DEVICE_PRIV_EN + Controls the ADV behavior while advertising ADV_DIR and only device privacy is set. When the ADV is transmitting INITA RPA, the bahavior when an Identity address in received from the Initiator in the CONN_REQ is given below +0 - Abort the CONN_REQ and continue with advertisement +1 - Check the address against PEER_SEC_ADDR_ADV and create connection on a match. + [14:14] + read-write + + + + + LL_CONTROL + LL Backward compatibility + 0xF00 + 32 + read-write + 0x2 + 0xFFFF + + + PRIV_1_2 + Enables Privacy 1.2 Feature. + [0:0] + read-write + + + DLE + Enables Data Length extension feature in DTM, connection and encryption modules. +This bit should always be set to 1'b1. 1'b0 is not supported. + [1:1] + read-write + + + WL_READ_AS_MEM + The Whilelist read logic is controlled using this bit. +0 - The reads to the whitelist address range is treated as FIFO reads and the pointers are reset by issueing the RESET_READ_PTR command. +1 - The reads to the whitelist address range is treated an memory reads. Any whilelist entry can be read. + [2:2] + read-write + + + ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL + Controls the ADVCH FIFO flushing when PRIV_1_2 is enabled. +0 - Flushes all ADV & INIT packets, as in non privacy 1.2 mode, except those with unresolved peer or self RPA. +1 - Does not flush any CRC good packets + [3:3] + read-write + + + HW_RSLV_LIST_FULL + This bit indicates that the resolving list in the hardware is full and the list is extended in the FW. This will affect the behavior of address resolution. +0 - The resolving list in the hardware is not fully filled. When Whitelist is disabled and a peer identity address not in the resolving list is received, the packet is responded to by the hardware. +1 - The resolving list in the hardware is fully filled. All address comparisons must be extended to the Firmware list as well, Any match in the Firmware list should be followed by copying the matching entry into the hardware resolving list. + [4:4] + read-write + + + RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV + This bit controls the ADV engine behavior when an initiator address match occurs but a privacy mismatch occurs +0 - The packet is aborted +1 - The packet is received and reported to the Link Layer firmware + [5:5] + read-write + + + RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV + This bit controls the ADV engine behavior when a scanner address match occurs but a privacy mismatch occurs +0 - The packet is aborted +1 - The packet is received and reported to the Link Layer firmware + [6:6] + read-write + + + RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN + This bit controls the SCAN engine behavior when an peer address match occurs but a privacy mismatch occurs +0 - The packet is aborted +1 - The packet is received and reported to the Link Layer firmware + [7:7] + read-write + + + RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI + This bit controls the INIT engine behavior when an peer address match occurs but a privacy mismatch occurs +0 - The packet is aborted +1 - The packet is received and reported to the Link Layer firmware + [8:8] + read-write + + + RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI + This bit controls the INIT engine behavior when a self address match occurs but a privacy mismatch occurs +0 - The packet is aborted +1 - The packet is received and reported to the Link Layer firmware + [9:9] + read-write + + + PRIV_1_2_ADV + Enables Privacy 1.2 for ADV engine + [10:10] + read-write + + + PRIV_1_2_SCAN + Enables Privacy 1.2 for SCAN engine + [11:11] + read-write + + + PRIV_1_2_INIT + Enables Privacy 1.2 for INIT engine + [12:12] + read-write + + + EN_CONN_RX_EN_MOD + This bit controls the Connection RX enable modification mode when SLV_CONN_PEER_RPA_NOT_RSLVD is set. +1'b0 - The Connection RX enable is unmodified +1'b1 - The Connection RX enable is during the Peer INIT RPA unresolved state is modified, until it is resolved. + [13:13] + read-write + + + SLV_CONN_PEER_RPA_NOT_RSLVD + This bit is asserted when SLV_CONN_PEER_RPA_UNMCH_INTR is set. The device does not enter into Connection established state until this bit is cleared after the RPA is resoved by the firmware. If the firmware is not able to resolve the RPA within the supervision timeout, the device aborts the connection establishement and this bit is cleared by the hardware. +This bit is valid only if PRIV_1_2 is set. + [14:14] + read-write + + + ADVCH_FIFO_FLUSH + When set, flushes the ADVCH FIFO. The bit is auto cleared. +Note that this should be used only when the FIFO is not read by the firmware. If firmware has started reading the FIFO, then the FIFO must be emptied exclusively by firmware reads + [15:15] + write-only + + + + + DEV_PA_ADDR_L + Device Resolvable/Non-Resolvable Private address lower register + 0xF04 + 32 + read-write + 0x3412 + 0xFFFF + + + DEV_PA_ADDR_L + Lower 16 bit of 48-bit Random Private address of the device. + [15:0] + read-write + + + + + DEV_PA_ADDR_M + Device Resolvable/Non-Resolvable Private address middle register + 0xF08 + 32 + read-write + 0x56 + 0xFFFF + + + DEV_PA_ADDR_M + Middle 16 bit of 48-bit Random Private address of the device. + [15:0] + read-write + + + + + DEV_PA_ADDR_H + Device Resolvable/Non-Resolvable Private address higher register + 0xF0C + 32 + read-write + 0x0 + 0xFFFF + + + DEV_PA_ADDR_H + Higher 16 bit of 48-bit Random Private address of the device. + [15:0] + read-write + + + + + 16 + 4 + RSLV_LIST_ENABLE[%s] + Resolving list entry control bit + 0xF10 + 32 + read-write + 0x0 + 0x7FF + + + VALID_ENTRY + Indicates if the index is valid + [0:0] + read-write + + + PEER_ADDR_IRK_SET + Indicates if the listed peer device has shared its IRK. +0 - Identity address in a received packet is accepted. If a valid peer device RPA is available in the list, then the RPA in a received packet is accepted. +1 - Only the peer device RPA, if available in the list, in a received packet is accepted. An Identity address in the received packet is reported as a privacy mismatch. + [1:1] + read-write + + + SELF_ADDR_IRK_SET_RX + Indicates if the local IRK has been shared with the listed peer device +0 - Self Identity address in a received packet is accepted. If a valid self RPA is available in the list, then the RPA in a received packet is accepted. +1 - Only the self device RPA, if available in the list, in a received packet is accepted. A Self Identity address in the received packet is reported as a privacy mismatch. + [2:2] + read-write + + + WHITELISTED_PEER + Indicates if the listed peer device is in the whitelist + [3:3] + read-write + + + PEER_ADDR_TYPE + Indicates the address type of the listed peer device + [4:4] + read-write + + + PEER_ADDR_RPA_VAL + Indicates that the peer device RPA in the list is valid + [5:5] + read-write + + + SELF_ADDR_RXD_RPA_VAL + Indicates that the received self RPA in the list is valid + [6:6] + read-write + + + SELF_ADDR_TX_RPA_VAL + Indicates that the self RPA in the list to be transmitted is valid + [7:7] + read-write + + + SELF_ADDR_INIT_RPA_SEL + When Initiator whitelist is disabled, this bit indicates the specific device to from which ADV packets will be accepted. + [8:8] + read-write + + + SELF_ADDR_TYPE_TX + Indicates the TX addr type to be used for SCANA and INITA +0 - Self Identity address is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets +1 - Self RPA address provided in RSLV_LIST_TX_INIT_RPA field in the resolving list with the associated valid bit in SELF_ADDR_TX_RPA_VAL above is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets + [9:9] + read-write + + + ENTRY_CONNECTED + Indicates if the entry is already in connection with our device + [10:10] + read-write + + + + + WL_CONNECTION_STATUS + whitelist valid entry bit + 0xFA0 + 32 + read-write + 0x0 + 0xFFFF + + + WL_ENTRY_CONNECTED + Stores the connection status of each of the sixteen device address stored in the whitelist. +1 - White list entry is already in a connection +0 - White list entry is not in a connection + [15:0] + read-write + + + + + CONN_RXMEM_BASE_ADDR_DLE + DLE Connection RX memory base address + 0x1800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CONN_RX_MEM_BASE_ADDR_DLE + Data from Rx memory are read as 32-bit wide data. This memory is valid only if DLE is set. + [31:0] + read-write + + + + + CONN_TXMEM_BASE_ADDR_DLE + DLE Connection TX memory base address + 0x2800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CONN_TX_MEM_BASE_ADDR_DLE + Data to Tx memory are written as 32-bit wide data. This memory is valid only if DLE is set. + [31:0] + read-write + + + + + CONN_1_PARAM_MEM_BASE_ADDR + Connection Parameter memory base address for connection 1 + 0x12800 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_1_PARAM + N/A + [15:0] + read-write + + + + + CONN_2_PARAM_MEM_BASE_ADDR + Connection Parameter memory base address for connection 2 + 0x12880 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_2_PARAM + N/A + [15:0] + read-write + + + + + CONN_3_PARAM_MEM_BASE_ADDR + Connection Parameter memory base address for connection 3 + 0x12900 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_3_PARAM + N/A + [15:0] + read-write + + + + + CONN_4_PARAM_MEM_BASE_ADDR + Connection Parameter memory base address for connection 4 + 0x12980 + 32 + read-write + 0x0 + 0xFFFF + + + CONN_4_PARAM + N/A + [15:0] + read-write + + + + + NI_TIMER + Next Instant Timer + 0x14000 + 32 + read-write + 0x0 + 0xFFFF + + + NI_TIMER + BT Slot at which the next connection has to be serviced, granularity is 625us. The NI timer has to be programmed 1.25ms before the connection event + [15:0] + read-write + + + + + US_OFFSET + Micro-second Offset + 0x14004 + 32 + read-write + 0x0 + 0x3FF + + + US_OFFSET_SLOT_BOUNDARY + Micro Second Offset from the Slot Bounday at which the connection programmed in NEXT_CONN has to be serviced. This register along with NI_TIMER has to be programmed 1.25ms before the connection event. The granularity is 1us + [9:0] + read-write + + + + + NEXT_CONN + Next Connection + 0x14008 + 32 + read-write + 0x0 + 0x7F + + + NEXT_CONN_INDEX + Connection Index to be serviced. Allowed values are 0,1,2,3. + [4:0] + read-write + + + NEXT_CONN_TYPE + Connection type +1 - Master Connection +0 - Slave Connection + [5:5] + read-write + + + NI_VALID + Flag indication if programmed NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the connection of if NI_TIMER is pointing to past value + [6:6] + read-write + + + + + NI_ABORT + Abort next scheduled connection + 0x1400C + 32 + read-write + 0x0 + 0x3 + + + NI_ABORT + Setting this bit clears the schedule NI + [0:0] + read-write + + + ABORT_ACK + This bit will set if the scheduled NI is aborted + [1:1] + read-write + + + + + CONN_NI_STATUS + Connection NI Status + 0x14020 + 32 + read-only + 0xFFFF + 0xFFFF + + + CONN_NI + HW updates this register with the next Connection Instant for current serviced connection, granularity is 625us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF. + [15:0] + read-only + + + + + NEXT_SUP_TO_STATUS + Next Supervision timeout Status + 0x14024 + 32 + read-only + 0x0 + 0xFFFF + + + NEXT_SUP_TO + HW updates this register for the SuperVision timeout next instant, granularity is 625us + [15:0] + read-only + + + + + MMMS_CONN_STATUS + Connection Status + 0x14028 + 32 + read-only + 0x0 + 0xFFFF + + + CURR_CONN_INDEX + Connection Index that was serviced. Legal values are 0,1,2,3. + [4:0] + read-only + + + CURR_CONN_TYPE + Connection type +1 - Master Connection +0 - Slave Connection + [5:5] + read-only + + + SN_CURR + Sequence Number of Packets exchanged + [6:6] + read-only + + + NESN_CURR + Next Sequence Number + [7:7] + read-only + + + LAST_UNMAPPED_CHANNEL + Last Unmapped Channel + [13:8] + read-only + + + PKT_MISS + 1 - Packet Missed +0 - Connection exchanged packets + [14:14] + read-only + + + ANCHOR_PT_STATE + Anchor Point State +0 - Anchor point missed +1 - Anchor point established + [15:15] + read-only + + + + + BT_SLOT_CAPT_STATUS + BT Slot Captured Status + 0x1402C + 32 + read-only + 0x0 + 0xFFFF + + + BT_SLOT + During slave connection event, HW updates this register with the captured BT_SLOT at anchor point, granularity is 625us + [15:0] + read-only + + + + + US_CAPT_STATUS + Micro-second Capture Status + 0x14030 + 32 + read-only + 0x0 + 0x3FF + + + US_CAPT + During slave connection event, HW updates this register with the captured microsecond at anchor point, granularity is 1us + [9:0] + read-only + + + + + US_OFFSET_STATUS + Micro-second Offset Status + 0x14034 + 32 + read-only + 0xD5 + 0xFFFF + + + US_OFFSET + During slave connection event, HW updates this register with the calculated us_offset at anchor point, granularity is 1us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0x00D5. + [15:0] + read-only + + + + + ACCU_WINDOW_WIDEN_STATUS + Accumulated Window Widen Status + 0x14038 + 32 + read-only + 0x0 + 0xFFFF + + + ACCU_WINDOW_WIDEN + Accumulated Window Widen Value. HW updates this register at the close of slave connection event + [15:0] + read-only + + + + + EARLY_INTR_STATUS + Status when early interrupt is raised + 0x1403C + 32 + read-only + 0x0 + 0xFFFF + + + CONN_INDEX_FOR_EARLY_INTR + Connection Index for which early interrupt is raised + [4:0] + read-only + + + CONN_TYPE_FOR_EARLY_INTR + Connection type for which early interrupt is raised. + [5:5] + read-only + + + US_FOR_EARLY_INTR + US offset when early interrupt is raised + [15:6] + read-only + + + + + MMMS_CONFIG + Multi-Master Multi-Slave Config + 0x14040 + 32 + read-write + 0x0 + 0x7FF + + + MMMS_ENABLE + Configuration bit to enable MMMS functionality + [0:0] + read-write + + + DISABLE_CONN_REQ_PARAM_IN_MEM + If set to 1'b1 and MMMS enabled, then the parameters received in connection request are not stored in CONN_REQ_PARAM memory. By default this bit is 1'b0 and the connection request parameters are stored in connection memory. +This bit is intended as a fail-safe. Should not be changed dynamically during runtime + [1:1] + read-write + + + DISABLE_CONN_PARAM_MEM_WR + By default on end_ce, the connection parameters memory is loaded with the updated connection parameters. Setting this bit prevent's this update. +This bit is intended as a fail-safe. Should not be changed dynamically during runtime + [2:2] + read-write + + + CONN_PARAM_FROM_REG + By default the parameters for the connection are picked up from the connection parameters memory. Setting this bit disables this and the parameters are picked up from registers +0 - HW loads the parameters from connection memory +1 - Firmware should program the paramters for the connection event +This bit is intended as a fail-safe. Should not be changed dynamically during runtime + [3:3] + read-write + + + ADV_CONN_INDEX + This field specifies the connection index for which ADV is enabled + [8:4] + read-write + + + CE_LEN_IMMEDIATE_EXPIRE + Enable for CE length immediate expiry + [9:9] + read-write + + + RESET_RX_FIFO_PTR + Setting this bit resets the receive FIFO pointers + [10:10] + read-write + + + + + US_COUNTER + Running US of the current BT Slot + 0x14044 + 32 + read-only + 0x0 + 0x3FF + + + US_COUNTER + Current value of the US Counter + [9:0] + read-only + + + + + US_CAPT_PREV + Previous captured US of the BT Slot + 0x14048 + 32 + read-write + 0x0 + 0x3FF + + + US_CAPT_LOAD + HW uses this register to load the us_offset from connection parameter memory. This can be used by firmware as a fail safe option if the HW load from memory is disabled. In alll other conditions firmware should not use this register. + [9:0] + read-write + + + + + EARLY_INTR_NI + NI at early interrupt + 0x1404C + 32 + read-only + 0x0 + 0xFFFF + + + EARLY_INTR_NI + Connection Next instant when the early interrupt is triggered + [15:0] + read-only + + + + + MMMS_MASTER_CREATE_BT_CAPT + BT slot capture for master connection creation + 0x14080 + 32 + read-only + 0x0 + 0xFFFF + + + BT_SLOT + This register captures the BT_SLOT when master connection is created, granularity is 625us + [15:0] + read-only + + + + + MMMS_SLAVE_CREATE_BT_CAPT + BT slot capture for slave connection creation + 0x14084 + 32 + read-only + 0x0 + 0x3FF + + + US_CAPT + This register captures the BT_SLOT when slave connection is created, granularity is 625us + [9:0] + read-only + + + + + MMMS_SLAVE_CREATE_US_CAPT + Micro second capture for slave connection creation + 0x14088 + 32 + read-only + 0x0 + 0xFFFF + + + US_OFFSET_SLAVE_CREATED + This register captures the us when slave connection is created, granularity is 1us + [15:0] + read-only + + + + + 16 + 4 + MMMS_DATA_MEM_DESCRIPTOR[%s] + Data buffer descriptor 0 to 15 + 0x14100 + 32 + read-write + 0x0 + 0x3FF + + + LLID_C1 + N/A + [1:0] + read-write + + + DATA_LENGTH_C1 + This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set. +Range 0x00 to 0xFF. + [9:2] + read-write + + + + + CONN_1_DATA_LIST_SENT + data list sent update and status for connection 1 + 0x14200 + 32 + read-write + 0x0 + 0xF8F + + + LIST_INDEX__TX_SENT_3_0_C1 + Write:Indicates the buffer index for which the SENT bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_SENT[3:0]. +The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are +1 - queued +0 - no packet / packet ack received by hardware +Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Used to set the SENT bit in hardware for the selected packet buffer. +1 - packet queued +When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. +The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. +Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. + [7:7] + write-only + + + BUFFER_NUM_TX_SENT_3_0_C1 + Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections + [11:8] + read-write + + + + + CONN_1_DATA_LIST_ACK + data list ack update and status for connection 1 + 0x14204 + 32 + read-write + 0x0 + 0x8F + + + LIST_INDEX__TX_ACK_3_0_C1 + Write: Indicates the buffer index for which the ACK bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_ACK[3:0] +If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. +Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. +Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. +Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. +For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. +This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. +The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. + [7:7] + write-only + + + + + CONN_1_CE_DATA_LIST_CFG + Connection specific pause resume for connection 1 + 0x14208 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_LIST_INDEX_LAST_ACK_INDEX_C1 + Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. +The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. +Hardware will start the next data transmission from the index indicated by this field. + [3:0] + read-write + + + DATA_LIST_HEAD_UP_C1 + Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. +The bit must be set every time the firmware needs to indicate the start/resume. + [4:4] + read-write + + + SLV_MD_CONFIG_C1 + This bit is set to configure the MD bit control when the design is in slave mode. +1 - MD bit will be decided on packet pending status +0 - MD bit will be decided on packet queued in next buffer status +This bit has valid only when MD_BIT_CLEAR bit is not set + [5:5] + read-write + + + MD_C1 + MD bit set to '1' indicates device has more data to be sent. + [6:6] + read-write + + + MD_BIT_CLEAR_C1 + This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' + +1 - MD bit is exclusively controlled by software, based on status of bit [6]. + +0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, +a) If there are packets queued for transmission. +b) If there is an acknowledgement awaited from the remote side for the packet transmitted. + [7:7] + read-write + + + PAUSE_DATA_C1 + Pause data. +1 - pause data, +0 - do not pause. +The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. +But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out + [8:8] + read-write + + + KILL_CONN + Kills the connection immediately when the connection event is active + [9:9] + read-write + + + KILL_CONN_AFTER_TX + Kills the connection when the connection event is active and a TX is completed + [10:10] + read-write + + + EMPTYPDU_SENT + This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW + [11:11] + read-write + + + CURRENT_PDU_INDEX_C1 + The index of the transmit packet buffer that is currently in transmission/waiting for transmission. + [15:12] + read-only + + + + + CONN_2_DATA_LIST_SENT + data list sent update and status for connection 2 + 0x14210 + 32 + read-write + 0x0 + 0xF8F + + + LIST_INDEX__TX_SENT_3_0_C1 + Write:Indicates the buffer index for which the SENT bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_SENT[3:0]. +The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are +1 - queued +0 - no packet / packet ack received by hardware +Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Used to set the SENT bit in hardware for the selected packet buffer. +1 - packet queued +When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. +The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. +Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. + [7:7] + write-only + + + BUFFER_NUM_TX_SENT_3_0_C1 + Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections + [11:8] + read-write + + + + + CONN_2_DATA_LIST_ACK + data list ack update and status for connection 2 + 0x14214 + 32 + read-write + 0x0 + 0x8F + + + LIST_INDEX__TX_ACK_3_0_C1 + Write: Indicates the buffer index for which the ACK bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_ACK[3:0] +If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. +Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. +Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. +Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. +For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. +This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. +The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. + [7:7] + write-only + + + + + CONN_2_CE_DATA_LIST_CFG + Connection specific pause resume for connection 2 + 0x14218 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_LIST_INDEX_LAST_ACK_INDEX_C1 + Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. +The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. +Hardware will start the next data transmission from the index indicated by this field. + [3:0] + read-write + + + DATA_LIST_HEAD_UP_C1 + Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. +The bit must be set every time the firmware needs to indicate the start/resume. + [4:4] + read-write + + + SLV_MD_CONFIG_C1 + This bit is set to configure the MD bit control when the design is in slave mode. +1 - MD bit will be decided on packet pending status +0 - MD bit will be decided on packet queued in next buffer status +This bit has valid only when MD_BIT_CLEAR bit is not set + [5:5] + read-write + + + MD_C1 + MD bit set to '1' indicates device has more data to be sent. + [6:6] + read-write + + + MD_BIT_CLEAR_C1 + This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' + +1 - MD bit is exclusively controlled by software, based on status of bit [6]. + +0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, +a) If there are packets queued for transmission. +b) If there is an acknowledgement awaited from the remote side for the packet transmitted. + [7:7] + read-write + + + PAUSE_DATA_C1 + Pause data. +1 - pause data, +0 - do not pause. +The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. +But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out + [8:8] + read-write + + + KILL_CONN + Kills the connection immediately when the connection event is active + [9:9] + read-write + + + KILL_CONN_AFTER_TX + Kills the connection when the connection event is active and a TX is completed + [10:10] + read-write + + + EMPTYPDU_SENT + This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW + [11:11] + read-write + + + CURRENT_PDU_INDEX_C1 + The index of the transmit packet buffer that is currently in transmission/waiting for transmission. + [15:12] + read-only + + + + + CONN_3_DATA_LIST_SENT + data list sent update and status for connection 3 + 0x14220 + 32 + read-write + 0x0 + 0xF8F + + + LIST_INDEX__TX_SENT_3_0_C1 + Write:Indicates the buffer index for which the SENT bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_SENT[3:0]. +The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are +1 - queued +0 - no packet / packet ack received by hardware +Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Used to set the SENT bit in hardware for the selected packet buffer. +1 - packet queued +When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. +The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. +Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. + [7:7] + write-only + + + BUFFER_NUM_TX_SENT_3_0_C1 + Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections + [11:8] + read-write + + + + + CONN_3_DATA_LIST_ACK + data list ack update and status for connection 3 + 0x14224 + 32 + read-write + 0x0 + 0x8F + + + LIST_INDEX__TX_ACK_3_0_C1 + Write: Indicates the buffer index for which the ACK bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_ACK[3:0] +If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. +Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. +Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. +Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. +For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. +This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. +The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. + [7:7] + write-only + + + + + CONN_3_CE_DATA_LIST_CFG + Connection specific pause resume for connection 3 + 0x14228 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_LIST_INDEX_LAST_ACK_INDEX_C1 + Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. +The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. +Hardware will start the next data transmission from the index indicated by this field. + [3:0] + read-write + + + DATA_LIST_HEAD_UP_C1 + Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. +The bit must be set every time the firmware needs to indicate the start/resume. + [4:4] + read-write + + + SLV_MD_CONFIG_C1 + This bit is set to configure the MD bit control when the design is in slave mode. +1 - MD bit will be decided on packet pending status +0 - MD bit will be decided on packet queued in next buffer status +This bit has valid only when MD_BIT_CLEAR bit is not set + [5:5] + read-write + + + MD_C1 + MD bit set to '1' indicates device has more data to be sent. + [6:6] + read-write + + + MD_BIT_CLEAR_C1 + This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' + +1 - MD bit is exclusively controlled by software, based on status of bit [6]. + +0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, +a) If there are packets queued for transmission. +b) If there is an acknowledgement awaited from the remote side for the packet transmitted. + [7:7] + read-write + + + PAUSE_DATA_C1 + Pause data. +1 - pause data, +0 - do not pause. +The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. +But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out + [8:8] + read-write + + + KILL_CONN + Kills the connection immediately when the connection event is active + [9:9] + read-write + + + KILL_CONN_AFTER_TX + Kills the connection when the connection event is active and a TX is completed + [10:10] + read-write + + + EMPTYPDU_SENT + This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW + [11:11] + read-write + + + CURRENT_PDU_INDEX_C1 + The index of the transmit packet buffer that is currently in transmission/waiting for transmission. + [15:12] + read-only + + + + + CONN_4_DATA_LIST_SENT + data list sent update and status for connection 4 + 0x14230 + 32 + read-write + 0x0 + 0xF8F + + + LIST_INDEX__TX_SENT_3_0_C1 + Write:Indicates the buffer index for which the SENT bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_SENT[3:0]. +The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are +1 - queued +0 - no packet / packet ack received by hardware +Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Used to set the SENT bit in hardware for the selected packet buffer. +1 - packet queued +When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. +The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. +Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified. + [7:7] + write-only + + + BUFFER_NUM_TX_SENT_3_0_C1 + Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections + [11:8] + read-write + + + + + CONN_4_DATA_LIST_ACK + data list ack update and status for connection 4 + 0x14234 + 32 + read-write + 0x0 + 0x8F + + + LIST_INDEX__TX_ACK_3_0_C1 + Write: Indicates the buffer index for which the ACK bit is being updated by firmware. +The default number of buffers in the IP is 5. The index range is 0-3. + +Read: Reads TX_ACK[3:0] +If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. +Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware. +Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware. + [3:0] + read-write + + + SET_CLEAR_C1 + Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware. +Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware. +For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0. +This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on. +The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet. + [7:7] + write-only + + + + + CONN_4_CE_DATA_LIST_CFG + Connection specific pause resume for connection 4 + 0x14238 + 32 + read-write + 0x0 + 0xFFFF + + + DATA_LIST_INDEX_LAST_ACK_INDEX_C1 + Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded. +The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4. +Hardware will start the next data transmission from the index indicated by this field. + [3:0] + read-write + + + DATA_LIST_HEAD_UP_C1 + Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause. +The bit must be set every time the firmware needs to indicate the start/resume. + [4:4] + read-write + + + SLV_MD_CONFIG_C1 + This bit is set to configure the MD bit control when the design is in slave mode. +1 - MD bit will be decided on packet pending status +0 - MD bit will be decided on packet queued in next buffer status +This bit has valid only when MD_BIT_CLEAR bit is not set + [5:5] + read-write + + + MD_C1 + MD bit set to '1' indicates device has more data to be sent. + [6:6] + read-write + + + MD_BIT_CLEAR_C1 + This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined' + +1 - MD bit is exclusively controlled by software, based on status of bit [6]. + +0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true, +a) If there are packets queued for transmission. +b) If there is an acknowledgement awaited from the remote side for the packet transmitted. + [7:7] + read-write + + + PAUSE_DATA_C1 + Pause data. +1 - pause data, +0 - do not pause. +The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared. +But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out + [8:8] + read-write + + + KILL_CONN + Kills the connection immediately when the connection event is active + [9:9] + read-write + + + KILL_CONN_AFTER_TX + Kills the connection when the connection event is active and a TX is completed + [10:10] + read-write + + + EMPTYPDU_SENT + This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW + [11:11] + read-write + + + CURRENT_PDU_INDEX_C1 + The index of the transmit packet buffer that is currently in transmission/waiting for transmission. + [15:12] + read-only + + + + + MMMS_ADVCH_NI_ENABLE + Enable bits for ADV_NI, SCAN_NI and INIT_NI + 0x14400 + 32 + read-write + 0x0 + 0x7 + + + ADV_NI_ENABLE + This bit is used to enable the Advertisement NI timer and is valid when MMMS_ENABLE=1. +0 - ADV_NI timer is disabled +1 - ADV_NI timer is enabled + +In this mode, the adv engine next instant is scheduled by firmware + [0:0] + read-write + + + SCAN_NI_ENABLE + This bit is used to enable the SCAN NI timer and is valid when MMMS_ENABLE=1. +0 - SCAN_NI timer is disabled +1 - SCAN_NI timer is enabled + +In this mode, the scan engine next instant is scheduled by firmware + [1:1] + read-write + + + INIT_NI_ENABLE + This bit is used to enable the INIT NI timer and is valid when MMMS_ENABLE=1. +0 - INIT_NI timer is disabled +1 - INIT_NI timer is enabled + +In this mode, the init engine next instant is scheduled by firmware + [2:2] + read-write + + + + + MMMS_ADVCH_NI_VALID + Next instant valid for ADV, SCAN, INIT + 0x14404 + 32 + read-write + 0x0 + 0x7 + + + ADV_NI_VALID + This bit indicates if the programmed advertisement NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the advertisment event +0 - ADV_NI timer is not valid +1 - ADV_NI timer is valid + [0:0] + read-write + + + SCAN_NI_VALID + This bit indicates if the programmed scan NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the scanner event +0 - SCAN_NI timer is not valid +1 - SCAN_NI timer is valid + [1:1] + read-write + + + INIT_NI_VALID + This bit indicates if the programmed initiator NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the initiator event +0 - INIT_NI timer is not valid +1 - INIT_NI timer is valid + [2:2] + read-write + + + + + MMMS_ADVCH_NI_ABORT + Abort the next instant of ADV, SCAN, INIT + 0x14408 + 32 + read-write + 0x0 + 0x3 + + + ADVCH_NI_ABORT + FW can use this bit to clear an unserviced NI_VALID for Advertisement or scanner or initiator. HW will clear NI_VALID for ADV/SCAN/INIT if the event has not yet started + [0:0] + write-only + + + ADVCH_ABORT_STATUS + The link layer hardware logic will set this bit when the NI_TIMER is aborted. Firmware to clear this by writing 1'b1 to this register bit + [1:1] + read-write + + + + + CONN_PARAM_NEXT_SUP_TO + Register to configure the supervision timeout for next scheduled connection + 0x14410 + 32 + read-write + 0x0 + 0xFFFF + + + NEXT_SUP_TO_LOAD + HW uses this register to load the Supervision timeout Next instant from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware. + [15:0] + read-write + + + + + CONN_PARAM_ACC_WIN_WIDEN + Register to configure Accumulated window widening for next scheduled connection + 0x14414 + 32 + read-write + 0x0 + 0x3FF + + + ACC_WINDOW_WIDEN + HW uses this register to load the accumulated window windeing value from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware. + [9:0] + read-write + + + + + HW_LOAD_OFFSET + Register to configure offset from connection anchor point at which connection parameter memory should be read + 0x14420 + 32 + read-write + 0x4 + 0x1F + + + LOAD_OFFSET + Load Offset in us before connection event at which the connection parameters are loaded from memory, granularity is in 1us + [4:0] + read-write + + + + + ADV_RAND + Random number generated by Hardware for ADV NI calculation + 0x14424 + 32 + read-only + 0x7 + 0xF + + + ADV_RAND + Random ADV delay, to be used for ADV next instant calculation. The granularity is in BT slot + [3:0] + read-only + + + + + MMMS_RX_PKT_CNTR + Packet Counter of packets in RX FIFO in MMMS mode + 0x14428 + 32 + read-only + 0x0 + 0x3F + + + MMMS_RX_PKT_CNT + Count of all packets in the RX FIFO in MMMS mode + [5:0] + read-only + + + + + 8 + 4 + CONN_RX_PKT_CNTR[%s] + Packet Counter for Individual connection index + 0x14430 + 32 + read-only + 0x0 + 0x3F + + + RX_PKT_CNT + Number of packets received for the connection. Incremented when the packet is received during the connection event and decremented when firmware has processed the packet. The register field FW_PKT_RCV_CONN_INDEX should be programmed before firmware issues the packet received command + [5:0] + read-only + + + + + WHITELIST_BASE_ADDR + Whitelist base address + 0x14800 + 32 + read-write + 0x0 + 0xFFFF + + + WL_BASE_ADDR + Device address values written to white list memory are written as 16-bit wide address. + [15:0] + read-write + + + + + RSLV_LIST_PEER_IDNTT_BASE_ADDR + Resolving list base address for storing Peer Identity address + 0x148C0 + 32 + read-write + 0x0 + 0xFFFF + + + RSLV_LIST_PEER_IDNTT_BASE_ADDR + Device address values written to the list are written as 16-bit wide address. + [15:0] + read-write + + + + + RSLV_LIST_PEER_RPA_BASE_ADDR + Resolving list base address for storing resolved Peer RPA address + 0x14980 + 32 + read-write + 0x0 + 0xFFFF + + + RSLV_LIST_PEER_RPA_BASE_ADDR + Device address values written to the list are written as 16-bit wide address. + [15:0] + read-write + + + + + RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR + Resolving list base address for storing Resolved received INITA RPA + 0x14A40 + 32 + read-write + 0x0 + 0xFFFF + + + RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR + Device address values written to the list are written as 16-bit wide address. + [15:0] + read-write + + + + + RSLV_LIST_TX_INIT_RPA_BASE_ADDR + Resolving list base address for storing generated TX INITA RPA + 0x14B00 + 32 + read-write + 0x0 + 0xFFFF + + + RSLV_LIST_TX_INIT_RPA_BASE_ADDR + Device address values written to the list are written as 16-bit wide address. + [15:0] + read-write + + + + + + BLESS + Bluetooth Low Energy Subsystem Miscellaneous + 0x0001F000 + + DDFT_CONFIG + BLESS DDFT configuration register + 0x60 + 32 + read-write + 0x0 + 0x1F1F03 + + + DDFT_ENABLE + Enables the DDFT output from BLESS +1: DDFT is enabled +0: DDFT is disabled + [0:0] + read-write + + + BLERD_DDFT_EN + Enables the DDFT inputs from CYBLERD55 chip +1: DDFT inputs are enabled +0: DDFT inputs are disabled + [1:1] + read-write + + + DDFT_MUX_CFG1 + dbg_mux_pin1 selection, combine with BLERD and BLESS +5'h00 blerd_ddft_out[0] +5'h01 rcb_tx_fifo_empty +5'h02 hv_ldo_lv_detect_raw +5'h03 dbus_rx_en +5'h04 1'b0 +5'h05 clk_switch_to_sysclk +5'h06 ll_clk_en_sync +5'h07 dsm_entry_stat +5'h08 proc_tx_en +5'h09 rssi_read_start +5'h0A tx_2mbps +5'h0B rcb_bus_busy +5'h0C hv_ldo_en_mt (act_stdbyb) +5'h0D ll_eco_clk_en +5'h0E blerd_reset_assert +5'h0F hv_ldo_byp_n +5'h10 hv_ldo_lv_detect_mt +5'h11 enable_ldo +5'h12 enable_ldo_dly +5'h13 bless_rcb_le_out +5'h14 bless_rcb_clk_out +5'h15 bless_dig_ldo_on_out +5'h16 bless_act_ldo_en_out +5'h17 bless_clk_en_out +5'h18 bless_buck_en_out +5'h19 bless_ret_switch_hv_out +5'h1A efuse_rw_out +5'h1B efuse_avdd_out +5'h1C efuse_config_efuse_mode +5'h1D bless_dbus_tx_en_pad +5'h1E bless_bpktctl_rd +5'h1F 1'b0 + [12:8] + read-write + + + DDFT_MUX_CFG2 + dbg_mux_pin2 selection, combine with BLERD and BLESS +5'h00 blerd_ddft_out[1] +5'h01 rcb_rx_fifo_empty +5'h02 ll_decode_rxdata +5'h03 dbus_tx_en +5'h04 fw_clk_en +5'h05 interrupt_ll_n +5'h06 llh_st_sm +5'h07 llh_st_dsm +5'h08 proc_rx_en +5'h09 rssi_rx_done +5'h0A rx_2mbps +5'h0B rcb_ll_ctrl +5'h0C hv_ldo_byp_n +5'h0D reset_deassert +5'h0E rcb_intr +5'h0F rcb_ll_intr +5'h10 hv_ldo_en_mt (act_stdbyb) +5'h11 hv_ldo_lv_detect_raw +5'h12 bless_rcb_data_in +5'h13 bless_xtal_en_out +5'h14 bless_isolate_n_out +5'h15 bless_reset_n_out +5'h16 bless_ret_ldo_ol_hv_out +5'h17 bless_txd_rxd_out +5'h18 tx_rx_ctrl_sel +5'h19 bless_bpktctl_cy +5'h1A efuse_cs_out +5'h1B efuse_pgm_out +5'h1C efuse_sclk_out +5'h1D hv_ldo_lv_detect_mt +5'h1E enable_ldo +5'h1F enable_ldo_dly + [20:16] + read-write + + + + + XTAL_CLK_DIV_CONFIG + Crystal clock divider configuration register + 0x64 + 32 + read-write + 0x0 + 0xF + + + SYSCLK_DIV + System clock pre-divider value. The 24 MHz crystal clock is divided to generate the system clock. +0: NO_DIV: SYSCLK= XTALCLK/1 +1: DIV_BY_2: SYSCLK= XTALCLK/2 +2: DIV_BY_4: SYSCLK= XTALCLK/4 +3: DIV_BY_8: SYSCLK= XTALCLK/8 + [1:0] + read-write + + + LLCLK_DIV + Link Layer clock pre-divider value. The 24 MHz crystal clock is divided to generate the Link Layer clock. +0: NO_DIV: LLCLK= XTALCLK/1 +1: DIV_BY_2: LLCLK= XTALCLK/2 +2: DIV_BY_4: LLCLK= XTALCLK/4 +3: DIV_BY_8: LLCLK= XTALCLK/8 + [3:2] + read-write + + + + + INTR_STAT + Link Layer interrupt status register + 0x68 + 32 + read-write + 0x0 + 0xFFF + + + DSM_ENTERED_INTR + On a firmware request to LL to enter into state machine, working on LF clock, LL transitions into Deep Sleep Mode and asserts this interrupt. The interrupt can be cleared by writing one into this location. + [0:0] + read-write + + + DSM_EXITED_INTR + On a firmware request to LL to exit from Deep Sleep Mode, working on LF clock, LL transitions from Deep Sleep Mode and asserts this interrupt when the Deep Sleep clock gater is turned ON. The interrupt can be cleared by writing one into this location. + [1:1] + read-write + + + RCBLL_DONE_INTR + RCB transaction Complete + [2:2] + read-only + + + BLERD_ACTIVE_INTR + CYBLERD55 is in active mode. RF is active + [3:3] + read-write + + + RCB_INTR + RCB controller Interrupt - Refer to RCB_INTR_STAT register + [4:4] + read-only + + + LL_INTR + LL controller interrupt - Refer to EVENT_INTR register + [5:5] + read-only + + + GPIO_INTR + GPIO interrupt + [6:6] + read-write + + + EFUSE_INTR + This bit when set by efuse controller logic when the efuse read/write is completed + [7:7] + read-write + + + XTAL_ON_INTR + enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by writing one into this location. + [8:8] + read-write + + + ENC_INTR + Encryption Interrupt Triggered + [9:9] + read-only + + + HVLDO_LV_DETECT_POS + This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output + [10:10] + read-write + + + HVLDO_LV_DETECT_NEG + This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output + [11:11] + read-write + + + + + INTR_MASK + Link Layer interrupt mask register + 0x6C + 32 + read-write + 0x0 + 0x1FFF + + + DSM_EXIT + When the Link Layer is in Deep Sleep Mode, firmware can set this bit to wake the Link Layer. + [0:0] + read-write + + + DSM_ENTERED_INTR_MASK + Masks the DSM Entered Interrupt, when disabled. + [1:1] + read-write + + + DSM_EXITED_INTR_MASK + Masks the DSM Exited Interrupt, when disabled. + [2:2] + read-write + + + XTAL_ON_INTR_MASK + Masks the Crystal Stable Interrupt, when disabled. + [3:3] + read-write + + + RCBLL_INTR_MASK + Mask for RCBLL interrupt + [4:4] + read-write + + + BLERD_ACTIVE_INTR_MASK + Mask for CYBLERD55 Active Interrupt + [5:5] + read-write + + + RCB_INTR_MASK + Mask for RCB interrupt + [6:6] + read-write + + + LL_INTR_MASK + Mask for LL interrupt + [7:7] + read-write + + + GPIO_INTR_MASK + Mask for GPIO interrupt + [8:8] + read-write + + + EFUSE_INTR_MASK + This bit enables the efuse interrupt to firmware + [9:9] + read-write + + + ENC_INTR_MASK + Mask for Encryption interrupt + [10:10] + read-write + + + HVLDO_LV_DETECT_POS_MASK + Mask for HVLDO LV Detector Rise edge interrupt + [11:11] + read-write + + + HVLDO_LV_DETECT_NEG_MASK + Mask for HVLDO LV Detector Fall edge interrupt + [12:12] + read-write + + + + + LL_CLK_EN + Link Layer primary clock enable + 0x70 + 32 + read-write + 0x26 + 0x3F + + + CLK_EN + Set this bit 1 to enable the clock to Link Layer. + [0:0] + read-write + + + CY_CORREL_EN + If MXD_IF option is 1, this bit needs to be set to enable configuring the correlator through BLELL.DPLL_CONFIG register + [1:1] + read-write + + + MXD_IF_OPTION + 1: MXD IF option 0: CYBLERD55 correlates Access Code +0: MXD IF option 1: LL correlates Access Code + [2:2] + read-write + + + SEL_RCB_CLK + 0: AHB clock (clk_sys) is used as the clock for RCB access +1: LL clock (clk_eco) is used as the clock for RCB access + [3:3] + read-write + + + BLESS_RESET + 0: No Soft Reset +1: Initiate Soft Reset +Setting this bit will reset entire BLESS_VER3 + [4:4] + read-write + + + DPSLP_HWRCB_EN + Controls the DPSLP entry and exit writes to RD and controls the active domain reset and clock. +1 - LL HW controls the RD active domain reset and clock. +0 - The RD active domain reset and clock. Must be controlled by the FW + [5:5] + read-write + + + + + LF_CLK_CTRL + BLESS LF clock control and BLESS revision ID indicator + 0x74 + 32 + read-write + 0x40000000 + 0xE0000003 + + + DISABLE_LF_CLK + When set to 1, gates the LF clock input to the Link Layer. Ths is done for extended DSM mode where the DSM state machine needs to be forzen to prevent a default auto exit. + [0:0] + read-write + + + ENABLE_ENC_CLK + This bit is used to enable the clock to the encryption engine +0 - Disable the clock to ENC engine +1 - Enable the clock to ENC engine + [1:1] + read-write + + + M0S8BLESS_REV_ID + Indicates the m0s8bless IP revision. + [31:29] + read-only + + + + + EXT_PA_LNA_CTRL + External TX PA and RX LNA control + 0x78 + 32 + read-write + 0x0 + 0x3E + + + ENABLE_EXT_PA_LNA + When set to 1, enables the external PA & LNA + [1:1] + read-write + + + CHIP_EN_POL + Controls the polarity of the chip enable control signal +0 - High enable, low disable +1 - Low enable, High disable + [2:2] + read-write + + + PA_CTRL_POL + Controls the polarity of the PA control signal +0 - High enable, low disable +1 - Low enable, High disable + [3:3] + read-write + + + LNA_CTRL_POL + Controls the polarity of the LNA control signal +0 - High enable, low disable +1 - Low enable, High disable + [4:4] + read-write + + + OUT_EN_DRIVE_VAL + Configures the drive value on the output enables of PA, LNA and CHI_EN signals +0 - drive 0 on the output enable signals +1 - drive 1 on the output enable signals + [5:5] + read-write + + + + + LL_PKT_RSSI_CH_ENERGY + Link Layer Last Received packet RSSI/Channel energy and channel number + 0x80 + 32 + read-only + 0x0 + 0x7FFFFF + + + RSSI + This field captures the RSSI of the packet when a packet reception is complete or gives the Channel energy when a Receive cycle is over without packet reception. + [15:0] + read-only + + + RX_CHANNEL + This field indicates the last channel for which the RSSI is captured + [21:16] + read-only + + + PKT_RSSI_OR_CH_ENERGY + This field indicates if the captured RSSI is for a received packet or is the channel energy + [22:22] + read-only + + + + + BT_CLOCK_CAPT + BT clock captured on an LL DSM exit + 0x84 + 32 + read-only + 0x0 + 0xFFFF + + + BT_CLOCK + This field captures the LF BT clock captured on an LL DSM exit. This register is valid only when MT_STATUS.LL_CLK_STATE is set. This value may be used to manage the low power entry. + [15:0] + read-only + + + + + MT_CFG + MT Configuration Register + 0xA0 + 32 + read-write + 0x8100000 + 0xFFFFFFF + + + ENABLE_BLERD + This register bit needs to be set to enable CYBLERD55 +1'b1 - CYBLERD55 enabled +1'b0 - CYBLERD55 disabled +On power up this bit needs to be set to make CYBLERD55 active. + [0:0] + read-write + + + DEEPSLEEP_EXIT_CFG + This register bit indicates the source for PSoC DeepSleep exit to BLESS +1'b0 - act_power_good from SRSS indicates PSoC DeepSleep exit +1'b1 - MT_CFG.DEEPSLEEP_EXITED indicates PSoC DeepSleep exit + [1:1] + read-write + + + DEEPSLEEP_EXITED + This register bit is used by FW to indicate that PSoC is out of DeepSleep +1'b0 - PSoC in DeepSleep +1'b1 - PSoC out of DeepSleep +This bit is cleared by HW on exit from DPSLP + [2:2] + read-write + + + ACT_LDO_NOT_BUCK + This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in active mode + [3:3] + read-write + + + OVERRIDE_HVLDO_BYPASS + This register should be set to override the HW generated signal to HVLDO. When set HVLDO_BYPASS is driven to the IP + [4:4] + read-write + + + HVLDO_BYPASS + Override value for HVLDO BYPASS +1'b0: bypass the HVLDO +1'b1: Do not bypass the HVLDO + [5:5] + read-write + + + OVERRIDE_ACT_REGULATOR + This register should be set to override the HW generated signal to enable ACTIVE_LDO/BUCK. When set ACT_REGULATOR_EN is driven to CYBLERD55 + [6:6] + read-write + + + ACT_REGULATOR_EN + Override value for ACT_LDO_EN/BUCK_EN + [7:7] + read-write + + + OVERRIDE_DIG_REGULATOR + This register should be set to override the HW generated signal to Digital regulator of CYBLERD55. When set DIG_REGULATOR_EN is driven to CYBLERD55 + [8:8] + read-write + + + DIG_REGULATOR_EN + Override value for digital regulator of CYBLERD55 + [9:9] + read-write + + + OVERRIDE_RET_SWITCH + This register should be set to override the HW generated signal to the retention switch of CYBLERD55. When set OVERRIDE_RET_SWITCH is driven to the IP + [10:10] + read-write + + + RET_SWITCH + Override value for RET_SWITCH + [11:11] + read-write + + + OVERRIDE_ISOLATE + This register should be set to override the HW generated isolation signal to CYBLERD55. When set ISOLATE_N is driven to the IP + [12:12] + read-write + + + ISOLATE_N + Override value for isolation to CYBLERD55 + [13:13] + read-write + + + OVERRIDE_LL_CLK_EN + This register should be set to override the HW generated ECO Clock gate. When set LL_CLK_EN is used to gate the clock + [14:14] + read-write + + + LL_CLK_EN + Override value for LL Clock gate + [15:15] + read-write + + + OVERRIDE_HVLDO_EN + This register should be set to override the HW generated enable to HVLSO. When set HVLDO_EN is used. + [16:16] + read-write + + + HVLDO_EN + Overrie value for HVLDO enable +1'b1: switch to Active LDO +1'b0: switch to standby LDO + [17:17] + read-write + + + DPSLP_ECO_ON + This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This bit must be toggled only when the Link Layer is active. + [18:18] + read-write + + + OVERRIDE_RESET_N + This register should be set to override the HW generated reset to CYBLERD55. When set RESET_N is used. + [19:19] + read-write + + + RESET_N + Overrie value for CYBLERD55 RESET_N + [20:20] + read-write + + + OVERRIDE_XTAL_EN + This register should be set to override the HW generated XTAL_EN to CYBLERD55. When set XTAL_EN is used. + [21:21] + read-write + + + XTAL_EN + Overrie value for CYBLERD55 XTAL_EN + [22:22] + read-write + + + OVERRIDE_CLK_EN + This register should be set to override the HW generated CLK_EN to CYBLERD55. When set CLK_EN is used. + [23:23] + read-write + + + BLERD_CLK_EN + Overrie value for CYBLERD55 CLK_EN + [24:24] + read-write + + + OVERRIDE_RET_LDO_OL + This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. When set CLK_EN is used. + [25:25] + read-write + + + RET_LDO_OL + Overrie value for CYBLERD55 RET_LDO_OL_HV + [26:26] + read-write + + + HVLDO_POR_HV + Reset for HVLDO +1'b1 - HVLDO Disabled +1'b0 - HVLDO Enabled + [27:27] + read-write + + + + + MT_DELAY_CFG + MT Delay configuration for state transitions + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HVLDO_STARTUP_DELAY + This register specifies the startup delay for the HVLDO interms of number of LF Clock cycles. FW has to program this register based on the selected LF clock frequency + [7:0] + read-write + + + ISOLATE_DEASSERT_DELAY + This register specifies the time from switching the CYBLERD55 logic to Active regulator to removal of ISOLATE_N + [15:8] + read-write + + + ACT_TO_SWITCH_DELAY + This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD55 logic to Retention LDO + [23:16] + read-write + + + HVLDO_DISABLE_DELAY + This register specifies the time from disabling XTAL to switching of the HVLDO. + [31:24] + read-write + + + + + MT_DELAY_CFG2 + MT Delay configuration for state transitions + 0xA8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OSC_STARTUP_DELAY_LF + This register specifies the time for OSC Startup. After this delay, clock is enabled to the link layer. Clock is enabled after OSC_STARTUP_DELAY + 1 LF clock cycles. If PSoC was in DPSLP when XTAL is enabled, then the wakeup delay will be OSC_STARTUP_DELAY + 1 + PSoC Wakeup time. Minimum value to be programmed in 1. This is equivalent to Link Layer register WAKEUP_CONFIG.OSC_STARTUP_DELAY, but is specified in LF cycles + [7:0] + read-write + + + DSM_OFFSET_TO_WAKEUP_INSTANT_LF + This register specifies the pre-processing time required in Link Layer. This is esentially the time from CLK_EN (ungating clock in CYBLERD55) to the time when logic in CYBLERD55 is switched to Active mode Regulator.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. This is equivalent to Link Layer register WAKEUP_CONFIG.DSM_OFFSET_TO_WAKEUP_INSTANT_LF, but is specified in LF cycles. + [15:8] + read-write + + + ACT_STARTUP_DELAY + This register specifes the Active Regulator startup time in CYBLERD55. The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The digital LDO will be turned on after this time elapses + [23:16] + read-write + + + DIG_LDO_STARTUP_DELAY + This register specifes the Digital LDO startup time in CYBLERD55.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The logic in CYBLERD55 is switched to Active mode Regulator after this (ACT_STARTUP_DELAY + DIG_LDO_STARTUP_DELAY) + [31:24] + read-write + + + + + MT_DELAY_CFG3 + MT Delay configuration for state transitions + 0xAC + 32 + read-write + 0x0 + 0xFFFFFF + + + XTAL_DISABLE_DELAY + This register specifies the time from switching of logic to Retention LDO in CYBLERD55 to XTAL Disable. This should include the post processing time +The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. +At the minimum XTAL_DISABLE_DELAY should be the sum of DIG_LDO_DISABLE_DELAY and the powerdown time of ACTIVE_LDO + [7:0] + read-write + + + DIG_LDO_DISABLE_DELAY + This field holds the delay from the time of diabling Digital LDO to the time at which ACTIVE regulator is disabled + [15:8] + read-write + + + VDDR_STABLE_DELAY + This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410 + [23:16] + read-write + + + + + MT_VIO_CTRL + MT Configuration Register to control VIO switches + 0xB0 + 32 + read-write + 0x0 + 0x3 + + + SRSS_SWITCH_EN + Enable to turn on HVLDO (One leg) +1'b0 - Switch is turned off +1'b1 - Switch is turned on + [0:0] + read-write + + + SRSS_SWITCH_EN_DLY + Enable to turn on HVLDO (All legs). This must be enabled 64us after enabling SRSS_SWITCH_EN +1'b0 - Switch is turned off +1'b1 - Switch is turned on + [1:1] + read-write + + + + + MT_STATUS + MT Status Register + 0xB4 + 32 + read-only + 0x0 + 0x1FF + + + BLESS_STATE + 1'b0 - BLESS in DPSLP state +1'b1 - BLESS in ACTIVE state + [0:0] + read-only + + + MT_CURR_STATE + This register reflects the current state of the MT FSM +4'h0 - IDLE +4'h1 - BLERD_DEEPSLEEP +4'h2 - HVLDO_STARTUP +4'h3 - WAIT_CLK +4'h4 - BLERD_IDLE +4'h5 - SWITCH_EN +4'h6 - ACTIVE +4'h7 - ISOLATE +4'h8 - WAIT_IDLE +4'h9 - XTAL_DISABLE +4'hA - HVLDO_DISABLE + [4:1] + read-only + + + HVLDO_STARTUP_CURR_STATE + This register reflects the current state of the HVLDO Startup FSM +3'h0 - HVLDO_OFF +3'h1 - HVLDO_WAIT +3'h2 - HVLDO_SAMPLE +3'h3 - HVLDO_ENABLED +3'h4 - HVLDO_SET_BYPASS + [7:5] + read-only + + + LL_CLK_STATE + This bit indicates when the Link Layer registers are accessible upon a DSM exit. This bit should not be used after a DSM entry command has been issued. +1'b0 - Link Layer clock is not available +1'b1 - Link Layer clock is active + [8:8] + read-only + + + + + PWR_CTRL_SM_ST + Link Layer Power Control FSM Status Register + 0xB8 + 32 + read-only + 0x0 + 0xF + + + PWR_CTRL_SM_CURR_STATE + This register reflects the current state of the LL Power Control FSM +4'h0 - IDLE +4'h1 - SLEEP +4'h2 - DEEP_SLEEP +4'h4 - WAIT_OSC_STABLE +4'h5 - INTR_GEN +4'h6 - ACTIVE +4'h7 - REQ_RF_OFF + [3:0] + read-only + + + + + HVLDO_CTRL + HVLDO Configuration register + 0xC0 + 32 + read-write + 0x0 + 0x8000005F + + + ADFT_EN + ADFT enable + [0:0] + read-write + + + ADFT_CTRL + ADFT select + [4:1] + read-write + + + VREF_EXT_EN + Vref ext input enable. + [6:6] + read-write + + + STATUS + hvldo LV detect status + [31:31] + read-only + + + + + MISC_EN_CTRL + Radio Buck and Active regulator enable control + 0xC4 + 32 + read-write + 0x8 + 0x1F + + + BUCK_EN_CTRL + Buck enable control. This must be programmed before enabling the Radio. +1'b1 - Buck enable output to radio is tied to 0 +1'b0 - Buck enable output to radio is controlled from Mode transition FSM + [0:0] + read-write + + + ACT_REG_EN_CTRL + Active regulator enable control. This must be programmed before enabling the Radio. +1'b0 - Active regulator enable output to radio is tied to 0 +1'b1 - Active regulator enable output to radio is controlled from Mode transition FSM + [1:1] + read-write + + + LPM_DRIFT_EN + Controls the LPM drift calculation. +1 - Enables the LPM drift mod +0 - Disables the LPM drift mod + [2:2] + read-write + + + LPM_DRIFT_MULTI + Controls the LPM drift multi level compensation. +1 - Enables the LPM drift multi comp +0 - Disables the LPM drift multi comp + [3:3] + read-write + + + LPM_ENTRY_CTRL_MODE + Controls the LPM entry control mode +1 - LPM can be entered in the same slot as the previous LPM exit +0 - LPM must not be entered in the same slot or the subsequent slot as the last LPM exit + [4:4] + read-write + + + + + EFUSE_CONFIG + EFUSE mode configuration register + 0xD0 + 32 + read-write + 0x0 + 0x7 + + + EFUSE_MODE + This register enables the efuse mode in m0s8bless_ver3 + [0:0] + read-write + + + EFUSE_READ + This bit when set by firmware enables the read from EFUSE macro. It is cleared when the efuse read is completed + [1:1] + read-write + + + EFUSE_WRITE + This bit when set by firmware enables the write to EFUSE macro. It is cleared when the efuse write is completed + [2:2] + read-write + + + + + EFUSE_TIM_CTRL1 + EFUSE timing control register (common for Program and Read modes) + 0xD4 + 32 + read-write + 0x111201C0 + 0xFFFFFFFF + + + SCLK_HIGH + Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode) +TPGM: Burning Time +TCKHP : SCLK high Period + [7:0] + read-write + + + SCLK_LOW + Duration of SCLK LOW (TCLKP_R) or TCKLP_P + [15:8] + read-write + + + CS_SCLK_SETUP_TIME + This register specifies the setup time between CS and SCLK (TSR_CLK) + [19:16] + read-write + + + CS_SCLK_HOLD_TIME + This register specifies the hold time between CS and SCLK +(THR_CLK) + [23:20] + read-write + + + RW_CS_SETUP_TIME + This field decides setup time between RW & CS (TSR_RW: in read mode) or RW & AVDD (TSP_RW: in Program mode). +TSR_RW: RW to CS setup time into Read mode +TSP_RW: RW to AVDD setup time into program mode + [27:24] + read-write + + + RW_CS_HOLD_TIME + This field decides hold time between RW & CS (THR_RW: in read mode) or RW & AVDD (THP_RW: in Program mode). +THR_RW: RW to CS hold time out of Read mode +THP_RW: RW to AVDD hold time out of program mode + [31:28] + read-write + + + + + EFUSE_TIM_CTRL2 + EFUSE timing control Register (for Read) + 0xD8 + 32 + read-write + 0x102 + 0xFFF + + + DATA_SAMPLE_TIME + This register specifies the time for data sampling from SCLK HIGH +(TCKDQ_H) + [7:0] + read-write + + + DOUT_CS_HOLD_TIME + Wait time +DOUT to CS hold time out of read mode (TDQH) + [11:8] + read-write + + + + + EFUSE_TIM_CTRL3 + EFUSE timing control Register (for Program) + 0xDC + 32 + read-write + 0x3A3A11 + 0xFFFFFF + + + PGM_SCLK_SETUP_TIME + PGM to SCLK setup time (TS_PGM) +PGM_SCLK_SETUP_TIME <CS_SCLK_SETUP_TIME + [3:0] + read-write + + + PGM_SCLK_HOLD_TIME + PGM to SCLK hold time (TH_PGM) + [7:4] + read-write + + + AVDD_CS_SETUP_TIME + AVDD to CS setup time into program mode (TSP_AVDD_CS) + [15:8] + read-write + + + AVDD_CS_HOLD_TIME + AVDD to CS hold time out of program mode (THP_AVDD_CS) + [23:16] + read-write + + + + + EFUSE_RDATA_L + EFUSE Lower read data + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + This register has the read value from the Efuse macro, fuse bits[31:0] + [31:0] + read-only + + + + + EFUSE_RDATA_H + EFUSE higher read data + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + This register has the read value from the Efuse macro, fuse bits[63:32] + [31:0] + read-only + + + + + EFUSE_WDATA_L + EFUSE lower write word + 0xE8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + This register has the write value to the Efuse macro, fuse bits[31:0] + [31:0] + read-write + + + + + EFUSE_WDATA_H + EFUSE higher write word + 0xEC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + This register has the write value to the Efuse macro, fuse bits[63:32] + [31:0] + read-write + + + + + DIV_BY_625_CFG + Divide by 625 for FW Use + 0xF0 + 32 + read-write + 0x0 + 0xFFFF02 + + + ENABLE + This bit enables the divider for use by FW +1'b0 - divider used by LL +1'b1 - divider can be used by FW +This divider can only be used in MMMS mode. Do not enable for legacy operation + [1:1] + read-write + + + DIVIDEND + This field holds the dividend + [23:8] + read-write + + + + + DIV_BY_625_STS + Output of divide by 625 divider + 0xF4 + 32 + read-only + 0x100 + 0x3FF3F + + + QUOTIENT + Quotient value from the divider. Available 1 cycle after dividend is programmed. + [5:0] + read-only + + + REMAINDER + Remainder value from the divider. Available 1 cycle after dividend is programmed. + [17:8] + read-only + + + + + PACKET_COUNTER0 + Packet counter 0 + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PACKET_COUNTER_LOWER + Lower 32-bits of the packet counter value passed as part of Nonce for the packet to be encrypted. + [31:0] + read-write + + + + + PACKET_COUNTER2 + Packet counter 2 + 0x104 + 32 + read-write + 0x0 + 0xFF + + + PACKET_COUNTER_UPPER + Upper 8 bits of the packet counter value passed as part of Nonce for the packet to be encrypted. + [7:0] + read-write + + + + + IV_MASTER0 + Master Initialization Vector 0 + 0x108 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IV_MASTER + This is the IVm field, which contains the master's portion of the initialization vector. + [31:0] + read-write + + + + + IV_SLAVE0 + Slave Initialization Vector 0 + 0x10C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IV_SLAVE + This is the IVs field, which contains the slave's portion of the initialization vector. + [31:0] + read-write + + + + + 4 + 4 + ENC_KEY[%s] + Encryption Key register 0-3 + 0x110 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + ENC_KEY + The encryption key / session key which is used in ECB encryption, CCM encryption and CCM decryption. + [31:0] + write-only + + + + + MIC_IN0 + MIC input register + 0x120 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MIC_IN + This is the MIC field used for CCM decryption. + [31:0] + read-write + + + + + MIC_OUT0 + MIC output register + 0x124 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MIC_OUT + This is the MIC generated during CCM encryption. + [31:0] + read-only + + + + + ENC_PARAMS + Encryption Parameter register + 0x128 + 32 + read-write + 0x0 + 0xFFF + + + DATA_PDU_HEADER + LLID of the packet. + [1:0] + read-write + + + PAYLOAD_LENGTH_LSB + Length of the input data. + [6:2] + read-write + + + DIRECTION + The directionBit shall be set to '1' for Data Channel PDUs sent by the master and set to '0' for Data Channel PDUs sent by the slave. + [7:7] + read-write + + + PAYLOAD_LENGTH_LSB_EXT + 3 Most significant bits of the LS byte of the length of the input data. Valid only when DLE is enabled. +When DLE is enabled total ENC payload length = {PAYLOAD_LENGTH_LSB_EXT, PAYLOAD_LENGTH_LSB} + [10:8] + read-write + + + MEM_LATENCY_HIDE + Controls the encryption memory access mode. Valid only when DLE is enabled. +0 - The AES is idle while memory fetch/store in progress. +1- The AES is pipelined while memory fetch/store in progress. + [11:11] + read-write + + + + + ENC_CONFIG + Encryption Configuration + 0x12C + 32 + read-write + 0x0 + 0x1FFFF07 + + + START_PROC + 1 Start the AES processing + [0:0] + read-write + + + ECB_CCM + 0 - CCM +1 - ECB + [1:1] + read-write + + + DEC_ENC + Decryption/Encryption +0 - Encrypt +1 - Decrypt + [2:2] + read-write + + + PAYLOAD_LENGTH_MSB + MS byte of the length of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled. +When AES_B0_DATA_OVERRIDE is enabled total ENC payload length = {PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH} + [15:8] + read-write + + + B0_FLAGS + LS byte of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled. + [23:16] + read-write + + + AES_B0_DATA_OVERRIDE + Configuration to use B0 DATA provided by FW for CCM computation + [24:24] + read-write + + + + + ENC_INTR_EN + Encryption Interrupt enable + 0x130 + 32 + read-write + 0x0 + 0x7 + + + AUTH_PASS_INTR_EN + Authentication interrupt enable +0 - Disable +1 - Enable + [0:0] + read-write + + + ECB_PROC_INTR_EN + ECB processed interrupt enable +0 - Disable +1 - Enable + [1:1] + read-write + + + CCM_PROC_INTR_EN + CCM processed interupt enable +0 - Disable +1 - Enable + [2:2] + read-write + + + + + ENC_INTR + Encryption Interrupt status and clear register + 0x134 + 32 + read-write + 0x0 + 0xF + + + AUTH_PASS_INTR + Authentication interrupt. +0x1- indicates MIC matched +0x0 -indicated MIC mismatched +Writing 1 to this register clears the interrupt. + [0:0] + read-write + + + ECB_PROC_INTR + ECB processed interrupt. +Writing 1 to this register clears the interrupt. + [1:1] + read-write + + + CCM_PROC_INTR + CCM processed interrupt. +Writing 1 to this register clears the interrupt + [2:2] + read-write + + + IN_DATA_CLEAR + Clears the input data. Used for Zero padding of encryption for less than block sized data. + [3:3] + read-write + + + + + 4 + 4 + B1_DATA_REG[%s] + Programmable B1 Data register (0-3) + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + B1_DATA + Programmable B1 Data register + [31:0] + read-write + + + + + ENC_MEM_BASE_ADDR + Encryption memory base address + 0x150 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ENC_MEM + Data values written to Enc memory are written as 16-bit wide data. This memory is valid only if DLE is set. + [31:0] + read-write + + + + + TRIM_LDO_0 + LDO Trim register 0 + 0xF00 + 32 + read-write + 0x58 + 0xFF + + + ACT_LDO_VREG + To trim the regulated voltage in steps of 25mV typically + [3:0] + read-write + + + ACT_LDO_ITAIL + To trim the bias currents for all the active mode blocks + [7:4] + read-write + + + + + TRIM_LDO_1 + LDO Trim register 1 + 0xF04 + 32 + read-write + 0x8 + 0xFF + + + ACT_REF_BGR + To trim active regulator reference voltage + [3:0] + read-write + + + SB_BGRES + To trim standby regulator reference voltage + [7:4] + read-write + + + + + TRIM_LDO_2 + LDO Trim register 2 + 0xF08 + 32 + read-write + 0x60 + 0x7F + + + SB_BMULT_RES + To trim standby regulator beta-multiplier current + [4:0] + read-write + + + SB_BMULT_NBIAS + To trim standby regulator beta-multiplier current + [6:5] + read-write + + + + + TRIM_LDO_3 + LDO Trim register 3 + 0xF0C + 32 + read-write + 0x10 + 0x7F + + + LVDET + To trim the trip points of the LV-Detect block + [4:0] + read-write + + + SLOPE_SB_BMULT + To trim standby regulator beta-multiplier temp-co slope + [6:5] + read-write + + + + + 4 + 4 + TRIM_MXD[%s] + MXD die Trim registers + 0xF10 + 32 + read-write + 0x0 + 0xFF + + + MXD_TRIM_BITS + MXD trim bits + [7:0] + read-write + + + + + TRIM_LDO_4 + LDO Trim register 4 + 0xF30 + 32 + read-write + 0x0 + 0xFF + + + T_LDO + To debug post layout or post silicon + [7:0] + read-write + + + + + TRIM_LDO_5 + LDO Trim register 5 + 0xF34 + 32 + read-write + 0x0 + 0xFF + + + RSVD + N/A + [7:0] + read-write + + + + + + + + USBFS0 + USB Host and Device Controller + USBFS + 0x403F0000 + + 0 + 65536 + registers + + + + USBDEV + USB Device + 0x00000000 + + 8 + 4 + EP0_DR[%s] + Control End point EP0 Data Register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + DATA_BYTE + This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. + [7:0] + read-write + + + + + CR0 + USB control 0 Register + 0x20 + 32 + read-write + 0x0 + 0xFF + + + DEVICE_ADDRESS + These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. +If USB bus reset is detected, these bits are initialized. + [6:0] + read-write + + + USB_ENABLE + This bit enables the device to respond to USB traffic. +If USB bus reset is detected, this bit is cleared. +Note: +When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. + [7:7] + read-write + + + + + CR1 + USB control 1 Register + 0x24 + 32 + read-write + 0x0 + 0xF + + + REG_ENABLE + This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. + [0:0] + read-write + + + ENABLE_LOCK + This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. + [1:1] + read-write + + + BUS_ACTIVITY + The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High +value until firmware clears it. + [2:2] + read-write + + + RSVD_3 + N/A + [3:3] + read-write + + + + + SIE_EP_INT_EN + USB SIE Data Endpoints Interrupt Enable Register + 0x28 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + SIE_EP_INT_SR + USB SIE Data Endpoint Interrupt Status + 0x2C + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-write + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-write + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-write + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-write + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-write + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-write + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-write + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-write + + + + + SIE_EP1_CNT0 + Non-control endpoint count register + 0x30 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP1_CNT1 + Non-control endpoint count register + 0x34 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP1_CR0 + Non-control endpoint's control Register + 0x38 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + USBIO_CR0 + USBIO Control 0 Register + 0x40 + 32 + read-write + 0x0 + 0xE0 + + + RD + Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. +If D+=D- (SE0), this value is undefined. + [0:0] + read-only + + + DIFF_LOW + D+ < D- (K state) + 0 + + + DIFF_HIGH + D+ > D- (J state) + 1 + + + + + TD + Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. + [5:5] + read-write + + + DIFF_K + Force USB K state (D+ is low D- is high). + 0 + + + DIFF_J + Force USB J state (D+ is high D- is low). + 1 + + + + + TSE0 + Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. + [6:6] + read-write + + + TEN + USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually +transmitting is to force a resume state on the bus. + [7:7] + read-write + + + + + USBIO_CR2 + USBIO control 2 Register + 0x44 + 32 + read-write + 0x0 + 0xFF + + + RSVD_5_0 + N/A + [5:0] + read-only + + + TEST_PKT + This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. + [6:6] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + + + USBIO_CR1 + USBIO control 1 Register + 0x48 + 32 + read-write + 0x20 + 0x20 + + + DMO + This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. +This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. +This bit is valid if USB Device. + [0:0] + read-only + + + DPO + This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. +This bit displays the output value of D+ pin when USB transmits SE0 or data. +This bit is valid if USB Device. + [1:1] + read-only + + + RSVD_2 + N/A + [2:2] + read-write + + + IOMODE + This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. + [5:5] + read-write + + + + + DYN_RECONFIG + USB Dynamic reconfiguration register + 0x50 + 32 + read-write + 0x0 + 0x1F + + + DYN_CONFIG_EN + This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. +Use 0 for EP1, 1 for EP2, etc. + [0:0] + read-write + + + DYN_RECONFIG_EPNO + These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. + [3:1] + read-write + + + DYN_RECONFIG_RDY_STS + This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. + [4:4] + read-only + + + + + SOF0 + Start Of Frame Register + 0x60 + 32 + read-only + 0x0 + 0xFF + + + FRAME_NUMBER + It has the lower 8 bits [7:0] of the SOF frame number. + [7:0] + read-only + + + + + SOF1 + Start Of Frame Register + 0x64 + 32 + read-only + 0x0 + 0x7 + + + FRAME_NUMBER_MSB + It has the upper 3 bits [10:8] of the SOF frame number. + [2:0] + read-only + + + + + SIE_EP2_CNT0 + Non-control endpoint count register + 0x70 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP2_CNT1 + Non-control endpoint count register + 0x74 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP2_CR0 + Non-control endpoint's control Register + 0x78 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + OSCLK_DR0 + Oscillator lock data register 0 + 0x80 + 32 + read-only + 0x0 + 0x0 + + + ADDER + These bits return the lower 8 bits of the oscillator locking circuits adder output. + [7:0] + read-only + + + + + OSCLK_DR1 + Oscillator lock data register 1 + 0x84 + 32 + read-only + 0x0 + 0x0 + + + ADDER_MSB + These bits return the upper 7 bits of the oscillator locking circuits adder output. + [6:0] + read-only + + + + + EP0_CR + Endpoint0 control Register + 0xA0 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + OUT_RCVD + When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. + [5:5] + read-write + + + IN_RCVD + When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. + [6:6] + read-write + + + SETUP_RCVD + When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. + [7:7] + read-write + + + + + EP0_CNT + Endpoint0 count Register + 0xA4 + 32 + read-write + 0x0 + 0xCF + + + BYTE_COUNT + These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. + [3:0] + read-write + + + DATA_VALID + This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT0 + Non-control endpoint count register + 0xB0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT1 + Non-control endpoint count register + 0xB4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP3_CR0 + Non-control endpoint's control Register + 0xB8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP4_CNT0 + Non-control endpoint count register + 0xF0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP4_CNT1 + Non-control endpoint count register + 0xF4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP4_CR0 + Non-control endpoint's control Register + 0xF8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP5_CNT0 + Non-control endpoint count register + 0x130 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP5_CNT1 + Non-control endpoint count register + 0x134 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP5_CR0 + Non-control endpoint's control Register + 0x138 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP6_CNT0 + Non-control endpoint count register + 0x170 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP6_CNT1 + Non-control endpoint count register + 0x174 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP6_CR0 + Non-control endpoint's control Register + 0x178 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP7_CNT0 + Non-control endpoint count register + 0x1B0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP7_CNT1 + Non-control endpoint count register + 0x1B4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP7_CR0 + Non-control endpoint's control Register + 0x1B8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP8_CNT0 + Non-control endpoint count register + 0x1F0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP8_CNT1 + Non-control endpoint count register + 0x1F4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP8_CR0 + Non-control endpoint's control Register + 0x1F8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + ARB_EP1_CFG + Endpoint Configuration Register *1 + 0x200 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP1_INT_EN + Endpoint Interrupt Enable Register *1 + 0x204 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP1_SR + Endpoint Interrupt Enable Register *1 + 0x208 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW1_WA + Endpoint Write Address value *1, *2 + 0x210 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW1_WA_MSB + Endpoint Write Address value *1, *2 + 0x214 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW1_RA + Endpoint Read Address value *1, *2 + 0x218 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW1_RA_MSB + Endpoint Read Address value *1, *2 + 0x21C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW1_DR + Endpoint Data Register + 0x220 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUF_SIZE + Dedicated Endpoint Buffer Size Register *1 + 0x230 + 32 + read-write + 0x0 + 0xFF + + + IN_BUF + Buffer size for IN Endpoints. + [3:0] + read-write + + + OUT_BUF + Buffer size for OUT Endpoints. + [7:4] + read-write + + + + + EP_ACTIVE + Endpoint Active Indication Register *1 + 0x238 + 32 + read-write + 0x0 + 0xFF + + + EP1_ACT + Indicates that Endpoint is currently active. + [0:0] + read-write + + + EP2_ACT + Indicates that Endpoint is currently active. + [1:1] + read-write + + + EP3_ACT + Indicates that Endpoint is currently active. + [2:2] + read-write + + + EP4_ACT + Indicates that Endpoint is currently active. + [3:3] + read-write + + + EP5_ACT + Indicates that Endpoint is currently active. + [4:4] + read-write + + + EP6_ACT + Indicates that Endpoint is currently active. + [5:5] + read-write + + + EP7_ACT + Indicates that Endpoint is currently active. + [6:6] + read-write + + + EP8_ACT + Indicates that Endpoint is currently active. + [7:7] + read-write + + + + + EP_TYPE + Endpoint Type (IN/OUT) Indication *1 + 0x23C + 32 + read-write + 0x0 + 0xFF + + + EP1_TYP + Endpoint Type Indication. + [0:0] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP2_TYP + Endpoint Type Indication. + [1:1] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP3_TYP + Endpoint Type Indication. + [2:2] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP4_TYP + Endpoint Type Indication. + [3:3] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP5_TYP + Endpoint Type Indication. + [4:4] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP6_TYP + Endpoint Type Indication. + [5:5] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP7_TYP + Endpoint Type Indication. + [6:6] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP8_TYP + Endpoint Type Indication. + [7:7] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + + + ARB_EP2_CFG + Endpoint Configuration Register *1 + 0x240 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP2_INT_EN + Endpoint Interrupt Enable Register *1 + 0x244 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP2_SR + Endpoint Interrupt Enable Register *1 + 0x248 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW2_WA + Endpoint Write Address value *1, *2 + 0x250 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW2_WA_MSB + Endpoint Write Address value *1, *2 + 0x254 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW2_RA + Endpoint Read Address value *1, *2 + 0x258 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW2_RA_MSB + Endpoint Read Address value *1, *2 + 0x25C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW2_DR + Endpoint Data Register + 0x260 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_CFG + Arbiter Configuration Register *1 + 0x270 + 32 + read-write + 0x0 + 0xF0 + + + AUTO_MEM + Enables Auto Memory Configuration. Manual memory configuration by default. + [4:4] + read-write + + + DMA_CFG + DMA Access Configuration. + [6:5] + read-write + + + DMA_NONE + No DMA + 0 + + + DMA_MANUAL + Manual DMA + 1 + + + DMA_AUTO + Auto DMA + 2 + + + + + CFG_CMP + Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. + [7:7] + read-write + + + + + USB_CLK_EN + USB Block Clock Enable Register + 0x274 + 32 + read-write + 0x0 + 0x1 + + + CSR_CLK_EN + Clock Enable for Core Logic clocked by AHB bus clock + [0:0] + read-write + + + + + ARB_INT_EN + Arbiter Interrupt Enable *1 + 0x278 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + ARB_INT_SR + Arbiter Interrupt Status *1 + 0x27C + 32 + read-only + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-only + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-only + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-only + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-only + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-only + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-only + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-only + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-only + + + + + ARB_EP3_CFG + Endpoint Configuration Register *1 + 0x280 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP3_INT_EN + Endpoint Interrupt Enable Register *1 + 0x284 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP3_SR + Endpoint Interrupt Enable Register *1 + 0x288 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW3_WA + Endpoint Write Address value *1, *2 + 0x290 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW3_WA_MSB + Endpoint Write Address value *1, *2 + 0x294 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW3_RA + Endpoint Read Address value *1, *2 + 0x298 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW3_RA_MSB + Endpoint Read Address value *1, *2 + 0x29C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW3_DR + Endpoint Data Register + 0x2A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + CWA + Common Area Write Address *1 + 0x2B0 + 32 + read-write + 0x0 + 0xFF + + + CWA + Write Address for Common Area + [7:0] + read-write + + + + + CWA_MSB + Endpoint Read Address value *1 + 0x2B4 + 32 + read-write + 0x0 + 0x1 + + + CWA_MSB + Write Address for Common Area + [0:0] + read-write + + + + + ARB_EP4_CFG + Endpoint Configuration Register *1 + 0x2C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP4_INT_EN + Endpoint Interrupt Enable Register *1 + 0x2C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP4_SR + Endpoint Interrupt Enable Register *1 + 0x2C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW4_WA + Endpoint Write Address value *1, *2 + 0x2D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW4_WA_MSB + Endpoint Write Address value *1, *2 + 0x2D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW4_RA + Endpoint Read Address value *1, *2 + 0x2D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW4_RA_MSB + Endpoint Read Address value *1, *2 + 0x2DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW4_DR + Endpoint Data Register + 0x2E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + DMA_THRES + DMA Burst / Threshold Configuration + 0x2F0 + 32 + read-write + 0x0 + 0xFF + + + DMA_THS + DMA Threshold count + [7:0] + read-write + + + + + DMA_THRES_MSB + DMA Burst / Threshold Configuration + 0x2F4 + 32 + read-write + 0x0 + 0x1 + + + DMA_THS_MSB + DMA Threshold count + [0:0] + read-write + + + + + ARB_EP5_CFG + Endpoint Configuration Register *1 + 0x300 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP5_INT_EN + Endpoint Interrupt Enable Register *1 + 0x304 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP5_SR + Endpoint Interrupt Enable Register *1 + 0x308 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW5_WA + Endpoint Write Address value *1, *2 + 0x310 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW5_WA_MSB + Endpoint Write Address value *1, *2 + 0x314 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW5_RA + Endpoint Read Address value *1, *2 + 0x318 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW5_RA_MSB + Endpoint Read Address value *1, *2 + 0x31C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW5_DR + Endpoint Data Register + 0x320 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUS_RST_CNT + Bus Reset Count Register + 0x330 + 32 + read-write + 0xA + 0xF + + + BUS_RST_CNT + Bus Reset Count Length + [3:0] + read-write + + + + + ARB_EP6_CFG + Endpoint Configuration Register *1 + 0x340 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP6_INT_EN + Endpoint Interrupt Enable Register *1 + 0x344 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP6_SR + Endpoint Interrupt Enable Register *1 + 0x348 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW6_WA + Endpoint Write Address value *1, *2 + 0x350 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW6_WA_MSB + Endpoint Write Address value *1, *2 + 0x354 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW6_RA + Endpoint Read Address value *1, *2 + 0x358 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW6_RA_MSB + Endpoint Read Address value *1, *2 + 0x35C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW6_DR + Endpoint Data Register + 0x360 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP7_CFG + Endpoint Configuration Register *1 + 0x380 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP7_INT_EN + Endpoint Interrupt Enable Register *1 + 0x384 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP7_SR + Endpoint Interrupt Enable Register *1 + 0x388 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW7_WA + Endpoint Write Address value *1, *2 + 0x390 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW7_WA_MSB + Endpoint Write Address value *1, *2 + 0x394 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW7_RA + Endpoint Read Address value *1, *2 + 0x398 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW7_RA_MSB + Endpoint Read Address value *1, *2 + 0x39C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW7_DR + Endpoint Data Register + 0x3A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP8_CFG + Endpoint Configuration Register *1 + 0x3C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP8_INT_EN + Endpoint Interrupt Enable Register *1 + 0x3C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP8_SR + Endpoint Interrupt Enable Register *1 + 0x3C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW8_WA + Endpoint Write Address value *1, *2 + 0x3D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW8_WA_MSB + Endpoint Write Address value *1, *2 + 0x3D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW8_RA + Endpoint Read Address value *1, *2 + 0x3D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW8_RA_MSB + Endpoint Read Address value *1, *2 + 0x3DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW8_DR + Endpoint Data Register + 0x3E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + 512 + 4 + MEM_DATA[%s] + DATA + 0x400 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + SOF16 + Start Of Frame Register + 0x1060 + 32 + read-only + 0x0 + 0x7FF + + + FRAME_NUMBER16 + The frame number (11b) + [10:0] + read-only + + + + + OSCLK_DR16 + Oscillator lock data register + 0x1080 + 32 + read-only + 0x0 + 0x0 + + + ADDER16 + These bits return the oscillator locking circuits adder output. + [14:0] + read-only + + + + + ARB_RW1_WA16 + Endpoint Write Address value *3 + 0x1210 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW1_RA16 + Endpoint Read Address value *3 + 0x1218 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW1_DR16 + Endpoint Data Register + 0x1220 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW2_WA16 + Endpoint Write Address value *3 + 0x1250 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW2_RA16 + Endpoint Read Address value *3 + 0x1258 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW2_DR16 + Endpoint Data Register + 0x1260 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW3_WA16 + Endpoint Write Address value *3 + 0x1290 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW3_RA16 + Endpoint Read Address value *3 + 0x1298 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW3_DR16 + Endpoint Data Register + 0x12A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + CWA16 + Common Area Write Address + 0x12B0 + 32 + read-write + 0x0 + 0x1FF + + + CWA16 + Write Address for Common Area + [8:0] + read-write + + + + + ARB_RW4_WA16 + Endpoint Write Address value *3 + 0x12D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW4_RA16 + Endpoint Read Address value *3 + 0x12D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW4_DR16 + Endpoint Data Register + 0x12E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + DMA_THRES16 + DMA Burst / Threshold Configuration + 0x12F0 + 32 + read-write + 0x0 + 0x1FF + + + DMA_THS16 + DMA Threshold count + [8:0] + read-write + + + + + ARB_RW5_WA16 + Endpoint Write Address value *3 + 0x1310 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW5_RA16 + Endpoint Read Address value *3 + 0x1318 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW5_DR16 + Endpoint Data Register + 0x1320 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW6_WA16 + Endpoint Write Address value *3 + 0x1350 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW6_RA16 + Endpoint Read Address value *3 + 0x1358 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW6_DR16 + Endpoint Data Register + 0x1360 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW7_WA16 + Endpoint Write Address value *3 + 0x1390 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW7_RA16 + Endpoint Read Address value *3 + 0x1398 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW7_DR16 + Endpoint Data Register + 0x13A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW8_WA16 + Endpoint Write Address value *3 + 0x13D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW8_RA16 + Endpoint Read Address value *3 + 0x13D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW8_DR16 + Endpoint Data Register + 0x13E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + + USBLPM + USB Device LPM and PHY Test + 0x00002000 + + POWER_CTL + Power Control Register + 0x0 + 32 + read-write + 0x0 + 0x303F0004 + + + SUSPEND + Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). +Note: +- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. + [2:2] + read-write + + + DP_UP_EN + Enables the pull up on the DP. +'0' : Disable. +'1' : Enable. + [16:16] + read-write + + + DP_BIG + Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DP. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DP + [17:17] + read-write + + + DP_DOWN_EN + Enables the ~15k pull down on the DP. + [18:18] + read-write + + + DM_UP_EN + Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. +'0' : Disable. +'1' : Enable. + [19:19] + read-write + + + DM_BIG + Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DM. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DM + [20:20] + read-write + + + DM_DOWN_EN + Enables the ~15k pull down on the DP. + [21:21] + read-write + + + ENABLE_DPO + Enables the single ended receiver on D+. + [28:28] + read-write + + + ENABLE_DMO + Enables the signle ended receiver on D-. + [29:29] + read-write + + + + + USBIO_CTL + USB IO Control Register + 0x8 + 32 + read-write + 0x0 + 0x3F + + + DM_P + The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. + [2:0] + read-write + + + OFF + Mode 0: Output buffer off (high Z). Input buffer off. + 0 + + + INPUT + Mode 1: Output buffer off (high Z). Input buffer on. + +Other values, not supported. + 1 + + + + + DM_M + The GPIO Drive Mode for DM IO pad. + [5:3] + read-write + + + + + FLOW_CTL + Flow Control Register + 0xC + 32 + read-write + 0x0 + 0xFF + + + EP1_ERR_RESP + End Point 1 error response +0: do nothing (backward compatibility mode) +1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK + [0:0] + read-write + + + EP2_ERR_RESP + End Point 2 error response + [1:1] + read-write + + + EP3_ERR_RESP + End Point 3 error response + [2:2] + read-write + + + EP4_ERR_RESP + End Point 4 error response + [3:3] + read-write + + + EP5_ERR_RESP + End Point 5 error response + [4:4] + read-write + + + EP6_ERR_RESP + End Point 6 error response + [5:5] + read-write + + + EP7_ERR_RESP + End Point 7 error response + [6:6] + read-write + + + EP8_ERR_RESP + End Point 8 error response + [7:7] + read-write + + + + + LPM_CTL + LPM Control Register + 0x10 + 32 + read-write + 0x0 + 0x17 + + + LPM_EN + LPM enable +0: Disabled, LPM token will not get a response (backward compatibility mode) +1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) + A STALL will be sent if the bLinkState is not 0001b + A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below + [0:0] + read-write + + + LPM_ACK_RESP + LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request +0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode +1: a LPM token will get an ACK response and the device will go to the requested low power mode + [1:1] + read-write + + + NYET_EN + Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). +0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. +1: a LPM token will get a NYET response + [2:2] + read-write + + + SUB_RESP + Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. + [4:4] + read-write + + + + + LPM_STAT + LPM Status register + 0x14 + 32 + read-only + 0x0 + 0x1F + + + LPM_BESL + Best Effort Service Latency +This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. + [3:0] + read-only + + + LPM_REMOTEWAKE + 0: Device is prohibited from initiating a remote wake +1: Device is allow to wake the host + [4:4] + read-only + + + + + INTR_SIE + USB SOF, BUS RESET and EP0 Interrupt Status + 0x20 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR + Interrupt status for USB SOF + [0:0] + read-write + + + BUS_RESET_INTR + Interrupt status for BUS RESET + [1:1] + read-write + + + EP0_INTR + Interrupt status for EP0 + [2:2] + read-write + + + LPM_INTR + Interrupt status for LPM (Link Power Management, L1 entry) + [3:3] + read-write + + + RESUME_INTR + Interrupt status for Resume + [4:4] + read-write + + + + + INTR_SIE_SET + USB SOF, BUS RESET and EP0 Interrupt Set + 0x24 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + BUS_RESET_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EP0_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + LPM_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + RESUME_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + + + INTR_SIE_MASK + USB SOF, BUS RESET and EP0 Interrupt Mask + 0x28 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [0:0] + read-write + + + BUS_RESET_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [1:1] + read-write + + + EP0_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [2:2] + read-write + + + LPM_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [3:3] + read-write + + + RESUME_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [4:4] + read-write + + + + + INTR_SIE_MASKED + USB SOF, BUS RESET and EP0 Interrupt Masked + 0x2C + 32 + read-only + 0x0 + 0x1F + + + SOF_INTR_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + BUS_RESET_INTR_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EP0_INTR_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + LPM_INTR_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + RESUME_INTR_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + + + INTR_LVL_SEL + Select interrupt level for each interrupt source + 0x30 + 32 + read-write + 0x0 + 0xFFFFC3FF + + + SOF_LVL_SEL + USB SOF Interrupt level select + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + BUS_RESET_LVL_SEL + BUS RESET Interrupt level select + [3:2] + read-write + + + EP0_LVL_SEL + EP0 Interrupt level select + [5:4] + read-write + + + LPM_LVL_SEL + LPM Interrupt level select + [7:6] + read-write + + + RESUME_LVL_SEL + Resume Interrupt level select + [9:8] + read-write + + + ARB_EP_LVL_SEL + Arbiter Endpoint Interrupt level select + [15:14] + read-write + + + EP1_LVL_SEL + EP1 Interrupt level select + [17:16] + read-write + + + EP2_LVL_SEL + EP2 Interrupt level select + [19:18] + read-write + + + EP3_LVL_SEL + EP3 Interrupt level select + [21:20] + read-write + + + EP4_LVL_SEL + EP4 Interrupt level select + [23:22] + read-write + + + EP5_LVL_SEL + EP5 Interrupt level select + [25:24] + read-write + + + EP6_LVL_SEL + EP6 Interrupt level select + [27:26] + read-write + + + EP7_LVL_SEL + EP7 Interrupt level select + [29:28] + read-write + + + EP8_LVL_SEL + EP8 Interrupt level select + [31:30] + read-write + + + + + INTR_CAUSE_HI + High priority interrupt Cause register + 0x34 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_MED + Medium priority interrupt Cause register + 0x38 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_LO + Low priority interrupt Cause register + 0x3C + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + DFT_CTL + DFT control + 0x70 + 32 + read-write + 0x0 + 0x1F + + + DDFT_OUT_SEL + DDFT output select signal + [2:0] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + DP_SE + Single Ended output of DP + 1 + + + DM_SE + Single Ended output of DM + 2 + + + TXOE + Output Enable + 3 + + + RCV_DF + Differential Receiver output + 4 + + + GPIO_DP_OUT + GPIO output of DP + 5 + + + GPIO_DM_OUT + GPIO output of DM + 6 + + + + + DDFT_IN_SEL + DDFT input select signal + [4:3] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + GPIO_DP_IN + GPIO input of DP + 1 + + + GPIO_DM_IN + GPIO input of DM + 2 + + + + + + + + USBHOST + USB Host Controller + 0x00004000 + + HOST_CTL0 + Host Control 0 Register. + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + HOST + This bit selects an operating mode of this IP. +'0' : USB Device +'1' : USB Host +Notes: +- The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. +- This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. +- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. + * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. + * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. + * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. + [0:0] + read-write + + + ENABLE + This bit enables the operation of this IP. +'0' : Disable USB Host +'1' : Enable USB Host +Note: +- This bit doesn't affect the USB Device. + [31:31] + read-write + + + + + HOST_CTL1 + Host Control 1 Register. + 0x10 + 32 + read-write + 0x83 + 0x83 + + + CLKSEL + This bit selects the operating clock of USB Host. +'0' : Low-speed clock +'1' : Full-speed clock +Notes: +- This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- This bit must always be set to '1' in the USB Device mode. + [0:0] + read-write + + + USTP + This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. +'0' : Normal operating mode. +'1' : Stops the clock for the USB Host operating unit. +Notes: +- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. + [1:1] + read-write + + + RST + This bit resets the USB Host. +'0' : Normal operating mode. +'1' : USB Host is reset. +Notes: +- This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. + [7:7] + read-write + + + + + HOST_CTL2 + Host Control 2 Register. + 0x100 + 32 + read-write + 0x1 + 0xFF + + + RETRY + If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). +* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' +'0' : Doesn't retry token sending. +'1' : Retries token sending +Note: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + CANCEL + When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). +'0' : Continues a token. +'1' : Cancels a token. + [1:1] + read-write + + + SOFSTEP + If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. +If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. +'0' : An interrupt occurred due to the HOST_HFCOMP setting. +'1' : An interrupt occurred. +Notes: +- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. + [2:2] + read-write + + + ALIVE + This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. +'0' : SOF output. +'1' : SE0 output (Keep alive) + [3:3] + read-write + + + RSVD_4 + N/A + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-write + + + TTEST + N/A + [7:6] + read-write + + + + + HOST_ERR + Host Error Status Register. + 0x104 + 32 + read-write + 0x3 + 0xFF + + + HS + These flags indicate the status of a handshake packet to be sent or received. +These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +These bits are updated when sending or receiving has been ended. +Write '11' to set the status back to 'NULL', all other write values are ignored. +Note: +This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:0] + read-write + + + ACK + Acknowledge Packet + 0 + + + NAK + Non-Acknowledge Packet + 1 + + + STALL + Stall Packet + 2 + + + NULL + Null Packet + 3 + + + + + STUFF + If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No stuffing error. +'1' : Stuffing error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + TGERR + If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No toggle error. +'1' : Toggle error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:3] + read-write + + + CRC + If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No CRC error. +'1' : CRC error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + TOUT + If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No timeout. +'1' : Timeout has detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RERR + When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No receive error. +'1' : Maximum packet receive error detected. +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:6] + read-write + + + LSTSOF + If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. +'0' : SOF sent without error. +'1' : SOF error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + HOST_STATUS + Host Status Register. + 0x108 + 32 + read-write + 0xC2 + 0x1FF + + + CSTAT + When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. +'0' : Device is disconnected. +'1' : Device is connected. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [0:0] + read-only + + + TMODE + If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. +'0' : Low-speed. +'1' : Full-speed. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [1:1] + read-only + + + SUSP + If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +Set to '1' : Suspend. +Set '0' when this bit is '1' : Resume. +Other conditions : Holds the status. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. +- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). +- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. + [2:2] + read-write + + + SOFBUSY + When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. +'0' : The SOF timer is stopped. +'1' : The SOF timer is active. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). +- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. + [3:3] + read-write + + + URST + When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-only + + + RSTBUSY + This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. +'0' : USB Host isn't being reset. +'1' : USB Host is being reset. +Notes: +- If this bit is '1', the a token must not be executed. +- This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. + [6:6] + read-only + + + CLKSEL_ST + This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +'0' : Low speed +'1' : Full speed +Note: +- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [7:7] + read-only + + + HOST_ST + This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. +'0' : USB Device +'1' : USB Host +Notes: +- If this bit is different from the HOST bit, The execution of a token must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [8:8] + read-only + + + + + HOST_FCOMP + Host SOF Interrupt Frame Compare Register + 0x10C + 32 + read-write + 0x0 + 0xFF + + + FRAMECOMP + These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. +If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:0] + read-write + + + + + HOST_RTIMER + Host Retry Timer Setup Register + 0x110 + 32 + read-write + 0x0 + 0x3FFFF + + + RTIMER + These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. +If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. + [17:0] + read-write + + + + + HOST_ADDR + Host Address Register + 0x114 + 32 + read-write + 0x0 + 0x7F + + + ADDRESS + These bits are used to specify a token address. +Note: +- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:0] + read-write + + + + + HOST_EOF + Host EOF Setup Register + 0x118 + 32 + read-write + 0x0 + 0x3FFF + + + EOF + These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. +Setting example: MAXPKT = 64 bytes, full-speed mode + (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time + =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit + Therefore, set 0x2C9. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [13:0] + read-write + + + + + HOST_FRAME + Host Frame Setup Register + 0x11C + 32 + read-write + 0x0 + 0x7FF + + + FRAME + These bits are used to specify a frame number of SOF. +Notes: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. + [10:0] + read-write + + + + + HOST_TOKEN + Host Token Endpoint Register + 0x120 + 32 + read-write + 0x0 + 0x17F + + + ENDPT + These bits are used to specify an endpoint to send or receive data to or from the device. +Note: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:0] + read-write + + + TKNEN + These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The PRE packet isn't supported. +- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' +- Mode should be USB Host before writing data to this bit. +- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. +- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. +- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [6:4] + read-write + + + NONE + Sends no data. + 0 + + + SETUP + Sends SETUP token. + 1 + + + IN + Sends IN token. + 2 + + + OUT + Sends OUT token. + 3 + + + SOF + Sends SOF token. + 4 + + + ISO_IN + Sends Isochronous IN. + 5 + + + ISO_OUT + Sends Isochronous OUT. + 6 + + + RSV + N/A + 7 + + + + + TGGL + This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. +'0' : DATA0 +'1' : DATA1 +Notes: +- This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. + [8:8] + read-write + + + + + HOST_EP1_CTL + Host Endpoint 1 Control Register + 0x400 + 32 + read-write + 0x8100 + 0x9DFF + + + PKS1 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. +- If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, + [8:0] + read-write + + + NULLE + When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the packet transfer mode. +'1' : Sets the packet transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. + [15:15] + read-write + + + + + HOST_EP1_STATUS + Host Endpoint 1 Status Register + 0x404 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE1 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. +The indication range is from 0x000 to 0x100. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [8:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP1 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. +'0' : Not initiatialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP1_RW1_DR + Host Endpoint 1 Data 1-Byte Register + 0x408 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP1 for 1-byte data + [7:0] + read-write + + + + + HOST_EP1_RW2_DR + Host Endpoint 1 Data 2-Byte Register + 0x40C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP1 for 2-byte data + [15:0] + read-write + + + + + HOST_EP2_CTL + Host Endpoint 2 Control Register + 0x500 + 32 + read-write + 0x8040 + 0x9C7F + + + PKS2 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. +- If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. + [6:0] + read-write + + + NULLE + When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the automatic buffer transfer mode. +'1' : Sets the automatic buffer transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. + [15:15] + read-write + + + + + HOST_EP2_STATUS + Host Endpoint 2 Status Register + 0x504 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE2 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. +The indication range is from 0x000 to 0x40. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [6:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP2 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. +'0' : Not Initialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP2_RW1_DR + Host Endpoint 2 Data 1-Byte Register + 0x508 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP2 for 1-byte data. + [7:0] + read-write + + + + + HOST_EP2_RW2_DR + Host Endpoint 2 Data 2-Byte Register + 0x50C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP2 for 2 byte data. + [15:0] + read-write + + + + + HOST_LVL1_SEL + Host Interrupt Level 1 Selection Register + 0x800 + 32 + read-write + 0x0 + 0xFFFF + + + SOFIRQ_SEL + These bits assign SOFIRQ interrupt flag to selected interrupt signals. + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + DIRQ_SEL + These bits assign DIRQ interrupt flag to selected interrupt signals. + [3:2] + read-write + + + CNNIRQ_SEL + These bits assign CNNIRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + CMPIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [7:6] + read-write + + + URIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + RWKIRQ_SEL + These bits assign RWKIRQ interrupt flag to selected interrupt signals. + [11:10] + read-write + + + RSVD_13_12 + N/A + [13:12] + read-write + + + TCAN_SEL + These bits assign TCAN interrupt flag to selected interrupt signals. + [15:14] + read-write + + + + + HOST_LVL2_SEL + Host Interrupt Level 2 Selection Register + 0x804 + 32 + read-write + 0x0 + 0xFF0 + + + EP1_DRQ_SEL + These bits assign EP1_DRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + EP1_SPK_SEL + These bits assign EP1_SPK interrupt flag to selected interrupt signals. + [7:6] + read-write + + + EP2_DRQ_SEL + These bits assign EP2_DRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + EP2_SPK_SEL + These bits assign EP2_SPK interrupt flag to selected interrupt signals. + [11:10] + read-write + + + + + INTR_USBHOST_CAUSE_HI + Interrupt USB Host Cause High Register + 0x900 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_MED + Interrupt USB Host Cause Medium Register + 0x904 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_LO + Interrupt USB Host Cause Low Register + 0x908 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_HOST_EP_CAUSE_HI + Interrupt USB Host Endpoint Cause High Register + 0x920 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_MED + Interrupt USB Host Endpoint Cause Medium Register + 0x924 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_LO + Interrupt USB Host Endpoint Cause Low Register + 0x928 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_USBHOST + Interrupt USB Host Register + 0x940 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQ + If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Does not issue an interrupt request by starting a SOF token. +'1' : Issues an interrupt request by starting a SOF token. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + DIRQ + If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device disconnection. +'1' : Issues an interrupt request by detecting a device disconnection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:1] + read-write + + + CNNIRQ + If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device connection. +'1' : Issues an interrupt request by detecting a device connection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + CMPIRQ + If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by token completion. +'1' : Issues an interrupt request by token completion. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. +- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [3:3] + read-write + + + URIRQ + If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by USB bus resetting. +'1' : Issues an interrupt request by USB bus resetting. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + RWKIRQ + If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by restart. +'1' : Issues an interrupt request by restart. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCAN + If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. +'0' : Does not cancel token sending. +'1' : Cancels token sending. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + INTR_USBHOST_SET + Interrupt USB Host Set Register + 0x944 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQS + This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [0:0] + read-write + + + DIRQS + This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [1:1] + read-write + + + CNNIRQS + This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [2:2] + read-write + + + CMPIRQS + This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [3:3] + read-write + + + URIRQS + This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [4:4] + read-write + + + RWKIRQS + This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANS + This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. + [7:7] + read-write + + + + + INTR_USBHOST_MASK + Interrupt USB Host Mask Register + 0x948 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQM + This bit masks the interrupt by SOF flag. +'0' : Disables +'1' : Enables + [0:0] + read-write + + + DIRQM + This bit masks the interrupt by DIRQ flag. +'0' : Disables +'1' : Enables + [1:1] + read-write + + + CNNIRQM + This bit masks the interrupt by CNNIRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + CMPIRQM + This bit masks the interrupt by CMPIRQ flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + URIRQM + This bit masks the interrupt by URIRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + RWKIRQM + This bit masks the interrupt by RWKIRQ flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANM + This bit masks the interrupt by TCAN flag. +'0' : Disables +'1' : Enables + [7:7] + read-write + + + + + INTR_USBHOST_MASKED + Interrupt USB Host Masked Register + 0x94C + 32 + read-only + 0x0 + 0xFF + + + SOFIRQED + This bit indicates the interrupt by SOF flag. +'0' : Doesn't request the interrupt by SOF +'1' : Request the interrupt by SOF + [0:0] + read-only + + + DIRQED + This bit indicates the interrupt by DIRQ flag. +'0' : Doesn't request the interrupt by DIRQ +'1' : Request the interrupt by DIRQ + [1:1] + read-only + + + CNNIRQED + This bit indicates the interrupt by CNNIRQ flag. +'0' : Doesn't request the interrupt by CNNIRQ +'1' : Request the interrupt by CNNIRQ + [2:2] + read-only + + + CMPIRQED + This bit indicates the interrupt by CMPIRQ flag. +'0' : Doesn't request the interrupt by CMPIRQ +'1' : Request the interrupt by CMPIRQ + [3:3] + read-only + + + URIRQED + This bit indicates the interrupt by URIRQ flag. +'0' : Doesn't request the interrupt by URIRQ +'1' : Request the interrupt by URIRQ + [4:4] + read-only + + + RWKIRQED + This bit indicates the interrupt by RWKIRQ flag. +'0' : Doesn't request the interrupt by RWKIRQ +'1' : Request the interrupt by RWKIRQ + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCANED + This bit indicates the interrupt by TCAN flag. +'0' : Doesn't request the interrupt by TCAN +'1' : Request the interrupt by TCAN + [7:7] + read-only + + + + + INTR_HOST_EP + Interrupt USB Host Endpoint Register + 0xA00 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQ + This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [2:2] + read-write + + + EP1SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The EP1SPK bit is not set during data transfer in the OUT direction. + [3:3] + read-write + + + EP2DRQ + This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [4:4] + read-write + + + EP2SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The SPK bit is not set during data transfer in the OUT direction. + [5:5] + read-write + + + + + INTR_HOST_EP_SET + Interrupt USB Host Endpoint Set Register + 0xA04 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQS + This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. + [2:2] + read-write + + + EP1SPKS + This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. + [3:3] + read-write + + + EP2DRQS + This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. + [4:4] + read-write + + + EP2SPKS + This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. + [5:5] + read-write + + + + + INTR_HOST_EP_MASK + Interrupt USB Host Endpoint Mask Register + 0xA08 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQM + This bit masks the interrupt by EP1DRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + EP1SPKM + This bit masks the interrupt by EP1SPK flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + EP2DRQM + This bit masks the interrupt by EP2DRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + EP2SPKM + This bit masks the interrupt by EP2SPK flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + + + INTR_HOST_EP_MASKED + Interrupt USB Host Endpoint Masked Register + 0xA0C + 32 + read-only + 0x0 + 0x3C + + + EP1DRQED + This bit indicates the interrupt by EP1DRQ flag. +'0' : Doesn't request the interrupt by EP1DRQ +'1' : Request the interrupt by EP1DRQ + [2:2] + read-only + + + EP1SPKED + This bit indicates the interrupt by EP1SPK flag. +'0' : Doesn't request the interrupt by EP1SPK +'1' : Request the interrupt by EP1SPK + [3:3] + read-only + + + EP2DRQED + This bit indicates the interrupt by EP2DRQ flag. +'0' : Doesn't request the interrupt by EP2DRQ +'1' : Request the interrupt by EP2DRQ + [4:4] + read-only + + + EP2SPKED + This bit indicates the interrupt by EP2SPK flag. +'0' : Doesn't request the interrupt by EP2SPK +'1' : Request the interrupt by EP2SPK + [5:5] + read-only + + + + + HOST_DMA_ENBL + Host DMA Enable Register + 0xB00 + 32 + read-write + 0x0 + 0xC + + + DM_EP1DRQE + This bit enables DMA Request by EP1DRQ. +'0' : Disable +'1' : Enable + [2:2] + read-write + + + DM_EP2DRQE + This bit enables DMA Request by EP2DRQ. +'0' : Disable +'1' : Enable + [3:3] + read-write + + + + + HOST_EP1_BLK + Host Endpoint 1 Block Register + 0xB20 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') + [31:16] + read-write + + + + + HOST_EP2_BLK + Host Endpoint 2 Block Register + 0xB30 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') + [31:16] + read-write + + + + + + + + SMIF0 + Serial Memory Interface + SMIF + 0x40420000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x3000 + 0x81073001 + + + XIP_MODE + Mode of operation. + +Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. + [0:0] + read-write + + + MMIO_MODE + '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. + 0 + + + XIP_MODE + 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. + 1 + + + + + CLOCK_IF_RX_SEL + Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. +'0': 'spi_clk_out' (internal clock) +'1': !'spi_clk_out' (internal clock) +'2': 'spi_clk_in' (feedback clock) +'3': !'spi_clk_in' (feedback clock) + +Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. + [13:12] + read-write + + + DESELECT_DELAY + Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: +'0': 1 interface clock cycle. +'1': 2 interface clock cycles. +'2': 3 interface clock cycles. +'3': 4 interface clock cycles. +'4': 5 interface clock cycles. +'5': 6 interface clock cycles. +'6': 7 interface clock cycles. +'7': 8 interface clock cycles. + +During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. + [18:16] + read-write + + + BLOCK + Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. + +This field is not used for test controller accesses. + [24:24] + read-write + + + BUS_ERROR + 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). + 0 + + + WAIT_STATES + 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). + 1 + + + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. +'1': Enabled. + +Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + Cache, cryptography, XIP, device interface or any other logic busy in the IP: +'0': not busy +'1': busy +When BUSY is '0', the IP can be safely disabled without: +- the potential loss of transient write data. +- the potential risk of aborting an inflight SPI device interface transfer. +When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. + [31:31] + read-only + + + + + TX_CMD_FIFO_STATUS + Transmitter command FIFO status + 0x44 + 32 + read-only + 0x0 + 0x7 + + + USED3 + Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. + [2:0] + read-only + + + + + TX_CMD_FIFO_WR + Transmitter command FIFO write + 0x50 + 32 + write-only + 0x0 + 0xFFFFF + + + DATA20 + Command data. The higher two bits DATA[19:18] specify the specific command +'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. +- DATA[17:16] specifies the width of the data transfer: + - '0': 1 bit/cycle (single data transfer). + - '1': 2 bits/cycle (dual data transfer). + - '2': 4 bits/cycle (quad data transfer). + - '3': 8 bits/cycle (octal data transfer). +- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. +- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. + - '0': device deselected + - '1': device selected +- DATA[7:0] specifies the transmitted Byte. + +'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. + +'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. + +'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. +- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. + [19:0] + write-only + + + + + TX_DATA_FIFO_CTL + Transmitter data FIFO control + 0x80 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. + [2:0] + read-write + + + + + TX_DATA_FIFO_STATUS + Transmitter data FIFO status + 0x84 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_DATA_FIFO_WR1 + Transmitter data FIFO write + 0x90 + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + TX_DATA_FIFO_WR2 + Transmitter data FIFO write + 0x94 + 32 + write-only + 0x0 + 0xFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + + + TX_DATA_FIFO_WR4 + Transmitter data FIFO write + 0x98 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + DATA2 + TX data (written to TX data FIFO, third byte). + [23:16] + write-only + + + DATA3 + TX data (written to TX data FIFO, fourth byte). + [31:24] + write-only + + + + + RX_DATA_FIFO_CTL + Receiver data FIFO control + 0xC0 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. + [2:0] + read-write + + + + + RX_DATA_FIFO_STATUS + Receiver data FIFO status + 0xC4 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + RX_DATA_FIFO_RD1 + Receiver data FIFO read + 0xD0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + RX_DATA_FIFO_RD2 + Receiver data FIFO read + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + + + RX_DATA_FIFO_RD4 + Receiver data FIFO read + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + DATA2 + RX data (read from RX data FIFO, third byte). + [23:16] + read-only + + + DATA3 + RX data (read from RX data FIFO, fourth byte). + [31:24] + read-only + + + + + RX_DATA_FIFO_RD1_SILENT + Receiver data FIFO silent read + 0xE0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + SLOW_CA_CTL + Slow cache control + 0x100 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. + [25:24] + read-write + + + PREF_EN + Prefetch enable: +'0': Disabled. +'1': Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + ENABLED + Cache enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + SLOW_CA_CMD + Slow cache command + 0x108 + 32 + read-write + 0x0 + 0x1 + + + INV + Cache and prefetch buffer invalidation. +SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. +Note, +A write access will invalidate the prefetch buffer automatically in hardware. +A write access should invalidate both fast and slow caches, by firmware. +Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. + [0:0] + read-write + + + + + FAST_CA_CTL + Fast cache control + 0x180 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + See SLOW_CA_CTL.WAY. + [17:16] + read-write + + + SET_ADDR + See SLOW_CA_CTL.SET_ADDR. + [25:24] + read-write + + + PREF_EN + See SLOW_CA_CTL.PREF_EN. + [30:30] + read-write + + + ENABLED + See SLOW_CA_CTL.ENABLED. + [31:31] + read-write + + + + + FAST_CA_CMD + Fast cache command + 0x188 + 32 + read-write + 0x0 + 0x1 + + + INV + See SLOW_CA_CMD.INV. + [0:0] + read-write + + + + + CRYPTO_CMD + Cryptography Command + 0x200 + 32 + read-write + 0x0 + 0x1 + + + START + SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. + +The operation takes roughly 13 clk_hf clock cycles. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + + + CRYPTO_INPUT0 + Cryptography input 0 + 0x220 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT1 + Cryptography input 1 + 0x224 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT2 + Cryptography input 2 + 0x228 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT3 + Cryptography input 3 + 0x22C + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_KEY0 + Cryptography key 0 + 0x240 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY1 + Cryptography key 1 + 0x244 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY2 + Cryptography key 2 + 0x248 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY3 + Cryptography key 3 + 0x24C + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_OUTPUT0 + Cryptography output 0 + 0x260 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT1 + Cryptography output 1 + 0x264 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT2 + Cryptography output 2 + 0x268 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT3 + Cryptography output 3 + 0x26C + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. + [31:0] + read-write + + + + + INTR + Interrupt register + 0x7C0 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. + [0:0] + read-write + + + TR_RX_REQ + Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Activated in XIP mode, if: +- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. +- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. + +Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. + [5:5] + read-write + + + + + INTR_SET + Interrupt set register + 0x7C4 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x7C8 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x7CC + 32 + read-only + 0x0 + 0x3F + + + TR_TX_REQ + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TR_RX_REQ + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + XIP_ALIGNMENT_ERROR + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TX_CMD_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + TX_DATA_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + RX_DATA_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + 4 + 128 + DEVICE[%s] + Device (only used in XIP mode) + 0x00000800 + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80030101 + + + WR_EN + Write enable: +'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. +'1': write transfers are allowed to this device. + [0:0] + read-write + + + CRYPTO_EN + Cryptography on read/write accesses: +'0': disabled. +'1': enabled. + [8:8] + read-write + + + DATA_SEL + Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): +'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. +'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. +'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. +'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. + [17:16] + read-write + + + ENABLED + Device enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + ADDR + Device region base address + 0x8 + 32 + read-write + 0x0 + 0x0 + + + ADDR + Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. + +In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. + +The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. + [31:8] + read-write + + + + + MASK + Device region mask + 0xC + 32 + read-write + 0x0 + 0x0 + + + MASK + Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. + +The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. + +Note: a transfer request that is not in any device region results in an AHB-Lite bus error. + [31:8] + read-write + + + + + ADDR_CTL + Address control + 0x20 + 32 + read-write + 0x0 + 0x103 + + + SIZE2 + Specifies the size of the XIP device address in Bytes: +'0': 1 Byte address. +'1': 2 Byte address. +'2': 3 Byte address. +'3': 4 Byte address. +The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [1:0] + read-write + + + DIV2 + Specifies if the AHB-Lite bus transfer address is divided by 2 or not: +'0': No divide by 2. +'1': Divide by 2. + +This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [8:8] + read-write + + + + + RD_CMD_CTL + Read command control + 0x40 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of data transfer: +'0': 1 bit/cycle (single data transfer). +'1': 2 bits/cycle (dual data transfer). +'2': 4 bits/cycle (quad data transfer). +'3': 8 bits/cycle (octal data transfer). + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_ADDR_CTL + Read address control + 0x44 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + RD_MODE_CTL + Read mode control + 0x48 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DUMMY_CTL + Read dummy control + 0x4C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + +Note: this field specifies dummy cycles, not dummy Bytes! + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DATA_CTL + Read data control + 0x50 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_CMD_CTL + Write command control + 0x60 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_ADDR_CTL + Write address control + 0x64 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_MODE_CTL + Write mode control + 0x68 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DUMMY_CTL + Write dummy control + 0x6C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DATA_CTL + Write data control + 0x70 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + + + + SCB0 + Serial Communications Block (SPI/UART/I2C) + SCB + 0x40610000 + + 0 + 65536 + registers + + + + CTRL + Generic control + 0x0 + 32 + read-write + 0x300000F + 0x83031F0F + + + OVS + N/A + [3:0] + read-write + + + EC_AM_MODE + Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field should be '0'. + [8:8] + read-write + + + EC_OP_MODE + Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). + +In UART mode this field should be '0'. + [9:9] + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field should be '0'. + [10:10] + read-write + + + BYTE_MODE + Determines the number of bits per FIFO data element: +'0': 16-bit FIFO data elements. +'1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. + [11:11] + read-write + + + CMD_RESP_MODE + Determines CMD_RESP mode of operation: +'0': CMD_RESP mode disabled. +'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). + [12:12] + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). + +In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. + +In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. + [16:16] + read-write + + + BLOCK + Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. + [17:17] + read-write + + + MODE + N/A + [25:24] + read-write + + + I2C + Inter-Integrated Circuits (I2C) mode. + 0 + + + SPI + Serial Peripheral Interface (SPI) mode. + 1 + + + UART + Universal Asynchronous Receiver/Transmitter (UART) mode. + 2 + + + + + ENABLED + IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: +- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL to enable IP, select the specific operation mode and oversampling factor. +When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + [31:31] + read-write + + + + + STATUS + Generic status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. + [0:0] + read-only + + + + + CMD_RESP_CTRL + Command/response control + 0x8 + 32 + read-write + 0x0 + 0x1FF01FF + + + BASE_RD_ADDR + I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. + [8:0] + read-write + + + BASE_WR_ADDR + I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. + [24:16] + read-write + + + + + CMD_RESP_STATUS + Command/response status + 0xC + 32 + read-only + 0x0 + 0x0 + + + CURR_RD_ADDR + I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [8:0] + read-only + + + CURR_WR_ADDR + I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [24:16] + read-only + + + CMD_RESP_EC_BUS_BUSY + Indicates whether there is an ongoing bus transfer to the IP. +'0': no ongoing bus transfer. +'1': ongoing bus transfer. + +For SPI, the field is '1' when the slave is selected. + +For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. + [30:30] + read-only + + + CMD_RESP_EC_BUSY + Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: +- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. + Note that this update lasts one I2C clock cycle, or two SPI clock cycles. + [31:31] + read-only + + + + + SPI_CTRL + SPI control + 0x20 + 32 + read-write + 0x3000000 + 0x8F010F3F + + + SSEL_CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. + +When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. + +When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames. + [0:0] + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. + +When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. + +When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. + [1:1] + read-write + + + CPHA + Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: +- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. +- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. + +In SPI Motorola submode, all four CPOL/CPHA modes are valid. +in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. +in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. + [2:2] + read-write + + + CPOL + Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: +- CPOL is '0': SCLK is '0' when not transmitting data. +- CPOL is '1': SCLK is '1' when not transmitting data. + [3:3] + read-write + + + LATE_MISO_SAMPLE + Changes the SCLK edge on which MISO is captured. Only used in master mode. + +When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). + +When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. + [4:4] + read-write + + + SCLK_CONTINUOUS + Only applicable in master mode. +'0': SCLK is generated, when the SPI master is enabled and data is transmitted. +'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. + [5:5] + read-write + + + SSEL_POLARITY0 + Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: +'0': slave select is low/'0' active. +'1': slave select is high/'1' active. +For Texas Instruments submode: +'0': high/'1' active precede/coincide pulse. +'1': low/'0' active precede/coincide pulse. + [8:8] + read-write + + + SSEL_POLARITY1 + Slave select polarity. + [9:9] + read-write + + + SSEL_POLARITY2 + Slave select polarity. + [10:10] + read-write + + + SSEL_POLARITY3 + Slave select polarity. + [11:11] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. +'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. +'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + SPI_MOTOROLA + SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 0 + + + SPI_TI + SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. + 1 + + + SPI_NS + SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 2 + + + + + SSEL + Selects one of the four incoming/outgoing SPI slave select signals: +- 0: Slave 0, SSEL[0]. +- 1: Slave 1, SSEL[1]. +- 2: Slave 2, SSEL[2]. +- 3: Slave 3, SSEL[3]. +The IP should be disabled when changes are made to this field. + [27:26] + read-write + + + MASTER_MODE + Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. + [31:31] + read-write + + + + + SPI_STATUS + SPI status + 0x24 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. + [0:0] + read-only + + + SPI_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. + [1:1] + read-only + + + CURR_EZ_ADDR + SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + UART_CTRL + UART control + 0x40 + 32 + read-write + 0x3000000 + 0x3010000 + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. + +This allows a SCB UART transmitter to communicate with its receiver counterpart. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + UART_STD + Standard UART submode. + 0 + + + UART_SMARTCARD + SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. + 1 + + + UART_IRDA + Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. + 2 + + + + + + + UART_TX_CTRL + UART transmitter control + 0x44 + 32 + read-write + 0x2 + 0x137 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware + [5:5] + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + [8:8] + read-write + + + + + UART_RX_CTRL + UART receiver control + 0x48 + 32 + read-write + 0xA0002 + 0xF3777 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + +Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. + [5:5] + read-write + + + POLARITY + Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + [6:6] + read-write + + + DROP_ON_PARITY_ERROR + Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). + [8:8] + read-write + + + DROP_ON_FRAME_ERROR + Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + [9:9] + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. + [10:10] + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [12:12] + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. + [13:13] + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. + [19:16] + read-write + + + + + UART_RX_STATUS + UART receiver status + 0x4C + 32 + read-only + 0x0 + 0x0 + + + BR_COUNTER + Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. + [11:0] + read-only + + + + + UART_FLOW_CTRL + UART flow control + 0x50 + 32 + read-write + 0x0 + 0x30100FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). + [7:0] + read-write + + + RTS_POLARITY + Polarity of the RTS output signal 'uart_rts_out': +'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. +'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. + +During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. + [16:16] + read-write + + + CTS_POLARITY + Polarity of the CTS input signal 'uart_cts_in': +'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. +'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. + [24:24] + read-write + + + CTS_ENABLED + Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: +'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. +'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. + +If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). + [25:25] + read-write + + + + + I2C_CTRL + I2C control + 0x60 + 32 + read-write + 0xFB88 + 0xC001FBFF + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. + [3:0] + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. + [7:4] + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. + [8:8] + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). + [9:9] + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. + [11:11] + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [12:12] + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [13:13] + read-write + + + S_NOT_READY_ADDR_NACK + For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: +- EC_AM is '0', EC_OP is '0' and non EZ mode. +Functionality is as follows: +- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + +For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): +- EC_AM is '1' and EC_OP is '0'. +- EC_AM is '1' and general call address match. +- EC_AM is '1' and non EZ mode. +Functionality is as follows: +- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). +- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. + [14:14] + read-write + + + S_NOT_READY_DATA_NACK + For internally clocked logic only. Only used when: +- non EZ mode. +Functionality is as follows: +- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + [15:15] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. + [16:16] + read-write + + + SLAVE_MODE + Slave mode enabled ('1') or not ('0'). + [30:30] + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. + [31:31] + read-write + + + + + I2C_STATUS + I2C status + 0x64 + 32 + read-only + 0x0 + 0x31 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). + +For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). + +For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). + [0:0] + read-only + + + I2C_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. + [1:1] + read-only + + + S_READ + I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. + [4:4] + read-only + + + M_READ + I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. + [5:5] + read-only + + + CURR_EZ_ADDR + I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + I2C_M_CMD + I2C master command + 0x68 + 32 + read-write + 0x0 + 0x1F + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. + [0:0] + read-write + + + M_START_ON_IDLE + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. + [1:1] + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + [2:2] + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + [3:3] + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. + I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. + [4:4] + read-write + + + + + I2C_S_CMD + I2C slave command + 0x6C + 32 + read-write + 0x0 + 0x3 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). + [0:0] + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. + [1:1] + read-write + + + + + I2C_CFG + I2C configuration + 0x70 + 32 + read-write + 0x2A1013 + 0x303F1313 + + + SDA_IN_FILT_TRIM + Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + +SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. +1: enable clock_scb_en, has no effect on ec_busy_pp +0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) + [1:0] + read-write + + + SDA_IN_FILT_SEL + Selection of 'i2c_sda_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [4:4] + read-write + + + SCL_IN_FILT_TRIM + Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [9:8] + read-write + + + SCL_IN_FILT_SEL + Selection of 'i2c_scl_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [12:12] + read-write + + + SDA_OUT_FILT0_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [17:16] + read-write + + + SDA_OUT_FILT1_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [19:18] + read-write + + + SDA_OUT_FILT2_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [21:20] + read-write + + + SDA_OUT_FILT_SEL + Selection of cumulative 'i2c_sda_out' filter delay: +'0': 0 ns. +'1': 50 ns (filter 0 enabled). +'2': 100 ns (filters 0 and 1 enabled). +'3': 150 ns (filters 0, 1 and 2 enabled). + [29:28] + read-write + + + + + TX_CTRL + Transmitter control + 0x200 + 32 + read-write + 0x107 + 0x1010F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + OPEN_DRAIN + Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. +'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. +'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). + +The open drain mode is supported for: +- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. +- UART mode, 'uart_tx' IO cell (SPI slave). +- SPI mode, 'spi_miso' IO cell. + [16:16] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control + 0x204 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + [17:17] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status + 0x208 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + [31:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write + 0x240 + 32 + write-only + 0x0 + 0xFFFF + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. + [15:0] + write-only + + + + + RX_CTRL + Receiver control + 0x300 + 32 + read-write + 0x107 + 0x30F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. + [9:9] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control + 0x304 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + [17:17] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status + 0x308 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + [31:24] + read-only + + + + + RX_MATCH + Slave address and mask + 0x310 + 32 + read-write + 0x0 + 0xFF00FF + + + ADDR + Slave device address. + +In UART multi-processor mode, all 8 bits are used. + +In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). + [7:0] + read-write + + + MASK + Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). + [23:16] + read-write + + + + + RX_FIFO_RD + Receiver FIFO read + 0x340 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read silent + 0x344 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + INTR_CAUSE + Active clocked interrupt signal + 0xE00 + 32 + read-only + 0x0 + 0x3F + + + M + Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. + [0:0] + read-only + + + S + Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. + [1:1] + read-only + + + TX + Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. + [2:2] + read-only + + + RX + Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. + [3:3] + read-only + + + I2C_EC + Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. + [4:4] + read-only + + + SPI_EC + Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. + [5:5] + read-only + + + + + INTR_I2C_EC + Externally clocked I2C interrupt request + 0xE80 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (I2C STOP). + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask + 0xE88 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_I2C_EC_MASKED + Externally clocked I2C interrupt masked + 0xE8C + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_SPI_EC + Externally clocked SPI interrupt request + 0xEC0 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (SPI deselection). + +Only available in EZ and CMD_RESP mode and when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask + 0xEC8 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked + 0xECC + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_M + Master interrupt request + 0xF00 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + [0:0] + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + [1:1] + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + [2:2] + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + [4:4] + read-write + + + I2C_BUS_ERROR + I2C master bus error (unexpected detection of START or STOP condition). + [8:8] + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. + [9:9] + read-write + + + + + INTR_M_SET + Master interrupt set request + 0xF04 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASK + Master interrupt mask + 0xF08 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASKED + Master interrupt masked request + 0xF0C + 32 + read-only + 0x0 + 0x317 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + + + INTR_S + Slave interrupt request + 0xF40 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [0:0] + read-write + + + I2C_NACK + I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). + [1:1] + read-write + + + I2C_ACK + I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). + [2:2] + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. + +In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). + [3:3] + read-write + + + I2C_STOP + I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. + [4:4] + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. + [5:5] + read-write + + + I2C_ADDR_MATCH + I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [6:6] + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [7:7] + read-write + + + I2C_BUS_ERROR + I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + SPI slave deselected after a write EZ SPI transfer occurred. + [9:9] + read-write + + + SPI_EZ_STOP + SPI slave deselected after any EZ SPI transfer occurred. + [10:10] + read-write + + + SPI_BUS_ERROR + SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [11:11] + read-write + + + + + INTR_S_SET + Slave interrupt set request + 0xF44 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASK + Slave interrupt mask + 0xF48 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASKED + Slave interrupt masked request + 0xF4C + 32 + read-only + 0x0 + 0xFFF + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_START + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + SPI_EZ_STOP + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + SPI_BUS_ERROR + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + INTR_TX + Transmitter interrupt request + 0xF80 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_FULL + TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries != FF_DATA_NR/2. +BYTE_MODE is '1': # entries != FF_DATA_NR. + +Only used in FIFO mode. + [1:1] + read-write + + + EMPTY + TX FIFO is empty; i.e. it has 0 entries. + +Only used in FIFO mode. + [4:4] + read-write + + + OVERFLOW + Attempt to write to a full TX FIFO. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + UART_NACK + UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. + [8:8] + read-write + + + UART_DONE + UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. + [9:9] + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + + + INTR_TX_SET + Transmitter interrupt set request + 0xF84 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASK + Transmitter interrupt mask + 0xF88 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASKED + Transmitter interrupt masked request + 0xF8C + 32 + read-only + 0x0 + 0x7F3 + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + UART_NACK + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + UART_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + INTR_RX + Receiver interrupt request + 0xFC0 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_EMPTY + RX FIFO is not empty. + +Only used in FIFO mode. + [2:2] + read-write + + + FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries == FF_DATA_NR/2. +BYTE_MODE is '1': # entries == FF_DATA_NR. + +Only used in FIFO mode. + [3:3] + read-write + + + OVERFLOW + Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty RX FIFO. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + FRAME_ERROR + Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: +Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. +Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. + +A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. + [8:8] + read-write + + + PARITY_ERROR + Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. + [9:9] + read-write + + + BAUD_DETECT + LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. + [11:11] + read-write + + + + + INTR_RX_SET + Receiver interrupt set request + 0xFC4 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt status register. + [2:2] + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt status register. + [3:3] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt status register. + [7:7] + read-write + + + FRAME_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [8:8] + read-write + + + PARITY_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [9:9] + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [10:10] + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [11:11] + read-write + + + + + INTR_RX_MASK + Receiver interrupt mask + 0xFC8 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + FRAME_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + PARITY_ERROR + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_RX_MASKED + Receiver interrupt masked request + 0xFCC + 32 + read-only + 0x0 + 0xFED + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + FULL + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + FRAME_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + PARITY_ERROR + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + BAUD_DETECT + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + BREAK_DETECT + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + + + SCB1 + 0x40620000 + + + SCB2 + 0x40630000 + + + SCB3 + 0x40640000 + + + SCB4 + 0x40650000 + + + SCB5 + 0x40660000 + + + SCB6 + 0x40670000 + + + SCB7 + 0x40680000 + + + SCB8 + 0x40690000 + + + CTBM0 + Continuous Time Block Mini + CTBM + 0x41100000 + + 0 + 65536 + registers + + + + CTB_CTRL + global CTB and power control + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + DEEPSLEEP_ON + - 0: CTB IP disabled off during DeepSleep power mode +- 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + - 0: CTB IP disabled (put analog in power down, open all switches) +- 1: CTB IP enabled + [31:31] + read-write + + + + + OA_RES0_CTRL + Opamp0 and resistor0 control + 0x4 + 32 + read-write + 0x0 + 0x1BFF + + + OA0_PWR_MODE + Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver + [2:0] + read-write + + + OFF + Off + 0 + + + LOW + Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x) + 1 + + + MEDIUM + Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x) + 2 + + + HIGH + High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x) + 3 + + + RSVD + N/A + 4 + + + PS_LOW + Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is disabled) + 5 + + + PS_MEDIUM + Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled) + 6 + + + PS_HIGH + Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled) + 7 + + + + + OA0_DRIVE_STR_SEL + Opamp0 output strength select 0=1x, 1=10x +This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM + [3:3] + read-write + + + OA0_COMP_EN + Opamp0 comparator enable + [4:4] + read-write + + + OA0_HYST_EN + Opamp0 hysteresis enable (10mV) + [5:5] + read-write + + + OA0_BYPASS_DSI_SYNC + Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async) + [6:6] + read-write + + + OA0_DSI_LEVEL + Opamp0 comparator DSI (trigger) out level : +0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI +1=level, DSI output is a synchronized version of the comparator output + [7:7] + read-write + + + OA0_COMPINT + Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger) + [9:8] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + OA0_PUMP_EN + Opamp0 pump enable + [11:11] + read-write + + + OA0_BOOST_EN + Opamp0 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 + [12:12] + read-write + + + + + OA_RES1_CTRL + Opamp1 and resistor1 control + 0x8 + 32 + read-write + 0x0 + 0x1BFF + + + OA1_PWR_MODE + Opamp1 power level: see description of OA0_PWR_MODE + [2:0] + read-write + + + OA1_DRIVE_STR_SEL + Opamp1 output strength select 0=1x, 1=10x +This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM + [3:3] + read-write + + + OA1_COMP_EN + Opamp1 comparator enable + [4:4] + read-write + + + OA1_HYST_EN + Opamp1 hysteresis enable (10mV) + [5:5] + read-write + + + OA1_BYPASS_DSI_SYNC + Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass + [6:6] + read-write + + + OA1_DSI_LEVEL + Opamp1 comparator DSI (trigger) out level : +0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI +1=level, DSI output is a synchronized version of the comparator output + [7:7] + read-write + + + OA1_COMPINT + Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger) + [9:8] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + OA1_PUMP_EN + Opamp1 pump enable + [11:11] + read-write + + + OA1_BOOST_EN + Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 + [12:12] + read-write + + + + + COMP_STAT + Comparator status + 0xC + 32 + read-only + 0x0 + 0x10001 + + + OA0_COMP + Opamp0 current comparator status + [0:0] + read-only + + + OA1_COMP + Opamp1 current comparator status + [16:16] + read-only + + + + + INTR + Interrupt request register + 0x20 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + Interrupt request set register + 0x24 + 32 + read-write + 0x0 + 0x3 + + + COMP0_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + Interrupt request mask + 0x28 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + Interrupt request masked + 0x2C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + OA0_SW + Opamp0 switch control + 0x80 + 32 + read-write + 0x0 + 0x24410D + + + OA0P_A00 + Opamp0 positive terminal amuxbusa + [0:0] + read-write + + + OA0P_A20 + Opamp0 positive terminal P0 + [2:2] + read-write + + + OA0P_A30 + Opamp0 positive terminal ctbbus0 + [3:3] + read-write + + + OA0M_A11 + Opamp0 negative terminal P1 + [8:8] + read-write + + + OA0M_A81 + Opamp0 negative terminal Opamp0 output + [14:14] + read-write + + + OA0O_D51 + Opamp0 output sarbus0 (ctbbus2 in CTB) + [18:18] + read-write + + + OA0O_D81 + Opamp0 output switch to short 1x with 10x drive + [21:21] + read-write + + + + + OA0_SW_CLEAR + Opamp0 switch control clear + 0x84 + 32 + read-write + 0x0 + 0x24410D + + + OA0P_A00 + see corresponding bit in OA0_SW + [0:0] + read-write + + + OA0P_A20 + see corresponding bit in OA0_SW + [2:2] + read-write + + + OA0P_A30 + see corresponding bit in OA0_SW + [3:3] + read-write + + + OA0M_A11 + see corresponding bit in OA0_SW + [8:8] + read-write + + + OA0M_A81 + see corresponding bit in OA0_SW + [14:14] + read-write + + + OA0O_D51 + see corresponding bit in OA0_SW + [18:18] + read-write + + + OA0O_D81 + see corresponding bit in OA0_SW + [21:21] + read-write + + + + + OA1_SW + Opamp1 switch control + 0x88 + 32 + read-write + 0x0 + 0x2C4193 + + + OA1P_A03 + Opamp1 positive terminal amuxbusb + [0:0] + read-write + + + OA1P_A13 + Opamp1 positive terminal P5 + [1:1] + read-write + + + OA1P_A43 + Opamp1 positive terminal ctbbus1 + [4:4] + read-write + + + OA1P_A73 + Opamp1 positive terminal to vref1 + [7:7] + read-write + + + OA1M_A22 + Opamp1 negative terminal P4 + [8:8] + read-write + + + OA1M_A82 + Opamp1 negative terminal Opamp1 output + [14:14] + read-write + + + OA1O_D52 + Opamp1 output sarbus0 (ctbbus2 in CTB) + [18:18] + read-write + + + OA1O_D62 + Opamp1 output sarbus1 (ctbbus3 in CTB) + [19:19] + read-write + + + OA1O_D82 + Opamp1 output switch to short 1x with 10x drive + [21:21] + read-write + + + + + OA1_SW_CLEAR + Opamp1 switch control clear + 0x8C + 32 + read-write + 0x0 + 0x2C4193 + + + OA1P_A03 + see corresponding bit in OA1_SW + [0:0] + read-write + + + OA1P_A13 + see corresponding bit in OA1_SW + [1:1] + read-write + + + OA1P_A43 + see corresponding bit in OA1_SW + [4:4] + read-write + + + OA1P_A73 + see corresponding bit in OA1_SW + [7:7] + read-write + + + OA1M_A22 + see corresponding bit in OA1_SW + [8:8] + read-write + + + OA1M_A82 + see corresponding bit in OA1_SW + [14:14] + read-write + + + OA1O_D52 + see corresponding bit in OA1_SW + [18:18] + read-write + + + OA1O_D62 + see corresponding bit in OA1_SW + [19:19] + read-write + + + OA1O_D82 + see corresponding bit in OA1_SW + [21:21] + read-write + + + + + CTD_SW + CTDAC connection switch control + 0xA0 + 32 + read-write + 0x0 + 0xF732 + + + CTDD_CRD + CTDAC Reference opamp output to ctdrefdrive + [1:1] + read-write + + + CTDS_CRS + ctdrefsense to opamp input + [4:4] + read-write + + + CTDS_COR + ctdvout to opamp input + [5:5] + read-write + + + CTDO_C6H + P6 pin to Hold capacitor + [8:8] + read-write + + + CTDO_COS + ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set + [9:9] + read-write + + + CTDH_COB + Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation + [10:10] + read-write + + + CTDH_CHD + Hold capacitor connect + [12:12] + read-write + + + CTDH_CA0 + Hold capacitor to opamp input + [13:13] + read-write + + + CTDH_CIS + Hold capacitor isolation (from all the other switches) + [14:14] + read-write + + + CTDH_ILR + Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage) + [15:15] + read-write + + + + + CTD_SW_CLEAR + CTDAC connection switch control clear + 0xA4 + 32 + read-write + 0x0 + 0xF732 + + + CTDD_CRD + see corresponding bit in CTD_SW + [1:1] + read-write + + + CTDS_CRS + see corresponding bit in CTD_SW + [4:4] + read-write + + + CTDS_COR + see corresponding bit in CTD_SW + [5:5] + read-write + + + CTDO_C6H + see corresponding bit in CTD_SW + [8:8] + read-write + + + CTDO_COS + see corresponding bit in CTD_SW + [9:9] + read-write + + + CTDH_COB + see corresponding bit in CTD_SW + [10:10] + read-write + + + CTDH_CHD + see corresponding bit in CTD_SW + [12:12] + read-write + + + CTDH_CA0 + see corresponding bit in CTD_SW + [13:13] + read-write + + + CTDH_CIS + see corresponding bit in CTD_SW + [14:14] + read-write + + + CTDH_ILR + see corresponding bit in CTD_SW + [15:15] + read-write + + + + + CTB_SW_DS_CTRL + CTB bus switch control + 0xC0 + 32 + read-write + 0x0 + 0x80000C00 + + + P2_DS_CTRL23 + for P22, D51 (dsi_out[2]) + [10:10] + read-write + + + P3_DS_CTRL23 + for P33, D52, D62 (dsi_out[3]) + [11:11] + read-write + + + CTD_COS_DS_CTRL + Hold capacitor Sample switch (COS) + [31:31] + read-write + + + + + CTB_SW_SQ_CTRL + CTB bus switch Sar Sequencer control + 0xC4 + 32 + read-write + 0x0 + 0xC00 + + + P2_SQ_CTRL23 + for D51 + [10:10] + read-write + + + P3_SQ_CTRL23 + for D52, D62 + [11:11] + read-write + + + + + CTB_SW_STATUS + CTB bus switch control status + 0xC8 + 32 + read-only + 0x0 + 0xF0000000 + + + OA0O_D51_STAT + see OA0O_D51 bit in OA0_SW + [28:28] + read-only + + + OA1O_D52_STAT + see OA1O_D52 bit in OA1_SW + [29:29] + read-only + + + OA1O_D62_STAT + see OA1O_D62 bit in OA1_SW + [30:30] + read-only + + + CTD_COS_STAT + see COS bit in CTD_SW + [31:31] + read-only + + + + + OA0_OFFSET_TRIM + Opamp0 trim control + 0xF00 + 32 + read-write + 0x0 + 0x3F + + + OA0_OFFSET_TRIM + Opamp0 offset trim + [5:0] + read-write + + + + + OA0_SLOPE_OFFSET_TRIM + Opamp0 trim control + 0xF04 + 32 + read-write + 0x0 + 0x3F + + + OA0_SLOPE_OFFSET_TRIM + Opamp0 slope offset drift trim + [5:0] + read-write + + + + + OA0_COMP_TRIM + Opamp0 trim control + 0xF08 + 32 + read-write + 0x0 + 0x3 + + + OA0_COMP_TRIM + Opamp0 Compensation Capacitor Trim. +Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 + [1:0] + read-write + + + + + OA1_OFFSET_TRIM + Opamp1 trim control + 0xF0C + 32 + read-write + 0x0 + 0x3F + + + OA1_OFFSET_TRIM + Opamp1 offset trim + [5:0] + read-write + + + + + OA1_SLOPE_OFFSET_TRIM + Opamp1 trim control + 0xF10 + 32 + read-write + 0x0 + 0x3F + + + OA1_SLOPE_OFFSET_TRIM + Opamp1 slope offset drift trim + [5:0] + read-write + + + + + OA1_COMP_TRIM + Opamp1 trim control + 0xF14 + 32 + read-write + 0x0 + 0x3 + + + OA1_COMP_TRIM + Opamp1 Compensation Capacitor Trim. +Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 + [1:0] + read-write + + + + + + + CTDAC0 + Continuous Time DAC + CTDAC + 0x41140000 + + 0 + 65536 + registers + + + + CTDAC_CTRL + Global CTDAC control + 0x0 + 32 + read-write + 0x0 + 0xFBC0033F + + + DEGLITCH_CNT + To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles. + [5:0] + read-write + + + DEGLITCH_CO6 + Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles. + [8:8] + read-write + + + DEGLITCH_COS + Force CTB.COS switch open after each VALUE change for the set number of clock cycles. + [9:9] + read-write + + + OUT_EN + Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : +0: output disabled, the output is either: + - Tri-state (DISABLED_MODE=0) + - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) + - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) +1: output enabled, CTDAC output drives the programmed VALUE + [22:22] + read-write + + + CTDAC_RANGE + By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 +0: Range is [0, 4095] * Vref / 4096 +1: Range is [1, 4096] * Vref / 4096 + [23:23] + read-write + + + CTDAC_MODE + DAC mode, this determines the Value decoding + [25:24] + read-write + + + UNSIGNED12 + Unsigned 12-bit VDAC, i.e. no value decoding. + 0 + + + VIRT_SIGNED12 + Virtual signed 12-bits' VDAC. Value decoding: +add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers. + 1 + + + RSVD2 + N/A + 2 + + + RSVD3 + N/A + 3 + + + + + DISABLED_MODE + Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) +0: Tri-state CTDAC output when disabled +1: output Vssa or Vref when disabled (see OUT_EN description) + [27:27] + read-write + + + DSI_STROBE_EN + DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. +0: Ignore DSI strobe input +1: Only do a CTDAC update if allowed by the DSI strobe (throttle), see below for level or edge + [28:28] + read-write + + + DSI_STROBE_LEVEL + Select level or edge detect for DSI strobe +- 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock +- 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock. + [29:29] + read-write + + + DEEPSLEEP_ON + - 0: CTDAC IP disabled off during DeepSleep power mode +- 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + 0: CTDAC IP disabled (put analog in power down, open all switches) +1: CTDAC IP enabled + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x20 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY + VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt request set register + 0x24 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt request mask + 0x28 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt request masked + 0x2C + 32 + read-only + 0x0 + 0x1 + + + VDAC_EMPTY_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + + + CTDAC_SW + CTDAC switch control + 0xB0 + 32 + read-write + 0x0 + 0x101 + + + CTDD_CVD + VDDA supply to ctdrefdrive + [0:0] + read-write + + + CTDO_CO6 + ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set + [8:8] + read-write + + + + + CTDAC_SW_CLEAR + CTDAC switch control clear + 0xB4 + 32 + read-write + 0x0 + 0x101 + + + CTDD_CVD + see corresponding bit in CTD_SW + [0:0] + read-write + + + CTDO_CO6 + see corresponding bit in CTD_SW + [8:8] + read-write + + + + + CTDAC_VAL + DAC Value + 0x100 + 32 + read-write + 0x0 + 0xFFF + + + VALUE + Value, in CTDAC_MODE 1 this value is decoded + [11:0] + read-write + + + + + CTDAC_VAL_NXT + Next DAC value (double buffering) + 0x104 + 32 + read-write + 0x0 + 0xFFF + + + VALUE + Next value for CTDAC_VAL.VALUE + [11:0] + read-write + + + + + + + SAR + SAR ADC with Sequencer + 0x411D0000 + + 0 + 65536 + registers + + + + CTRL + Analog control register. + 0x0 + 32 + read-write + 0x10000000 + 0xFF3FEEF7 + + + PWR_CTRL_VREF + VREF buffer low power mode. + [2:0] + read-write + + + PWR_100 + full power (100 percent) (default), bypass cap, max clk_sar is 18MHz. + 0 + + + PWR_80 + 80 percent power + 1 + + + PWR_60 + 60 percent power + 2 + + + PWR_50 + 50 percent power + 3 + + + PWR_40 + 40 percent power + 4 + + + PWR_30 + 30 percent power + 5 + + + PWR_20 + 20 percent power + 6 + + + PWR_10 + 10 percent power + 7 + + + + + VREF_SEL + SARADC internal VREF selection. + [6:4] + read-write + + + VREF0 + VREF0 from PRB (VREF buffer on) + 0 + + + VREF1 + VREF1 from PRB (VREF buffer on) + 1 + + + VREF2 + VREF2 from PRB (VREF buffer on) + 2 + + + VREF_AROUTE + VREF from AROUTE (VREF buffer on) + 3 + + + VBGR + 1.024V from BandGap (VREF buffer on) + 4 + + + VREF_EXT + External precision Vref direct from a pin (low impedance path). + 5 + + + VDDA_DIV_2 + Vdda/2 (VREF buffer on) + 6 + + + VDDA + Vdda. + 7 + + + + + VREF_BYP_CAP_EN + VREF bypass cap enable for when VREF buffer is on + [7:7] + read-write + + + NEG_SEL + SARADC internal NEG selection for Single ended conversion + [11:9] + read-write + + + VSSA_KELVIN + NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high. + 0 + + + ART_VSSA + NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC + 1 + + + P1 + NEG input of SARADC is connected to P1 pin of SARMUX + 2 + + + P3 + NEG input of SARADC is connected to P3 pin of SARMUX + 3 + + + P5 + NEG input of SARADC is connected to P5 pin of SARMUX + 4 + + + P7 + NEG input of SARADC is connected to P7 pin of SARMUX + 5 + + + ACORE + NEG input of SARADC is connected to an ACORE in AROUTE + 6 + + + VREF + NEG input of SARADC is shorted with VREF input of SARADC. + 7 + + + + + SAR_HW_CTRL_NEGVREF + Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. + [13:13] + read-write + + + COMP_DLY + Set the comparator latch delay in accordance with SAR conversion rate + [15:14] + read-write + + + D2P5 + 2.5ns delay, use this for 2.5Msps + 0 + + + D4 + 4.0ns delay, use this for 2.0Msps + 1 + + + D10 + 10ns delay, use this for 1.5Msps + 2 + + + D12 + 12ns delay, use this for 1.0Msps or less + 3 + + + + + SPARE + Spare controls, not yet designated, for late changes done with an ECO + [19:16] + read-write + + + BOOSTPUMP_EN + deprecated + [20:20] + read-write + + + REFBUF_EN + For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. +Setting this bit is critical to proper function of switches inside SARREF block. + [21:21] + read-write + + + COMP_PWR + Comparator power mode. + [26:24] + read-write + + + P100 + Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz + 0 + + + P80 + N/A + 1 + + + P60 + Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz. + 2 + + + P50 + N/A + 3 + + + P40 + N/A + 4 + + + P30 + N/A + 5 + + + P20 + Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz + 6 + + + P10 + N/A + 7 + + + + + DEEPSLEEP_ON + - 0: SARMUX IP disabled off during DeepSleep power mode +- 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) + [27:27] + read-write + + + DSI_SYNC_CONFIG + - 0: bypass clock domain synchronization of the DSI config signals. +- 1: synchronize the DSI config signals to peripheral clock domain. + [28:28] + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) +- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations +- 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored + [29:29] + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) +- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations +- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX + [30:30] + read-write + + + ENABLED + - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgating) on write. +- 1: SAR IP enabled. + [31:31] + read-write + + + + + SAMPLE_CTRL + Sample control register. + 0x4 + 32 + read-write + 0x80008 + 0xDFCF01FE + + + LEFT_ALIGN + Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. + [1:1] + read-write + + + SINGLE_ENDED_SIGNED + Output data from a single ended conversion as a signed value + +If AVG_MODE = 1 (Interleaved averaging), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED. + [2:2] + read-write + + + UNSIGNED + Default: result data is unsigned (zero extended if needed) + 0 + + + SIGNED + result data is signed (sign extended if needed) + 1 + + + + + DIFFERENTIAL_SIGNED + Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 + +If AVG_MODE = 1 (Interleaved averaging), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED. + [3:3] + read-write + + + UNSIGNED + result data is unsigned (zero extended if needed) + 0 + + + SIGNED + Default: result data is signed (sign extended if needed) + 1 + + + + + AVG_CNT + Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. +- In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). +- In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). + [6:4] + read-write + + + AVG_SHIFT + Averaging shifting: after averaging the result is shifted right to fit in 12 bits. + [7:7] + read-write + + + AVG_MODE + Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. + [8:8] + read-write + + + ACCUNDUMP + Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged + 0 + + + INTERLEAVED + Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans. + 1 + + + + + CONTINUOUS + - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. +- 1: Continuously scan enabled channels, ignore triggers. + [16:16] + read-write + + + DSI_TRIGGER_EN + - 0: firmware trigger only: disable hardware trigger tr_sar_in. +- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). + [17:17] + read-write + + + DSI_TRIGGER_LEVEL + - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. +- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. + [18:18] + read-write + + + DSI_SYNC_TRIGGER + - 0: bypass clock domain synchronization of the trigger signal. +- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. + [19:19] + read-write + + + UAB_SCAN_MODE + Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored. + [22:22] + read-write + + + UNSCHEDULED + Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable. + 0 + + + SCHEDULED + Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. +This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator. + 1 + + + + + REPEAT_INVALID + For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: +- 0: use the last known valid sample for that channel and clear the NEWVALUE flag +- 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling) + [23:23] + read-write + + + VALID_SEL + Static UAB Valid select +0=UAB0 half 0 Valid output +1=UAB0 half 1 Valid output +2=UAB1 half 0 Valid output +3=UAB1 half 1 Valid output +4=UAB2 half 0 Valid output +5=UAB2 half 1 Valid output +6=UAB3 half 0 Valid output +7=UAB3 half 1 Valid output + [26:24] + read-write + + + VALID_SEL_EN + Enable static UAB Valid selection (override Hardware) + [27:27] + read-write + + + VALID_IGNORE + Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above + [28:28] + read-write + + + TRIGGER_OUT_EN + SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1). + [30:30] + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. + [31:31] + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x10 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. + [9:0] + read-write + + + SAMPLE_TIME1 + Sample time1 + [25:16] + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x14 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME2 + Sample time2 + [9:0] + read-write + + + SAMPLE_TIME3 + Sample time3 + [25:16] + read-write + + + + + RANGE_THRES + Global range detect threshold register. + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RANGE_LOW + Low threshold for range detect. + [15:0] + read-write + + + RANGE_HIGH + High threshold for range detect. + [31:16] + read-write + + + + + RANGE_COND + Global range detect mode register. + 0x1C + 32 + read-write + 0x0 + 0xC0000000 + + + RANGE_COND + Range condition select. + [31:30] + read-write + + + BELOW + result < RANGE_LOW + 0 + + + INSIDE + RANGE_LOW <= result < RANGE_HIGH + 1 + + + ABOVE + RANGE_HIGH <= result + 2 + + + OUTSIDE + result < RANGE_LOW || RANGE_HIGH <= result + 3 + + + + + + + CHAN_EN + Enable bits for the channels + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CHAN_EN + Channel enable. +- 0: the corresponding channel is disabled. +- 1: the corresponding channel is enabled, it will be included in the next scan. + [15:0] + read-write + + + + + START_CTRL + Start control register (firmware trigger). + 0x24 + 32 + read-write + 0x0 + 0x1 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. + [0:0] + read-write + + + + + 16 + 4 + CHAN_CONFIG[%s] + Channel configuration register. + 0x80 + 32 + read-write + 0x0 + 0x81773577 + + + POS_PIN_ADDR + Address of the pin to be sampled by this channel (connected to Vplus) + [2:0] + read-write + + + POS_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel (connected to Vplus) + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + DIFFERENTIAL_EN + Differential enable for this channel. +If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + NEG_PIN_ADDR + Address of the neg pin to be sampled by this channel. + [18:16] + read-write + + + NEG_PORT_ADDR + Address of the neg port that contains the pin to be sampled by this channel. + [22:20] + read-write + + + SARMUX + SARMUX pins. + 0 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + NEG_ADDR_EN + 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. + [24:24] + read-write + + + DSI_OUT_EN + DSI data output enable for this channel. +- 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. +- 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. + [31:31] + read-write + + + + + 16 + 4 + CHAN_WORK[%s] + Channel working data register + 0x100 + 32 + read-only + 0x0 + 0x88000000 + + + WORK + SAR conversion working data of the channel. The data is written here right after sampling this channel. + [15:0] + read-only + + + CHAN_WORK_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register + [27:27] + read-only + + + CHAN_WORK_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register + [31:31] + read-only + + + + + 16 + 4 + CHAN_RESULT[%s] + Channel result data register + 0x180 + 32 + read-only + 0x0 + 0xE8000000 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + [15:0] + read-only + + + CHAN_RESULT_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register + [27:27] + read-only + + + SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_SATURATE_INTR register + [29:29] + read-only + + + RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_RANGE_INTR register + [30:30] + read-only + + + CHAN_RESULT_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register + [31:31] + read-only + + + + + CHAN_WORK_UPDATED + Channel working data register 'updated' bits + 0x200 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_UPDATED + If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_RESULT_UPDATED + Channel result data register 'updated' bits + 0x204 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_UPDATED + If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_WORK_NEWVALUE + Channel working data register 'new value' bits + 0x208 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_NEWVALUE + If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + CHAN_RESULT_NEWVALUE + Channel result data register 'new value' bits + 0x20C + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_NEWVALUE + If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + INTR + Interrupt request register. + 0x210 + 32 + read-write + 0x0 + 0xFF + + + EOS_INTR + End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. + [0:0] + read-write + + + OVERFLOW_INTR + Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. + [1:1] + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [2:2] + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [3:3] + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. + [4:4] + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [5:5] + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [6:6] + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit. + [7:7] + read-write + + + + + INTR_SET + Interrupt set request register + 0x214 + 32 + read-write + 0x0 + 0xFF + + + EOS_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask register. + 0x218 + 32 + read-write + 0x0 + 0xFF + + + EOS_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_MASK + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x21C + 32 + read-only + 0x0 + 0xFF + + + EOS_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + OVERFLOW_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + FW_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + DSI_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + INJ_EOC_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + INJ_SATURATE_MASKED + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + INJ_RANGE_MASKED + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + INJ_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + + + SATURATE_INTR + Saturate interrupt request register. + 0x220 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_INTR + Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [15:0] + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x224 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register. + 0x228 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x22C + 32 + read-only + 0x0 + 0xFFFF + + + SATURATE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + RANGE_INTR + Range detect interrupt request register. + 0x230 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_INTR + Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [15:0] + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x234 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register. + 0x238 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x23C + 32 + read-only + 0x0 + 0xFFFF + + + RANGE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + INTR_CAUSE + Interrupt cause register + 0x240 + 32 + read-only + 0x0 + 0xC00000FF + + + EOS_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [0:0] + read-only + + + OVERFLOW_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [1:1] + read-only + + + FW_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [2:2] + read-only + + + DSI_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [3:3] + read-only + + + INJ_EOC_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [4:4] + read-only + + + INJ_SATURATE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [5:5] + read-only + + + INJ_RANGE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [6:6] + read-only + + + INJ_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [7:7] + read-only + + + SATURATE_MASKED_RED + Reduction OR of all SAR_SATURATION_INTR_MASKED bits + [30:30] + read-only + + + RANGE_MASKED_RED + Reduction OR of all SAR_RANGE_INTR_MASKED bits + [31:31] + read-only + + + + + INJ_CHAN_CONFIG + Injection channel configuration register. + 0x280 + 32 + read-write + 0x0 + 0xC0003577 + + + INJ_PIN_ADDR + Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. + [2:0] + read-write + + + INJ_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel. + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT + AROUTE virtual port + 6 + + + SARMUX_VIRT + SARMUX virtual port + 7 + + + + + INJ_DIFFERENTIAL_EN + Differential enable for this channel. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + INJ_AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + INJ_SAMPLE_TIME_SEL + Injection sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + INJ_TAILGATING + Injection channel tailgating. +- 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set if the SAR is not busy. If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan. +- 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. + [30:30] + read-write + + + INJ_START_EN + Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. + [31:31] + read-write + + + + + INJ_RESULT + Injection channel result register + 0x290 + 32 + read-only + 0x0 + 0xF8000000 + + + INJ_RESULT + SAR conversion result of the channel. + [15:0] + read-only + + + INJ_NEWVALUE + The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit) + [27:27] + read-only + + + INJ_COLLISION_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [28:28] + read-only + + + INJ_SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [29:29] + read-only + + + INJ_RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [30:30] + read-only + + + INJ_EOC_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [31:31] + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x2A0 + 32 + read-only + 0x0 + 0xC000001F + + + CUR_CHAN + current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. + [4:0] + read-only + + + SW_VREF_NEG + the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). + [30:30] + read-only + + + BUSY + If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. + [31:31] + read-only + + + + + AVG_STAT + Current averaging status (for debug) + 0x2A4 + 32 + read-only + 0x0 + 0xFF8FFFFF + + + CUR_AVG_ACCU + the current value of the averaging accumulator + [19:0] + read-only + + + INTRLV_BUSY + If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. +This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. + [23:23] + read-only + + + CUR_AVG_CNT + the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. + [31:24] + read-only + + + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x300 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit. + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit. + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit. + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit. + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit. + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit. + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit. + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit. + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit. + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit. + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit. + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit. + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit. + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit. + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit. + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit. + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit. + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit. + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit. + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit. + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit. + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit. + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit. + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit. + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit. + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit. + [29:29] + read-write + + + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x304 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [29:29] + read-write + + + + + MUX_SWITCH_DS_CTRL + SARMUX switch DSI control + 0x340 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_DS_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_DS_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_DS_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_DS_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_DS_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_DS_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_DS_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_DS_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_DS_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_DS_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_DS_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_DS_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_DS_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_DS_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_SQ_CTRL + SARMUX switch Sar Sequencer control + 0x344 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_SQ_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_SQ_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_SQ_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_SQ_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_SQ_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_SQ_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_SQ_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_SQ_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_SQ_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_SQ_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_SQ_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_SQ_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_SQ_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_SQ_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x348 + 32 + read-only + 0x0 + 0x3FFFFFF + + + MUX_FW_P0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [0:0] + read-only + + + MUX_FW_P1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [1:1] + read-only + + + MUX_FW_P2_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [2:2] + read-only + + + MUX_FW_P3_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [3:3] + read-only + + + MUX_FW_P4_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [4:4] + read-only + + + MUX_FW_P5_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [5:5] + read-only + + + MUX_FW_P6_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [6:6] + read-only + + + MUX_FW_P7_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [7:7] + read-only + + + MUX_FW_P0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [8:8] + read-only + + + MUX_FW_P1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [9:9] + read-only + + + MUX_FW_P2_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [10:10] + read-only + + + MUX_FW_P3_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [11:11] + read-only + + + MUX_FW_P4_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [12:12] + read-only + + + MUX_FW_P5_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [13:13] + read-only + + + MUX_FW_P6_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [14:14] + read-only + + + MUX_FW_P7_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [15:15] + read-only + + + MUX_FW_VSSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [16:16] + read-only + + + MUX_FW_TEMP_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [17:17] + read-only + + + MUX_FW_AMUXBUSA_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [18:18] + read-only + + + MUX_FW_AMUXBUSB_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [19:19] + read-only + + + MUX_FW_AMUXBUSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [20:20] + read-only + + + MUX_FW_AMUXBUSB_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [21:21] + read-only + + + MUX_FW_SARBUS0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [22:22] + read-only + + + MUX_FW_SARBUS1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [23:23] + read-only + + + MUX_FW_SARBUS0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [24:24] + read-only + + + MUX_FW_SARBUS1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [25:25] + read-only + + + + + ANA_TRIM0 + Analog trim register. + 0xF00 + 32 + read-write + 0x0 + 0x3F + + + CAP_TRIM + Attenuation cap trimming + [4:0] + read-write + + + TRIMUNIT + Attenuation cap trimming + [5:5] + read-write + + + + + ANA_TRIM1 + Analog trim register. + 0xF04 + 32 + read-write + 0x0 + 0x3F + + + SAR_REF_BUF_TRIM + SAR Reference buffer trim + [5:0] + read-write + + + + + + + PASS + PASS top-level MMIO (DSABv2, INTR) + 0x411F0000 + + 0 + 65536 + registers + + + + INTR_CAUSE + Interrupt cause register + 0x0 + 32 + read-only + 0x0 + 0xFF + + + CTB0_INT + CTB0 interrupt pending + [0:0] + read-only + + + CTB1_INT + CTB1 interrupt pending + [1:1] + read-only + + + CTB2_INT + CTB2 interrupt pending + [2:2] + read-only + + + CTB3_INT + CTB3 interrupt pending + [3:3] + read-only + + + CTDAC0_INT + CTDAC0 interrupt pending + [4:4] + read-only + + + CTDAC1_INT + CTDAC1 interrupt pending + [5:5] + read-only + + + CTDAC2_INT + CTDAC2 interrupt pending + [6:6] + read-only + + + CTDAC3_INT + CTDAC3 interrupt pending + [7:7] + read-only + + + + + AREF + AREF configuration + 0x00000E00 + + AREF_CTRL + global AREF control + 0x0 + 32 + read-write + 0x0 + 0xF039FFFD + + + AREF_MODE + Control bit to trade off AREF settling and noise performance + [0:0] + read-write + + + NORMAL + Nominal noise normal startup mode (meets normal mode settling and noise specifications) + 0 + + + FAST_START + High noise fast startup mode (meets fast mode settling and noise specifications) + 1 + + + + + AREF_BIAS_SCALE + BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) +0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) +1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) +2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) +3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) + [3:2] + read-write + + + AREF_RMB + AREF control signals (RMB). + +Bit 0: Manual VBG startup circuit enable + 0: normal VBG startup circuit operation + 1: VBG startup circuit is forced 'always on' + +Bit 1: Manual disable of IPTAT2 DAC + 0: normal IPTAT2 DAC operation + 1: PTAT2 DAC is disabled while VBG startup is active + +Bit 2: Manual enable of VBG offset correction DAC + 0: normal VBG offset correction DAC operation + 1: VBG offset correction DAC is enabled while VBG startup is active + [6:4] + read-write + + + CTB_IPTAT_SCALE + CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). +0: 1uA +1: 100nA + [7:7] + read-write + + + CTB_IPTAT_REDIRECT + Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). +0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT +1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT + +*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. + [15:8] + read-write + + + IZTAT_SEL + iztat current select control + [16:16] + read-write + + + SRSS + Use 250nA IZTAT from SRSS + 0 + + + LOCAL + Use locally generated 250nA + 1 + + + + + CLOCK_PUMP_PERI_SEL + CTBm charge pump clock source select. This field has nothing to do with the AREF. +0: Use the dedicated pump clock from SRSS (default) +1: Use one of the CLK_PERI dividers + [19:19] + read-write + + + VREF_SEL + bandgap voltage select control + [21:20] + read-write + + + SRSS + Use 0.8V Vref from SRSS + 0 + + + LOCAL + Use locally generated Vref + 1 + + + EXTERNAL + Use externally supplied Vref (aref_ext_vref) + 2 + + + + + DEEPSLEEP_MODE + AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) + [29:28] + read-write + + + OFF + All blocks 'OFF' in DeepSleep + 0 + + + IPTAT + IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) + 1 + + + IPTAT_IZTAT + IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) + +*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep + 2 + + + IPTAT_IZTAT_VREF + IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. + 3 + + + + + DEEPSLEEP_ON + - 0: AREF IP disabled/off during DeepSleep power mode +- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + Disable AREF + [31:31] + read-write + + + + + + VREF_TRIM0 + VREF Trim bits + 0xF00 + 32 + read-write + 0x0 + 0xFF + + + VREF_ABS_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM1 + VREF Trim bits + 0xF04 + 32 + read-write + 0x0 + 0xFF + + + VREF_TEMPCO_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM2 + VREF Trim bits + 0xF08 + 32 + read-write + 0x0 + 0xFF + + + VREF_CURV_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM3 + VREF Trim bits + 0xF0C + 32 + read-write + 0x0 + 0xF + + + VREF_ATTEN_TRIM + Obsolete + [3:0] + read-write + + + + + IZTAT_TRIM0 + IZTAT Trim bits + 0xF10 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_ABS_TRIM + N/A + [7:0] + read-write + + + + + IZTAT_TRIM1 + IZTAT Trim bits + 0xF14 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_TC_TRIM + IZTAT temperature correction trim (RMB) +0x00 : No IZTAT temperature correction +0xFF : Maximum IZTAT temperature correction + +As this is a Risk Mitigation Register, it should be loaded with 0x08. + [7:0] + read-write + + + + + IPTAT_TRIM0 + IPTAT Trim bits + 0xF18 + 32 + read-write + 0x0 + 0xFF + + + IPTAT_CORE_TRIM + IPTAT trim +0x0 : Minimum IPTAT current (~150nA at room) +0xF : Maximum IPTAT current (~350nA at room) + [3:0] + read-write + + + IPTAT_CTBM_TRIM + CTMB PTAT Current Trim +0x0 : Minimum CTMB IPTAT Current (~875nA) +0xF : Maximum CTMB IPTAT Current (~1.1uA) + [7:4] + read-write + + + + + ICTAT_TRIM0 + ICTAT Trim bits + 0xF1C + 32 + read-write + 0x0 + 0xF + + + ICTAT_TRIM + ICTAT trim +0x00 : Minimum ICTAT current (~150nA at room) +0x0F : Maximum ICTAT current (~350nA at room) + [3:0] + read-write + + + + + + + I2S0 + I2S registers + I2S + 0x42A10000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + TX_ENABLED + Enables the I2S TX component: +'0': Disabled. +'1': Enabled. + [30:30] + read-write + + + RX_ENABLED + Enables the I2S RX component: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CLOCK_CTL + Clock control + 0x10 + 32 + read-write + 0x0 + 0x13F + + + CLOCK_DIV + Frequency divisor for generating I2S clock frequency. +The selected clock with CLOCK_SEL is divided by this. +'0': Bypass +'1': 2 x +'2': 3 x +'3': 4 x +... +'62': 63 x +'63': 64 x + [5:0] + read-write + + + CLOCK_SEL + Selects clock to be used by I2S: +'0': Internal clock ('clk_audio_i2s') +'1': External clock ('clk_i2s_if') + [8:8] + read-write + + + + + CMD + Command + 0x20 + 32 + read-write + 0x0 + 0x10101 + + + TX_START + Transmitter enable: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + TX_PAUSE + Pause enable: +'0': Disabled (TX FIFO data is sent over I2S). +'1': Enabled ('0' data is sent over I2S, instead of TX FIFO data). + [8:8] + read-write + + + RX_START + Receiver enable: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + TR_CTL + Trigger control + 0x40 + 32 + read-write + 0x0 + 0x10001 + + + TX_REQ_EN + Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + RX_REQ_EN + Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + TX_CTL + Transmitter control + 0x80 + 32 + read-write + 0x440510 + 0x37737F8 + + + B_CLOCK_INV + Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. +When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'. + +1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge +2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1) +3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge +4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3) + +(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. +Note: When Master mode, must be '0'. +(Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV) + [3:3] + read-write + + + FALLING_EDGE_TX + SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0 + 0 + + + RISING_EDGE_TX + SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0 + 1 + + + + + CH_NR + Specifies number of channels per frame: + +Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. +(Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET) + [6:4] + read-write + + + CH_NUM1 + 1 channel + 0 + + + CH_NUM2 + 2 channels + 1 + + + CH_NUM3 + 3 channels + 2 + + + CH_NUM4 + 4 channels + 3 + + + CH_NUM5 + 5 channels + 4 + + + CH_NUM6 + 6 channels + 5 + + + CH_NUM7 + 7 channels + 6 + + + CH_NUM8 + 8 channels + 7 + + + + + MS + Set interface in master or slave mode: + +(Note: This bit is connected to AR38U12.TX_CFG.TX_MS) + [7:7] + read-write + + + SLAVE + Slave + 0 + + + MASTER + Master + 1 + + + + + I2S_MODE + Select I2S, left-justified or TDM: + +(Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE) + [9:8] + read-write + + + LEFT_JUSTIFIED + Left Justified + 0 + + + I2S + I2S mode + 1 + + + TDM_A + TDM mode A, the 1st Channel align to WSO +Rising Edge + 2 + + + TDM_B + TDM mode B, the 1st Channel align to WSO +Rising edge with1 SCK Delay + 3 + + + + + WS_PULSE + Set WS pulse width in TDM mode: + +(Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) +Note: When not TDM mode, must be '1'. + [10:10] + read-write + + + SCK_PERIOD + Pulse width is 1 SCK period + 0 + + + CH_LENGTH + Pulse width is 1 channel length + 1 + + + + + OVHDATA + Set overhead value: +'0': Set to '0' +'1': Set to '1' +(Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA) + [12:12] + read-write + + + WD_EN + Set watchdog for 'tx_ws_in': +'0': Disabled. +'1': Enabled. + [13:13] + read-write + + + CH_LEN + Channel length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- When TDM mode, must be 32-bit length to this field. +(Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN) + [18:16] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + WORD_LEN + Word length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- Don't configure this field as beyond Channel length. +(Note: These bits are connected to AR38U12.TX_CFG.TX_IWL) + [22:20] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + SCKO_POL + TX master bit clock polarity. +When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. +'0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge +'1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge + [24:24] + read-write + + + SCKI_POL + TX slave bit clock polarity. +When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details. + [25:25] + read-write + + + + + TX_WATCHDOG + Transmitter watchdog + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WD_COUNTER + Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. + [31:0] + read-write + + + + + RX_CTL + Receiver control + 0xA0 + 32 + read-write + 0x440510 + 0x3F727F8 + + + B_CLOCK_INV + Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. +When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'. + +1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge +2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1) +3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge +4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3) + +(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. +Note: When Slave mode, must be '0'. +(Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV) + [3:3] + read-write + + + RISING_EDGE_RX + SDI received at SCK rising edge when RX_CTL.SCKO_POL=0 + 0 + + + FALLING_EDGE_RX + SDI received at SCK falling edge when RX_CTL.SCKO_POL=0 + 1 + + + + + CH_NR + Specifies number of channels per frame: + +Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. +(Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET) + [6:4] + read-write + + + CH_NUM1 + 1 channel + 0 + + + CH_NUM2 + 2 channels + 1 + + + CH_NUM3 + 3 channels + 2 + + + CH_NUM4 + 4 channels + 3 + + + CH_NUM5 + 5 channels + 4 + + + CH_NUM6 + 6 channels + 5 + + + CH_NUM7 + 7 channels + 6 + + + CH_NUM8 + 8 channels + 7 + + + + + MS + Set interface in master or slave mode: + +(Note: This bit is connected to AR38U12.TX_CFG.RX_MS) + [7:7] + read-write + + + SLAVE + Slave + 0 + + + MASTER + Master + 1 + + + + + I2S_MODE + Select I2S, left-justified or TDM: + +(Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE) + [9:8] + read-write + + + LEFT_JUSTIFIED + Left Justified + 0 + + + I2S + I2S mode + 1 + + + TDM_A + TDM mode A, the 1st Channel align to WSO +Rising Edge + 2 + + + TDM_B + TDM mode B, the 1st Channel align to WSO +Rising edge with1 SCK Delay + 3 + + + + + WS_PULSE + Set WS pulse width in TDM mode: + +(Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) +Note: When not TDM mode, must be '1'. + [10:10] + read-write + + + SCK_PERIOD + Pulse width is 1 SCK period + 0 + + + CH_LENGTH + Pulse width is 1 channel length + 1 + + + + + WD_EN + Set watchdog for 'rx_ws_in' +'0': Disabled. +'1': Enabled. + [13:13] + read-write + + + CH_LEN + Channel length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- When TDM mode, must be 32-bit length to this field. +(Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN) + [18:16] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + WORD_LEN + Word length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- Don't configure this field as beyond Channel length. +(Note: These bits are connected to AR38U12.RX_CFG.RX_IWL) + [22:20] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + BIT_EXTENSION + When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. +'0': Extended by '0' +'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') + [23:23] + read-write + + + SCKO_POL + RX master bit clock polarity. +When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details. + [24:24] + read-write + + + SCKI_POL + RX slave bit clock polarity. +When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting. +'0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge +'1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge + [25:25] + read-write + + + + + RX_WATCHDOG + Receiver watchdog + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WD_COUNTER + Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. + [31:0] + read-write + + + + + TX_FIFO_CTL + TX FIFO control + 0x200 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. + [7:0] + read-write + + + CLEAR + When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes. + [17:17] + read-write + + + + + TX_FIFO_STATUS + TX FIFO status + 0x204 + 32 + read-only + 0x0 + 0xFFFF01FF + + + USED + Number of entries in the TX FIFO. The field value is in the range [0, 256]. + [8:0] + read-only + + + RD_PTR + TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes. + [31:24] + read-only + + + + + TX_FIFO_WR + TX FIFO write + 0x208 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA + Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. +Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'. + [31:0] + write-only + + + + + RX_FIFO_CTL + RX FIFO control + 0x300 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. +Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)]. + [7:0] + read-write + + + CLEAR + When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee. + [17:17] + read-write + + + + + RX_FIFO_STATUS + RX FIFO status + 0x304 + 32 + read-only + 0x0 + 0xFFFF01FF + + + USED + Number of entries in the RX FIFO. The field value is in the range [0, 256]. + [8:0] + read-only + + + RD_PTR + RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes. + [31:24] + read-only + + + + + RX_FIFO_RD + RX FIFO read + 0x308 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. +Notes: + - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. + - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + RX FIFO silent read + 0x30C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. +Notes: + - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. + - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. + [31:0] + read-only + + + + + INTR + Interrupt register + 0xF00 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL. + [0:0] + read-write + + + TX_NOT_FULL + TX FIFO is not full. + [1:1] + read-write + + + TX_EMPTY + TX FIFO is empty; i.e. it has 0 entries. + [4:4] + read-write + + + TX_OVERFLOW + Attempt to write to a full TX FIFO. + [5:5] + read-write + + + TX_UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'. + [6:6] + read-write + + + TX_WD + Triggers (sets to '1') when the Tx watchdog event occurs. + [8:8] + read-write + + + RX_TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL. + [16:16] + read-write + + + RX_NOT_EMPTY + RX FIFO is not empty. + [18:18] + read-write + + + RX_FULL + RX FIFO is full. + [19:19] + read-write + + + RX_OVERFLOW + Attempt to write to a full RX FIFO. + [21:21] + read-write + + + RX_UNDERFLOW + Attempt to read from an empty RX FIFO. + [22:22] + read-write + + + RX_WD + Triggers (sets to '1') when the Rx watchdog event occurs. + [24:24] + read-write + + + + + INTR_SET + Interrupt set register + 0xF04 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + TX_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + TX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + TX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + TX_WD + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + RX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FULL + Write with '1' to set corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [22:22] + read-write + + + RX_WD + Write with '1' to set corresponding bit in interrupt request register. + [24:24] + read-write + + + + + INTR_MASK + Interrupt mask register + 0xF08 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + TX_EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + TX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + TX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + TX_WD + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + RX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FULL + Mask bit for corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [22:22] + read-write + + + RX_WD + Mask bit for corresponding bit in interrupt request register. + [24:24] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0xF0C + 32 + read-only + 0x0 + 0x16D0173 + + + TX_TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TX_NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + TX_EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + TX_OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + TX_UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + TX_WD + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + RX_TRIGGER + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + RX_NOT_EMPTY + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + RX_FULL + Logical and of corresponding request and mask bits. + [19:19] + read-only + + + RX_OVERFLOW + Logical and of corresponding request and mask bits. + [21:21] + read-only + + + RX_UNDERFLOW + Logical and of corresponding request and mask bits. + [22:22] + read-only + + + RX_WD + Logical and of corresponding request and mask bits. + [24:24] + read-only + + + + + + + PDM0 + PDM registers + PDM + 0x42A20000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x20808 + 0x80030F0F + + + PGA_R + Right channel PGA gain: ++1.5dB/step, -12dB ~ +10.5dB +'0': -12 dB +'1': -10.5 dB +... +'15' +10.5 dB +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R) + [3:0] + read-write + + + PGA_L + Left channel PGA gain: ++1.5dB/step, -12dB ~ +10.5dB +'0': -12 dB +'1': -10.5 dB +... +'15': +10.5 dB +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L) + [11:8] + read-write + + + SOFT_MUTE + Soft mute function to mute the volume smoothly +'0': Disabled. +'1': Enabled. +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE) + [16:16] + read-write + + + STEP_SEL + Set fine gain step for smooth PGA or Soft-Mute attenuation transition. +'0': 0.13dB +'1': 0.26dB +(Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP) + [17:17] + read-write + + + ENABLED + Enables the PDM component: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CLOCK_CTL + Clock control + 0x10 + 32 + read-write + 0x200310 + 0x7F0F33 + + + CLK_CLOCK_DIV + PDM CLK (FPDM_CLK) (1st divider): +This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. + +Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider. + [1:0] + read-write + + + DIVBY1 + Divide by 1 + 0 + + + DIVBY2 + Divide by 2 (no 50 percent duty cycle) + 1 + + + DIVBY3 + Divide by 3 (no 50 percent duty cycle) + 2 + + + DIVBY4 + Divide by 4 (no 50 percent duty cycle) + 3 + + + + + MCLKQ_CLOCK_DIV + MCLKQ divider (2nd divider) + +(Note: These bits are connected to +AR36U12.PDM_CORE2_CFG.DIV_MCLKQ) + [5:4] + read-write + + + DIVBY1 + Divide by 1 + 0 + + + DIVBY2 + Divide by 2 (no 50 percent duty cycle) + 1 + + + DIVBY3 + Divide by 3 (no 50 percent duty cycle) + 2 + + + DIVBY4 + Divide by 4 (no 50 percent duty cycle) + 3 + + + + + CKO_CLOCK_DIV + PDM CKO (FPDM_CKO) clock divider (3rd divider): +FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1) + +Note: To configure '0' to this field is prohibited. +(Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. ) +(Note: These bits are connected to +AR36U12.PDM_CORE_CFG.MCLKDIV) + [11:8] + read-write + + + SINC_RATE + SINC Decimation Rate. For details, see the data sheet provided by Archband. +Oversampling Ratio = Decimation Rate = 2 X SINC_RATE +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE) + [22:16] + read-write + + + + + MODE_CTL + Mode control + 0x14 + 32 + read-write + 0x1B000103 + 0x1F070707 + + + PCM_CH_SET + Specifies PCM output channels as mono or stereo: + +(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET) + [1:0] + read-write + + + DISABLED + Channel disabled + 0 + + + MONO_L + Mono left channel enable + 1 + + + MONO_R + Mono right channel enable + 2 + + + STEREO + Stereo channel enable + 3 + + + + + SWAP_LR + Input data L/R channel swap: +'1': Right/Left channel recording swap +'0': No Swap +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP) + [2:2] + read-write + + + S_CYCLES + Set time step for gain change during PGA or soft mute operation in +number of 1/a sampling rate. +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES) + [10:8] + read-write + + + STEP_NUM64 + 64steps + 0 + + + STEP_NUM96 + 96steps + 1 + + + STEP_NUM128 + 128steps + 2 + + + STEP_NUM160 + 160steps + 3 + + + STEP_NUM192 + 192steps + 4 + + + STEP_NUM256 + 256steps + 5 + + + STEP_NUM384 + 384steps + 6 + + + STEP_NUM512 + 512steps + 7 + + + + + CKO_DELAY + Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock: + +(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY) + [18:16] + read-write + + + ADV3 + CLK_IS is 3*PDM_CLK period early + 0 + + + ADV2 + CLK_IS is 2*PDM_CLK period early + 1 + + + ADV1 + CLK_IS is 1*PDM_CLK period early + 2 + + + NO_DELAY + CLK_IS is the same as PDM_CKO + 3 + + + DLY1 + CLK_IS is 1*PDM_CLK period late + 4 + + + DLY2 + CLK_IS is 2*PDM_CLK period late + 5 + + + DLY3 + CLK_IS is 3*PDM_CLK period late + 6 + + + DLY4 + CLK_IS is 4*PDM_CLK period late + 7 + + + + + HPF_GAIN + Adjust high pass filter coefficients. +H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ] +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN) + [27:24] + read-write + + + HPF_EN_N + Enable high pass filter (active low) +'1': Disabled. +'0': Enabled. +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD) + [28:28] + read-write + + + + + DATA_CTL + Data control + 0x18 + 32 + read-write + 0x0 + 0x103 + + + WORD_LEN + PCM Word Length in number of bits: + +(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL) + [1:0] + read-write + + + BIT_LEN16 + 16-bit + 0 + + + BIT_LEN18 + 18-bit + 1 + + + BIT_LEN20 + 20-bit + 2 + + + BIT_LEN24 + 24-bit + 3 + + + + + BIT_EXTENSION + When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. +'0': Extended by '0' +'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') + [8:8] + read-write + + + + + CMD + Command + 0x20 + 32 + read-write + 0x0 + 0x1 + + + STREAM_EN + Enable data streaming flow: +'0': Disabled. +'1': Enabled. +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN) + [0:0] + read-write + + + + + TR_CTL + Trigger control + 0x40 + 32 + read-write + 0x0 + 0x10000 + + + RX_REQ_EN + Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + RX_FIFO_CTL + RX FIFO control + 0x300 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. +Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3'). + [7:0] + read-write + + + CLEAR + When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes. + [17:17] + read-write + + + + + RX_FIFO_STATUS + RX FIFO status + 0x304 + 32 + read-only + 0x0 + 0xFFFF00FF + + + USED + Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty. + [7:0] + read-only + + + RD_PTR + RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes. + [31:24] + read-only + + + + + RX_FIFO_RD + RX FIFO read + 0x308 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. +Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + RX FIFO silent read + 0x30C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. +Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. + [31:0] + read-only + + + + + INTR + Interrupt register + 0xF00 + 32 + read-write + 0x0 + 0x650000 + + + RX_TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL. + [16:16] + read-write + + + RX_NOT_EMPTY + RX FIFO is not empty. + [18:18] + read-write + + + RX_OVERFLOW + Attempt to write to a full RX FIFO + [21:21] + read-write + + + RX_UNDERFLOW + Attempt to read from an empty RX FIFO + [22:22] + read-write + + + + + INTR_SET + Interrupt set register + 0xF04 + 32 + read-write + 0x0 + 0x650000 + + + RX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [22:22] + read-write + + + + + INTR_MASK + Interrupt mask register + 0xF08 + 32 + read-write + 0x0 + 0x650000 + + + RX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [22:22] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0xF0C + 32 + read-only + 0x0 + 0x650000 + + + RX_TRIGGER + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + RX_NOT_EMPTY + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + RX_OVERFLOW + Logical and of corresponding request and mask bits. + [21:21] + read-only + + + RX_UNDERFLOW + Logical and of corresponding request and mask bits. + [22:22] + read-only + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_02.svd b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_02.svd new file mode 100644 index 0000000000..0a88c85fe6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_02.svd @@ -0,0 +1,43440 @@ + + + + Cypress Semiconductor + Cypress + psoc6_02 + PSoC6_02 + 1.0 + PSoC6_02 + Copyright 2016-2021 Cypress Semiconductor Corporation\n + SPDX-License-Identifier: Apache-2.0\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + CM4 + r0p1 + little + true + true + 1 + 3 + 0 + + 8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERI + Peripheral interconnect + 0x40000000 + + 0 + 65536 + registers + + + + TIMEOUT_CTL + Timeout control + 0x200 + 32 + read-write + 0xFFFF + 0xFFFF + + + TIMEOUT + This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). +'0x0000'-'0xfffe': Number of clock cycles. +'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. + [15:0] + read-write + + + + + TR_CMD + Trigger command + 0x220 + 32 + read-write + 0x0 + 0xE0001FFF + + + TR_SEL + Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. + [7:0] + read-write + + + GROUP_SEL + Specifies the trigger group: +'0'-'15': trigger multiplexer groups. +'16'-'31': trigger 1-to-1 groups. + [12:8] + read-write + + + TR_EDGE + Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. +'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. + [29:29] + read-write + + + OUT_SEL + Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. +'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. +'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. + +Note: this field is not used for trigger 1-to-1 groups. + [30:30] + read-write + + + ACTIVATE + SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. + +Note: when ACTIVATE is '1', SW should not modify the other register fields. + [31:31] + read-write + + + + + DIV_CMD + Divider command + 0x400 + 32 + read-write + 0x3FF03FF + 0xC3FF03FF + + + DIV_SEL + (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. + [7:0] + read-write + + + TYPE_SEL + Specifies the divider type of the divider on which the command is performed: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + PA_DIV_SEL + (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. + +If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. + [23:16] + read-write + + + PA_TYPE_SEL + Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [25:24] + read-write + + + DISABLE + Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. + +The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. + [30:30] + read-write + + + ENABLE + Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the DIV_CMD.DISABLE field. +1: Configure the divider's DIV_XXX_CTL register. +2: Enable the divider using the DIV_CMD_ENABLE field. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. + +The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. + +The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. + [31:31] + read-write + + + + + 256 + 4 + CLOCK_CTL[%s] + Clock control + 0xC00 + 32 + read-write + 0x3FF + 0x3FF + + + DIV_SEL + Specifies one of the dividers of the divider type specified by TYPE_SEL. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. + +When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. + [7:0] + read-write + + + TYPE_SEL + Specifies divider type: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + + + 256 + 4 + DIV_8_CTL[%s] + Divider control (for 8.0 divider) + 0x1000 + 32 + read-write + 0x0 + 0xFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT8_DIV + Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 256]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + 256 + 4 + DIV_16_CTL[%s] + Divider control (for 16.0 divider) + 0x1400 + 32 + read-write + 0x0 + 0xFFFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 256 + 4 + DIV_16_5_CTL[%s] + Divider control (for 16.5 divider) + 0x1800 + 32 + read-write + 0x0 + 0xFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. + +For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 255 + 4 + DIV_24_5_CTL[%s] + Divider control (for 24.5 divider) + 0x1C00 + 32 + read-write + 0x0 + 0xFFFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT24_DIV + Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. + +For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [31:8] + read-write + + + + + ECC_CTL + ECC control + 0x2000 + 32 + read-write + 0x10000 + 0xFF0507FF + + + WORD_ADDR + Specifies the word address where the parity is injected. +- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [10:0] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_INJ_EN + Enable error injection for PERI protection structure SRAM. +When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. + [18:18] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:24] + read-write + + + + + 11 + 32 + GR[%s] + Peripheral group structure + 0x00004000 + + CLOCK_CTL + Clock control + 0x0 + 32 + read-write + 0x0 + 0xFF00 + + + INT8_DIV + Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + SL_CTL + Slave control + 0x10 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ENABLED_0 + Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [0:0] + read-write + + + ENABLED_1 + Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [1:1] + read-write + + + ENABLED_2 + N/A + [2:2] + read-write + + + ENABLED_3 + N/A + [3:3] + read-write + + + ENABLED_4 + N/A + [4:4] + read-write + + + ENABLED_5 + N/A + [5:5] + read-write + + + ENABLED_6 + N/A + [6:6] + read-write + + + ENABLED_7 + N/A + [7:7] + read-write + + + ENABLED_8 + N/A + [8:8] + read-write + + + ENABLED_9 + N/A + [9:9] + read-write + + + ENABLED_10 + N/A + [10:10] + read-write + + + ENABLED_11 + N/A + [11:11] + read-write + + + ENABLED_12 + N/A + [12:12] + read-write + + + ENABLED_13 + N/A + [13:13] + read-write + + + ENABLED_14 + N/A + [14:14] + read-write + + + ENABLED_15 + N/A + [15:15] + read-write + + + DISABLED_0 + Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. + [16:16] + read-write + + + DISABLED_1 + N/A + [17:17] + read-write + + + DISABLED_2 + N/A + [18:18] + read-write + + + DISABLED_3 + N/A + [19:19] + read-write + + + DISABLED_4 + N/A + [20:20] + read-write + + + DISABLED_5 + N/A + [21:21] + read-write + + + DISABLED_6 + N/A + [22:22] + read-write + + + DISABLED_7 + N/A + [23:23] + read-write + + + DISABLED_8 + N/A + [24:24] + read-write + + + DISABLED_9 + N/A + [25:25] + read-write + + + DISABLED_10 + N/A + [26:26] + read-write + + + DISABLED_11 + N/A + [27:27] + read-write + + + DISABLED_12 + N/A + [28:28] + read-write + + + DISABLED_13 + N/A + [29:29] + read-write + + + DISABLED_14 + N/A + [30:30] + read-write + + + DISABLED_15 + N/A + [31:31] + read-write + + + + + + 10 + 1024 + TR_GR[%s] + Trigger group + 0x00008000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x13FF + + + TR_SEL + Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. + [7:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + 7 + 1024 + TR_1TO1_GR[%s] + Trigger 1-to-1 group + 0x0000C000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x1301 + + + TR_SEL + Specifies input trigger: +'0'': constant signal level '0'. +'1': input trigger. + [0:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + + + PERI_MS + Peripheral interconnect, master interface + 0x40010000 + + 0 + 65536 + registers + + + + 8 + 64 + PPU_PR[%s] + Programmable protection structure pair + 0x00000000 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-write + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-write + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + 230 + 64 + PPU_FX[%s] + Fixed protection structure pair + 0x00000800 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFC + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-only + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-only + 0x80000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-only + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-only + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + + + CPUSS + CPU subsystem (CPUSS) + 0x40200000 + + 0 + 65536 + registers + + + ioss_interrupts_gpio_0 + GPIO Port Interrupt #0 + 0 + + + ioss_interrupts_gpio_1 + GPIO Port Interrupt #1 + 1 + + + ioss_interrupts_gpio_2 + GPIO Port Interrupt #2 + 2 + + + ioss_interrupts_gpio_3 + GPIO Port Interrupt #3 + 3 + + + ioss_interrupts_gpio_4 + GPIO Port Interrupt #4 + 4 + + + ioss_interrupts_gpio_5 + GPIO Port Interrupt #5 + 5 + + + ioss_interrupts_gpio_6 + GPIO Port Interrupt #6 + 6 + + + ioss_interrupts_gpio_7 + GPIO Port Interrupt #7 + 7 + + + ioss_interrupts_gpio_8 + GPIO Port Interrupt #8 + 8 + + + ioss_interrupts_gpio_9 + GPIO Port Interrupt #9 + 9 + + + ioss_interrupts_gpio_10 + GPIO Port Interrupt #10 + 10 + + + ioss_interrupts_gpio_11 + GPIO Port Interrupt #11 + 11 + + + ioss_interrupts_gpio_12 + GPIO Port Interrupt #12 + 12 + + + ioss_interrupts_gpio_13 + GPIO Port Interrupt #13 + 13 + + + ioss_interrupts_gpio_14 + GPIO Port Interrupt #14 + 14 + + + ioss_interrupt_gpio + GPIO All Ports + 15 + + + ioss_interrupt_vdd + GPIO Supply Detect Interrupt + 16 + + + lpcomp_interrupt + Low Power Comparator Interrupt + 17 + + + scb_8_interrupt + Serial Communication Block #8 (DeepSleep capable) + 18 + + + srss_interrupt_mcwdt_0 + Multi Counter Watchdog Timer interrupt + 19 + + + srss_interrupt_mcwdt_1 + Multi Counter Watchdog Timer interrupt + 20 + + + srss_interrupt_backup + Backup domain interrupt + 21 + + + srss_interrupt + Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + 22 + + + cpuss_interrupts_ipc_0 + CPUSS Inter Process Communication Interrupt #0 + 23 + + + cpuss_interrupts_ipc_1 + CPUSS Inter Process Communication Interrupt #1 + 24 + + + cpuss_interrupts_ipc_2 + CPUSS Inter Process Communication Interrupt #2 + 25 + + + cpuss_interrupts_ipc_3 + CPUSS Inter Process Communication Interrupt #3 + 26 + + + cpuss_interrupts_ipc_4 + CPUSS Inter Process Communication Interrupt #4 + 27 + + + cpuss_interrupts_ipc_5 + CPUSS Inter Process Communication Interrupt #5 + 28 + + + cpuss_interrupts_ipc_6 + CPUSS Inter Process Communication Interrupt #6 + 29 + + + cpuss_interrupts_ipc_7 + CPUSS Inter Process Communication Interrupt #7 + 30 + + + cpuss_interrupts_ipc_8 + CPUSS Inter Process Communication Interrupt #8 + 31 + + + cpuss_interrupts_ipc_9 + CPUSS Inter Process Communication Interrupt #9 + 32 + + + cpuss_interrupts_ipc_10 + CPUSS Inter Process Communication Interrupt #10 + 33 + + + cpuss_interrupts_ipc_11 + CPUSS Inter Process Communication Interrupt #11 + 34 + + + cpuss_interrupts_ipc_12 + CPUSS Inter Process Communication Interrupt #12 + 35 + + + cpuss_interrupts_ipc_13 + CPUSS Inter Process Communication Interrupt #13 + 36 + + + cpuss_interrupts_ipc_14 + CPUSS Inter Process Communication Interrupt #14 + 37 + + + cpuss_interrupts_ipc_15 + CPUSS Inter Process Communication Interrupt #15 + 38 + + + scb_0_interrupt + Serial Communication Block #0 + 39 + + + scb_1_interrupt + Serial Communication Block #1 + 40 + + + scb_2_interrupt + Serial Communication Block #2 + 41 + + + scb_3_interrupt + Serial Communication Block #3 + 42 + + + scb_4_interrupt + Serial Communication Block #4 + 43 + + + scb_5_interrupt + Serial Communication Block #5 + 44 + + + scb_6_interrupt + Serial Communication Block #6 + 45 + + + scb_7_interrupt + Serial Communication Block #7 + 46 + + + scb_9_interrupt + Serial Communication Block #9 + 47 + + + scb_10_interrupt + Serial Communication Block #10 + 48 + + + scb_11_interrupt + Serial Communication Block #11 + 49 + + + scb_12_interrupt + Serial Communication Block #12 + 50 + + + csd_interrupt + CSD (Capsense) interrupt + 51 + + + cpuss_interrupts_dmac_0 + CPUSS DMAC, Channel #0 + 52 + + + cpuss_interrupts_dmac_1 + CPUSS DMAC, Channel #1 + 53 + + + cpuss_interrupts_dmac_2 + CPUSS DMAC, Channel #2 + 54 + + + cpuss_interrupts_dmac_3 + CPUSS DMAC, Channel #3 + 55 + + + cpuss_interrupts_dw0_0 + CPUSS DataWire #0, Channel #0 + 56 + + + cpuss_interrupts_dw0_1 + CPUSS DataWire #0, Channel #1 + 57 + + + cpuss_interrupts_dw0_2 + CPUSS DataWire #0, Channel #2 + 58 + + + cpuss_interrupts_dw0_3 + CPUSS DataWire #0, Channel #3 + 59 + + + cpuss_interrupts_dw0_4 + CPUSS DataWire #0, Channel #4 + 60 + + + cpuss_interrupts_dw0_5 + CPUSS DataWire #0, Channel #5 + 61 + + + cpuss_interrupts_dw0_6 + CPUSS DataWire #0, Channel #6 + 62 + + + cpuss_interrupts_dw0_7 + CPUSS DataWire #0, Channel #7 + 63 + + + cpuss_interrupts_dw0_8 + CPUSS DataWire #0, Channel #8 + 64 + + + cpuss_interrupts_dw0_9 + CPUSS DataWire #0, Channel #9 + 65 + + + cpuss_interrupts_dw0_10 + CPUSS DataWire #0, Channel #10 + 66 + + + cpuss_interrupts_dw0_11 + CPUSS DataWire #0, Channel #11 + 67 + + + cpuss_interrupts_dw0_12 + CPUSS DataWire #0, Channel #12 + 68 + + + cpuss_interrupts_dw0_13 + CPUSS DataWire #0, Channel #13 + 69 + + + cpuss_interrupts_dw0_14 + CPUSS DataWire #0, Channel #14 + 70 + + + cpuss_interrupts_dw0_15 + CPUSS DataWire #0, Channel #15 + 71 + + + cpuss_interrupts_dw0_16 + CPUSS DataWire #0, Channel #16 + 72 + + + cpuss_interrupts_dw0_17 + CPUSS DataWire #0, Channel #17 + 73 + + + cpuss_interrupts_dw0_18 + CPUSS DataWire #0, Channel #18 + 74 + + + cpuss_interrupts_dw0_19 + CPUSS DataWire #0, Channel #19 + 75 + + + cpuss_interrupts_dw0_20 + CPUSS DataWire #0, Channel #20 + 76 + + + cpuss_interrupts_dw0_21 + CPUSS DataWire #0, Channel #21 + 77 + + + cpuss_interrupts_dw0_22 + CPUSS DataWire #0, Channel #22 + 78 + + + cpuss_interrupts_dw0_23 + CPUSS DataWire #0, Channel #23 + 79 + + + cpuss_interrupts_dw0_24 + CPUSS DataWire #0, Channel #24 + 80 + + + cpuss_interrupts_dw0_25 + CPUSS DataWire #0, Channel #25 + 81 + + + cpuss_interrupts_dw0_26 + CPUSS DataWire #0, Channel #26 + 82 + + + cpuss_interrupts_dw0_27 + CPUSS DataWire #0, Channel #27 + 83 + + + cpuss_interrupts_dw0_28 + CPUSS DataWire #0, Channel #28 + 84 + + + cpuss_interrupts_dw1_0 + CPUSS DataWire #1, Channel #0 + 85 + + + cpuss_interrupts_dw1_1 + CPUSS DataWire #1, Channel #1 + 86 + + + cpuss_interrupts_dw1_2 + CPUSS DataWire #1, Channel #2 + 87 + + + cpuss_interrupts_dw1_3 + CPUSS DataWire #1, Channel #3 + 88 + + + cpuss_interrupts_dw1_4 + CPUSS DataWire #1, Channel #4 + 89 + + + cpuss_interrupts_dw1_5 + CPUSS DataWire #1, Channel #5 + 90 + + + cpuss_interrupts_dw1_6 + CPUSS DataWire #1, Channel #6 + 91 + + + cpuss_interrupts_dw1_7 + CPUSS DataWire #1, Channel #7 + 92 + + + cpuss_interrupts_dw1_8 + CPUSS DataWire #1, Channel #8 + 93 + + + cpuss_interrupts_dw1_9 + CPUSS DataWire #1, Channel #9 + 94 + + + cpuss_interrupts_dw1_10 + CPUSS DataWire #1, Channel #10 + 95 + + + cpuss_interrupts_dw1_11 + CPUSS DataWire #1, Channel #11 + 96 + + + cpuss_interrupts_dw1_12 + CPUSS DataWire #1, Channel #12 + 97 + + + cpuss_interrupts_dw1_13 + CPUSS DataWire #1, Channel #13 + 98 + + + cpuss_interrupts_dw1_14 + CPUSS DataWire #1, Channel #14 + 99 + + + cpuss_interrupts_dw1_15 + CPUSS DataWire #1, Channel #15 + 100 + + + cpuss_interrupts_dw1_16 + CPUSS DataWire #1, Channel #16 + 101 + + + cpuss_interrupts_dw1_17 + CPUSS DataWire #1, Channel #17 + 102 + + + cpuss_interrupts_dw1_18 + CPUSS DataWire #1, Channel #18 + 103 + + + cpuss_interrupts_dw1_19 + CPUSS DataWire #1, Channel #19 + 104 + + + cpuss_interrupts_dw1_20 + CPUSS DataWire #1, Channel #20 + 105 + + + cpuss_interrupts_dw1_21 + CPUSS DataWire #1, Channel #21 + 106 + + + cpuss_interrupts_dw1_22 + CPUSS DataWire #1, Channel #22 + 107 + + + cpuss_interrupts_dw1_23 + CPUSS DataWire #1, Channel #23 + 108 + + + cpuss_interrupts_dw1_24 + CPUSS DataWire #1, Channel #24 + 109 + + + cpuss_interrupts_dw1_25 + CPUSS DataWire #1, Channel #25 + 110 + + + cpuss_interrupts_dw1_26 + CPUSS DataWire #1, Channel #26 + 111 + + + cpuss_interrupts_dw1_27 + CPUSS DataWire #1, Channel #27 + 112 + + + cpuss_interrupts_dw1_28 + CPUSS DataWire #1, Channel #28 + 113 + + + cpuss_interrupts_fault_0 + CPUSS Fault Structure Interrupt #0 + 114 + + + cpuss_interrupts_fault_1 + CPUSS Fault Structure Interrupt #1 + 115 + + + cpuss_interrupt_crypto + CRYPTO Accelerator Interrupt + 116 + + + cpuss_interrupt_fm + FLASH Macro Interrupt + 117 + + + cpuss_interrupts_cm4_fp + Floating Point operation fault + 118 + + + cpuss_interrupts_cm0_cti_0 + CM0+ CTI #0 + 119 + + + cpuss_interrupts_cm0_cti_1 + CM0+ CTI #1 + 120 + + + cpuss_interrupts_cm4_cti_0 + CM4 CTI #0 + 121 + + + cpuss_interrupts_cm4_cti_1 + CM4 CTI #1 + 122 + + + tcpwm_0_interrupts_0 + TCPWM #0, Counter #0 + 123 + + + tcpwm_0_interrupts_1 + TCPWM #0, Counter #1 + 124 + + + tcpwm_0_interrupts_2 + TCPWM #0, Counter #2 + 125 + + + tcpwm_0_interrupts_3 + TCPWM #0, Counter #3 + 126 + + + tcpwm_0_interrupts_4 + TCPWM #0, Counter #4 + 127 + + + tcpwm_0_interrupts_5 + TCPWM #0, Counter #5 + 128 + + + tcpwm_0_interrupts_6 + TCPWM #0, Counter #6 + 129 + + + tcpwm_0_interrupts_7 + TCPWM #0, Counter #7 + 130 + + + tcpwm_1_interrupts_0 + TCPWM #1, Counter #0 + 131 + + + tcpwm_1_interrupts_1 + TCPWM #1, Counter #1 + 132 + + + tcpwm_1_interrupts_2 + TCPWM #1, Counter #2 + 133 + + + tcpwm_1_interrupts_3 + TCPWM #1, Counter #3 + 134 + + + tcpwm_1_interrupts_4 + TCPWM #1, Counter #4 + 135 + + + tcpwm_1_interrupts_5 + TCPWM #1, Counter #5 + 136 + + + tcpwm_1_interrupts_6 + TCPWM #1, Counter #6 + 137 + + + tcpwm_1_interrupts_7 + TCPWM #1, Counter #7 + 138 + + + tcpwm_1_interrupts_8 + TCPWM #1, Counter #8 + 139 + + + tcpwm_1_interrupts_9 + TCPWM #1, Counter #9 + 140 + + + tcpwm_1_interrupts_10 + TCPWM #1, Counter #10 + 141 + + + tcpwm_1_interrupts_11 + TCPWM #1, Counter #11 + 142 + + + tcpwm_1_interrupts_12 + TCPWM #1, Counter #12 + 143 + + + tcpwm_1_interrupts_13 + TCPWM #1, Counter #13 + 144 + + + tcpwm_1_interrupts_14 + TCPWM #1, Counter #14 + 145 + + + tcpwm_1_interrupts_15 + TCPWM #1, Counter #15 + 146 + + + tcpwm_1_interrupts_16 + TCPWM #1, Counter #16 + 147 + + + tcpwm_1_interrupts_17 + TCPWM #1, Counter #17 + 148 + + + tcpwm_1_interrupts_18 + TCPWM #1, Counter #18 + 149 + + + tcpwm_1_interrupts_19 + TCPWM #1, Counter #19 + 150 + + + tcpwm_1_interrupts_20 + TCPWM #1, Counter #20 + 151 + + + tcpwm_1_interrupts_21 + TCPWM #1, Counter #21 + 152 + + + tcpwm_1_interrupts_22 + TCPWM #1, Counter #22 + 153 + + + tcpwm_1_interrupts_23 + TCPWM #1, Counter #23 + 154 + + + pass_interrupt_sar + SAR ADC interrupt + 155 + + + audioss_0_interrupt_i2s + I2S0 Audio interrupt + 156 + + + audioss_0_interrupt_pdm + PDM0/PCM0 Audio interrupt + 157 + + + audioss_1_interrupt_i2s + I2S1 Audio interrupt + 158 + + + profile_interrupt + Energy Profiler interrupt + 159 + + + smif_interrupt + Serial Memory Interface interrupt + 160 + + + usb_interrupt_hi + USB Interrupt + 161 + + + usb_interrupt_med + USB Interrupt + 162 + + + usb_interrupt_lo + USB Interrupt + 163 + + + sdhc_0_interrupt_wakeup + SDIO wakeup interrupt for mxsdhc + 164 + + + sdhc_0_interrupt_general + Consolidated interrupt for mxsdhc for everything else + 165 + + + sdhc_1_interrupt_wakeup + EEMC wakeup interrupt for mxsdhc, not used + 166 + + + sdhc_1_interrupt_general + Consolidated interrupt for mxsdhc for everything else + 167 + + + + IDENTITY + Identity + 0x0 + 32 + read-only + 0x0 + 0x0 + + + P + This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. + [0:0] + read-only + + + NS + This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. + [1:1] + read-only + + + PC + This field specifies the protection context of the transfer that reads the register. + [7:4] + read-only + + + MS + This field specifies the bus master identifier of the transfer that reads the register. + [11:8] + read-only + + + + + CM4_STATUS + CM4 status + 0x4 + 32 + read-only + 0x13 + 0x13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + + + CM4_CLOCK_CTL + CM4 clock control + 0x8 + 32 + read-write + 0x0 + 0xFF00 + + + FAST_INT_DIV + Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM4_CTL + CM4 control + 0xC + 32 + read-write + 0x0 + 0x9F000000 + + + IOC_MASK + CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. + +Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. + +Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. + [24:24] + read-write + + + DZC_MASK + CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [25:25] + read-write + + + OFC_MASK + CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [26:26] + read-write + + + UFC_MASK + CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [27:27] + read-write + + + IXC_MASK + CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. + [28:28] + read-write + + + IDC_MASK + CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. + [31:31] + read-write + + + + + CM4_INT0_STATUS + CM4 interrupt 0 status + 0x100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 0. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT1_STATUS + CM4 interrupt 1 status + 0x104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT2_STATUS + CM4 interrupt 2 status + 0x108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT3_STATUS + CM4 interrupt 3 status + 0x10C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT4_STATUS + CM4 interrupt 4 status + 0x110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT5_STATUS + CM4 interrupt 5 status + 0x114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT6_STATUS + CM4 interrupt 6 status + 0x118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT7_STATUS + CM4 interrupt 7 status + 0x11C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_VECTOR_TABLE_BASE + CM4 vector table base + 0x200 + 32 + read-write + 0x0 + 0xFFFFFC00 + + + ADDR22 + Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. + +Note: the CM4 vector table is at an address that is a 1024 B multiple. + [31:10] + read-write + + + + + 4 + 4 + CM4_NMI_CTL[%s] + CM4 NMI control + 0x240 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + UDB_PWR_CTL + UDB power control + 0x300 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for UDBs + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RESET + See CM4_PWR_CTL + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + UDB_PWR_DELAY_CTL + UDB power control + 0x304 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CTL + CM0+ control + 0x1000 + 32 + read-write + 0xFA050002 + 0xFFFF0003 + + + SLV_STALL + Processor debug access control: +'0': Access. +'1': Stall access. + +This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. + [0:0] + read-write + + + ENABLED + Processor enable: +'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. +'1': Enabled. +Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). + +Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). + [1:1] + read-write + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_STATUS + CM0+ status + 0x1004 + 32 + read-only + 0x0 + 0x3 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + + + CM0_CLOCK_CTL + CM0+ clock control + 0x1008 + 32 + read-write + 0x0 + 0xFF00FF00 + + + SLOW_INT_DIV + Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + PERI_INT_DIV + Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + +Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. + [31:24] + read-write + + + + + CM0_INT0_STATUS + CM0+ interrupt 0 status + 0x1100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 0. + +Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). + +The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. + [9:0] + read-only + + + SYSTEM_INT_VALID + Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. + [31:31] + read-only + + + + + CM0_INT1_STATUS + CM0+ interrupt 1 status + 0x1104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT2_STATUS + CM0+ interrupt 2 status + 0x1108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT3_STATUS + CM0+ interrupt 3 status + 0x110C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT4_STATUS + CM0+ interrupt 4 status + 0x1110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT5_STATUS + CM0+ interrupt 5 status + 0x1114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT6_STATUS + CM0+ interrupt 6 status + 0x1118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT7_STATUS + CM0+ interrupt 7 status + 0x111C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_VECTOR_TABLE_BASE + CM0+ vector table base + 0x1120 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. + +Note: the CM0+ vector table is at an address that is a 256 B multiple. + [31:8] + read-write + + + + + 4 + 4 + CM0_NMI_CTL[%s] + CM0+ NMI control + 0x1140 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + CM4_PWR_CTL + CM4 power control + 0x1200 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Switch CM4 off +Power off, clock off, isolate, reset and no retain. + 0 + + + RESET + Reset CM4 +Clock off, no isolated, no retain and reset. + +Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. + 1 + + + RETAINED + Put CM4 in Retained mode +This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. +Power off, clock off, isolate, no reset and retain. + 2 + + + ENABLED + Switch CM4 on. +Power on, clock on, no isolate, no reset and no retain. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM4_PWR_DELAY_CTL + CM4 power control + 0x1204 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + RAM0_CTL0 + RAM 0 control + 0x1300 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_AUTO_CORRECT + HW ECC autocorrect functionality: +'0': Disabled. +'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. + [17:17] + read-write + + + ECC_INJ_EN + Enable error injection for system SRAM 0. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. + [18:18] + read-write + + + + + RAM0_STATUS + RAM 0 status + 0x1304 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. +'0': Write buffer NOT empty. +'1': Write buffer empty. + +Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). + [0:0] + read-only + + + + + 16 + 4 + RAM0_PWR_MACRO_CTL[%s] + RAM 0 power control + 0x1340 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + SRAM Power mode. + [1:0] + read-write + + + OFF + Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. + 0 + + + RSVD + undefined + 1 + + + RETAINED + Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. +The SRAM contents will be retained in DeepSleep system power mode. + 2 + + + ENABLED + Enable SRAM for regular operation. +The SRAM contents will be retained in DeepSleep system power mode. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + RAM1_CTL0 + RAM 1 control + 0x1380 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM1_STATUS + RAM 1 status + 0x1384 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM1_PWR_CTL + RAM 1 power control + 0x1388 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM2_CTL0 + RAM 2 control + 0x13A0 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM2_STATUS + RAM 2 status + 0x13A4 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM2_PWR_CTL + RAM 2 power control + 0x13A8 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM_PWR_DELAY_CTL + Power up delay used for all SRAM power domains + 0x13C0 + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles (clk_slow) delay needed after power domain power up + [9:0] + read-write + + + + + ROM_CTL + ROM control + 0x13C4 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + +Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. +ROM_CTL.SLOW_WS = '0' when clk_hf <=100 MHz. +ROM_CTL.SLOW_WS = '1' when 100MHz < clk_hf <=clk_hf_max. +Note: clk_hf_max depends on the target device. Refer datasheet. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. +ROM_CTL.FAST_WS = '0' when clk_hf <= clk_hf_max. + [9:8] + read-write + + + + + ECC_CTL + ECC control + 0x13C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. +This field needs to be written with the offset address within the memory, divided by 4. +For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. + [24:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + PRODUCT_ID + Product identifier and version (same as CoreSight RomTables) + 0x1400 + 32 + read-only + 0x0 + 0xFFF + + + FAMILY_ID + Family ID. Common ID for a product family. + [11:0] + read-only + + + MAJOR_REV + Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) + [19:16] + read-only + + + MINOR_REV + Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) + [23:20] + read-only + + + + + DP_STATUS + Debug port status + 0x1410 + 32 + read-only + 0x4 + 0x7 + + + SWJ_CONNECTED + Specifies if the SWJ debug port is connected; i.e. debug host interface is active: +'0': Not connected/not active. +'1': Connected/active. + [0:0] + read-only + + + SWJ_DEBUG_EN + Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: +'0': Disabled. +'1': Enabled. + [1:1] + read-only + + + SWJ_JTAG_SEL + Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). +'0': SWD selected. +'1': JTAG selected. + [2:2] + read-only + + + + + AP_CTL + Access port control + 0x1414 + 32 + read-write + 0x0 + 0x70007 + + + CM0_ENABLE + Enables the CM0 AP interface: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + CM4_ENABLE + Enables the CM4 AP interface: +'0': Disabled. +'1': Enabled. + [1:1] + read-write + + + SYS_ENABLE + Enables the system AP interface: +'0': Disabled. +'1': Enabled. + [2:2] + read-write + + + CM0_DISABLE + Disables the CM0 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. + [16:16] + read-write + + + CM4_DISABLE + Disables the CM4 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. + [17:17] + read-write + + + SYS_DISABLE + Disables the system AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. + [18:18] + read-write + + + + + BUFF_CTL + Buffer control + 0x1500 + 32 + read-write + 0x1 + 0x1 + + + WRITE_BUFF + Specifies if write transfer can be buffered in the bus infrastructure bridges: +'0': Write transfers are not buffered, independent of the transfer's bufferable attribute. +'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. + [0:0] + read-write + + + + + SYSTICK_CTL + SysTick timer control + 0x1600 + 32 + read-write + 0x40000147 + 0xC3FFFFFF + + + TENMS + Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. + [23:0] + read-write + + + CLOCK_SOURCE + Specifies an external clock source: +'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). +'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. +o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. +'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). + +Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. +Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. + [25:24] + read-write + + + SKEW + Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: +'0': Precise. +'1': Imprecise. + [30:30] + read-write + + + NOREF + Specifies if an external clock source is provided: +'0': An external clock source is provided. +'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. + [31:31] + read-write + + + + + MBIST_STAT + Memory BIST status + 0x1704 + 32 + read-only + 0x0 + 0x3 + + + SFP_READY + Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. + [0:0] + read-only + + + SFP_FAIL + Report status of the BIST run, only valid if SFP_READY=1 + [1:1] + read-only + + + + + CAL_SUP_SET + Calibration support set and read + 0x1800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read without side effect, write 1 to set + [31:0] + read-write + + + + + CAL_SUP_CLR + Calibration support clear and reset + 0x1804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read side effect: when read all bits are cleared, write 1 to clear a specific bit +Note: no exception for the debug host, it also causes the read side effect + [31:0] + read-write + + + + + CM0_PC_CTL + CM0+ protection context control + 0x2000 + 32 + read-write + 0x0 + 0xF + + + VALID + Valid fields for the protection context handler CM0_PCi_HANDLER registers: +Bit 0: Valid field for CM0_PC0_HANDLER. +Bit 1: Valid field for CM0_PC1_HANDLER. +Bit 2: Valid field for CM0_PC2_HANDLER. +Bit 3: Valid field for CM0_PC3_HANDLER. + [3:0] + read-write + + + + + CM0_PC0_HANDLER + CM0+ protection context 0 handler + 0x2040 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. + [31:0] + read-write + + + + + CM0_PC1_HANDLER + CM0+ protection context 1 handler + 0x2044 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 1 handler. + [31:0] + read-write + + + + + CM0_PC2_HANDLER + CM0+ protection context 2 handler + 0x2048 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 2 handler. + [31:0] + read-write + + + + + CM0_PC3_HANDLER + CM0+ protection context 3 handler + 0x204C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 3 handler. + [31:0] + read-write + + + + + PROTECTION + Protection status + 0x20C4 + 32 + read-write + 0x0 + 0x7 + + + STATE + Protection state: +'0': UNKNOWN. +'1': VIRGIN. +'2': NORMAL. +'3': SECURE. +'4': DEAD. + +The following state transitions are allowed (and enforced by HW): +- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD +- NORMAL => DEAD +- SECURE => DEAD +An attempt to make a NOT allowed state transition will NOT affect this register field. + [2:0] + read-write + + + + + TRIM_ROM_CTL + ROM trim control + 0x2100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + TRIM_RAM_CTL + RAM trim control + 0x2104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + 1023 + 4 + CM0_SYSTEM_INT_CTL[%s] + CM0+ system interrupt control + 0x8000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. + +Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. + [2:0] + read-write + + + CPU_INT_VALID + Interrupt enable: +'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. +'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. + +Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. + [31:31] + read-write + + + + + 1023 + 4 + CM4_SYSTEM_INT_CTL[%s] + CM4 system interrupt control + 0xA000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + N/A + [2:0] + read-write + + + CPU_INT_VALID + N/A + [31:31] + read-write + + + + + + + FAULT + Fault structures + 0x40210000 + + 0 + 65536 + registers + + + + 2 + 256 + STRUCT[%s] + Fault structure + 0x00000000 + + CTL + Fault control + 0x0 + 32 + read-write + 0x0 + 0x7 + + + TR_EN + Trigger output enable: +'0': Disabled. The trigger output 'tr_fault' is '0'. +'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). + [0:0] + read-write + + + OUT_EN + IO output signal enable: +'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. +'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. + [1:1] + read-write + + + RESET_REQ_EN + Reset request enable: +'0': Disabled. +'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). + +The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. + [2:2] + read-write + + + + + STATUS + Fault status + 0xC + 32 + read-write + 0x0 + 0x80000000 + + + IDX + The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. + +Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. + [6:0] + read-write + + + VALID + Valid indication: +'0': Invalid. +'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. + +Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. + +An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: +- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. + +Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) + [31:31] + read-write + + + + + 4 + 4 + DATA[%s] + Fault data + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + Captured fault source data. + +Note: the DATA registers can only be written when STATUS.VALID is '0'. + +Note: the fault source index STATUS.IDX specifies the format of the DATA registers. + [31:0] + read-write + + + + + PENDING0 + Fault pending 0 + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: CM0 MPU. +Bit 1: CRYPTO MPU. +Bit 2: DW 0 MPU. +Bit 3: DW 1 MPU. +Bit 4: DMA controller MPU. +... +Bit 15: DAP MPU. +Bit 16: CM4 system bus MPU. +Bit 17: CM4 code bus MPU (for non FLASH controller accesses). +Bit 18: CM4 code bus MPU (for FLASH controller accesses). + [31:0] + read-only + + + + + PENDING1 + Fault pending 1 + 0x44 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: Peripheral group 0 PPU. +Bit 1: Peripheral group 1 PPU. +Bit 2: Peripheral group 2 PPU. +Bit 3: Peripheral group 3 PPU. +Bit 4: Peripheral group 4 PPU. +Bit 5: Peripheral group 5 PPU. +Bit 6: Peripheral group 6 PPU. +Bit 7: Peripheral group 7 PPU. +... +Bit 15: Peripheral group 15 PPU. + +Bit 16 - 31: See STATUS register. + [31:0] + read-only + + + + + PENDING2 + Fault pending 2 + 0x48 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0 - 31: See STATUS register. + [31:0] + read-only + + + + + MASK0 + Fault mask 0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 31 to 0. + [31:0] + read-write + + + + + MASK1 + Fault mask 1 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 63 to 32. + [31:0] + read-write + + + + + MASK2 + Fault mask 2 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 95 to 64. + [31:0] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1 + + + FAULT + This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: +- STATUS.VALID is set to '1'. +- STATUS.IDX specifies the fault source index. +- DATA0 through DATA3 captures the fault source data. + +SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1 + + + FAULT + SW writes a '1' to this field to set the corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1 + + + FAULT + Mask bit for corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1 + + + FAULT + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + IPC + IPC + 0x40220000 + + 0 + 65536 + registers + + + + 16 + 32 + STRUCT[%s] + IPC structure + 0x00000000 + + ACQUIRE + IPC acquire + 0x0 + 32 + read-only + 0x0 + 0x80000000 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the access that successfully acquired the lock. + [0:0] + read-only + + + NS + Secure/non-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the access that successfully acquired the lock. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + SUCCESS + Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): +'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. +'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. + +Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). + [31:31] + read-only + + + + + RELEASE + IPC release + 0x4 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_RELEASE + Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. + +SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + NOTIFY + IPC notification + 0x8 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_NOTIFY + This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. + +SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + DATA0 + IPC data 0 + 0xC + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + DATA1 + IPC data 1 + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + LOCK_STATUS + IPC lock status + 0x1C + 32 + read-only + 0x0 + 0x80000000 + + + P + This field specifies the user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + This field specifies the secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + ACQUIRED + Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. + [31:31] + read-only + + + + + + 16 + 32 + INTR_STRUCT[%s] + IPC interrupt structure + 0x00001000 + + INTR + Interrupt + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [15:0] + read-write + + + NOTIFY + These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [31:16] + read-write + + + + + INTR_SET + Interrupt set + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + SW writes a '1' to this field to set the corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASK + Interrupt mask + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + Mask bit for corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RELEASE + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + NOTIFY + Logical and of corresponding INTR and INTR_MASK fields. + [31:16] + read-only + + + + + + + + PROT + Protection + 0x40230000 + + 0 + 65536 + registers + + + + SMPU + SMPU + 0x00000000 + + MS0_CTL + Master 0 protection context control + 0x0 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + Privileged setting ('0': user mode; '1': privileged mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. +The default/reset field value provides privileged mode access capabilities. + [0:0] + read-write + + + NS + Security setting ('0': secure mode; '1': non-secure mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. +Note that the default/reset field value provides non-secure mode access capabilities to all masters. + [1:1] + read-write + + + PRIO + Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). + +Notes: +The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). +The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). +Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. + [9:8] + read-write + + + PC_MASK_0 + Protection context mask for protection context '0'. This field is a constant '0': +- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. + [16:16] + read-only + + + PC_MASK_15_TO_1 + Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': +- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. +- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. + +Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). + [31:17] + read-write + + + + + MS1_CTL + Master 1 protection context control + 0x4 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS2_CTL + Master 2 protection context control + 0x8 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS3_CTL + Master 3 protection context control + 0xC + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS4_CTL + Master 4 protection context control + 0x10 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS5_CTL + Master 5 protection context control + 0x14 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS6_CTL + Master 6 protection context control + 0x18 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS7_CTL + Master 7 protection context control + 0x1C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS8_CTL + Master 8 protection context control + 0x20 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS9_CTL + Master 9 protection context control + 0x24 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS10_CTL + Master 10 protection context control + 0x28 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS11_CTL + Master 11 protection context control + 0x2C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS12_CTL + Master 12 protection context control + 0x30 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS13_CTL + Master 13 protection context control + 0x34 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS14_CTL + Master 14 protection context control + 0x38 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS15_CTL + Master 15 protection context control + 0x3C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + 16 + 64 + SMPU_STRUCT[%s] + SMPU structure + 0x00002000 + + ADDR0 + SMPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + SMPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x100 + 0x80000100 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + SMPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + SMPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'7': 256 B region (8 32 B subregions) + +Note: this field is read-only. + [28:24] + read-only + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + [31:31] + read-write + + + + + + + 16 + 1024 + MPU[%s] + MPU + 0x00004000 + + MS_CTL + Master control + 0x0 + 32 + read-write + 0x0 + 0xF000F + + + PC + Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). + +The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: +* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: + IF (the new PC is the same as MS_CTL.PC) + PC is not affected; PC_SAVED is not affected. + ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) + An AHB-Lite bus error is generated for the exception handler fetch; + PC is not affected; PC_SAVED is not affected. + ELSE + PC = 'new PC'; PC_SAVED = PC (push operation). +* On entry of any other exception/interrupt handler: + PC = PC_SAVED; PC_SAVED is not affected (pop operation). + +Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. + +Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. + [3:0] + read-write + + + PC_SAVED + Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. + +Note: this field is ONLY used by the CM0+. + [19:16] + read-write + + + + + 127 + 4 + MS_CTL_READ_MIR[%s] + Master control read mirror + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + PC + Read-only mirror of MS_CTL.PC + [3:0] + read-only + + + PC_SAVED + Read-only mirror of MS_CTL.PC_SAVED + [19:16] + read-only + + + + + 8 + 32 + MPU_STRUCT[%s] + MPU structure + 0x00000200 + + ADDR + MPU region address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT + MPU region attrributes + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + + + + + FLASHC + Flash controller + 0x40240000 + + 0 + 65536 + registers + + + + FLASH_CTL + Control + 0x0 + 32 + read-write + 0x110000 + 0x77330F + + + MAIN_WS + FLASH macro main interface wait states: +'0': 0 wait states. +... +'15': 15 wait states + [3:0] + read-write + + + MAIN_MAP + Specifies mapping of FLASH macro main array. +0: Mapping A. +1: Mapping B. + +This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). + [8:8] + read-write + + + WORK_MAP + Specifies mapping of FLASH macro work array. +0: Mapping A. +1: Mapping B. + +This field is only used when WORK_BANK_MODE is '1' (dual bank mode). + [9:9] + read-write + + + MAIN_BANK_MODE + Specifies bank mode of FLASH macro main array. +0: Single bank mode. +1: Dual bank mode. + [12:12] + read-write + + + WORK_BANK_MODE + Specifies bank mode of FLASH macro work array. +0: Single bank mode. +1: Dual bank mode. + [13:13] + read-write + + + MAIN_ECC_EN + Enable ECC checking for FLASH main interface: +0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [16:16] + read-write + + + MAIN_ECC_INJ_EN + Enable error injection for FLASH main interface. +When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [17:17] + read-write + + + MAIN_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro main interface internal error. +- FLASH macro main interface non-recoverable ECC error. +- FLASH macro main interface recoverable ECC error. +- FLASH macro main interface memory hole error. + [18:18] + read-write + + + WORK_ECC_EN + Enable ECC checking for FLASH work interface: +0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [20:20] + read-write + + + WORK_ECC_INJ_EN + Enable error injection for FLASH work interface. +When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [21:21] + read-write + + + WORK_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro work interface internal error. +- FLASH macro work interface non-recoverable ECC error. +- FLASH macro work interface recoverable ECC error. +- FLASH macro work interface memory hole error. + [22:22] + read-write + + + + + FLASH_PWR_CTL + Flash power control + 0x4 + 32 + read-write + 0x3 + 0x3 + + + ENABLE + Controls 'enable' pin of the Flash memory. + [0:0] + read-write + + + ENABLE_HV + Controls 'enable_hv' pin of the Flash memory. + [1:1] + read-write + + + + + FLASH_CMD + Command + 0x8 + 32 + read-write + 0x0 + 0x3 + + + INV + Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. + [0:0] + read-write + + + BUFF_INV + Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. + +Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. + [1:1] + read-write + + + + + ECC_CTL + ECC control + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. +- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). +- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). + [23:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. +- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. +- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. +- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. + [31:24] + read-write + + + + + FM_SRAM_ECC_CTL0 + eCT Flash SRAM ECC control 0 + 0x2B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ECC_INJ_DATA + 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. + [31:0] + read-write + + + + + FM_SRAM_ECC_CTL1 + eCT Flash SRAM ECC control 1 + 0x2B4 + 32 + read-write + 0x0 + 0x7F + + + ECC_INJ_PARITY + 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. + [6:0] + read-write + + + + + FM_SRAM_ECC_CTL2 + eCT Flash SRAM ECC control 2 + 0x2B8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CORRECTED_DATA + 32-bit corrected data output of the ECC syndrome logic. + [31:0] + read-only + + + + + FM_SRAM_ECC_CTL3 + eCT Flash SRAM ECC control 3 + 0x2BC + 32 + read-write + 0x1 + 0x111 + + + ECC_ENABLE + ECC generation/check enable for eCT Flash SRAM memory. + [0:0] + read-write + + + ECC_INJ_EN + eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: +1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. +2. Set the ECC_INJ_EN bit to '1'. +3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. +4. Check the corrected data in FM_SRAM_ECC_CTL2. +5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if +corrupted data was written in step 1). +6. If not finished, start over at 1 with different data. + [4:4] + read-write + + + ECC_TEST_FAIL + Status of ECC test. +1 : ECC test failed because eCT Flash macro is busy and using the SRAM. +0: ECC was performed. + [8:8] + read-only + + + + + CM0_CA_CTL0 + CM0+ cache control + 0x400 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + Enable ECC checking for cache accesses: +0: Disabled. +1: Enabled. + [0:0] + read-write + + + RAM_ECC_INJ_EN + Enable error injection for cache. +When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. + [1:1] + read-write + + + WAY + Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. + [26:24] + read-write + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + CA_EN + Cache enable: +0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). +1: Enabled. + [31:31] + read-write + + + + + CM0_CA_CTL1 + CM0+ cache control + 0x404 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM0 cache. +The following sequnece should be followed for turning OFF/ON the cache SRAM. +Turn OFF sequence: +a) Write CM0_CA_CTL0 to disable cache. +b) Write CM0_CA_CTL1 to turn OFF cache SRAM. +Turn ON sequence: +a) Write CM0_CA_CTL1 to turn ON cache SRAM. +b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. +c) Write CM0_CA_CTL0 to enable cache. + [1:0] + read-write + + + OFF + Power OFF the CM0 cache SRAM. + 0 + + + RSVD + Undefined + 1 + + + RETAINED + Put CM0 cache SRAM in retained mode. + 2 + + + ENABLED + Enable/Turn ON the CM0 cache SRAM. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_CA_CTL2 + CM0+ cache control + 0x408 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CA_STATUS0 + CM0+ cache status 0 + 0x440 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS1 + CM0+ cache status 1 + 0x444 + 32 + read-only + 0x0 + 0x0 + + + TAG + Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS2 + CM0+ cache status 2 + 0x448 + 32 + read-only + 0x0 + 0x0 + + + LRU + Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): +Bit 5: 0_LRU_1: way 0 less recently used than way 1. +Bit 4: 0_LRU_2. +Bit 3: 0_LRU_3. +Bit 2: 1_LRU_2. +Bit 1: 1_LRU_3. +Bit 0: 2_LRU_3. + [5:0] + read-only + + + + + CM0_STATUS + CM0+ interface status + 0x460 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CM4_CA_CTL0 + CM4 cache control + 0x480 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + See CM0_CA_CTL. + [0:0] + read-write + + + RAM_ECC_INJ_EN + See CM0_CA_CTL. + [1:1] + read-write + + + WAY + See CM0_CA_CTL. + [17:16] + read-write + + + SET_ADDR + See CM0_CA_CTL. + [26:24] + read-write + + + PREF_EN + See CM0_CA_CTL. + [30:30] + read-write + + + CA_EN + See CM0_CA_CTL. + [31:31] + read-write + + + + + CM4_CA_CTL1 + CM4 cache control + 0x484 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. + [1:0] + read-write + + + OFF + See CM0_CA_CTL1 + 0 + + + RSVD + Undefined + 1 + + + RETAINED + See CM0_CA_CTL1 + 2 + + + ENABLED + See CM0_CA_CTL1 + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM4_CA_CTL2 + CM4 cache control + 0x488 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM4_CA_STATUS0 + CM4 cache status 0 + 0x4C0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + See CM0_CA_STATUS0. + [31:0] + read-only + + + + + CM4_CA_STATUS1 + CM4 cache status 1 + 0x4C4 + 32 + read-only + 0x0 + 0x0 + + + TAG + See CM0_CA_STATUS1. + [31:0] + read-only + + + + + CM4_CA_STATUS2 + CM4 cache status 2 + 0x4C8 + 32 + read-only + 0x0 + 0x0 + + + LRU + See CM0_CA_STATUS2. + [5:0] + read-only + + + + + CM4_STATUS + CM4 interface status + 0x4E0 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM4_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CRYPTO_BUFF_CTL + Cryptography buffer control + 0x500 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. +A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. +For eCT work Flash, prefetch will not be done. + [30:30] + read-write + + + + + DW0_BUFF_CTL + Datawire 0 buffer control + 0x580 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DW1_BUFF_CTL + Datawire 1 buffer control + 0x600 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DMAC_BUFF_CTL + DMA controller buffer control + 0x680 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS0_BUFF_CTL + External master 0 buffer control + 0x700 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS1_BUFF_CTL + External master 1 buffer control + 0x780 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + FM_CTL + Flash Macro Registers + 0x0000F000 + + FM_CTL + Flash macro control + 0x0 + 32 + read-write + 0x0 + 0x37F030F + + + FM_MODE + Requires (IF_SEL|WR_EN)=1 +Flash macro mode selection + [3:0] + read-write + + + FM_SEQ + Requires (IF_SEL|WR_EN)=1 +Flash macro sequence selection + [9:8] + read-write + + + DAA_MUX_SEL + Direct memory cell access address. + [22:16] + read-write + + + IF_SEL + Interface selection. Specifies the interface that is used for flash memory read operations: +0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. +1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. +Note: IF_SEL and WR_EN cannot be changed at the same time + [24:24] + read-write + + + WR_EN + 0: normal mode +1: Fm Write Enable +Note: IF_SEL and WR_EN cannot be changed at the same time + [25:25] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x1800 + 0xFFFFFFFF + + + TIMER_ENABLED + This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires +0: timer not running +1: Timer is enabled and not expired yet + [0:0] + read-only + + + HV_REGS_ISOLATED + Indicates the isolation status at HV trim and redundancy registers inputs +0: Not isolated, writing permitted +1: isolated writing disabled + [1:1] + read-only + + + ILLEGAL_HVOP + Indicates a bulk, sector erase, program has been requested when axa=1 +0: no error +1: illegal HV operation error + [2:2] + read-only + + + TURBO_N + After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. +Used in the testchip boot only as an 'FM READY' flag. +0: turbo mode +1: normal mode + [3:3] + read-only + + + WR_EN_MON + FM_CTL.WR_EN bit after being synchronized in clk_r domain + [4:4] + read-only + + + IF_SEL_MON + FM_CTL.IF_SEL bit after being synchronized in clk_r domain + [5:5] + read-only + + + TIMER_STATUS + The actual timer state sync-ed in clk_c domain: +0: timer is not running: +1: timer is running; + [6:6] + read-only + + + R_GRANT_DELAY_STATUS + 0: R_GRANT_DELAY timer is not running +1: R_GRANT_DELAY timer is running + [7:7] + read-only + + + FM_BUSY + 0': FM not busy +1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. + [8:8] + read-only + + + FM_READY + 0: FM not ready +1: FM ready + [9:9] + read-only + + + POS_PUMP_VLO + POS pump VLO + [10:10] + read-only + + + NEG_PUMP_VHI + NEG pump VHI + [11:11] + read-only + + + RWW + FM Type (Read While Write or Not Read While Write): +0: Non RWW FM Type +1: RWW FM Type + [12:12] + read-only + + + MAX_DOUT_WIDTH + Internal memory core max data out size +(number of data out bits per column): +0: x128 bits +1: x256 bits + [13:13] + read-only + + + SECTOR0_SR + 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. +1: Sector 0 contains special rows + [14:14] + read-only + + + RESET_MM + Test_only, internal node: mpcon reset_mm + [15:15] + read-only + + + ROW_ODD + Test_only, internal node: mpcon row_odd + [16:16] + read-only + + + ROW_EVEN + Test_only, internal node: mpcon row_even + [17:17] + read-only + + + HVOP_SUB_SECTOR_N + Test_only, internal node: mpcon bk_subb + [18:18] + read-only + + + HVOP_SECTOR + Test_only, internal node: mpcon bk_sec + [19:19] + read-only + + + HVOP_BULK_ALL + Test_only, internal node: mpcon bk_all + [20:20] + read-only + + + CBUS_RA_MATCH + Test_only, internal node: mpcon ra match + [21:21] + read-only + + + CBUS_RED_ROW_EN + Test_only, internal node: mpcon red_row_en + [22:22] + read-only + + + RQ_ERROR + Test_only, internal node: rq_error sync-de in clk_c domain + [23:23] + read-only + + + PUMP_PDAC + Test_only, internal node: regif pdac outputs to pos pump + [27:24] + read-only + + + PUMP_NDAC + Test_only, internal node: regif ndac outputs to pos pump + [31:28] + read-only + + + + + FM_ADDR + Flash macro address + 0x8 + 32 + read-write + 0x0 + 0x1FFFFFF + + + RA + Row address. + [15:0] + read-write + + + BA + Bank address. + [23:16] + read-write + + + AXA + Auxiliary address field: +0: regular flash memory. +1: supervisory flash memory. + [24:24] + read-write + + + + + BOOKMARK + Bookmark register - keeps the current FW HV seq + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BOOKMARK + Used by FW. Keeps the Current HV cycle sequence + [31:0] + read-write + + + + + GEOMETRY + Regular flash geometry + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1): +0: 1 row +1: 2 rows +2: 3 rows +... +'65535': 65536 rows + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1): +0: 1 bank +1: 2 banks +... +'255': 256 banks + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +3: 128 Bytes + +The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2): +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +15: 32768 Bytes + +The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. + [31:28] + read-only + + + + + GEOMETRY_SUPERVISORY + Supervisory flash geometry + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. + [31:28] + read-only + + + + + ANA_CTL0 + Analog control 0 + 0x18 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + MDAC + Trimming of the output margin Voltage as a function of Vpos and Vneg. + [7:0] + read-write + + + CSLDAC + Trimming of common source line DAC. + [10:8] + read-write + + + FLIP_AMUXBUS_AB + Flips amuxbusa and amuxbusb +0: amuxbusa, amuxbusb +1: amuxbusb, amuxbusb + [11:11] + read-write + + + NDAC_MIN + NDAC staircase min value + [15:12] + read-write + + + PDAC_MIN + PDAC staircase min value + [19:16] + read-write + + + SCALE_PRG_SEQ01 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [21:20] + read-write + + + SCALE_PRG_SEQ12 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [23:22] + read-write + + + SCALE_PRG_SEQ23 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [25:24] + read-write + + + SCALE_SEQ30 + PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [27:26] + read-write + + + SCALE_PRG_PEON + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [29:28] + read-write + + + SCALE_PRG_PEOFF + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [31:30] + read-write + + + + + ANA_CTL1 + Analog control 1 + 0x1C + 32 + read-write + 0xD32FAFA + 0xFFFFFFFF + + + NDAC_MAX + Ndac Max Value.Trimming of negative pump output Voltage. + [3:0] + read-write + + + NDAC_STEP + Ndac step increment + [7:4] + read-write + + + PDAC_MAX + Pdac Max Value.Trimming of positive pump output Voltage: + [11:8] + read-write + + + PDAC_STEP + Pdac step increment + [15:12] + read-write + + + NPDAC_STEP_TIME + Ndac/Pdac step duration: (1uS .. 255uS) * 8 +When = 0 N/PDAC_MAX control the pumps + [23:16] + read-write + + + NPDAC_ZERO_TIME + Ndac/Pdac LO duration: (1uS .. 255uS) * 8 +When 0, N/PDAC don't return to 0 + [31:24] + read-write + + + + + WAIT_CTL + Wait State control + 0x28 + 32 + read-write + 0x30B09 + 0x3F070F0F + + + WAIT_FM_MEM_RD + Number of C interface wait cycles (on 'clk_c') for a read from the memory + [3:0] + read-write + + + WAIT_FM_HV_RD + Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. +Common for reading HV Page Latches and the DATA_COMP_RESULT bit + [11:8] + read-write + + + WAIT_FM_HV_WR + Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. + [18:16] + read-write + + + FM_RWW_MODE + 00: Full CBUS MODE +01: RWW +10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration + [25:24] + read-write + + + LV_SPARE_1 + Spare register + [26:26] + read-write + + + DRMM + 0: Normal +1: Test mode to enable Margin mode for 2 rows at a time + [27:27] + read-write + + + MBA + 0: Normal +1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). + [28:28] + read-write + + + PL_SOFT_SET_EN + Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API + [29:29] + read-write + + + + + TIMER_CLK_CTL + Timer prescaler (clk_t to timer clock frequency divider) + 0x34 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TIMER_CLOCK_FREQ + Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. +Equal to the frequency in MHz of the timer clock 'clk_t'. +Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' +Max clk_t frequency = 100MHz. +This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table + [7:0] + read-write + + + RGRANT_DELAY_PRG_PEON + PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_PRG_PEOFF + PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_PRG_SEQ01 + PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + TIMER_CTL + Timer control + 0x38 + 32 + read-write + 0x4000001 + 0xE700FFFF + + + PERIOD + Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. + [14:0] + read-write + + + SCALE + Timer tick scale: +0: 1 microsecond. +1: 100 microseconds. + [15:15] + read-write + + + AUTO_SEQUENCE + 1': Starts1 the HV automatic sequencing +Cleared by HW + [24:24] + read-write + + + PRE_PROG + 1 during pre-program operation + [25:25] + read-write + + + PRE_PROG_CSL + 0: CSL lines driven by CSL_DAC +1: CSL lines driven by VNEG_G + [26:26] + read-write + + + PUMP_EN + Pump enable: +0: disabled +1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). +SW sets this field to '1' to generate a single PE pulse. +HW clears this field when timer is expired. + [29:29] + read-write + + + ACLK_EN + ACLK enable (generates a single cycle pulse for the FM): +0: disabled +1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. + [30:30] + read-write + + + TIMER_EN + Timer enable: +0: disabled +1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. + [31:31] + read-write + + + + + ACLK_CTL + MPCON clock + 0x3C + 32 + write-only + 0x0 + 0x1 + + + ACLK_GEN + A write to this register generates the clock pulse for HV control registers (mpcon outputs) + [0:0] + write-only + + + + + INTR + Interrupt + 0x40 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x44 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x48 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x4C + 32 + read-only + 0x0 + 0x1 + + + TIMER_EXPIRED + Logical and of corresponding request and mask fields. + [0:0] + read-only + + + + + CAL_CTL0 + Cal control BG LO trim bits + 0x50 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_LO_HV + LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_LO_HV + LO Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control + [15:13] + read-write + + + ICREF_TC_TRIM_LO_HV + LO Bandgap Current Temperature Compensation trim control + [18:16] + read-write + + + IPREF_TRIMA_LO_HV + Adds 100-150nA boost on IPREF_LO + [19:19] + read-write + + + + + CAL_CTL1 + Cal control BG HI trim bits + 0x54 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_HI_HV + HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_HI_HV + HI Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [15:13] + read-write + + + ICREF_TC_TRIM_HI_HV + HI Bandgap Current Temperature Compensation trim control. + [18:16] + read-write + + + IPREF_TRIMA_HI_HV + Adds 100-150nA boost on IPREF_HI + [19:19] + read-write + + + + + CAL_CTL2 + Cal control BG LO&HI trim bits + 0x58 + 32 + read-write + 0x7BE10 + 0xFFFFF + + + ICREF_TRIM_LO_HV + LO Bandgap Current trim control. + [4:0] + read-write + + + ICREF_TRIM_HI_HV + HI Bandgap Current trim control. + [9:5] + read-write + + + IPREF_TRIM_LO_HV + LO Bandgap IPTAT trim control. + [14:10] + read-write + + + IPREF_TRIM_HI_HV + HI Bandgap IPTAT trim control. + [19:15] + read-write + + + + + CAL_CTL3 + Cal control osc trim bits, idac, sdac, itim + 0x5C + 32 + read-write + 0x2004 + 0xFFFFF + + + OSC_TRIM_HV + Flash macro pump clock trim control. + [3:0] + read-write + + + OSC_RANGE_TRIM_HV + 0: Oscillator High Frequency Range +1: Oscillator Low Frequency range + [4:4] + read-write + + + VPROT_ACT_HV + Forces VPROT in active mode all the time + [5:5] + read-write + + + IPREF_TC_HV + 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA +1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA + [6:6] + read-write + + + VREF_SEL_HV + Voltage reference: +0: internal bandgap reference +1: external voltage reference + [7:7] + read-write + + + IREF_SEL_HV + Current reference: +0: internal current reference +1: external current reference + [8:8] + read-write + + + REG_ACT_HV + 0: VBST regulator will operate in active/standby mode based on control signal. +1: Forces the VBST regulator in active mode all the time + [9:9] + read-write + + + FDIV_TRIM_HV + FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. +Following are the clock frequencies seen by doubler +00: F = 1MHz +01: F = 0.5MHz +10: F = 2MHz +11: F = 4MHz + [11:10] + read-write + + + VDDHI_HV + 0: vdd < 2.3V +1: vdd >= 2.3V +'0' setting can used for vdd > 2.3V also, but with a current penalty. + [12:12] + read-write + + + TURBO_PULSEW_HV + Turbo pulse width trim (Typical) +00: 40 us +01: 20 us +10: 15 us +11: 8 us + [14:13] + read-write + + + BGLO_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable LO Bandgap + [15:15] + read-write + + + BGHI_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable HI Bandgap +When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active + [16:16] + read-write + + + CL_ISO_DIS_HV + 0: The internal logic controls the CL isolation +1: Forces CL bypass + [17:17] + read-write + + + R_GRANT_EN_HV + 0: r_grant handshake disabled, r_grant always 1. +1: r_grand handshake enabled + [18:18] + read-write + + + LP_ULP_SW_HV + LP<-->ULP switch for trim signals: +0: LP +1: ULP + [19:19] + read-write + + + + + CAL_CTL4 + Cal Control Vlim, SA, fdiv, reg_act + 0x60 + 32 + read-write + 0x12AE0 + 0xFFFFF + + + VLIM_TRIM_ULP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_ULP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_ULP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_ULP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_ULP_HV + 00: Default : delay 1ns +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_ULP_HV + N/A + [15:15] + read-write + + + READY_RESTART_N_HV + Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. + [16:16] + read-write + + + VBST_S_DIS_HV + 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. +1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. + [17:17] + read-write + + + AUTO_HVPULSE_HV + 0: HV Pulse controlled by FW +1: HV Pulse controlled by Hardware + [18:18] + read-write + + + UGB_EN_HV + UGB enable in TM control + [19:19] + read-write + + + + + CAL_CTL5 + Cal control + 0x64 + 32 + read-write + 0x2AE0 + 0xFFFFF + + + VLIM_TRIM_LP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_LP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_LP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_LP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_LP_HV + 00: Delayed by 1us +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_LP_HV + N/A + [15:15] + read-write + + + SPARE52_HV + N/A + [17:16] + read-write + + + AMUX_SEL_HV + Amux Select in AMUX_UGB +00: Bypass UGB for both amuxbusa and amuxbusb +01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. +10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. +11: UGB Calibrate mode + [19:18] + read-write + + + + + CAL_CTL6 + SA trim LP/ULP + 0x68 + 32 + read-write + 0x36F7F + 0xFFFFF + + + SA_CTL_TRIM_T1_ULP_HV + clk_trk delay + [0:0] + read-write + + + SA_CTL_TRIM_T4_ULP_HV + SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) + [3:1] + read-write + + + SA_CTL_TRIM_T5_ULP_HV + SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) + [6:4] + read-write + + + SA_CTL_TRIM_T6_ULP_HV + SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) + [8:7] + read-write + + + SA_CTL_TRIM_T8_ULP_HV + saen3 pulse width trim (Current trim) + [9:9] + read-write + + + SA_CTL_TRIM_T1_LP_HV + clk_trk delay + [10:10] + read-write + + + SA_CTL_TRIM_T4_LP_HV + SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) + [13:11] + read-write + + + SA_CTL_TRIM_T5_LP_HV + SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) + [16:14] + read-write + + + SA_CTL_TRIM_T6_LP_HV + SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) + [18:17] + read-write + + + SA_CTL_TRIM_T8_LP_HV + saen3 pulse width trim (Current trim) + [19:19] + read-write + + + + + CAL_CTL7 + Cal control + 0x6C + 32 + read-write + 0x0 + 0xFFFFF + + + ERSX8_CLK_SEL_HV + Clock frequency into the ersx8 shift register block +00: Oscillator clock +01: Oscillator clock / 2 +10: Oscillator clock / 4 +11: Oscillator clock + [1:0] + read-write + + + FM_ACTIVE_HV + 0: Normal operation +1: Forces FM SYS in active mode + [2:2] + read-write + + + TURBO_EXT_HV + 0: Normal operation +1: Uses external turbo pulse + [3:3] + read-write + + + NPDAC_HWCTL_DIS_HV + 0': ndac, pdac staircase hardware controlled +1: ndac, pdac staircase disabled. Enables FW control. + [4:4] + read-write + + + FM_READY_DIS_HV + 0': fm ready is enabled +1: fm ready is disabled (fm_ready is always '1') + [5:5] + read-write + + + ERSX8_EN_ALL_HV + 0': Staggered turn on/off of GWL +1: GWL are turned on/off at the same time (old FM legacy) + [6:6] + read-write + + + DISABLE_LOAD_ONCE_HV + 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. +1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. + [7:7] + read-write + + + SPARE7_HV + N/A + [9:8] + read-write + + + SPARE7_ULP_HV + N/A + [14:10] + read-write + + + SPARE7_LP_HV + N/A + [19:15] + read-write + + + + + RED_CTL01 + Redundancy Control normal sectors 0,1 + 0x80 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_0 + Bad Row Pair Address for Sector 0 + [7:0] + read-write + + + RED_EN_0 + 1: Redundancy Enable for Sector 0 + [8:8] + read-write + + + RED_ADDR_1 + Bad Row Pair Address for Sector 1 + [23:16] + read-write + + + RED_EN_1 + 1: Redundancy Enable for Sector 1 + [24:24] + read-write + + + + + RED_CTL23 + Redundancy Control normal sectors 2,3 + 0x84 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_2 + Bad Row Pair Address for Sector 2 + [7:0] + read-write + + + RED_EN_2 + 1: Redundancy Enable for Sector 2 + [8:8] + read-write + + + RED_ADDR_3 + Bad Row Pair Address for Sector 3 + [23:16] + read-write + + + RED_EN_3 + 1: Redundancy Enable for Sector 3 + [24:24] + read-write + + + + + RED_CTL45 + Redundancy Control normal sectors 4,5 + 0x88 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_4 + Bad Row Pair Address for Sector 4 + [7:0] + read-write + + + RED_EN_4 + 1: Redundancy Enable for Sector 4 + [8:8] + read-write + + + RED_ADDR_5 + Bad Row Pair Address for Sector 5 + [23:16] + read-write + + + RED_EN_5 + 1: Redundancy Enable for Sector 5 + [24:24] + read-write + + + + + RED_CTL67 + Redundancy Control normal sectors 6,7 + 0x8C + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_6 + Bad Row Pair Address for Sector 6 + [7:0] + read-write + + + RED_EN_6 + 1: Redundancy Enable for Sector 6 + [8:8] + read-write + + + RED_ADDR_7 + Bad Row Pair Address for Sector 7 + [23:16] + read-write + + + RED_EN_7 + 1: Redundancy Enable for Sector 7 + [24:24] + read-write + + + + + RED_CTL_SM01 + Redundancy Control special sectors 0,1 + 0x90 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_SM0 + Bad Row Pair Address for Special Sector 0 + [7:0] + read-write + + + RED_EN_SM0 + Redundancy Enable for Special Sector 0 + [8:8] + read-write + + + RED_ADDR_SM1 + Bad Row Pair Address for Special Sector 1 + [23:16] + read-write + + + RED_EN_SM1 + Redundancy Enable for Special Sector 1 + [24:24] + read-write + + + + + RGRANT_DELAY_PRG + R-grant delay for program + 0x98 + 32 + read-write + 0x1000000 + 0x8FFFFFFF + + + RGRANT_DELAY_PRG_SEQ12 + PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_PRG_SEQ23 + PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_SEQ30 + PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_CLK + Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay +The value of this field is the integer result of 'clk_t frequency / 8'. +Example: for clk_t=100 this field is INT(100/8) =12. +This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table + [27:24] + read-write + + + HV_PARAMS_LOADED + 0: HV Pulse common params not loaded +1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 + [31:31] + read-write + + + + + PW_SEQ12 + HV Pulse Delay for seq 1&2 pre + 0xA0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ1 + Seq1 delay + [15:0] + read-write + + + PW_SEQ2_PRE + Seq2 pre delay + [31:16] + read-write + + + + + PW_SEQ23 + HV Pulse Delay for seq2 post & seq3 + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ2_POST + Seq2 post delay + [15:0] + read-write + + + PW_SEQ3 + Seq3 delay + [31:16] + read-write + + + + + RGRANT_SCALE_ERS + R-grant delay scale for erase + 0xA8 + 32 + read-write + 0x0 + 0xFFFF03FF + + + SCALE_ERS_SEQ01 + ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [1:0] + read-write + + + SCALE_ERS_SEQ12 + ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [3:2] + read-write + + + SCALE_ERS_SEQ23 + ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [5:4] + read-write + + + SCALE_ERS_PEON + ERASE: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [7:6] + read-write + + + SCALE_ERS_PEOFF + ERASE: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [9:8] + read-write + + + RGRANT_DELAY_ERS_PEON + ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_ERS_PEOFF + ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + RGRANT_DELAY_ERS + R-grant delay for erase + 0xAC + 32 + read-write + 0x0 + 0xFFFFFF + + + RGRANT_DELAY_ERS_SEQ01 + ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_ERS_SEQ12 + ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_ERS_SEQ23 + ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + + + FM_PL_WRDATA_ALL + Flash macro write page latches all + 0x7FC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Write all high Voltage page latches with the same 32-bit data in a single write cycle +Read always returns 0. + [31:0] + read-write + + + + + 256 + 4 + FM_PL_DATA[%s] + Flash macro Page Latches data + 0x800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Four page latch Bytes +When reading the page latches it requires FM_CTL.IF_SEL to be '1' +Note: the high Voltage page latches are readable for test mode functionality. + [31:0] + read-write + + + + + 256 + 4 + FM_MEM_DATA[%s] + Flash macro memory sense amplifier and column decoder data + 0xC00 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: +- IF_SEL is 0: data as specified by the R interface address +- IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. + [31:0] + read-only + + + + + + + + SRSS + SRSS Core Registers + 0x40260000 + + 0 + 65536 + registers + + + + PWR_CTL + Power Mode Control + 0x0 + 32 + read-write + 0x0 + 0xFFFC0033 + + + POWER_MODE + Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. + [1:0] + read-only + + + RESET + System is resetting. + 0 + + + ACTIVE + At least one CPU is running. + 1 + + + SLEEP + No CPUs are running. Peripherals may be running. + 2 + + + DEEPSLEEP + Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. + 3 + + + + + DEBUG_SESSION + Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) + [4:4] + read-only + + + NO_SESSION + No debug session active + 0 + + + SESSION_ACTIVE + Debug session is active. Power modes behave differently to keep the debug session active. + 1 + + + + + LPM_READY + Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. +1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. + [5:5] + read-only + + + IREF_LPMODE + Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. +1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. + [18:18] + read-write + + + VREFBUF_OK + Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. + [19:19] + read-only + + + DPSLP_REG_DIS + Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: DeepSleep Regulator is on. +1: DeepSleep Regulator is off. + [20:20] + read-write + + + RET_REG_DIS + Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Retention Regulator is on. +1: Retention Regulator is off. + [21:21] + read-write + + + NWELL_REG_DIS + Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Nwell Regulator is on. +1: Nwell Regulator is off. + [22:22] + read-write + + + LINREG_DIS + Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear regulator is on. +1: Linear regulator is off. + [23:23] + read-write + + + LINREG_LPMODE + Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. +1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. + [24:24] + read-write + + + PORBOD_LPMODE + Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [25:25] + read-write + + + BGREF_LPMODE + Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0. + [26:26] + read-write + + + PLL_LS_BYPASS + Bypass level shifter inside the PLL. +0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. +1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. + [27:27] + read-write + + + VREFBUF_LPMODE + Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. +0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/HIBERNATE. +1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [28:28] + read-write + + + VREFBUF_DIS + Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. + [29:29] + read-write + + + ACT_REF_DIS + Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Reference is enabled +1: Active Reference is disabled + [30:30] + read-write + + + ACT_REF_OK + Indicates that the normal mode of the Active Reference is ready. + [31:31] + read-only + + + + + PWR_HIBERNATE + HIBERNATE Mode Register + 0x4 + 32 + read-write + 0x0 + 0xCFFEFFFF + + + TOKEN + Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. + [7:0] + read-write + + + UNLOCK + This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. + [15:8] + read-write + + + FREEZE + Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. + [17:17] + read-write + + + MASK_HIBALARM + When set, HIBERNATE will wakeup for a RTC interrupt + [18:18] + read-write + + + MASK_HIBWDT + When set, HIBERNATE will wakeup if WDT matches + [19:19] + read-write + + + POLARITY_HIBPIN + Each bit sets the active polarity of the corresponding wakeup pin. +0: Pin input of 0 will wakeup the part from HIBERNATE +1: Pin input of 1 will wakeup the part from HIBERNATE + [23:20] + read-write + + + MASK_HIBPIN + When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. + [27:24] + read-write + + + HIBERNATE_DISABLE + Hibernate disable bit. +0: Normal operation, HIBERNATE works as described +1: Further writes to this register are ignored +Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. + [30:30] + read-write + + + HIBERNATE + Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. + [31:31] + read-write + + + + + PWR_LVD_CTL + Low Voltage Detector (LVD) Configuration Register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + HVLVD1_TRIPSEL + Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. +0: rise=1.225V (nom), fall=1.2V (nom) +1: rise=1.425V (nom), fall=1.4V (nom) +2: rise=1.625V (nom), fall=1.6V (nom) +3: rise=1.825V (nom), fall=1.8V (nom) +4: rise=2.025V (nom), fall=2V (nom) +5: rise=2.125V (nom), fall=2.1V (nom) +6: rise=2.225V (nom), fall=2.2V (nom) +7: rise=2.325V (nom), fall=2.3V (nom) +8: rise=2.425V (nom), fall=2.4V (nom) +9: rise=2.525V (nom), fall=2.5V (nom) +10: rise=2.625V (nom), fall=2.6V (nom) +11: rise=2.725V (nom), fall=2.7V (nom) +12: rise=2.825V (nom), fall=2.8V (nom) +13: rise=2.925V (nom), fall=2.9V (nom) +14: rise=3.025V (nom), fall=3.0V (nom) +15: rise=3.125V (nom), fall=3.1V (nom) + [3:0] + read-write + + + HVLVD1_SRCSEL + Source selection for HVLVD1 + [6:4] + read-write + + + VDDD + Select VDDD + 0 + + + AMUXBUSA + Select AMUXBUSA (VDDD branch) + 1 + + + RSVD + N/A + 2 + + + VDDIO + N/A + 3 + + + AMUXBUSB + Select AMUXBUSB (VDDD branch) + 4 + + + + + HVLVD1_EN + Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. + [7:7] + read-write + + + + + PWR_BUCK_CTL + Buck Control Register + 0x14 + 32 + read-write + 0x5 + 0xC0000007 + + + BUCK_OUT1_SEL + Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 0.85V +1: 0.875V +2: 0.90V +3: 0.95V +4: 1.05V +5: 1.10V +6: 1.15V +7: 1.20V + [2:0] + read-write + + + BUCK_EN + Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. + [30:30] + read-write + + + BUCK_OUT1_EN + Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. TRM must follow the SAS. + [31:31] + read-write + + + + + PWR_BUCK_CTL2 + Buck Control Register 2 + 0x18 + 32 + read-write + 0x0 + 0xC0000007 + + + BUCK_OUT2_SEL + Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 1.15V +1: 1.20V +2: 1.25V +3: 1.30V +4: 1.35V +5: 1.40V +6: 1.45V +7: 1.50V + [2:0] + read-write + + + BUCK_OUT2_HW_SEL + Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. + [30:30] + read-write + + + BUCK_OUT2_EN + Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. + [31:31] + read-write + + + + + PWR_LVD_STATUS + Low Voltage Detector (LVD) Status Register + 0x1C + 32 + read-only + 0x0 + 0x1 + + + HVLVD1_OK + HVLVD1 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + 16 + 4 + PWR_HIB_DATA[%s] + HIBERNATE Data Register + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HIB_DATA + Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. + [31:0] + read-write + + + + + WDT_CTL + Watchdog Counter Control Register + 0x180 + 32 + read-write + 0xC0000001 + 0xC0000001 + + + WDT_EN + Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. + [0:0] + read-write + + + WDT_LOCK + Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. +Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + WDT_CNT + Watchdog Counter Count Register + 0x184 + 32 + read-write + 0x0 + 0xFFFF + + + COUNTER + Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. + [15:0] + read-write + + + + + WDT_MATCH + Watchdog Counter Match Register + 0x188 + 32 + read-write + 0x1000 + 0xFFFFF + + + MATCH + Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). + [15:0] + read-write + + + IGNORE_BITS + The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. + [19:16] + read-write + + + + + 2 + 64 + MCWDT_STRUCT[%s] + Multi-Counter Watchdog Timer + MCWDT_STRUCT + 0x00000200 + + MCWDT_CNTLOW + Multi-Counter Watchdog Sub-counters 0/1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR0 + Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. + [15:0] + read-write + + + WDT_CTR1 + Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:16] + read-write + + + + + MCWDT_CNTHIGH + Multi-Counter Watchdog Sub-counter 2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR2 + Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:0] + read-write + + + + + MCWDT_MATCH + Multi-Counter Watchdog Counter Match Register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_MATCH0 + Match value for sub-counter 0 of this MCWDT + [15:0] + read-write + + + WDT_MATCH1 + Match value for sub-counter 1 of this MCWDT + [31:16] + read-write + + + + + MCWDT_CONFIG + Multi-Counter Watchdog Counter Configuration + 0x10 + 32 + read-write + 0x0 + 0x1F010F0F + + + WDT_MODE0 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). + [1:0] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR0 + Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. + [2:2] + read-write + + + WDT_CASCADE0_1 + Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. +0: Independent counters +1: Cascaded counters + [3:3] + read-write + + + WDT_MODE1 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). + [9:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR1 + Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. + [10:10] + read-write + + + WDT_CASCADE1_2 + Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. +0: Independent counters +1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. + [11:11] + read-write + + + WDT_MODE2 + Watchdog Counter 2 Mode. + [16:16] + read-write + + + NOTHING + Free running counter with no interrupt requests + 0 + + + INT + Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). + 1 + + + + + WDT_BITS2 + Bit to observe for WDT_INT2: +0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) +... +31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) + [28:24] + read-write + + + + + MCWDT_CTL + Multi-Counter Watchdog Counter Control + 0x14 + 32 + read-write + 0x0 + 0xB0B0B + + + WDT_ENABLE0 + Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [0:0] + read-write + + + WDT_ENABLED0 + Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. + [1:1] + read-only + + + WDT_RESET0 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [3:3] + read-write + + + WDT_ENABLE1 + Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [8:8] + read-write + + + WDT_ENABLED1 + Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. + [9:9] + read-only + + + WDT_RESET1 + Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [11:11] + read-write + + + WDT_ENABLE2 + Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [16:16] + read-write + + + WDT_ENABLED2 + Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. + [17:17] + read-only + + + WDT_RESET2 + Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [19:19] + read-write + + + + + MCWDT_INTR + Multi-Counter Watchdog Counter Interrupt Register + 0x18 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. + [0:0] + read-write + + + MCWDT_INT1 + MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. + [1:1] + read-write + + + MCWDT_INT2 + MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. + [2:2] + read-write + + + + + MCWDT_INTR_SET + Multi-Counter Watchdog Counter Interrupt Set Register + 0x1C + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Set interrupt for MCWDT_INT0 + [0:0] + read-write + + + MCWDT_INT1 + Set interrupt for MCWDT_INT1 + [1:1] + read-write + + + MCWDT_INT2 + Set interrupt for MCWDT_INT2 + [2:2] + read-write + + + + + MCWDT_INTR_MASK + Multi-Counter Watchdog Counter Interrupt Mask Register + 0x20 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Mask for sub-counter 0 + [0:0] + read-write + + + MCWDT_INT1 + Mask for sub-counter 1 + [1:1] + read-write + + + MCWDT_INT2 + Mask for sub-counter 2 + [2:2] + read-write + + + + + MCWDT_INTR_MASKED + Multi-Counter Watchdog Counter Interrupt Masked Register + 0x24 + 32 + read-only + 0x0 + 0x7 + + + MCWDT_INT0 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + MCWDT_INT1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + MCWDT_INT2 + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + MCWDT_LOCK + Multi-Counter Watchdog Counter Lock Register + 0x28 + 32 + read-write + 0x0 + 0xC0000000 + + + MCWDT_LOCK + Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + + 16 + 4 + CLK_DSI_SELECT[%s] + Clock DSI Select Register + 0x300 + 32 + read-write + 0x0 + 0x1F + + + DSI_MUX + Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. + [4:0] + read-write + + + DSI_OUT0 + DSI0 - dsi_out[0] + 0 + + + DSI_OUT1 + DSI1 - dsi_out[1] + 1 + + + DSI_OUT2 + DSI2 - dsi_out[2] + 2 + + + DSI_OUT3 + DSI3 - dsi_out[3] + 3 + + + DSI_OUT4 + DSI4 - dsi_out[4] + 4 + + + DSI_OUT5 + DSI5 - dsi_out[5] + 5 + + + DSI_OUT6 + DSI6 - dsi_out[6] + 6 + + + DSI_OUT7 + DSI7 - dsi_out[7] + 7 + + + DSI_OUT8 + DSI8 - dsi_out[8] + 8 + + + DSI_OUT9 + DSI9 - dsi_out[9] + 9 + + + DSI_OUT10 + DSI10 - dsi_out[10] + 10 + + + DSI_OUT11 + DSI11 - dsi_out[11] + 11 + + + DSI_OUT12 + DSI12 - dsi_out[12] + 12 + + + DSI_OUT13 + DSI13 - dsi_out[13] + 13 + + + DSI_OUT14 + DSI14 - dsi_out[14] + 14 + + + DSI_OUT15 + DSI15 - dsi_out[15] + 15 + + + ILO + ILO - Internal Low-speed Oscillator + 16 + + + WCO + WCO - Watch-Crystal Oscillator + 17 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock + 18 + + + PILO + PILO - Precision Internal Low-speed Oscillator + 19 + + + + + + + 16 + 4 + CLK_PATH_SELECT[%s] + Clock Path Select Register + 0x340 + 32 + read-write + 0x0 + 0x7 + + + PATH_MUX + Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + DSI_MUX + DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. + 4 + + + + + + + 16 + 4 + CLK_ROOT_SELECT[%s] + Clock Root Select Register + 0x380 + 32 + read-write + 0x0 + 0x8000003F + + + ROOT_MUX + Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [3:0] + read-write + + + PATH0 + Select PATH0 (can be configured for FLL) + 0 + + + PATH1 + Select PATH1 (can be configured for PLL0, if available in the product) + 1 + + + PATH2 + Select PATH2 (can be configured for PLL1, if available in the product) + 2 + + + PATH3 + Select PATH3 (can be configured for PLL2, if available in the product) + 3 + + + PATH4 + Select PATH4 (can be configured for PLL3, if available in the product) + 4 + + + PATH5 + Select PATH5 (can be configured for PLL4, if available in the product) + 5 + + + PATH6 + Select PATH6 (can be configured for PLL5, if available in the product) + 6 + + + PATH7 + Select PATH7 (can be configured for PLL6, if available in the product) + 7 + + + PATH8 + Select PATH8 (can be configured for PLL7, if available in the product) + 8 + + + PATH9 + Select PATH9 (can be configured for PLL8, if available in the product) + 9 + + + PATH10 + Select PATH10 (can be configured for PLL9, if available in the product) + 10 + + + PATH11 + Select PATH11 (can be configured for PLL10, if available in the product) + 11 + + + PATH12 + Select PATH12 (can be configured for PLL11, if available in the product) + 12 + + + PATH13 + Select PATH13 (can be configured for PLL12, if available in the product) + 13 + + + PATH14 + Select PATH14 (can be configured for PLL13, if available in the product) + 14 + + + PATH15 + Select PATH15 (can be configured for PLL14, if available in the product) + 15 + + + + + ROOT_DIV + Selects predivider value for this clock root and DSI input. + [5:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + + + ENABLE + Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. + [31:31] + read-write + + + + + CLK_SELECT + Clock selection register + 0x500 + 32 + read-write + 0x0 + 0xFF03 + + + LFCLK_SEL + Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. + [1:0] + read-write + + + ILO + ILO - Internal Low-speed Oscillator + 0 + + + WCO + WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). + 1 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock. Capability is product-specific + 2 + + + PILO + PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. + 3 + + + + + PUMP_SEL + Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. + [11:8] + read-write + + + PUMP_DIV + Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. + [14:12] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + + + PUMP_ENABLE + Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: +1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. +2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. +3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. + [15:15] + read-write + + + + + CLK_TIMER_CTL + Timer Clock Control Register + 0x504 + 32 + read-write + 0x70000 + 0x80FF0301 + + + TIMER_SEL + Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. + [0:0] + read-write + + + IMO + IMO - Internal Main Oscillator + 0 + + + HF0_DIV + Select the output of the predivider configured by TIMER_HF0_DIV. + 1 + + + + + TIMER_HF0_DIV + Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. + [9:8] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. + 0 + + + DIV_BY_2 + Divide HFCLK0 by 2. + 1 + + + DIV_BY_4 + Divide HFCLK0 by 4. + 2 + + + DIV_BY_8 + Divide HFCLK0 by 8. + 3 + + + + + TIMER_DIV + Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. + [23:16] + read-write + + + ENABLE + Enable for TIMERCLK. +0: TIMERCLK is off +1: TIMERCLK is enabled + [31:31] + read-write + + + + + CLK_ILO_CONFIG + ILO Configuration + 0x50C + 32 + read-write + 0x80000000 + 0x80000001 + + + ILO_BACKUP + If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. +0: ILO turns off at XRES/BOD event or HIBERNATE entry. +1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. + [0:0] + read-write + + + ENABLE + Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. + [31:31] + read-write + + + + + CLK_IMO_CONFIG + IMO Configuration + 0x510 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLE + Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0. + [31:31] + read-write + + + + + CLK_OUTPUT_FAST + Fast Clock Output Select Register + 0x514 + 32 + read-write + 0x0 + 0xFFF0FFF + + + FAST_SEL0 + Select signal for fast clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL0 + Selects the clock path chosen by PATH_SEL0 field + 5 + + + HFCLK_SEL0 + Selects the output of the HFCLK_SEL0 mux + 6 + + + SLOW_SEL0 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 + 7 + + + + + PATH_SEL0 + Selects a clock path to use in fast clock output #0 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [7:4] + read-write + + + HFCLK_SEL0 + Selects a HFCLK tree for use in fast clock output #0 + [11:8] + read-write + + + FAST_SEL1 + Select signal for fast clock output #1 + [19:16] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL1 + Selects the clock path chosen by PATH_SEL1 field + 5 + + + HFCLK_SEL1 + Selects the output of the HFCLK_SEL1 mux + 6 + + + SLOW_SEL1 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 + 7 + + + + + PATH_SEL1 + Selects a clock path to use in fast clock output #1 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [23:20] + read-write + + + HFCLK_SEL1 + Selects a HFCLK tree for use in fast clock output #1 logic + [27:24] + read-write + + + + + CLK_OUTPUT_SLOW + Slow Clock Output Select Register + 0x518 + 32 + read-write + 0x0 + 0xFF + + + SLOW_SEL0 + Select signal for slow clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + SLOW_SEL1 + Select signal for slow clock output #1 + [7:4] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + + + CLK_CAL_CNT1 + Clock Calibration Counter 1 + 0x51C + 32 + read-write + 0x80000000 + 0x80FFFFFF + + + CAL_COUNTER1 + Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. + [23:0] + read-write + + + CAL_COUNTER_DONE + Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up + [31:31] + read-only + + + + + CLK_CAL_CNT2 + Clock Calibration Counter 2 + 0x520 + 32 + read-only + 0x0 + 0xFFFFFF + + + CAL_COUNTER2 + Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) + [23:0] + read-only + + + + + CLK_ECO_CONFIG + ECO Configuration Register + 0x52C + 32 + read-write + 0x2 + 0x80000002 + + + AGC_EN + Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. + [1:1] + read-write + + + ECO_EN + Master enable for ECO oscillator. + [31:31] + read-write + + + + + CLK_ECO_STATUS + ECO Status Register + 0x530 + 32 + read-only + 0x0 + 0x3 + + + ECO_OK + Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. + [0:0] + read-only + + + ECO_READY + Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. + [1:1] + read-only + + + + + CLK_PILO_CONFIG + Precision ILO Configuration Register + 0x53C + 32 + read-write + 0x80 + 0xE00003FF + + + PILO_FFREQ + Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. + [9:0] + read-write + + + PILO_CLK_EN + Enable the PILO clock output. See PILO_EN field for required sequencing. + [29:29] + read-write + + + PILO_RESET_N + Reset the PILO. See PILO_EN field for required sequencing. + [30:30] + read-write + + + PILO_EN + Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. + [31:31] + read-write + + + + + CLK_FLL_CONFIG + FLL Configuration Register + 0x580 + 32 + read-write + 0x1000000 + 0x8103FFFF + + + FLL_MULT + Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). + +Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) + [17:0] + read-write + + + FLL_OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: no division +1: divide by 2 + [24:24] + read-write + + + FLL_ENABLE + Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. + +To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. + +To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. + +Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. + +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_CONFIG2 + FLL Configuration Register 2 + 0x584 + 32 + read-write + 0x20001 + 0x1FF1FFF + + + FLL_REF_DIV + Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +8191: divide by 8191 + [12:0] + read-write + + + LOCK_TOL + Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. +0: tolerate error of 1 count value +1: tolerate error of 2 count values +... +511: tolerate error of 512 count values + [24:16] + read-write + + + + + CLK_FLL_CONFIG3 + FLL Configuration Register 3 + 0x588 + 32 + read-write + 0x2800 + 0x301FFFFF + + + FLL_LF_IGAIN + FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [3:0] + read-write + + + FLL_LF_PGAIN + FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [7:4] + read-write + + + SETTLING_COUNT + Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. +0: no settling time +1: wait one reference clock cycle +... +8191: wait 8191 reference clock cycles + [20:8] + read-write + + + BYPASS_SEL + Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. + [29:28] + read-write + + + AUTO + N/A + 0 + + + AUTO1 + N/A + 1 + + + FLL_REF + Select FLL reference input (bypass mode). Ignores lock indicator + 2 + + + FLL_OUT + Select FLL output. Ignores lock indicator. + 3 + + + + + + + CLK_FLL_CONFIG4 + FLL Configuration Register 4 + 0x58C + 32 + read-write + 0xFF + 0xC1FF07FF + + + CCO_LIMIT + Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) + [7:0] + read-write + + + CCO_RANGE + Frequency range of CCO + [10:8] + read-write + + + RANGE0 + Target frequency is in range [48, 64) MHz + 0 + + + RANGE1 + Target frequency is in range [64, 85) MHz + 1 + + + RANGE2 + Target frequency is in range [85, 113) MHz + 2 + + + RANGE3 + Target frequency is in range [113, 150) MHz + 3 + + + RANGE4 + Target frequency is in range [150, 200] MHz + 4 + + + + + CCO_FREQ + CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. + [24:16] + read-write + + + CCO_HW_UPDATE_DIS + Disable CCO frequency update by FLL hardware +0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. +1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. + [30:30] + read-write + + + CCO_ENABLE + Enable the CCO. It is required to enable the CCO before using the FLL. +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_STATUS + FLL Status Register + 0x590 + 32 + read-write + 0x0 + 0x7 + + + LOCKED + FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. + [0:0] + read-only + + + UNLOCK_OCCURRED + N/A + [1:1] + read-write + + + CCO_READY + This indicates that the CCO is internally settled and ready to use. + [2:2] + read-only + + + + + 15 + 4 + CLK_PLL_CONFIG[%s] + PLL Configuration Register + 0x600 + 32 + read-write + 0x20116 + 0xB81F1F7F + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-21: illegal (undefined behavior) +22: divide by 22 +... +112: divide by 112 +>112: illegal (undefined behavior) + [6:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +20: divide by 20 +others: illegal (undefined behavior) + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + PLL_LF_MODE + VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. +0: VCO frequency is [200MHz, 400MHz] +1: VCO frequency is [170MHz, 200MHz) + [27:27] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. + 0 + + + AUTO1 + Same as AUTO + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. + +Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled +1: Block is enabled + [31:31] + read-write + + + + + 15 + 4 + CLK_PLL_STATUS[%s] + PLL Status Register + 0x640 + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + SRSS_INTR + SRSS Interrupt Register + 0x700 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. + [0:0] + read-write + + + HVLVD1 + Interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Clock calibration counter is done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_SET + SRSS Interrupt Set Register + 0x704 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Set interrupt for low voltage detector WDT_MATCH + [0:0] + read-write + + + HVLVD1 + Set interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_MASK + SRSS Interrupt Mask Register + 0x708 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. + [0:0] + read-write + + + HVLVD1 + Mask for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Mask for clock calibration done + [5:5] + read-write + + + + + SRSS_INTR_MASKED + SRSS Interrupt Masked Register + 0x70C + 32 + read-only + 0x0 + 0x23 + + + WDT_MATCH + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + HVLVD1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CLK_CAL + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + SRSS_INTR_CFG + SRSS Interrupt Configuration Register + 0x710 + 32 + read-write + 0x0 + 0x3 + + + HVLVD1_EDGE_SEL + Sets which edge(s) will trigger an IRQ for HVLVD1 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + + + RES_CAUSE + Reset Cause Observation Register + 0x800 + 32 + read-write + 0x0 + 0x1FF + + + RESET_WDT + A basic WatchDog Timer (WDT) reset has occurred since last power cycle. + [0:0] + read-write + + + RESET_ACT_FAULT + Fault logging system requested a reset from its Active logic. + [1:1] + read-write + + + RESET_DPSLP_FAULT + Fault logging system requested a reset from its DeepSleep logic. + [2:2] + read-write + + + RESET_CSV_WCO_LOSS + Clock supervision logic requested a reset due to loss of a watch-crystal clock. + [3:3] + read-write + + + RESET_SOFT + A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. + [4:4] + read-write + + + RESET_MCWDT0 + Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. + [5:5] + read-write + + + RESET_MCWDT1 + Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. + [6:6] + read-write + + + RESET_MCWDT2 + Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. + [7:7] + read-write + + + RESET_MCWDT3 + Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. + [8:8] + read-write + + + + + RES_CAUSE2 + Reset Cause Observation Register 2 + 0x804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESET_CSV_HF_LOSS + Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [15:0] + read-write + + + RESET_CSV_HF_FREQ + Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [31:16] + read-write + + + + + PWR_TRIM_REF_CTL + Reference Trim Register + 0x7F00 + 32 + read-write + 0x70F00000 + 0xF1FF5FFF + + + ACT_REF_TCTRIM + Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [3:0] + read-write + + + ACT_REF_ITRIM + Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [7:4] + read-write + + + ACT_REF_ABSTRIM + Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [12:8] + read-write + + + ACT_REF_IBOOST + Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: normal operation +others: risk mitigation + [14:14] + read-write + + + DPSLP_REF_TCTRIM + DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [19:16] + read-write + + + DPSLP_REF_ABSTRIM + DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [24:20] + read-write + + + DPSLP_REF_ITRIM + DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:28] + read-write + + + + + PWR_TRIM_BODOVP_CTL + BOD/OVP Trim Register + 0x7F04 + 32 + read-write + 0x40D04 + 0xFDFF7 + + + HVPORBOD_TRIPSEL + HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [2:0] + read-write + + + HVPORBOD_OFSTRIM + HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [6:4] + read-write + + + HVPORBOD_ITRIM + HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [9:7] + read-write + + + LVPORBOD_TRIPSEL + LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [12:10] + read-write + + + LVPORBOD_OFSTRIM + LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [16:14] + read-write + + + LVPORBOD_ITRIM + LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [19:17] + read-write + + + + + CLK_TRIM_CCO_CTL + CCO Trim Register + 0x7F08 + 32 + read-write + 0xA7000020 + 0xBF00003F + + + CCO_RCSTRIM + CCO reference current source trim. + [5:0] + read-write + + + CCO_STABLE_CNT + Terminal count for the stabilization counter from CCO_ENABLE until stable. + [29:24] + read-write + + + ENABLE_CNT + Enables the automatic stabilization counter. + [31:31] + read-write + + + + + CLK_TRIM_CCO_CTL2 + CCO Trim Register 2 + 0x7F0C + 32 + read-write + 0x884110 + 0x1FFFFFF + + + CCO_FCTRIM1 + CCO frequency 1st range calibration + [4:0] + read-write + + + CCO_FCTRIM2 + CCO frequency 2nd range calibration + [9:5] + read-write + + + CCO_FCTRIM3 + CCO frequency 3rd range calibration + [14:10] + read-write + + + CCO_FCTRIM4 + CCO frequency 4th range calibration + [19:15] + read-write + + + CCO_FCTRIM5 + CCO frequency 5th range calibration + [24:20] + read-write + + + + + PWR_TRIM_WAKE_CTL + Wakeup Trim Register + 0x7F30 + 32 + read-write + 0x0 + 0xFF + + + WAKE_DELAY + Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. + [7:0] + read-write + + + + + PWR_TRIM_LVD_CTL + LVD Trim Register + 0xFF10 + 32 + read-write + 0x20 + 0x77 + + + HVLVD1_OFSTRIM + HVLVD1 offset trim + [2:0] + read-write + + + HVLVD1_ITRIM + HVLVD1 current trim + [6:4] + read-write + + + + + CLK_TRIM_ILO_CTL + ILO Trim Register + 0xFF18 + 32 + read-write + 0x2C + 0x3F + + + ILO_FTRIM + ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + + + PWR_TRIM_PWRSYS_CTL + Power System Trim Register + 0xFF1C + 32 + read-write + 0x17 + 0x1F + + + ACT_REG_TRIM + Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively. + [4:0] + read-write + + + ACT_REG_BOOST + Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: +2'b00: 50uA +2'b01: 100uA +2'b10: 150uA +2'b11: 200uA + +The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. +50mA chip: 2'b00 (default); +100mA chip: 2'b00 (default); +150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); +200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); +250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); +300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); + +This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:30] + read-write + + + + + CLK_TRIM_ECO_CTL + ECO Trim Register + 0xFF20 + 32 + read-write + 0x1F0003 + 0x3F3FF7 + + + WDTRIM + Watch Dog Trim - Delta voltage below steady state level +0x0 - 50mV +0x1 - 75mV +0x2 - 100mV +0x3 - 125mV +0x4 - 150mV +0x5 - 175mV +0x6 - 200mV +0x7 - 225mV + [2:0] + read-write + + + ATRIM + Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. +0x0 - 150mV +0x1 - 175mV +0x2 - 200mV +0x3 - 225mV +0x4 - 250mV +0x5 - 275mV +0x6 - 300mV +0x7 - 325mV +0x8 - 350mV +0x9 - 375mV +0xA - 400mV +0xB - 425mV +0xC - 450mV +0xD - 475mV +0xE - 500mV +0xF - 525mV + [7:4] + read-write + + + FTRIM + Filter Trim - 3rd harmonic oscillation + [9:8] + read-write + + + RTRIM + Feedback resistor Trim + [11:10] + read-write + + + GTRIM + Gain Trim - Startup time + [13:12] + read-write + + + ITRIM + Current Trim + [21:16] + read-write + + + + + CLK_TRIM_PILO_CTL + PILO Trim Register + 0xFF24 + 32 + read-write + 0x108500F + 0x7DFF703F + + + PILO_CFREQ + Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. + [5:0] + read-write + + + PILO_OSC_TRIM + Trim for current in oscillator block. + [14:12] + read-write + + + PILO_COMP_TRIM + Trim for comparator bias current. + [17:16] + read-write + + + PILO_NBIAS_TRIM + Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier + [19:18] + read-write + + + PILO_RES_TRIM + Trim for beta-multiplier branch current + [24:20] + read-write + + + PILO_ISLOPE_TRIM + Trim for beta-multiplier current slope + [27:26] + read-write + + + PILO_VTDIFF_TRIM + Trim for VT-DIFF output (internal power supply) + [30:28] + read-write + + + + + CLK_TRIM_PILO_CTL2 + PILO Trim Register 2 + 0xFF28 + 32 + read-write + 0xDA10E0 + 0xFF1FFF + + + PILO_VREF_TRIM + Trim for voltage reference + [7:0] + read-write + + + PILO_IREFBM_TRIM + Trim for beta-multiplier current reference + [12:8] + read-write + + + PILO_IREF_TRIM + Trim for current reference + [23:16] + read-write + + + + + CLK_TRIM_PILO_CTL3 + PILO Trim Register 3 + 0xFF2C + 32 + read-write + 0x4800 + 0xFFFF + + + PILO_ENGOPT + Engineering options for PILO circuits +0: Short vdda to vpwr +1: Beta:mult current change +2: Iref generation Ptat current addition +3: Disable current path in secondary Beta:mult startup circuit +4: Double oscillator current +5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block +6: Spare +7: Ptat component increase in Iref +8: vpwr_rc and vpwr_dig_rc shorting testmode +9: Switch b/w psub connection for cascode nfet for vref generation +10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. +15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. + [15:0] + read-write + + + + + + + BACKUP + SRSS Backup Domain + 0x40270000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFF0F3308 + + + WCO_EN + Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. +After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. + [3:3] + read-write + + + CLK_SEL + Clock select for BAK clock + [9:8] + read-write + + + WCO + Watch-crystal oscillator input. + 0 + + + ALTBAK + This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. + 1 + + + + + PRESCALER + N/A + [13:12] + read-write + + + WCO_BYPASS + Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. +0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. +1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. + [16:16] + read-write + + + VDDBAK_CTL + Controls the behavior of the switch that generates vddbak from vbackup or vddd. +0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. +1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. + [18:17] + read-write + + + VBACKUP_MEAS + Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. + [19:19] + read-write + + + EN_CHARGE_KEY + When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. + [31:24] + read-write + + + + + RTC_RW + RTC Read Write register + 0x8 + 32 + read-write + 0x0 + 0x3 + + + READ + Read bit +When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. +Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. + [0:0] + read-write + + + WRITE + Write bit +Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. +The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. +Only user RTC registers that were written to will get copied, others will not be affected. +When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). +When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. +Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. + [1:1] + read-write + + + + + CAL_CTL + Oscillator calibration for absolute frequency + 0xC + 32 + read-write + 0x0 + 0x8000007F + + + CALIB_VAL + Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). +Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) + +Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. + [5:0] + read-write + + + CALIB_SIGN + Calibration sign: +0= Negative sign: remove pulses (it takes more clock ticks to count one second) +1= Positive sign: add pulses (it takes less clock ticks to count one second) + [6:6] + read-write + + + CAL_OUT + Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. + [31:31] + read-write + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x0 + 0x5 + + + RTC_BUSY + pending RTC write + [0:0] + read-only + + + WCO_OK + Indicates that output has transitioned. + [2:2] + read-only + + + + + RTC_TIME + Calendar Seconds, Minutes, Hours, Day of Week + 0x14 + 32 + read-write + 0x0 + 0x77F7F7F + + + RTC_SEC + Calendar seconds in BCD, 0-59 + [6:0] + read-write + + + RTC_MIN + Calendar minutes in BCD, 0-59 + [14:8] + read-write + + + RTC_HOUR + Calendar hours in BCD, value depending on 12/24HR mode +0=24HR: [21:16]=0-23 +1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 + [21:16] + read-write + + + CTRL_12HR + Select 12/24HR mode: 1=12HR, 0=24HR + [22:22] + read-write + + + RTC_DAY + Calendar Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + + + RTC_DATE + Calendar Day of Month, Month, Year + 0x18 + 32 + read-write + 0x0 + 0xFF1F3F + + + RTC_DATE + Calendar Day of the Month in BCD, 1-31 +Automatic Leap Year Correction + [5:0] + read-write + + + RTC_MON + Calendar Month in BCD, 1-12 + [12:8] + read-write + + + RTC_YEAR + Calendar year in BCD, 0-99 + [23:16] + read-write + + + + + ALM1_TIME + Alarm 1 Seconds, Minute, Hours, Day of Week + 0x1C + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM1_DATE + Alarm 1 Day of Month, Month + 0x20 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 1. +0: Alarm 1 is disabled. Fields for date and time are ignored. +1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + ALM2_TIME + Alarm 2 Seconds, Minute, Hours, Day of Week + 0x24 + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM2_DATE + Alarm 2 Day of Month, Month + 0x28 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 2. +0: Alarm 2 is disabled. Fields for date and time are ignored. +1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x2C + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Alarm 1 Interrupt + [0:0] + read-write + + + ALARM2 + Alarm 2 Interrupt + [1:1] + read-write + + + CENTURY + Century overflow interrupt + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x30 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x34 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x38 + 32 + read-only + 0x0 + 0x7 + + + ALARM1 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + ALARM2 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CENTURY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + OSCCNT + 32kHz oscillator counter + 0x3C + 32 + read-only + 0x0 + 0xFF + + + CNT32KHZ + 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. + [7:0] + read-only + + + + + TICKS + 128Hz tick counter + 0x40 + 32 + read-only + 0x0 + 0x3F + + + CNT128HZ + 128Hz counter (msb=2Hz) +When SECONDS is written this field will be reset. + [5:0] + read-only + + + + + PMIC_CTL + PMIC control register + 0x44 + 32 + read-write + 0xA0000000 + 0xE001FF00 + + + UNLOCK + This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. + [15:8] + read-write + + + POLARITY + N/A + [16:16] + read-write + + + PMIC_EN_OUTEN + Output enable for the output driver in the PMIC_EN pad. +0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present +1: Output pad is enabled for PMIC_EN pin. + [29:29] + read-write + + + PMIC_ALWAYSEN + Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. +0: Normal operation, PMIC_EN and PMIC_OUTEN work as described +1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. +Note: This bit is a write-once bit until the next backup reset. + [30:30] + read-write + + + PMIC_EN + Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. + [31:31] + read-write + + + + + RESET + Backup reset register + 0x48 + 32 + read-write + 0x0 + 0x80000000 + + + RESET + Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. + [31:31] + read-write + + + + + 64 + 4 + BREG[%s] + Backup register region + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BREG + Backup memory that contains application-specific data. Memory is retained on vbackup supply. + [31:0] + read-write + + + + + TRIM + Trim Register + 0xFF00 + 32 + read-write + 0x0 + 0x3F + + + TRIM + WCO trim + [5:0] + read-write + + + + + + + DW0 + Datawire Controller + DW + 0x40280000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x1 + 0x80000003 + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + ECC_INJ_EN + Enable parity injection for SRAM. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. + [1:1] + read-write + + + ENABLED + IP enable: +'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0xF0000000 + + + P + Active channel, user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + Active channel, secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + B + Active channel, non-bufferable/bufferable access control: +'0': non-bufferable +'1': bufferable. + [2:2] + read-only + + + PC + Active channel protection context. + [7:4] + read-only + + + PRIO + Active channel priority. + [9:8] + read-only + + + PREEMPTABLE + Active channel preemptable. + [11:11] + read-only + + + CH_IDX + Active channel index. + [24:16] + read-only + + + STATE + State of the DW controller. +'0': Default/inactive state. +'1': Loading descriptor. +'2': Loading data element from source location. +'3': Storing data element to destination location. +'4': CRC functionality (only used for CRC transfer descriptor type). +'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. +'6': Error. + [30:28] + read-only + + + ACTIVE + Active channel present: +'0': No. +'1': Yes. + [31:31] + read-only + + + + + ACT_DESCR_CTL + Active descriptor control + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-only + + + + + ACT_DESCR_SRC + Active descriptor source + 0x24 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_SRC of the currently active descriptor. + +Base address of source location. + [31:0] + read-only + + + + + ACT_DESCR_DST + Active descriptor destination + 0x28 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_DST of the currently active descriptor. + +Base address of destination location. + +Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. + [31:0] + read-only + + + + + ACT_DESCR_X_CTL + Active descriptor X loop control + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_X_CTL of the currently active descriptor. + +[11:0] SRC_X_INCR +Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + +[23:12] DST_X_INCR +Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + +Note: this field is not used for CRC transfer descriptors and must be set to '0'. + +[31:24] X_COUNT +Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For a single transfer descriptor type, descriptor will not have X_CTL. + [31:0] + read-only + + + + + ACT_DESCR_Y_CTL + Active descriptor Y loop control + 0x34 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_Y_CTL of the currently active descriptor. + +[11:0] SRC_Y_INCR +Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[23:12] DST_Y_INCR +Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[31:24] Y_COUNT +Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. + [31:0] + read-only + + + + + ACT_DESCR_NEXT_PTR + Active descriptor next pointer + 0x38 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Copy of DESCR_NEXT_PTR of the currently active descriptor. + +[31:2] ADDR +Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + ACT_SRC + Active source + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SRC_ADDR + Current address of source location. + [31:0] + read-only + + + + + ACT_DST + Active destination + 0x44 + 32 + read-only + 0x0 + 0x0 + + + DST_ADDR + Current address of destination location. + [31:0] + read-only + + + + + ECC_CTL + ECC control + 0x80 + 32 + read-write + 0x0 + 0xFE0003FF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [9:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + CRC_CTL + CRC control + 0x100 + 32 + read-write + 0x0 + 0x101 + + + DATA_REVERSE + Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): +'0': Most significant bit (bit 1) first. +'1': Least significant bit (bit 0) first. + [0:0] + read-write + + + REM_REVERSE + Specifies whether the remainder is bit reversed (reversal is performed after XORing): +'0': No. +'1': Yes. + [8:8] + read-write + + + + + CRC_DATA_CTL + CRC data control + 0x110 + 32 + read-write + 0x0 + 0xFF + + + DATA_XOR + Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. + [7:0] + read-write + + + + + CRC_POL_CTL + CRC polynomial control + 0x120 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POLYNOMIAL + CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: +- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). +- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). +- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). + [31:0] + read-write + + + + + CRC_LFSR_CTL + CRC LFSR control + 0x130 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LFSR32 + State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. + +The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. + +Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). + [31:0] + read-write + + + + + CRC_REM_CTL + CRC remainder control + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REM_XOR + Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. + [31:0] + read-write + + + + + CRC_REM_RESULT + CRC remainder result + 0x148 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REM + Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: +'0': the more significant bits (bit 31 and down) contain the remainder. +'1': the less significant bits (bit 0 and up) contain the remainder. + +Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. + [31:0] + read-only + + + + + 29 + 64 + CH_STRUCT[%s] + DW channel structure + 0x00008000 + + CH_CTL + Channel control + 0x0 + 32 + read-write + 0x0 + 0x80000300 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). + [9:8] + read-write + + + PREEMPTABLE + Specifies if the channel is preemptable. +'0': Not preemptable. +'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. + [11:11] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). + [31:31] + read-write + + + + + CH_STATUS + Channel status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + INTR_CAUSE + Specifies the source of the interrupt cause: +'0': No interrupt generated +'1': Interrupt based on transfer complettion configuration based on INTR_TYPE +'2': Source transfer bus error +'3': Destination transfer bus error +'4': Source address misalignment +'5': Destination address misalignment +'6': Current descriptor pointer is null +'7': Active channel is disabled +'8': Descriptor bus error +'9'-'15': Not used. + +For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). + [3:0] + read-only + + + PENDING + Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). + [31:31] + read-only + + + + + CH_IDX + Channel current indices + 0x8 + 32 + read-write + 0x0 + 0x0 + + + X_IDX + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [7:0] + read-write + + + Y_IDX + Specifies the Y loop index, with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [15:8] + read-write + + + + + CH_CURR_PTR + Channel current descriptor pointer + 0xC + 32 + read-write + 0x0 + 0x0 + + + ADDR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. + [31:2] + read-write + + + + + INTR + Interrupt + 0x10 + 32 + read-write + 0x0 + 0x1 + + + CH + Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x14 + 32 + read-write + 0x0 + 0x1 + + + CH + Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x18 + 32 + read-write + 0x0 + 0x1 + + + CH + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x1C + 32 + read-only + 0x0 + 0x1 + + + CH + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + SRAM_DATA0 + SRAM data 0 + 0x20 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + SRAM_DATA1 + SRAM data 1 + 0x24 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + TR_CMD + Channel software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + + + + DW1 + 0x40290000 + + + DMAC + DMAC + 0x402A0000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + ACTIVE + Active channels + 0x8 + 32 + read-only + 0x0 + 0xFF + + + ACTIVE + Specifies active channels; i.e. enabled channels whose trigger got activated. + [7:0] + read-only + + + + + 4 + 256 + CH[%s] + DMA controller channel + 0x00001000 + + CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x800003F7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. +A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. + [9:8] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' when an error interrupt cause is activated. + [31:31] + read-write + + + + + IDX + Channel current indices + 0x10 + 32 + read-only + 0x0 + 0x0 + + + X + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor. + [15:0] + read-only + + + Y + Specifies the Y loop index, with Y_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor.. + [31:16] + read-only + + + + + SRC + Channel current source address + 0x14 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of source location. + [31:0] + read-only + + + + + DST + Channel current destination address + 0x18 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of destination location. + [31:0] + read-only + + + + + CURR + Channel current descriptor pointer + 0x20 + 32 + read-write + 0x0 + 0x0 + + + PTR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + [31:2] + read-write + + + + + TR_CMD + Channle software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + DESCR_STATUS + Channel descriptor status + 0x40 + 32 + read-only + 0x0 + 0x80000000 + + + VALID + Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. + [31:31] + read-only + + + + + DESCR_CTL + Channel descriptor control + 0x60 + 32 + read-only + 0x0 + 0x0 + + + WAIT_FOR_DEACT + Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. +'0': Do not wait for trigger de-activation (for pulse sensitive triggers). +'1': Wait for up to 4 cycles. +'2': Wait for up to 16 cycles. +'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. + [1:0] + read-only + + + INTR_TYPE + Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): +'0': An interrupt is generated after a single transfer. +'1': An interrupt is generated after a single 1D transfer or a memory copy transfer +- If the descriptor type is 'single', the interrupt is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. +'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). +'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [3:2] + read-only + + + TR_OUT_TYPE + Specifies when an output trigger is generated: +'0': An output trigger is generated after a single transfer. +'1': An output trigger is generated after a single 1D transfer or a memory copy transfer. +- If the descriptor type is 'single', the output trigger is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. +'2': An output trigger is generated after the execution of the current descriptor. +'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [5:4] + read-only + + + TR_IN_TYPE + Specifies the input trigger type (not to be confused with the descriptor type): +'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. +'1': A trigger results in the execution of a single 1D transfer. +- If the descriptor type is 'single', the trigger results in the execution of a single transfer. +- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. +'2': A trigger results in the execution of the current descriptor. +'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. + [7:6] + read-only + + + DATA_PREFETCH + Source data prefetch: +'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. +'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. + +Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. + [8:8] + read-only + + + DATA_SIZE + Specifies the data element size: +'0': Byte (8 bits). +'1': Halfword (16 bits). +'2': Word (32 bits). +DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: +- DATA is 8 bit, SRC is 8 bit, DST is 8 bit. +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. +- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). +- DATA is 16 bit, SRC is 16 bit, DST is 16 bit. +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. +- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). +- DATA is 32 bit, SRC is 32 bit, DST is 32 bit. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. + [17:16] + read-only + + + CH_DISABLE + Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): +'0': Channel is not disabled. +'1': Channel is disabled. + [24:24] + read-only + + + SRC_TRANSFER_SIZE + Specifies the bus transfer size to the source location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [26:26] + read-only + + + DST_TRANSFER_SIZE + Specifies the bus transfer size to the destination location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [27:27] + read-only + + + DESCR_TYPE + Specifies the descriptor type (not to be confused with the trigger type): +'0': Single transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. +'1': 1D transfer. +The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. +'2': 2D transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. +'3': Memory copy. +The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. +'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. +'5'-'7': Undefined. + +After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. + [30:28] + read-only + + + + + DESCR_SRC + Channel descriptor source + 0x64 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of source location. + [31:0] + read-only + + + + + DESCR_DST + Channel descriptor destination + 0x68 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of destination location. + [31:0] + read-only + + + + + DESCR_X_SIZE + Channel descriptor X size + 0x6C + 32 + read-only + 0x0 + 0x0 + + + X_COUNT + Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + +For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. + [15:0] + read-only + + + + + DESCR_X_INCR + Channel descriptor X increment + 0x70 + 32 + read-only + 0x0 + 0x0 + + + SRC_X + Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + [15:0] + read-only + + + DST_X + Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + [31:16] + read-only + + + + + DESCR_Y_SIZE + Channel descriptor Y size + 0x74 + 32 + read-only + 0x0 + 0x0 + + + Y_COUNT + Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + [15:0] + read-only + + + + + DESCR_Y_INCR + Channel descriptor Y increment + 0x78 + 32 + read-only + 0x0 + 0x0 + + + SRC_Y + Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [15:0] + read-only + + + DST_Y + Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [31:16] + read-only + + + + + DESCR_NEXT + Channel descriptor next pointer + 0x7C + 32 + read-only + 0x0 + 0x0 + + + PTR + Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + INTR + Interrupt + 0x80 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. + [0:0] + read-write + + + SRC_BUS_ERROR + Activated (set to '1') on a bus error for a load from the source. + [1:1] + read-write + + + DST_BUS_ERROR + Activated (set to '1') on a bus error for a store to the destination. + [2:2] + read-write + + + SRC_MISAL + Activated (set to '1') on a misalignment of the source address. + [3:3] + read-write + + + DST_MISAL + Activated (set to '1') on a misalignment of the destination address. + [4:4] + read-write + + + CURR_PTR_NULL + Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. + [6:6] + read-write + + + DESCR_BUS_ERROR + Activated (set to '1') on a bus error for a load of the descriptor. + [7:7] + read-write + + + + + INTR_SET + Interrupt set + 0x84 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). + [0:0] + read-write + + + SRC_BUS_ERROR + Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). + [1:1] + read-write + + + DST_BUS_ERROR + Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). + [2:2] + read-write + + + SRC_MISAL + Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). + [3:3] + read-write + + + DST_MISAL + Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). + [4:4] + read-write + + + CURR_PTR_NULL + Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). + [6:6] + read-write + + + DESCR_BUS_ERROR + Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask + 0x88 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Mask for INTR.COMPLETION interrupt. + [0:0] + read-write + + + SRC_BUS_ERROR + Mask for INTR.SRC_BUS_ERROR interrupt. + [1:1] + read-write + + + DST_BUS_ERROR + Mask for INTR.DST_BUS_ERROR interrupt. + [2:2] + read-write + + + SRC_MISAL + Mask for INTR.SRC_MISAL interrupt. + [3:3] + read-write + + + DST_MISAL + Mask for INTR.DST_MISAL interrupt. + [4:4] + read-write + + + CURR_PTR_NULL + Mask for INTR.CURR_PTR_NULL interrupt. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Mask for INTR.ACTIVE_CH_DISABLED interrupt. + [6:6] + read-write + + + DESCR_BUS_ERROR + Mask for INTR.DESCR_BUS_ERROR interrupt. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x8C + 32 + read-only + 0x0 + 0xFF + + + COMPLETION + Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. + [0:0] + read-only + + + SRC_BUS_ERROR + Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. + [1:1] + read-only + + + DST_BUS_ERROR + Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. + [2:2] + read-only + + + SRC_MISAL + Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. + [3:3] + read-only + + + DST_MISAL + Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. + [4:4] + read-only + + + CURR_PTR_NULL + Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. + [5:5] + read-only + + + ACTIVE_CH_DISABLED + Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. + [6:6] + read-only + + + DESCR_BUS_ERROR + Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. + [7:7] + read-only + + + + + + + + EFUSE + EFUSE MXS40 registers + 0x402C0000 + + 0 + 128 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + + + CMD + Command + 0x10 + 32 + read-write + 0x1 + 0x800F1F71 + + + BIT_DATA + Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. + [0:0] + read-write + + + BIT_ADDR + Bit address. This field specifies a bit within a Byte. + [6:4] + read-write + + + BYTE_ADDR + Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). + [12:8] + read-write + + + MACRO_ADDR + Macro address. This field specifies an eFUSE macro. + [19:16] + read-write + + + START + FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. + +Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. + +Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. + +Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. + [31:31] + read-write + + + + + SEQ_DEFAULT + Sequencer Default value + 0x20 + 32 + read-write + 0x1D0000 + 0x7F0000 + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + + + SEQ_READ_CTL_0 + Sequencer read control 0 + 0x40 + 32 + read-write + 0x80560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_1 + Sequencer read control 1 + 0x44 + 32 + read-write + 0x540004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_2 + Sequencer read control 2 + 0x48 + 32 + read-write + 0x560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_3 + Sequencer read control 3 + 0x4C + 32 + read-write + 0x540003 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_4 + Sequencer read control 4 + 0x50 + 32 + read-write + 0x80150001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_5 + Sequencer read control 5 + 0x54 + 32 + read-write + 0x310004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_0 + Sequencer program control 0 + 0x60 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_1 + Sequencer program control 1 + 0x64 + 32 + read-write + 0x220020 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_2 + Sequencer program control 2 + 0x68 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_3 + Sequencer program control 3 + 0x6C + 32 + read-write + 0x310005 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_4 + Sequencer program control 4 + 0x70 + 32 + read-write + 0x80350006 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_5 + Sequencer program control 5 + 0x74 + 32 + read-write + 0x803D0019 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + + + PROFILE + Energy Profiler IP + 0x402D0000 + + 0 + 65536 + registers + + + + CTL + Profile control + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + WIN_MODE + Specifies the profiling time window mode: +'0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs. +In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped. +'1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect. + [0:0] + read-write + + + ENABLED + Enables the profiling block: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Profile status + 0x4 + 32 + read-only + 0x0 + 0x1 + + + WIN_ACTIVE + Indicates if the profiling time window is active. +'0': Not active. +'1': Active. + [0:0] + read-only + + + + + CMD + Profile command + 0x10 + 32 + read-write + 0x0 + 0x103 + + + START_TR + Software start trigger for the profiling time window. When written with '1', the profiling time window is started. +Can only be used in start / stop mode (PROFILE_WIN_MODE=0). +Has no effect in enable mode (PROFILE_WIN_MODE=1). + [0:0] + read-write + + + STOP_TR + Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped. +Can only be used in start / stop mode (PROFILE_WIN_MODE=0). +Has no effect in enable mode (PROFILE_WIN_MODE=1). + [1:1] + read-write + + + CLR_ALL_CNT + Counter clear. When written with '1', all profiling counter registers are cleared to 0x00. + [8:8] + read-write + + + + + INTR + Profile interrupt + 0x7C0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter. + +SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0'). + [31:0] + read-write + + + + + INTR_SET + Profile interrupt set + 0x7C4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register. + [31:0] + read-write + + + + + INTR_MASK + Profile interrupt mask + 0x7C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + Mask bit for corresponding field in the INTR register. + [31:0] + read-write + + + + + INTR_MASKED + Profile interrupt masked + 0x7CC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CNT_OVFLW + Logical and of corresponding INTR and INTR_MASK fields. + [31:0] + read-only + + + + + 8 + 16 + CNT_STRUCT[%s] + Profile counter structure + 0x00000800 + + CTL + Profile counter configuration + 0x0 + 32 + read-write + 0x0 + 0x807F0071 + + + CNT_DURATION + This field specifies if events (edges) or a duration of the monitor signal is counted. +'0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. +'1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. + +Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results. + [0:0] + read-write + + + REF_CLK_SEL + This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0. + [6:4] + read-write + + + CLK_TIMER + Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL. + 0 + + + CLK_IMO + IMO - Internal Main Oscillator + 1 + + + CLK_ECO + ECO - External-Crystal Oscillator + 2 + + + CLK_LF + Low frequency clock (ILO, WCO or ALTLF). +Selection is done in SRSS register CLK_SELECT.LFCLK_SEL. + 3 + + + CLK_HF + High frequuency clock ('clk_hfx'). + 4 + + + CLK_PERI + Peripheral clock ('clk_peri'). + 5 + + + RSVD_6 + N/A + 6 + + + RSVD_7 + N/A + 7 + + + + + MON_SEL + This field specifies the montior input signal to be observed by the profiling counter. +The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details. + [22:16] + read-write + + + ENABLED + Enables the profiling counter: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CNT + Profile counter value + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT + This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter. + [31:0] + read-write + + + + + + + + HSIOM + High Speed IO Matrix (HSIOM) + 0x40300000 + + 0 + 16384 + registers + + + + 15 + 16 + PRT[%s] + HSIOM port registers + 0x00000000 + + PORT_SEL0 + Port selection 0 + 0x0 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO0_SEL + Selects connection for IO pin 0 route. + [4:0] + read-write + + + GPIO + GPIO controls 'out' + 0 + + + GPIO_DSI + GPIO controls 'out', DSI controls 'output enable' + 1 + + + DSI_DSI + DSI controls 'out' and 'output enable' + 2 + + + DSI_GPIO + DSI controls 'out', GPIO controls 'output enable' + 3 + + + AMUXA + Analog mux bus A + 4 + + + AMUXB + Analog mux bus B + 5 + + + AMUXA_DSI + Analog mux bus A, DSI control + 6 + + + AMUXB_DSI + Analog mux bus B, DSI control + 7 + + + ACT_0 + Active functionality 0 + 8 + + + ACT_1 + Active functionality 1 + 9 + + + ACT_2 + Active functionality 2 + 10 + + + ACT_3 + Active functionality 3 + 11 + + + DS_0 + DeepSleep functionality 0 + 12 + + + DS_1 + DeepSleep functionality 1 + 13 + + + DS_2 + DeepSleep functionality 2 + 14 + + + DS_3 + DeepSleep functionality 3 + 15 + + + ACT_4 + Active functionality 4 + 16 + + + ACT_5 + Active functionality 5 + 17 + + + ACT_6 + Active functionality 6 + 18 + + + ACT_7 + Active functionality 7 + 19 + + + ACT_8 + Active functionality 8 + 20 + + + ACT_9 + Active functionality 9 + 21 + + + ACT_10 + Active functionality 10 + 22 + + + ACT_11 + Active functionality 11 + 23 + + + ACT_12 + Active functionality 12 + 24 + + + ACT_13 + Active functionality 13 + 25 + + + ACT_14 + Active functionality 14 + 26 + + + ACT_15 + Active functionality 15 + 27 + + + DS_4 + DeepSleep functionality 4 + 28 + + + DS_5 + DeepSleep functionality 5 + 29 + + + DS_6 + DeepSleep functionality 6 + 30 + + + DS_7 + DeepSleep functionality 7 + 31 + + + + + IO1_SEL + Selects connection for IO pin 1 route. + [12:8] + read-write + + + IO2_SEL + Selects connection for IO pin 2 route. + [20:16] + read-write + + + IO3_SEL + Selects connection for IO pin 3 route. + [28:24] + read-write + + + + + PORT_SEL1 + Port selection 1 + 0x4 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO4_SEL + Selects connection for IO pin 4 route. +See PORT_SEL0 for connection details. + [4:0] + read-write + + + IO5_SEL + Selects connection for IO pin 5 route. + [12:8] + read-write + + + IO6_SEL + Selects connection for IO pin 6 route. + [20:16] + read-write + + + IO7_SEL + Selects connection for IO pin 7 route. + [28:24] + read-write + + + + + + 64 + 4 + AMUX_SPLIT_CTL[%s] + AMUX splitter cell control + 0x2000 + 32 + read-write + 0x0 + 0x77 + + + SWITCH_AA_SL + T-switch control for Left AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [0:0] + read-write + + + SWITCH_AA_SR + T-switch control for Right AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [1:1] + read-write + + + SWITCH_AA_S0 + T-switch control for AMUXBUSA vssa/ground switch: +'0': switch open. +'1': switch closed. + [2:2] + read-write + + + SWITCH_BB_SL + T-switch control for Left AMUXBUSB switch. + [4:4] + read-write + + + SWITCH_BB_SR + T-switch control for Right AMUXBUSB switch. + [5:5] + read-write + + + SWITCH_BB_S0 + T-switch control for AMUXBUSB vssa/ground switch. + [6:6] + read-write + + + + + MONITOR_CTL_0 + Power/Ground Monitor cell control 0 + 0x2200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_1 + Power/Ground Monitor cell control 1 + 0x2204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_2 + Power/Ground Monitor cell control 2 + 0x2208 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_3 + Power/Ground Monitor cell control 3 + 0x220C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + ALT_JTAG_EN + Alternate JTAG IF selection register + 0x2240 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + Provides the selection for alternate JTAG IF connectivity. +0: Primary JTAG interface is selected +1: Secondary (alternate) JTAG interface is selected. + +This connectivity works ONLY in ACTIVE mode. + [31:31] + read-write + + + + + + + GPIO + GPIO port control/configuration + 0x40310000 + + 0 + 65536 + registers + + + + 15 + 128 + PRT[%s] + GPIO port registers + 0x00000000 + + OUT + Port output data register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO output data for pin 0 +'0': Output state set to '0' +'1': Output state set to '1' + [0:0] + read-write + + + OUT1 + IO output data for pin 1 + [1:1] + read-write + + + OUT2 + IO output data for pin 2 + [2:2] + read-write + + + OUT3 + IO output data for pin 3 + [3:3] + read-write + + + OUT4 + IO output data for pin 4 + [4:4] + read-write + + + OUT5 + IO output data for pin 5 + [5:5] + read-write + + + OUT6 + IO output data for pin 6 + [6:6] + read-write + + + OUT7 + IO output data for pin 7 + [7:7] + read-write + + + + + OUT_CLR + Port output data clear register + 0x4 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO clear output for pin 0: +'0': Output state not affected. +'1': Output state set to '0'. + [0:0] + read-write + + + OUT1 + IO clear output for pin 1 + [1:1] + read-write + + + OUT2 + IO clear output for pin 2 + [2:2] + read-write + + + OUT3 + IO clear output for pin 3 + [3:3] + read-write + + + OUT4 + IO clear output for pin 4 + [4:4] + read-write + + + OUT5 + IO clear output for pin 5 + [5:5] + read-write + + + OUT6 + IO clear output for pin 6 + [6:6] + read-write + + + OUT7 + IO clear output for pin 7 + [7:7] + read-write + + + + + OUT_SET + Port output data set register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO set output for pin 0: +'0': Output state not affected. +'1': Output state set to '1'. + [0:0] + read-write + + + OUT1 + IO set output for pin 1 + [1:1] + read-write + + + OUT2 + IO set output for pin 2 + [2:2] + read-write + + + OUT3 + IO set output for pin 3 + [3:3] + read-write + + + OUT4 + IO set output for pin 4 + [4:4] + read-write + + + OUT5 + IO set output for pin 5 + [5:5] + read-write + + + OUT6 + IO set output for pin 6 + [6:6] + read-write + + + OUT7 + IO set output for pin 7 + [7:7] + read-write + + + + + OUT_INV + Port output data invert register + 0xC + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO invert output for pin 0: +'0': Output state not affected. +'1': Output state inverted ('0' => '1', '1' => '0'). + [0:0] + read-write + + + OUT1 + IO invert output for pin 1 + [1:1] + read-write + + + OUT2 + IO invert output for pin 2 + [2:2] + read-write + + + OUT3 + IO invert output for pin 3 + [3:3] + read-write + + + OUT4 + IO invert output for pin 4 + [4:4] + read-write + + + OUT5 + IO invert output for pin 5 + [5:5] + read-write + + + OUT6 + IO invert output for pin 6 + [6:6] + read-write + + + OUT7 + IO invert output for pin 7 + [7:7] + read-write + + + + + IN + Port input state register + 0x10 + 32 + read-only + 0x0 + 0x1FF + + + IN0 + IO pin state for pin 0 +'0': Low logic level present on pin. +'1': High logic level present on pin. +On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. + [0:0] + read-only + + + IN1 + IO pin state for pin 1 + [1:1] + read-only + + + IN2 + IO pin state for pin 2 + [2:2] + read-only + + + IN3 + IO pin state for pin 3 + [3:3] + read-only + + + IN4 + IO pin state for pin 4 + [4:4] + read-only + + + IN5 + IO pin state for pin 5 + [5:5] + read-only + + + IN6 + IO pin state for pin 6 + [6:6] + read-only + + + IN7 + IO pin state for pin 7 + [7:7] + read-only + + + FLT_IN + Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. + [8:8] + read-only + + + + + INTR + Port interrupt status register + 0x14 + 32 + read-write + 0x0 + 0x1FF01FF + + + EDGE0 + Edge detect for IO pin 0 +'0': No edge was detected on pin. +'1': An edge was detected on pin. + [0:0] + read-write + + + EDGE1 + Edge detect for IO pin 1 + [1:1] + read-write + + + EDGE2 + Edge detect for IO pin 2 + [2:2] + read-write + + + EDGE3 + Edge detect for IO pin 3 + [3:3] + read-write + + + EDGE4 + Edge detect for IO pin 4 + [4:4] + read-write + + + EDGE5 + Edge detect for IO pin 5 + [5:5] + read-write + + + EDGE6 + Edge detect for IO pin 6 + [6:6] + read-write + + + EDGE7 + Edge detect for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Edge detected on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + IN_IN0 + IO pin state for pin 0 + [16:16] + read-only + + + IN_IN1 + IO pin state for pin 1 + [17:17] + read-only + + + IN_IN2 + IO pin state for pin 2 + [18:18] + read-only + + + IN_IN3 + IO pin state for pin 3 + [19:19] + read-only + + + IN_IN4 + IO pin state for pin 4 + [20:20] + read-only + + + IN_IN5 + IO pin state for pin 5 + [21:21] + read-only + + + IN_IN6 + IO pin state for pin 6 + [22:22] + read-only + + + IN_IN7 + IO pin state for pin 7 + [23:23] + read-only + + + FLT_IN_IN + Filtered pin state for pin selected by INTR_CFG.FLT_SEL + [24:24] + read-only + + + + + INTR_MASK + Port interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Masks edge interrupt on IO pin 0 +'0': Pin interrupt forwarding disabled +'1': Pin interrupt forwarding enabled + [0:0] + read-write + + + EDGE1 + Masks edge interrupt on IO pin 1 + [1:1] + read-write + + + EDGE2 + Masks edge interrupt on IO pin 2 + [2:2] + read-write + + + EDGE3 + Masks edge interrupt on IO pin 3 + [3:3] + read-write + + + EDGE4 + Masks edge interrupt on IO pin 4 + [4:4] + read-write + + + EDGE5 + Masks edge interrupt on IO pin 5 + [5:5] + read-write + + + EDGE6 + Masks edge interrupt on IO pin 6 + [6:6] + read-write + + + EDGE7 + Masks edge interrupt on IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_MASKED + Port interrupt masked status register + 0x1C + 32 + read-only + 0x0 + 0x1FF + + + EDGE0 + Edge detected AND masked on IO pin 0 +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [0:0] + read-only + + + EDGE1 + Edge detected and masked on IO pin 1 + [1:1] + read-only + + + EDGE2 + Edge detected and masked on IO pin 2 + [2:2] + read-only + + + EDGE3 + Edge detected and masked on IO pin 3 + [3:3] + read-only + + + EDGE4 + Edge detected and masked on IO pin 4 + [4:4] + read-only + + + EDGE5 + Edge detected and masked on IO pin 5 + [5:5] + read-only + + + EDGE6 + Edge detected and masked on IO pin 6 + [6:6] + read-only + + + EDGE7 + Edge detected and masked on IO pin 7 + [7:7] + read-only + + + FLT_EDGE + Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-only + + + + + INTR_SET + Port interrupt set register + 0x20 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Sets edge detect interrupt for IO pin 0 +'0': Interrupt state not affected +'1': Interrupt set + [0:0] + read-write + + + EDGE1 + Sets edge detect interrupt for IO pin 1 + [1:1] + read-write + + + EDGE2 + Sets edge detect interrupt for IO pin 2 + [2:2] + read-write + + + EDGE3 + Sets edge detect interrupt for IO pin 3 + [3:3] + read-write + + + EDGE4 + Sets edge detect interrupt for IO pin 4 + [4:4] + read-write + + + EDGE5 + Sets edge detect interrupt for IO pin 5 + [5:5] + read-write + + + EDGE6 + Sets edge detect interrupt for IO pin 6 + [6:6] + read-write + + + EDGE7 + Sets edge detect interrupt for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_CFG + Port interrupt configuration register + 0x40 + 32 + read-write + 0x0 + 0x1FFFFF + + + EDGE0_SEL + Sets which edge will trigger an IRQ for IO pin 0 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + EDGE1_SEL + Sets which edge will trigger an IRQ for IO pin 1 + [3:2] + read-write + + + EDGE2_SEL + Sets which edge will trigger an IRQ for IO pin 2 + [5:4] + read-write + + + EDGE3_SEL + Sets which edge will trigger an IRQ for IO pin 3 + [7:6] + read-write + + + EDGE4_SEL + Sets which edge will trigger an IRQ for IO pin 4 + [9:8] + read-write + + + EDGE5_SEL + Sets which edge will trigger an IRQ for IO pin 5 + [11:10] + read-write + + + EDGE6_SEL + Sets which edge will trigger an IRQ for IO pin 6 + [13:12] + read-write + + + EDGE7_SEL + Sets which edge will trigger an IRQ for IO pin 7 + [15:14] + read-write + + + FLT_EDGE_SEL + Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + FLT_SEL + Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. + [20:18] + read-write + + + + + CFG + Port configuration register + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DRIVE_MODE0 + The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [2:0] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Weak/resistive pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull up + D_OUT = '1': Weak/resistive pull up + 2 + + + PULLDOWN + Resistive pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': High Impedance +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 4 + + + OD_DRIVESHIGH + Open drain, drives high + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': High Impedance + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 5 + + + STRONG + Strong D_OUTput buffer + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 6 + + + PULLUP_DOWN + Pull up or pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = '0': + GPIO_DSI_OUT = '0': Weak/resistive pull down + GPIO_DSI_OUT = '1': Weak/resistive pull up +where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull up + 7 + + + + + IN_EN0 + Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. +'0': Input buffer disabled +'1': Input buffer enabled + [3:3] + read-write + + + DRIVE_MODE1 + The GPIO drive mode for IO pin 1 + [6:4] + read-write + + + IN_EN1 + Enables the input buffer for IO pin 1 + [7:7] + read-write + + + DRIVE_MODE2 + The GPIO drive mode for IO pin 2 + [10:8] + read-write + + + IN_EN2 + Enables the input buffer for IO pin 2 + [11:11] + read-write + + + DRIVE_MODE3 + The GPIO drive mode for IO pin 3 + [14:12] + read-write + + + IN_EN3 + Enables the input buffer for IO pin 3 + [15:15] + read-write + + + DRIVE_MODE4 + The GPIO drive mode for IO pin4 + [18:16] + read-write + + + IN_EN4 + Enables the input buffer for IO pin 4 + [19:19] + read-write + + + DRIVE_MODE5 + The GPIO drive mode for IO pin 5 + [22:20] + read-write + + + IN_EN5 + Enables the input buffer for IO pin 5 + [23:23] + read-write + + + DRIVE_MODE6 + The GPIO drive mode for IO pin 6 + [26:24] + read-write + + + IN_EN6 + Enables the input buffer for IO pin 6 + [27:27] + read-write + + + DRIVE_MODE7 + The GPIO drive mode for IO pin 7 + [30:28] + read-write + + + IN_EN7 + Enables the input buffer for IO pin 7 + [31:31] + read-write + + + + + CFG_IN + Port input buffer configuration register + 0x48 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_0 + Configures the pin 0 input buffer mode (trip points and hysteresis) + [0:0] + read-write + + + CMOS + PSoC 6:: Input buffer compatible with CMOS and I2C interfaces +Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 0 + + + TTL + PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces +Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 1 + + + + + VTRIP_SEL1_0 + Configures the pin 1 input buffer mode (trip points and hysteresis) + [1:1] + read-write + + + VTRIP_SEL2_0 + Configures the pin 2 input buffer mode (trip points and hysteresis) + [2:2] + read-write + + + VTRIP_SEL3_0 + Configures the pin 3 input buffer mode (trip points and hysteresis) + [3:3] + read-write + + + VTRIP_SEL4_0 + Configures the pin 4 input buffer mode (trip points and hysteresis) + [4:4] + read-write + + + VTRIP_SEL5_0 + Configures the pin 5 input buffer mode (trip points and hysteresis) + [5:5] + read-write + + + VTRIP_SEL6_0 + Configures the pin 6 input buffer mode (trip points and hysteresis) + [6:6] + read-write + + + VTRIP_SEL7_0 + Configures the pin 7 input buffer mode (trip points and hysteresis) + [7:7] + read-write + + + + + CFG_OUT + Port output buffer configuration register + 0x4C + 32 + read-write + 0x0 + 0xFFFF00FF + + + SLOW0 + Enables slow slew rate for IO pin 0 +'0': Fast slew rate +'1': Slow slew rate + [0:0] + read-write + + + SLOW1 + Enables slow slew rate for IO pin 1 + [1:1] + read-write + + + SLOW2 + Enables slow slew rate for IO pin 2 + [2:2] + read-write + + + SLOW3 + Enables slow slew rate for IO pin 3 + [3:3] + read-write + + + SLOW4 + Enables slow slew rate for IO pin 4 + [4:4] + read-write + + + SLOW5 + Enables slow slew rate for IO pin 5 + [5:5] + read-write + + + SLOW6 + Enables slow slew rate for IO pin 6 + [6:6] + read-write + + + SLOW7 + Enables slow slew rate for IO pin 7 + [7:7] + read-write + + + DRIVE_SEL0 + Sets the GPIO drive strength for IO pin 0 + [17:16] + read-write + + + DRIVE_SEL_ZERO + Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +Traveo II:_GPIO_SMC: GPIO_SMC default mode. +Traveo II:_HSIO_STD: HSIO default mode. +PSoC 6: GPIO cells and HSIO_STD cells: Full drive strength: GPIO drives current at its max rated spec. + 0 + + + DRIVE_SEL_ONE + Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +Traveo II:_GPIO_SMC: GPIO full drive strength. +Traveo II:_HSIO_STD: GPIO full drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec + 1 + + + DRIVE_SEL_TWO + Traveo II: GPIO_STD/GPIO_ENH: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec. +Traveo II:_GPIO_SMC: GPIO 1/2 drive strength. +Traveo II:_HSIO_STD: GPIO 1/2 drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/4 drive strength. GPIO drives current at 1/4 of its max rated spec. + 2 + + + DRIVE_SEL_THREE + Traveo II: GPIO_STD/GPIO_ENH: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec. +Traveo II:_GPIO_SMC: GPIO 1/4 drive strength. +Traveo II:_HSIO_STD: GPIO 1/4 drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/8 drive strength. GPIO drives current at 1/8 of its max rated spec. + 3 + + + + + DRIVE_SEL1 + Sets the GPIO drive strength for IO pin 1 + [19:18] + read-write + + + DRIVE_SEL2 + Sets the GPIO drive strength for IO pin 2 + [21:20] + read-write + + + DRIVE_SEL3 + Sets the GPIO drive strength for IO pin 3 + [23:22] + read-write + + + DRIVE_SEL4 + Sets the GPIO drive strength for IO pin 4 + [25:24] + read-write + + + DRIVE_SEL5 + Sets the GPIO drive strength for IO pin 5 + [27:26] + read-write + + + DRIVE_SEL6 + Sets the GPIO drive strength for IO pin 6 + [29:28] + read-write + + + DRIVE_SEL7 + Sets the GPIO drive strength for IO pin 7 + [31:30] + read-write + + + + + CFG_SIO + Port SIO configuration register + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VREG_EN01 + Selects the output buffer mode: +'0': Unregulated output buffer +'1': Regulated output buffer +The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. + [0:0] + read-write + + + IBUF_SEL01 + Selects the input buffer mode: +0: Singled ended input buffer +1: Differential input buffer + [1:1] + read-write + + + VTRIP_SEL01 + Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): +'0': Input buffer functions as a CMOS input buffer. +'1': Input buffer functions as a TTL input buffer. +In differential input buffer mode (IBUF_SEL = '1') +'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) +'1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) + [2:2] + read-write + + + VREF_SEL01 + Selects reference voltage (Vref) trip-point of the input buffer: +'0': Trip-point reference from pin_ref +'1': Trip-point reference of SRSS internal reference Vref (1.2 V) +'2': Trip-point reference of AMUXBUS_A +'3': Trip-point reference of AMUXBUS_B + [4:3] + read-write + + + VOH_SEL01 + Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). +'0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V +'1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V +'2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V +'3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V +'4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V +'5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V +'6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V +'7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V +Note: The upper value on Voh is limited to Vddio - 400mV + [7:5] + read-write + + + VREG_EN23 + See corresponding definition for IO pins 0 and 1 + [8:8] + read-write + + + IBUF_SEL23 + See corresponding definition for IO pins 0 and 1 + [9:9] + read-write + + + VTRIP_SEL23 + See corresponding definition for IO pins 0 and 1 + [10:10] + read-write + + + VREF_SEL23 + See corresponding definition for IO pins 0 and 1 + [12:11] + read-write + + + VOH_SEL23 + See corresponding definition for IO pins 0 and 1 + [15:13] + read-write + + + VREG_EN45 + See corresponding definition for IO pins 0 and 1 + [16:16] + read-write + + + IBUF_SEL45 + See corresponding definition for IO pins 0 and 1 + [17:17] + read-write + + + VTRIP_SEL45 + See corresponding definition for IO pins 0 and 1 + [18:18] + read-write + + + VREF_SEL45 + See corresponding definition for IO pins 0 and 1 + [20:19] + read-write + + + VOH_SEL45 + See corresponding definition for IO pins 0 and 1 + [23:21] + read-write + + + VREG_EN67 + See corresponding definition for IO pins 0 and 1 + [24:24] + read-write + + + IBUF_SEL67 + See corresponding definition for IO pins 0 and 1 + [25:25] + read-write + + + VTRIP_SEL67 + See corresponding definition for IO pins 0 and 1 + [26:26] + read-write + + + VREF_SEL67 + See corresponding definition for IO pins 0 and 1 + [28:27] + read-write + + + VOH_SEL67 + See corresponding definition for IO pins 0 and 1 + [31:29] + read-write + + + + + CFG_IN_AUTOLVL + Port input buffer AUTOLVL configuration register + 0x58 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_1 + Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: +{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: +0,0: CMOS +0,1: TTL +1,0: input buffer is compatible with automotive. +1,1: input buffer is compatible with automotvie + [0:0] + read-write + + + CMOS_OR_TTL + Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. + 0 + + + AUTO + Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. + 1 + + + + + VTRIP_SEL1_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [1:1] + read-write + + + VTRIP_SEL2_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [2:2] + read-write + + + VTRIP_SEL3_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [3:3] + read-write + + + VTRIP_SEL4_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [4:4] + read-write + + + VTRIP_SEL5_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [5:5] + read-write + + + VTRIP_SEL6_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [6:6] + read-write + + + VTRIP_SEL7_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [7:7] + read-write + + + + + + INTR_CAUSE0 + Interrupt port cause register 0 + 0x4000 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE1 + Interrupt port cause register 1 + 0x4004 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE2 + Interrupt port cause register 2 + 0x4008 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE3 + Interrupt port cause register 3 + 0x400C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + VDD_ACTIVE + Extern power supply detection register + 0x4010 + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. +'0': Supply is not present +'1': Supply is present + +When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. +For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: +0: vbackup, +1: vddio_0, +2: vddio_1, +3: vddio_a, +4: vddio_r, +5: vddusb' + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) + [31:31] + read-only + + + + + VDD_INTR + Supply detection interrupt register + 0x4014 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply state change detected. +'0': No change to supply detected +'1': Change to supply detected + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. + [31:31] + read-write + + + + + VDD_INTR_MASK + Supply detection interrupt mask register + 0x4018 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Masks supply interrupt on VDDIO. +'0': VDDIO interrupt forwarding disabled +'1': VDDIO interrupt forwarding enabled + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + VDD_INTR_MASKED + Supply detection interrupt masked register + 0x401C + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply transition detected AND masked +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-only + + + + + VDD_INTR_SET + Supply detection interrupt set register + 0x4020 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Sets supply interrupt. +'0': Interrupt state not affected +'1': Interrupt set + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + + + SMARTIO + Programmable IO configuration + 0x40320000 + + 0 + 65536 + registers + + + + 10 + 256 + PRT[%s] + Programmable IO port registers + 0x00000000 + + CTL + Control register + 0x0 + 32 + read-write + 0x2001400 + 0x82001F00 + + + BYPASS + Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. +'0': No bypass (programmable SMARTIO fabric is exposed). +'1': Bypass (programmable SMARTIOIO fabric is hidden). + [7:0] + read-write + + + CLOCK_SRC + Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: +'0': io_data_in[0]/'1'. +... +'7': io_data_in[7]/'1'. +'8': chip_data[0]/'1'. +... +'15': chip_data[7]/'1'. +'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. +'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. +'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. +'31': asynchronous mode/'1'. Select this when clockless operation is configured. + +NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. + [12:8] + read-write + + + HLD_OVR + IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: +'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). +'1': The SMARTIO controls the IO cel hold override functionality: +- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. +- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). + [24:24] + read-write + + + PIPELINE_EN + Enable for pipeline register: +'0': Disabled (register is bypassed). +'1': Enabled. + [25:25] + read-write + + + ENABLED + Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: +'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. + +If the IP is disabled: +- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. +- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. + +'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. + [31:31] + read-write + + + + + SYNC_CTL + Synchronization control register + 0x10 + 32 + read-write + 0x0 + 0x0 + + + IO_SYNC_EN + Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. +'0': No synchronization. +'1': Synchronization. + [7:0] + read-write + + + CHIP_SYNC_EN + Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. +'0': No synchronization. +'1': Synchronization. + [15:8] + read-write + + + + + 8 + 4 + LUT_SEL[%s] + LUT component input selection + 0x20 + 32 + read-write + 0x0 + 0x0 + + + LUT_TR0_SEL + LUT input signal 'tr0_in' source selection: +'0': Data unit output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [3:0] + read-write + + + LUT_TR1_SEL + LUT input signal 'tr1_in' source selection: +'0': LUT 0 output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [11:8] + read-write + + + LUT_TR2_SEL + LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. + [19:16] + read-write + + + + + 8 + 4 + LUT_CTL[%s] + LUT component control register + 0x40 + 32 + read-write + 0x0 + 0x0 + + + LUT + LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). + [7:0] + read-write + + + LUT_OPC + LUT opcode specifies the LUT operation: +'0': Combinatoral output, no feedback. + tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. +'1': Combinatorial output, feedback. + tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. +On clock: + lut_reg <= tr_in2. +'2': Sequential output, no feedback. + temp = LUT[{tr2_in, tr1_in, tr0_in}]. + tr_out = lut_reg. +On clock: + lut_reg <= temp. +'3': Register with asynchronous set and reset. + tr_out = lut_reg. + enable = (tr2_in ^ LUT[4]) | LUT[5]. + set = enable & (tr1_in ^ LUT[2]) & LUT[3]. + clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. +Asynchronously (no clock required): + lut_reg <= if (clr) '0' else if (set) '1' + [9:8] + read-write + + + + + DU_SEL + Data unit component input selection + 0xC0 + 32 + read-write + 0x0 + 0x0 + + + DU_TR0_SEL + Data unit input signal 'tr0_in' source selection: +'0': Constant '0'. +'1': Constant '1'. +'2': Data unit output. +'10-3': LUT 7 - 0 outputs. +Otherwise: Undefined. + [3:0] + read-write + + + DU_TR1_SEL + Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. + [11:8] + read-write + + + DU_TR2_SEL + Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. + [19:16] + read-write + + + DU_DATA0_SEL + Data unit input data 'data0_in' source selection: +'0': Constant '0'. +'1': chip_data[7:0]. +'2': io_data_in[7:0]. +'3': DATA.DATA MMIO register field. + [25:24] + read-write + + + DU_DATA1_SEL + Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. + [29:28] + read-write + + + + + DU_CTL + Data unit component control register + 0xC4 + 32 + read-write + 0x0 + 0x0 + + + DU_SIZE + Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. + [2:0] + read-write + + + DU_OPC + Data unit opcode specifies the data unit operation: +'1': INCR +'2': DECR +'3': INCR_WRAP +'4': DECR_WRAP +'5': INCR_DECR +'6': INCR_DECR_WRAP +'7': ROR +'8': SHR +'9': AND_OR +'10': SHR_MAJ3 +'11': SHR_EQL. +Otherwise: Undefined. + [11:8] + read-write + + + + + DATA + Data register + 0xF0 + 32 + read-write + 0x0 + 0x0 + + + DATA + Data unit input data source. + [7:0] + read-write + + + + + + + + LPCOMP + Low Power Comparators + 0x40350000 + + 0 + 65536 + registers + + + + CONFIG + LPCOMP Configuration Register + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + LPREF_EN + Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. + [30:30] + read-write + + + ENABLED + - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) +- 1: IP enabled + [31:31] + read-write + + + + + STATUS + LPCOMP Status Register + 0x4 + 32 + read-only + 0x0 + 0x10001 + + + OUT0 + Current output value of the comparator 0. + [0:0] + read-only + + + OUT1 + Current output value of the comparator 1. + [16:16] + read-only + + + + + INTR + LPCOMP Interrupt request register + 0x10 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + LPCOMP Interrupt set register + 0x14 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + LPCOMP Interrupt request mask + 0x18 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + LPCOMP Interrupt request masked + 0x1C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + CMP0_CTRL + Comparator 0 control Register + 0x40 + 32 + read-write + 0x0 + 0xCE3 + + + MODE0 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST0 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE0 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS0 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL0 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP0_SW + Comparator 0 switch control + 0x50 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + Comparator 0 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP0_AP0 + Comparator 0 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP0_BP0 + Comparator 0 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP0_IN0 + Comparator 0 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP0_AN0 + Comparator 0 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP0_BN0 + Comparator 0 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP0_VN0 + Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP0_SW_CLEAR + Comparator 0 switch control clear + 0x54 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + see corresponding bit in CMP0_SW + [0:0] + read-write + + + CMP0_AP0 + see corresponding bit in CMP0_SW + [1:1] + read-write + + + CMP0_BP0 + see corresponding bit in CMP0_SW + [2:2] + read-write + + + CMP0_IN0 + see corresponding bit in CMP0_SW + [4:4] + read-write + + + CMP0_AN0 + see corresponding bit in CMP0_SW + [5:5] + read-write + + + CMP0_BN0 + see corresponding bit in CMP0_SW + [6:6] + read-write + + + CMP0_VN0 + see corresponding bit in CMP0_SW + [7:7] + read-write + + + + + CMP1_CTRL + Comparator 1 control Register + 0x80 + 32 + read-write + 0x0 + 0xCE3 + + + MODE1 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST1 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE1 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS1 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL1 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP1_SW + Comparator 1 switch control + 0x90 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + Comparator 1 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP1_AP1 + Comparator 1 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP1_BP1 + Comparator 1 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP1_IN1 + Comparator 1 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP1_AN1 + Comparator 1 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP1_BN1 + Comparator 1 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP1_VN1 + Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP1_SW_CLEAR + Comparator 1 switch control clear + 0x94 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + see corresponding bit in CMP1_SW + [0:0] + read-write + + + CMP1_AP1 + see corresponding bit in CMP1_SW + [1:1] + read-write + + + CMP1_BP1 + see corresponding bit in CMP1_SW + [2:2] + read-write + + + CMP1_IN1 + see corresponding bit in CMP1_SW + [4:4] + read-write + + + CMP1_AN1 + see corresponding bit in CMP1_SW + [5:5] + read-write + + + CMP1_BN1 + see corresponding bit in CMP1_SW + [6:6] + read-write + + + CMP1_VN1 + see corresponding bit in CMP1_SW + [7:7] + read-write + + + + + + + CSD0 + Capsense Controller + CSD + 0x40360000 + + 0 + 4096 + registers + + + + CONFIG + Configuration and Control + 0x0 + 32 + read-write + 0x4000000 + 0xCF0E1DF1 + + + IREF_SEL + Select Iref supply. + [0:0] + read-write + + + IREF_SRSS + select SRSS Iref (default) + 0 + + + IREF_PASS + select PASS.AREF Iref, only available if PASS IP is on the chip. + 1 + + + + + FILTER_DELAY + This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on. +When set to 0 the digital filter is off. When set to any other value the ignoring will last for FILTER_DELAY clk_csd cycles after the start of each measurement and from the first comparator trip to the end of each measurement. + [8:4] + read-write + + + SHIELD_DELAY + Selects the delay by which csd_shield is delayed relative to csd_sense. + [11:10] + read-write + + + OFF + Delay line is off, csd_shield=csd_sense + 0 + + + D5NS + Introduces a 5ns delay (typ) + 1 + + + D10NS + Introduces a 10ns delay (typ) + 2 + + + D20NS + Introduces a 20ns delay (typ) + 3 + + + + + SENSE_EN + Enables the sense modulator output. +0: all switches, static or dynamic, are open and IDAC in CSD mode is off +1: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer. + [12:12] + read-write + + + FULL_WAVE + Enables full wave cap sensing mode + [17:17] + read-write + + + HALFWAVE + Half Wave mode (normal). +In this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change. + 0 + + + FULLWAVE + Full Wave mode. +In this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips. + 1 + + + + + MUTUAL_CAP + Enables mutual cap sensing mode + [18:18] + read-write + + + SELFCAP + Self-cap mode (configure sense line as CSD_SENSE) + 0 + + + MUTUALCAP + Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense. + 1 + + + + + CSX_DUAL_CNT + Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUTUAL_CAP=0 + [19:19] + read-write + + + ONE + Use one counter for both phases (source and sink). + 0 + + + TWO + Use two counters, separate count for when csd_sense is high and when csd_sense is low. + 1 + + + + + DSI_COUNT_SEL + Select what to output on the dsi_count bus. + [24:24] + read-write + + + CSD_RESULT + depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially. + 0 + + + ADC_RESULT + output ADC_RES.VIN_CNT on the dsi_count bus + 1 + + + + + DSI_SAMPLE_EN + Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER. + [25:25] + read-write + + + SAMPLE_SYNC + Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1). + [26:26] + read-write + + + DSI_SENSE_EN + Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals. + [27:27] + read-write + + + LP_MODE + Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP): +0: High Power mode +1: Low Power mode + [30:30] + read-write + + + ENABLE + Master enable of the CSDv2 IP. Must be set to 1 for any CSDv2, ADC or IDAC operation to function. +When 0 all analog components will be off and all switches will be open. + [31:31] + read-write + + + + + SPARE + Spare MMIO + 0x4 + 32 + read-write + 0x0 + 0xF + + + SPARE + Spare MMIO + [3:0] + read-write + + + + + STATUS + Status Register + 0x80 + 32 + read-only + 0x0 + 0xE + + + CSD_SENSE + Signal used to drive the Cs switches. + [1:1] + read-only + + + HSCMP_OUT + Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized) + [2:2] + read-only + + + C_LT_VREF + Vin < Vref + 0 + + + C_GT_VREF + Vin > Vref + 1 + + + + + CSDCMP_OUT + Output of main sensing comparator (synchronized) + [3:3] + read-only + + + + + STAT_SEQ + Current Sequencer status + 0x84 + 32 + read-only + 0x0 + 0x70007 + + + SEQ_STATE + CSD sequencer state + [2:0] + read-only + + + ADC_STATE + ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) + [18:16] + read-only + + + + + STAT_CNTS + Current status counts + 0x88 + 32 + read-only + 0x0 + 0xFFFF + + + NUM_CONV + Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) + [15:0] + read-only + + + + + STAT_HCNT + Current count of the HSCMP counter + 0x8C + 32 + read-only + 0x0 + 0xFFFF + + + CNT + Current value of HSCMP counter + [15:0] + read-only + + + + + RESULT_VAL1 + Result CSD/CSX accumulation counter value 1 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFF + + + VALUE + Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. + [15:0] + read-only + + + BAD_CONVS + Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. + [23:16] + read-only + + + + + RESULT_VAL2 + Result CSX accumulation counter value 2 + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + VALUE + Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. + [15:0] + read-only + + + + + ADC_RES + ADC measurement + 0xE0 + 32 + read-only + 0x0 + 0xC001FFFF + + + VIN_CNT + Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. + [15:0] + read-only + + + HSCMP_POL + Polarity used for IDACB for this last ADC result, 0= source, 1= sink + [16:16] + read-only + + + ADC_OVERFLOW + This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. + [30:30] + read-only + + + ADC_ABORT + This flag is set when the ADC sequencer was aborted before tripping HSCMP. + [31:31] + read-only + + + + + INTR + CSD Interrupt Request Register + 0xF0 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + A normal sample is complete + [1:1] + read-write + + + INIT + Coarse initialization complete or Sample initialization complete (the latter is typically ignored) + [2:2] + read-write + + + ADC_RES + ADC Result ready + [8:8] + read-write + + + + + INTR_SET + CSD Interrupt set register + 0xF4 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASK + CSD Interrupt mask register + 0xF8 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASKED + CSD Interrupt masked register + 0xFC + 32 + read-only + 0x0 + 0x106 + + + SAMPLE + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + INIT + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + ADC_RES + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + + + HSCMP + High Speed Comparator configuration + 0x180 + 32 + read-write + 0x0 + 0x80000011 + + + HSCMP_EN + High Speed Comparator enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + HSCMP_INVERT + Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT + [4:4] + read-write + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + AMBUF + Reference Generator configuration + 0x184 + 32 + read-write + 0x0 + 0x3 + + + PWR_MODE + Amux buffer power level + [1:0] + read-write + + + OFF + Disable buffer + 0 + + + NORM + On, normal or low power level depending on CONFIG.LP_MODE. + 1 + + + HI + On, high or low power level depending on CONFIG.LP_MODE. + 2 + + + + + + + REFGEN + Reference Generator configuration + 0x188 + 32 + read-write + 0x0 + 0x9F1F71 + + + REFGEN_EN + Reference Generator Enable + [0:0] + read-write + + + OFF + Disable Reference Generator + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + BYPASS + Bypass selected input reference unbuffered to Vrefhi + [4:4] + read-write + + + VDDA_EN + Close Vdda switch to top of resistor string (or Vrefhi?) + [5:5] + read-write + + + RES_EN + Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) + [6:6] + read-write + + + GAIN + Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) + [12:8] + read-write + + + VREFLO_SEL + Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) + [20:16] + read-write + + + VREFLO_INT + Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). + [23:23] + read-write + + + + + CSDCMP + CSD Comparator configuration + 0x18C + 32 + read-write + 0x0 + 0xB0000331 + + + CSDCMP_EN + CSD Comparator Enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + POLARITY_SEL + Select which IDAC polarity to use to detect CSDCMP triggering + [5:4] + read-write + + + IDACA_POL + Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX + 0 + + + IDACB_POL + Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) + 1 + + + DUAL_POL + Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case + 2 + + + + + CMP_PHASE + Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). + [9:8] + read-write + + + FULL + Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + Comparator is active during Phi1 only. Currently no known use-case. + 1 + + + PHI2 + Comparator is active during Phi2 only. Intended usage: CSD Low EMI. + 2 + + + PHI1_2 + Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. + 3 + + + + + CMP_MODE + Select which signal to output on dsi_sample_out. + [28:28] + read-write + + + CSD + CSD mode: output the filtered sample signal on dsi_sample_out + 0 + + + GP + General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. + 1 + + + + + FEEDBACK_MODE + This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. + [29:29] + read-write + + + FLOP + Use feedback from sampling flip-flop (used in most modes). + 0 + + + COMP + Use feedback from comparator directly (used in single Cmod mutual cap sensing only) + 1 + + + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + SW_RES + Switch Resistance configuration + 0x1F0 + 32 + read-write + 0x0 + 0xF00FF + + + RES_HCAV + Select resistance or low EMI (slow ramp) for the HCAV switch + [1:0] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + LOWEMI + Low EMI (slow ramp: 3 switches closed by fixed delay line) + 3 + + + + + RES_HCAG + Select resistance or low EMI for the corresponding switch + [3:2] + read-write + + + RES_HCBV + Select resistance or low EMI for the corresponding switch + [5:4] + read-write + + + RES_HCBG + Select resistance or low EMI for the corresponding switch + [7:6] + read-write + + + RES_F1PM + Select resistance for the corresponding switch + [17:16] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + RSVD + N/A + 3 + + + + + RES_F2PT + Select resistance for the corresponding switch + [19:18] + read-write + + + + + SENSE_PERIOD + Sense clock period + 0x200 + 32 + read-write + 0xC000000 + 0xFF70FFF + + + SENSE_DIV + The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . +Note this is the base divider, clock dithering may change the actual period length. +Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. +In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. + [11:0] + read-write + + + LFSR_SIZE + Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. + [18:16] + read-write + + + OFF + Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) + 0 + + + 6B + 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) + 1 + + + 7B + 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) + 2 + + + 9B + 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) + 3 + + + 10B + 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) + 4 + + + 8B + 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) + 5 + + + 12B + 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) + 6 + + + + + LFSR_SCALE + Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. +The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). +Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. + [23:20] + read-write + + + LFSR_CLEAR + When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. +Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. + [24:24] + read-write + + + SEL_LFSR_MSB + Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. + [25:25] + read-write + + + LFSR_BITS + Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. +Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. + [27:26] + read-write + + + 2B + use 2 bits: range = [-2,1] + 0 + + + 3B + use 3 bits: range = [-4,3] + 1 + + + 4B + use 4 bits: range = [-8,7] + 2 + + + 5B + use 5 bits: range = [-16,15] (default) + 3 + + + + + + + SENSE_DUTY + Sense clock duty cycle + 0x204 + 32 + read-write + 0x0 + 0xD0FFF + + + SENSE_WIDTH + Defines the length of the first phase of the sense clock in clk_csd cycles. +A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. +Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. + [11:0] + read-write + + + SENSE_POL + Polarity of the sense clock +0 = start with low phase (typical for regular negative transfer CSD) +1 = start with high phase + [16:16] + read-write + + + OVERLAP_PHI1 + NonOverlap or not for Phi1 (csd_sense=0). +0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. +1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. + [18:18] + read-write + + + OVERLAP_PHI2 + Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). + [19:19] + read-write + + + + + SW_HS_P_SEL + HSCMP Pos input switch Waveform selection + 0x280 + 32 + read-write + 0x0 + 0x11111111 + + + SW_HMPM + Set HMPM switch +0: static open +1: static closed + [0:0] + read-write + + + SW_HMPT + Set corresponding switch + [4:4] + read-write + + + SW_HMPS + Set corresponding switch + [8:8] + read-write + + + SW_HMMA + Set corresponding switch + [12:12] + read-write + + + SW_HMMB + Set corresponding switch + [16:16] + read-write + + + SW_HMCA + Set corresponding switch + [20:20] + read-write + + + SW_HMCB + Set corresponding switch + [24:24] + read-write + + + SW_HMRH + Set corresponding switch + [28:28] + read-write + + + + + SW_HS_N_SEL + HSCMP Neg input switch Waveform selection + 0x284 + 32 + read-write + 0x0 + 0x77110000 + + + SW_HCCC + Set corresponding switch + [16:16] + read-write + + + SW_HCCD + Set corresponding switch + [20:20] + read-write + + + SW_HCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_HCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_SHIELD_SEL + Shielding switches Waveform selection + 0x288 + 32 + read-write + 0x0 + 0x117777 + + + SW_HCAV + N/A + [2:0] + read-write + + + SW_HCAG + Select waveform for corresponding switch + [6:4] + read-write + + + SW_HCBV + N/A + [10:8] + read-write + + + SW_HCBG + Select waveform for corresponding switch, using csd_shield as base + [14:12] + read-write + + + SW_HCCV + Set corresponding switch + [16:16] + read-write + + + SW_HCCG + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_AMUXBUF_SEL + Amuxbuffer switches Waveform selection + 0x290 + 32 + read-write + 0x0 + 0x11171110 + + + SW_IRBY + Set corresponding switch + [4:4] + read-write + + + SW_IRLB + Set corresponding switch + [8:8] + read-write + + + SW_ICA + Set corresponding switch + [12:12] + read-write + + + SW_ICB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_IRLI + Set corresponding switch + [20:20] + read-write + + + SW_IRH + Set corresponding switch + [24:24] + read-write + + + SW_IRL + Set corresponding switch + [28:28] + read-write + + + + + SW_BYP_SEL + AMUXBUS bypass switches Waveform selection + 0x294 + 32 + read-write + 0x0 + 0x111000 + + + SW_BYA + Set corresponding switch + [12:12] + read-write + + + SW_BYB + Set corresponding switch + [16:16] + read-write + + + SW_CBCC + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_CMP_P_SEL + CSDCMP Pos Switch Waveform selection + 0x2A0 + 32 + read-write + 0x0 + 0x1111777 + + + SW_SFPM + Select waveform for corresponding switch + [2:0] + read-write + + + SW_SFPT + Select waveform for corresponding switch + [6:4] + read-write + + + SW_SFPS + Select waveform for corresponding switch + [10:8] + read-write + + + SW_SFMA + Set corresponding switch + [12:12] + read-write + + + SW_SFMB + Set corresponding switch + [16:16] + read-write + + + SW_SFCA + Set corresponding switch + [20:20] + read-write + + + SW_SFCB + Set corresponding switch + [24:24] + read-write + + + + + SW_CMP_N_SEL + CSDCMP Neg Switch Waveform selection + 0x2A4 + 32 + read-write + 0x0 + 0x77000000 + + + SW_SCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_SCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_REFGEN_SEL + Reference Generator Switch Waveform selection + 0x2A8 + 32 + read-write + 0x0 + 0x11110011 + + + SW_IAIB + Set corresponding switch + [0:0] + read-write + + + SW_IBCB + Set corresponding switch + [4:4] + read-write + + + SW_SGMB + Set corresponding switch + [16:16] + read-write + + + SW_SGRP + Set corresponding switch + [20:20] + read-write + + + SW_SGRE + Set corresponding switch + [24:24] + read-write + + + SW_SGR + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_MOD_SEL + Full Wave Cmod Switch Waveform selection + 0x2B0 + 32 + read-write + 0x0 + 0x11170701 + + + SW_F1PM + Set corresponding switch + [0:0] + read-write + + + SW_F1MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F1CA + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C1CC + Set corresponding switch + [20:20] + read-write + + + SW_C1CD + Set corresponding switch + [24:24] + read-write + + + SW_C1F1 + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_TANK_SEL + Full Wave Csh_tank Switch Waveform selection + 0x2B4 + 32 + read-write + 0x0 + 0x11177710 + + + SW_F2PT + Set corresponding switch + [4:4] + read-write + + + SW_F2MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F2CA + Select waveform for corresponding switch + [14:12] + read-write + + + SW_F2CB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C2CC + Set corresponding switch + [20:20] + read-write + + + SW_C2CD + Set corresponding switch + [24:24] + read-write + + + SW_C2F2 + Set corresponding switch + [28:28] + read-write + + + + + SW_DSI_SEL + DSI output switch control Waveform selection + 0x2C0 + 32 + read-write + 0x0 + 0xFF + + + DSI_CSH_TANK + Select waveform for dsi_csh_tank output signal +0: static open +1: static closed +2: phi1 +3: phi2 +4: phi1 & HSCMP +5: phi2 & HSCMP +6: HSCMP // ignores phi1/2 +7: !sense // = phi1 but ignores OVERLAP_PHI1 + +8: phi1_delay // phi1 delayed with shield delay +9: phi2_delay // phi2 delayed with shield delay + +10: !phi1 +11: !phi2 +12: !(phi1 & HSCMP) +13: !(phi2 & HSCMP) +14: !HSCMP // ignores phi1/2 +15: sense // = phi2 but ignores OVERLAP_PHI2 + [3:0] + read-write + + + DSI_CMOD + Select waveform for dsi_cmod output signal + [7:4] + read-write + + + + + IO_SEL + IO output control Waveform selection + 0x2D0 + 32 + read-write + 0x0 + 0xFFFF0FF + + + CSD_TX_OUT + Select waveform for csd_tx_out output signal + [3:0] + read-write + + + CSD_TX_OUT_EN + Select waveform for csd_tx_out_en output signal + [7:4] + read-write + + + CSD_TX_AMUXB_EN + Select waveform for csd_tx_amuxb_en output signal + [15:12] + read-write + + + CSD_TX_N_OUT + Select waveform for csd_tx_n_out output signal + [19:16] + read-write + + + CSD_TX_N_OUT_EN + Select waveform for csd_tx_n_out_en output signal + [23:20] + read-write + + + CSD_TX_N_AMUXA_EN + Select waveform for csd_tx_n_amuxa_en output signal + [27:24] + read-write + + + + + SEQ_TIME + Sequencer Timing + 0x300 + 32 + read-write + 0x0 + 0xFF + + + AZ_TIME + Define Auto-Zero time in csd_sense cycles -1. + [7:0] + read-write + + + + + SEQ_INIT_CNT + Sequencer Initial conversion and sample counts + 0x310 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. + [15:0] + read-write + + + + + SEQ_NORM_CNT + Sequencer Normal conversion and sample counts + 0x314 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. +Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). +Note for CSDv1 Sample window size = PERIOD + [15:0] + read-write + + + + + ADC_CTL + ADC Control + 0x320 + 32 + read-write + 0x0 + 0x300FF + + + ADC_TIME + ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 + [7:0] + read-write + + + ADC_MODE + Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state + [17:16] + read-write + + + OFF + No ADC measurement + 0 + + + VREF_CNT + Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB + 1 + + + VREF_BY2_CNT + Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) + 2 + + + VIN_CNT + Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. + 3 + + + + + + + SEQ_START + Sequencer start + 0x340 + 32 + read-write + 0x0 + 0x31B + + + START + Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). + [0:0] + read-write + + + SEQ_MODE + 0 = regular CSD scan + optional ADC +1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. + [1:1] + read-write + + + ABORT + When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. + [3:3] + read-write + + + DSI_START_EN + When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. + [4:4] + read-write + + + AZ0_SKIP + When set the AutoZero_0 state will be skipped + [8:8] + read-write + + + AZ1_SKIP + When set the AutoZero_1 state will be skipped + [9:9] + read-write + + + + + IDACA + IDACA Configuration + 0x400 + 32 + read-write + 0x0 + 0x3EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_MODE==CSD also mixed with the CSD configuration and operation. However in mutual cap mode with one IDAC (config.mutual_cap=1 & config.csx_dual_idac=0) the polarity of the IDAC is controlled by csd_sense. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + Balancing mode: only applies to legs configured as CSD. + [11:10] + read-write + + + FULL + enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking. + 1 + + + PHI2 + enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or dual IDAC CSX or Full-Wave. + 2 + + + PHI1_2 + enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave. + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled). +0: no DSI control + IDACA_POLARITY = IDACA.POLARITY + IDACA_LEG1_EN = IDACA.LEG1_EN + IDACA_LEG2_EN = IDACA.LEG2_EN +1: Mix MMIO with DSI control + IDACA_POLARITY = IDACA.POLARITY EXOR dsi_idaca_pol + IDACA_LEG1_EN = IDACA.LEG1_EN AND dsi_idaca_leg1_en + IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSA + [25:25] + read-write + + + + + IDACB + IDACB Configuration + 0x500 + 32 + read-write + 0x0 + 0x7EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_EN==1 and LEG1_MODE==CSD also mixed with the CSD configuration and operation. In mutual cap mode however (see config.mutual_cap) the polarity of the IDAC is controlled by csd_sense. If LEG3_EN=1 (the other two legs must be off) then the ADC sequencer controls the IDACB polarity, optionally mixed with DSI. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + same as corresponding IDACA Balancing mode + [11:10] + read-write + + + FULL + same as corresponding IDACA Balancing mode + 0 + + + PHI1 + same as corresponding IDACA Balancing mode + 1 + + + PHI2 + same as corresponding IDACA Balancing mode + 2 + + + PHI1_2 + same as corresponding IDACA Balancing mode + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG1_MODE + 0 + + + GP + same as corresponding IDACA.LEG1_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG1_MODE + 2 + + + CSD + same as corresponding IDACA.LEG1_MODE + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG2_MODE + 0 + + + GP + same as corresponding IDACA.LEG2_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG2_MODE + 2 + + + CSD + same as corresponding IDACA.LEG2_MODE + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled) +0: no DSI control + IDACB_POLARITY = IDACB.POLARITY + IDACB_LEG1_EN = IDACB.LEG1_EN + IDACB_LEG2_EN = IDACB.LEG2_EN + IDACB_LEG3_EN = IDACB.LEG3_EN +1: Mix MMIO with DSI control + IDACB_POLARITY = IDACB.POLARITY EXOR dsi_idacb_pol + IDACB_LEG1_EN = IDACB.LEG1_EN AND dsi_idacb_leg1_en + IDACB_LEG2_EN = IDACB.LEG2_EN AND dsi_idacb_leg2_en + IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSB or CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSB or CSDBUSA + [25:25] + read-write + + + LEG3_EN + output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit is set both other legs should be off. +Note that leg3 can only be used for ADC mode, not GP mode. Which means that leg3 can only be on when the ADC Sequencer is in the ADC_measure or Calib_measure state. In those states leg3 is controlled by the ADC configuration and the HSCMP output. In addition this leg3 enable bit can optionally be mixed with DSI (see DSI_CTRL_EN). +When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer. + [26:26] + read-write + + + + + + + TCPWM0 + Timer/Counter/PWM + TCPWM + 0x40380000 + + 0 + 65536 + registers + + + + CTRL + TCPWM control register + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Counter enables for counters 0 up to CNT_NR-1. +'0': counter disabled. +'1': counter enabled. +Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: +- the associated counter triggers in the CMD register are set to '0'. +- the counter's interrupt cause fields in counter's INTR register. +- the counter's status fields in counter's STATUS register.. +- the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). +- the counter's line outputs ('line_out' and 'line_compl_out'). +In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. + [31:0] + read-write + + + + + CTRL_CLR + TCPWM control clear register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Alias of CTRL that only allows disabling of counters. A write access: +'0': Does nothing. +'1': Clears respective COUNTER_ENABLED field. + +A read access returns CTRL.COUNTER_ENABLED. + [31:0] + read-write + + + + + CTRL_SET + TCPWM control set register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Alias of CTRL that only allows enabling of counters. A write access: +'0': Does nothing. +'1': Sets respective COUNTER_ENABLED field. + +A read access returns CTRL.COUNTER_ENABLED. + [31:0] + read-write + + + + + CMD_CAPTURE + TCPWM capture command register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_CAPTURE + Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. + [31:0] + read-write + + + + + CMD_RELOAD + TCPWM reload command register + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_RELOAD + Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + CMD_STOP + TCPWM stop command register + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_STOP + Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + CMD_START + TCPWM start command register + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_START + Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + INTR_CAUSE + TCPWM Counter interrupt cause register + 0x1C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNTER_INT + Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. + [31:0] + read-only + + + + + 24 + 64 + CNT[%s] + Timer/Counter/PWM Counter Module + 0x00000100 + + CTRL + Counter control register + 0x0 + 32 + read-write + 0x0 + 0x737FF0F + + + AUTO_RELOAD_CC + Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. +Timer mode: +'0': never switch. +'1': switch on a compare match event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [0:0] + read-write + + + AUTO_RELOAD_PERIOD + Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + [1:1] + read-write + + + PWM_SYNC_KILL + Specifies asynchronous/synchronous kill behavior: +'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. +'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. + +This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. + [2:2] + read-write + + + PWM_STOP_ON_KILL + Specifies whether the counter stops on a kill events: +'0': kill event does NOT stop counter. +'1': kill event stops counter. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [3:3] + read-write + + + GENERIC + Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. + [15:8] + read-write + + + UP_DOWN_MODE + Determines counter direction. + [17:16] + read-write + + + COUNT_UP + Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. + 0 + + + COUNT_DOWN + Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 1 + + + COUNT_UPDN1 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 2 + + + COUNT_UPDN2 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). + 3 + + + + + ONE_SHOT + When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. + [18:18] + read-write + + + QUADRATURE_MODE + In QUAD mode selects quadrature encoding mode (X1/X2/X4). +In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1]. + [21:20] + read-write + + + X1 + X1 encoding (QUAD mode) + 0 + + + X2 + X2 encoding (QUAD mode) + 1 + + + X4 + X4 encoding (QUAD mode) + 2 + + + + + MODE + Counter mode. + [26:24] + read-write + + + TIMER + Timer mode + 0 + + + CAPTURE + Capture mode + 2 + + + QUAD + Quadrature encoding mode + 3 + + + PWM + Pulse width modulation (PWM) mode + 4 + + + PWM_DT + PWM with deadtime insertion mode + 5 + + + PWM_PR + Pseudo random pulse width modulation + 6 + + + + + + + STATUS + Counter status register + 0x4 + 32 + read-only + 0x0 + 0x8000FF01 + + + DOWN + When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. + [0:0] + read-only + + + GENERIC + Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. + [15:8] + read-only + + + RUNNING + When '0', the counter is NOT running. When '1', the counter is running. + [31:31] + read-only + + + + + COUNTER + Counter count register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER + 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. + [31:0] + read-write + + + + + CC + Counter compare/capture register + 0xC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC_BUFF + Counter buffered compare/capture register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC register. + [31:0] + read-write + + + + + PERIOD + Counter period register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. + [31:0] + read-write + + + + + PERIOD_BUFF + Counter buffered period register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Additional buffer for counter PERIOD register. + [31:0] + read-write + + + + + TR_CTRL0 + Counter trigger control register 0 + 0x20 + 32 + read-write + 0x10 + 0xFFFFF + + + CAPTURE_SEL + Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. + [3:0] + read-write + + + COUNT_SEL + Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. + [7:4] + read-write + + + RELOAD_SEL + Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint). + [11:8] + read-write + + + STOP_SEL + Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. + [15:12] + read-write + + + START_SEL + Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). + [19:16] + read-write + + + + + TR_CTRL1 + Counter trigger control register 1 + 0x24 + 32 + read-write + 0x3FF + 0x3FF + + + CAPTURE_EDGE + A capture event will copy the counter value into the CC register. + [1:0] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + COUNT_EDGE + A counter event will increase or decrease the counter by '1'. + [3:2] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + RELOAD_EDGE + A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. + [5:4] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + STOP_EDGE + A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. + [7:6] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + START_EDGE + A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. + [9:8] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + + + TR_CTRL2 + Counter trigger control register 2 + 0x28 + 32 + read-write + 0x3F + 0x3F + + + CC_MATCH_MODE + Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. +To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. + [1:0] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + OVERFLOW_MODE + Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. + [3:2] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + UNDERFLOW_MODE + Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. + [5:4] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + + + INTR + Interrupt request register + 0x30 + 32 + read-write + 0x0 + 0x3 + + + TC + Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. + [0:0] + read-write + + + CC_MATCH + Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + Interrupt set request register + 0x34 + 32 + read-write + 0x0 + 0x3 + + + TC + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + CC_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x38 + 32 + read-write + 0x0 + 0x3 + + + TC + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + CC_MATCH + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x3C + 32 + read-only + 0x0 + 0x3 + + + TC + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CC_MATCH + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + + + + TCPWM1 + 0x40390000 + + + LCD0 + LCD Controller Block + LCD + 0x403B0000 + + 0 + 65536 + registers + + + + ID + ID & Revision + 0x0 + 32 + read-only + 0x1F0F0 + 0xFFFFFFFF + + + ID + the ID of LCD controller peripheral is 0xF0F0 + [15:0] + read-only + + + REVISION + the version number is 0x0001 + [31:16] + read-only + + + + + DIVIDER + LCD Divider Register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SUBFR_DIV + Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. + [15:0] + read-write + + + DEAD_DIV + Length of the dead time period in cycles. When set to zero, no dead time period exists. + [31:16] + read-write + + + + + CONTROL + LCD Configuration Register + 0x8 + 32 + read-write + 0x0 + 0x80000F7F + + + LS_EN + Low speed (LS) generator enable +1: enable +0: disable + [0:0] + read-write + + + HS_EN + High speed (HS) generator enable +1: enable +0: disable + [1:1] + read-write + + + LCD_MODE + HS/LS Mode selection + [2:2] + read-write + + + LS + Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes). + 0 + + + HS + Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). + 1 + + + + + TYPE + LCD driving waveform type configuration. + [3:3] + read-write + + + TYPE_A + Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. + 0 + + + TYPE_B + Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). + 1 + + + + + OP_MODE + Driving mode configuration + [4:4] + read-write + + + PWM + PWM Mode + 0 + + + CORRELATION + Digital Correlation Mode + 1 + + + + + BIAS + PWM bias selection + [6:5] + read-write + + + HALF + 1/2 Bias + 0 + + + THIRD + 1/3 Bias + 1 + + + FOURTH + 1/4 Bias (not supported by LS generator) + 2 + + + FIFTH + 1/5 Bias (not supported by LS generator) + 3 + + + + + COM_NUM + The number of COM connections minus 2. So: +0: 2 COM's +1: 3 COM's +... +13: 15 COM's +14: 16 COM's +15: undefined + [11:8] + read-write + + + LS_EN_STAT + LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. +The following procedure should be followed to disable the LS generator: +1. If LS_EN=0 we are done. Exit the procedure. +2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. +3. Set LS_EN=0. +4. Wait until LS_EN_STAT=0. + [31:31] + read-only + + + + + 8 + 4 + DATA0[%s] + LCD Pin Data Registers + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA1[%s] + LCD Pin Data Registers + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA2[%s] + LCD Pin Data Registers + 0x300 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA3[%s] + LCD Pin Data Registers + 0x400 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). + [31:0] + read-write + + + + + + + USBFS0 + USB Host and Device Controller + USBFS + 0x403F0000 + + 0 + 65536 + registers + + + + USBDEV + USB Device + 0x00000000 + + 8 + 4 + EP0_DR[%s] + Control End point EP0 Data Register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + DATA_BYTE + This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. + [7:0] + read-write + + + + + CR0 + USB control 0 Register + 0x20 + 32 + read-write + 0x0 + 0xFF + + + DEVICE_ADDRESS + These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. +If USB bus reset is detected, these bits are initialized. + [6:0] + read-write + + + USB_ENABLE + This bit enables the device to respond to USB traffic. +If USB bus reset is detected, this bit is cleared. +Note: +When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. + [7:7] + read-write + + + + + CR1 + USB control 1 Register + 0x24 + 32 + read-write + 0x0 + 0xF + + + REG_ENABLE + This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. + [0:0] + read-write + + + ENABLE_LOCK + This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. + [1:1] + read-write + + + BUS_ACTIVITY + The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High +value until firmware clears it. + [2:2] + read-write + + + RSVD_3 + N/A + [3:3] + read-write + + + + + SIE_EP_INT_EN + USB SIE Data Endpoints Interrupt Enable Register + 0x28 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + SIE_EP_INT_SR + USB SIE Data Endpoint Interrupt Status + 0x2C + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-write + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-write + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-write + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-write + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-write + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-write + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-write + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-write + + + + + SIE_EP1_CNT0 + Non-control endpoint count register + 0x30 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP1_CNT1 + Non-control endpoint count register + 0x34 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP1_CR0 + Non-control endpoint's control Register + 0x38 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + USBIO_CR0 + USBIO Control 0 Register + 0x40 + 32 + read-write + 0x0 + 0xE0 + + + RD + Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. +If D+=D- (SE0), this value is undefined. + [0:0] + read-only + + + DIFF_LOW + D+ < D- (K state) + 0 + + + DIFF_HIGH + D+ > D- (J state) + 1 + + + + + TD + Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. + [5:5] + read-write + + + DIFF_K + Force USB K state (D+ is low D- is high). + 0 + + + DIFF_J + Force USB J state (D+ is high D- is low). + 1 + + + + + TSE0 + Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. + [6:6] + read-write + + + TEN + USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually +transmitting is to force a resume state on the bus. + [7:7] + read-write + + + + + USBIO_CR2 + USBIO control 2 Register + 0x44 + 32 + read-write + 0x0 + 0xFF + + + RSVD_5_0 + N/A + [5:0] + read-only + + + TEST_PKT + This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. + [6:6] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + + + USBIO_CR1 + USBIO control 1 Register + 0x48 + 32 + read-write + 0x20 + 0x20 + + + DMO + This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. +This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. +This bit is valid if USB Device. + [0:0] + read-only + + + DPO + This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. +This bit displays the output value of D+ pin when USB transmits SE0 or data. +This bit is valid if USB Device. + [1:1] + read-only + + + RSVD_2 + N/A + [2:2] + read-write + + + IOMODE + This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. + [5:5] + read-write + + + + + DYN_RECONFIG + USB Dynamic reconfiguration register + 0x50 + 32 + read-write + 0x0 + 0x1F + + + DYN_CONFIG_EN + This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. +Use 0 for EP1, 1 for EP2, etc. + [0:0] + read-write + + + DYN_RECONFIG_EPNO + These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. + [3:1] + read-write + + + DYN_RECONFIG_RDY_STS + This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. + [4:4] + read-only + + + + + SOF0 + Start Of Frame Register + 0x60 + 32 + read-only + 0x0 + 0xFF + + + FRAME_NUMBER + It has the lower 8 bits [7:0] of the SOF frame number. + [7:0] + read-only + + + + + SOF1 + Start Of Frame Register + 0x64 + 32 + read-only + 0x0 + 0x7 + + + FRAME_NUMBER_MSB + It has the upper 3 bits [10:8] of the SOF frame number. + [2:0] + read-only + + + + + SIE_EP2_CNT0 + Non-control endpoint count register + 0x70 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP2_CNT1 + Non-control endpoint count register + 0x74 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP2_CR0 + Non-control endpoint's control Register + 0x78 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + OSCLK_DR0 + Oscillator lock data register 0 + 0x80 + 32 + read-only + 0x0 + 0x0 + + + ADDER + These bits return the lower 8 bits of the oscillator locking circuits adder output. + [7:0] + read-only + + + + + OSCLK_DR1 + Oscillator lock data register 1 + 0x84 + 32 + read-only + 0x0 + 0x0 + + + ADDER_MSB + These bits return the upper 7 bits of the oscillator locking circuits adder output. + [6:0] + read-only + + + + + EP0_CR + Endpoint0 control Register + 0xA0 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + OUT_RCVD + When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. + [5:5] + read-write + + + IN_RCVD + When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. + [6:6] + read-write + + + SETUP_RCVD + When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. + [7:7] + read-write + + + + + EP0_CNT + Endpoint0 count Register + 0xA4 + 32 + read-write + 0x0 + 0xCF + + + BYTE_COUNT + These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. + [3:0] + read-write + + + DATA_VALID + This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT0 + Non-control endpoint count register + 0xB0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT1 + Non-control endpoint count register + 0xB4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP3_CR0 + Non-control endpoint's control Register + 0xB8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP4_CNT0 + Non-control endpoint count register + 0xF0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP4_CNT1 + Non-control endpoint count register + 0xF4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP4_CR0 + Non-control endpoint's control Register + 0xF8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP5_CNT0 + Non-control endpoint count register + 0x130 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP5_CNT1 + Non-control endpoint count register + 0x134 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP5_CR0 + Non-control endpoint's control Register + 0x138 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP6_CNT0 + Non-control endpoint count register + 0x170 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP6_CNT1 + Non-control endpoint count register + 0x174 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP6_CR0 + Non-control endpoint's control Register + 0x178 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP7_CNT0 + Non-control endpoint count register + 0x1B0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP7_CNT1 + Non-control endpoint count register + 0x1B4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP7_CR0 + Non-control endpoint's control Register + 0x1B8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP8_CNT0 + Non-control endpoint count register + 0x1F0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP8_CNT1 + Non-control endpoint count register + 0x1F4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP8_CR0 + Non-control endpoint's control Register + 0x1F8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + ARB_EP1_CFG + Endpoint Configuration Register *1 + 0x200 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP1_INT_EN + Endpoint Interrupt Enable Register *1 + 0x204 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP1_SR + Endpoint Interrupt Enable Register *1 + 0x208 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW1_WA + Endpoint Write Address value *1, *2 + 0x210 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW1_WA_MSB + Endpoint Write Address value *1, *2 + 0x214 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW1_RA + Endpoint Read Address value *1, *2 + 0x218 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW1_RA_MSB + Endpoint Read Address value *1, *2 + 0x21C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW1_DR + Endpoint Data Register + 0x220 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUF_SIZE + Dedicated Endpoint Buffer Size Register *1 + 0x230 + 32 + read-write + 0x0 + 0xFF + + + IN_BUF + Buffer size for IN Endpoints. + [3:0] + read-write + + + OUT_BUF + Buffer size for OUT Endpoints. + [7:4] + read-write + + + + + EP_ACTIVE + Endpoint Active Indication Register *1 + 0x238 + 32 + read-write + 0x0 + 0xFF + + + EP1_ACT + Indicates that Endpoint is currently active. + [0:0] + read-write + + + EP2_ACT + Indicates that Endpoint is currently active. + [1:1] + read-write + + + EP3_ACT + Indicates that Endpoint is currently active. + [2:2] + read-write + + + EP4_ACT + Indicates that Endpoint is currently active. + [3:3] + read-write + + + EP5_ACT + Indicates that Endpoint is currently active. + [4:4] + read-write + + + EP6_ACT + Indicates that Endpoint is currently active. + [5:5] + read-write + + + EP7_ACT + Indicates that Endpoint is currently active. + [6:6] + read-write + + + EP8_ACT + Indicates that Endpoint is currently active. + [7:7] + read-write + + + + + EP_TYPE + Endpoint Type (IN/OUT) Indication *1 + 0x23C + 32 + read-write + 0x0 + 0xFF + + + EP1_TYP + Endpoint Type Indication. + [0:0] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP2_TYP + Endpoint Type Indication. + [1:1] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP3_TYP + Endpoint Type Indication. + [2:2] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP4_TYP + Endpoint Type Indication. + [3:3] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP5_TYP + Endpoint Type Indication. + [4:4] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP6_TYP + Endpoint Type Indication. + [5:5] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP7_TYP + Endpoint Type Indication. + [6:6] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP8_TYP + Endpoint Type Indication. + [7:7] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + + + ARB_EP2_CFG + Endpoint Configuration Register *1 + 0x240 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP2_INT_EN + Endpoint Interrupt Enable Register *1 + 0x244 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP2_SR + Endpoint Interrupt Enable Register *1 + 0x248 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW2_WA + Endpoint Write Address value *1, *2 + 0x250 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW2_WA_MSB + Endpoint Write Address value *1, *2 + 0x254 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW2_RA + Endpoint Read Address value *1, *2 + 0x258 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW2_RA_MSB + Endpoint Read Address value *1, *2 + 0x25C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW2_DR + Endpoint Data Register + 0x260 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_CFG + Arbiter Configuration Register *1 + 0x270 + 32 + read-write + 0x0 + 0xF0 + + + AUTO_MEM + Enables Auto Memory Configuration. Manual memory configuration by default. + [4:4] + read-write + + + DMA_CFG + DMA Access Configuration. + [6:5] + read-write + + + DMA_NONE + No DMA + 0 + + + DMA_MANUAL + Manual DMA + 1 + + + DMA_AUTO + Auto DMA + 2 + + + + + CFG_CMP + Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. + [7:7] + read-write + + + + + USB_CLK_EN + USB Block Clock Enable Register + 0x274 + 32 + read-write + 0x0 + 0x1 + + + CSR_CLK_EN + Clock Enable for Core Logic clocked by AHB bus clock + [0:0] + read-write + + + + + ARB_INT_EN + Arbiter Interrupt Enable *1 + 0x278 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + ARB_INT_SR + Arbiter Interrupt Status *1 + 0x27C + 32 + read-only + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-only + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-only + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-only + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-only + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-only + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-only + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-only + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-only + + + + + ARB_EP3_CFG + Endpoint Configuration Register *1 + 0x280 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP3_INT_EN + Endpoint Interrupt Enable Register *1 + 0x284 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP3_SR + Endpoint Interrupt Enable Register *1 + 0x288 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW3_WA + Endpoint Write Address value *1, *2 + 0x290 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW3_WA_MSB + Endpoint Write Address value *1, *2 + 0x294 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW3_RA + Endpoint Read Address value *1, *2 + 0x298 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW3_RA_MSB + Endpoint Read Address value *1, *2 + 0x29C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW3_DR + Endpoint Data Register + 0x2A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + CWA + Common Area Write Address *1 + 0x2B0 + 32 + read-write + 0x0 + 0xFF + + + CWA + Write Address for Common Area + [7:0] + read-write + + + + + CWA_MSB + Endpoint Read Address value *1 + 0x2B4 + 32 + read-write + 0x0 + 0x1 + + + CWA_MSB + Write Address for Common Area + [0:0] + read-write + + + + + ARB_EP4_CFG + Endpoint Configuration Register *1 + 0x2C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP4_INT_EN + Endpoint Interrupt Enable Register *1 + 0x2C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP4_SR + Endpoint Interrupt Enable Register *1 + 0x2C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW4_WA + Endpoint Write Address value *1, *2 + 0x2D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW4_WA_MSB + Endpoint Write Address value *1, *2 + 0x2D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW4_RA + Endpoint Read Address value *1, *2 + 0x2D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW4_RA_MSB + Endpoint Read Address value *1, *2 + 0x2DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW4_DR + Endpoint Data Register + 0x2E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + DMA_THRES + DMA Burst / Threshold Configuration + 0x2F0 + 32 + read-write + 0x0 + 0xFF + + + DMA_THS + DMA Threshold count + [7:0] + read-write + + + + + DMA_THRES_MSB + DMA Burst / Threshold Configuration + 0x2F4 + 32 + read-write + 0x0 + 0x1 + + + DMA_THS_MSB + DMA Threshold count + [0:0] + read-write + + + + + ARB_EP5_CFG + Endpoint Configuration Register *1 + 0x300 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP5_INT_EN + Endpoint Interrupt Enable Register *1 + 0x304 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP5_SR + Endpoint Interrupt Enable Register *1 + 0x308 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW5_WA + Endpoint Write Address value *1, *2 + 0x310 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW5_WA_MSB + Endpoint Write Address value *1, *2 + 0x314 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW5_RA + Endpoint Read Address value *1, *2 + 0x318 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW5_RA_MSB + Endpoint Read Address value *1, *2 + 0x31C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW5_DR + Endpoint Data Register + 0x320 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUS_RST_CNT + Bus Reset Count Register + 0x330 + 32 + read-write + 0xA + 0xF + + + BUS_RST_CNT + Bus Reset Count Length + [3:0] + read-write + + + + + ARB_EP6_CFG + Endpoint Configuration Register *1 + 0x340 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP6_INT_EN + Endpoint Interrupt Enable Register *1 + 0x344 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP6_SR + Endpoint Interrupt Enable Register *1 + 0x348 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW6_WA + Endpoint Write Address value *1, *2 + 0x350 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW6_WA_MSB + Endpoint Write Address value *1, *2 + 0x354 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW6_RA + Endpoint Read Address value *1, *2 + 0x358 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW6_RA_MSB + Endpoint Read Address value *1, *2 + 0x35C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW6_DR + Endpoint Data Register + 0x360 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP7_CFG + Endpoint Configuration Register *1 + 0x380 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP7_INT_EN + Endpoint Interrupt Enable Register *1 + 0x384 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP7_SR + Endpoint Interrupt Enable Register *1 + 0x388 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW7_WA + Endpoint Write Address value *1, *2 + 0x390 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW7_WA_MSB + Endpoint Write Address value *1, *2 + 0x394 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW7_RA + Endpoint Read Address value *1, *2 + 0x398 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW7_RA_MSB + Endpoint Read Address value *1, *2 + 0x39C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW7_DR + Endpoint Data Register + 0x3A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP8_CFG + Endpoint Configuration Register *1 + 0x3C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP8_INT_EN + Endpoint Interrupt Enable Register *1 + 0x3C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP8_SR + Endpoint Interrupt Enable Register *1 + 0x3C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW8_WA + Endpoint Write Address value *1, *2 + 0x3D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW8_WA_MSB + Endpoint Write Address value *1, *2 + 0x3D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW8_RA + Endpoint Read Address value *1, *2 + 0x3D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW8_RA_MSB + Endpoint Read Address value *1, *2 + 0x3DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW8_DR + Endpoint Data Register + 0x3E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + 512 + 4 + MEM_DATA[%s] + DATA + 0x400 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + SOF16 + Start Of Frame Register + 0x1060 + 32 + read-only + 0x0 + 0x7FF + + + FRAME_NUMBER16 + The frame number (11b) + [10:0] + read-only + + + + + OSCLK_DR16 + Oscillator lock data register + 0x1080 + 32 + read-only + 0x0 + 0x0 + + + ADDER16 + These bits return the oscillator locking circuits adder output. + [14:0] + read-only + + + + + ARB_RW1_WA16 + Endpoint Write Address value *3 + 0x1210 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW1_RA16 + Endpoint Read Address value *3 + 0x1218 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW1_DR16 + Endpoint Data Register + 0x1220 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW2_WA16 + Endpoint Write Address value *3 + 0x1250 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW2_RA16 + Endpoint Read Address value *3 + 0x1258 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW2_DR16 + Endpoint Data Register + 0x1260 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW3_WA16 + Endpoint Write Address value *3 + 0x1290 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW3_RA16 + Endpoint Read Address value *3 + 0x1298 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW3_DR16 + Endpoint Data Register + 0x12A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + CWA16 + Common Area Write Address + 0x12B0 + 32 + read-write + 0x0 + 0x1FF + + + CWA16 + Write Address for Common Area + [8:0] + read-write + + + + + ARB_RW4_WA16 + Endpoint Write Address value *3 + 0x12D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW4_RA16 + Endpoint Read Address value *3 + 0x12D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW4_DR16 + Endpoint Data Register + 0x12E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + DMA_THRES16 + DMA Burst / Threshold Configuration + 0x12F0 + 32 + read-write + 0x0 + 0x1FF + + + DMA_THS16 + DMA Threshold count + [8:0] + read-write + + + + + ARB_RW5_WA16 + Endpoint Write Address value *3 + 0x1310 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW5_RA16 + Endpoint Read Address value *3 + 0x1318 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW5_DR16 + Endpoint Data Register + 0x1320 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW6_WA16 + Endpoint Write Address value *3 + 0x1350 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW6_RA16 + Endpoint Read Address value *3 + 0x1358 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW6_DR16 + Endpoint Data Register + 0x1360 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW7_WA16 + Endpoint Write Address value *3 + 0x1390 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW7_RA16 + Endpoint Read Address value *3 + 0x1398 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW7_DR16 + Endpoint Data Register + 0x13A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW8_WA16 + Endpoint Write Address value *3 + 0x13D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW8_RA16 + Endpoint Read Address value *3 + 0x13D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW8_DR16 + Endpoint Data Register + 0x13E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + + USBLPM + USB Device LPM and PHY Test + 0x00002000 + + POWER_CTL + Power Control Register + 0x0 + 32 + read-write + 0x0 + 0x303F0004 + + + SUSPEND + Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). +Note: +- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. + [2:2] + read-write + + + DP_UP_EN + Enables the pull up on the DP. +'0' : Disable. +'1' : Enable. + [16:16] + read-write + + + DP_BIG + Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DP. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DP + [17:17] + read-write + + + DP_DOWN_EN + Enables the ~15k pull down on the DP. + [18:18] + read-write + + + DM_UP_EN + Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. +'0' : Disable. +'1' : Enable. + [19:19] + read-write + + + DM_BIG + Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DM. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DM + [20:20] + read-write + + + DM_DOWN_EN + Enables the ~15k pull down on the DP. + [21:21] + read-write + + + ENABLE_DPO + Enables the single ended receiver on D+. + [28:28] + read-write + + + ENABLE_DMO + Enables the signle ended receiver on D-. + [29:29] + read-write + + + + + USBIO_CTL + USB IO Control Register + 0x8 + 32 + read-write + 0x0 + 0x3F + + + DM_P + The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. + [2:0] + read-write + + + OFF + Mode 0: Output buffer off (high Z). Input buffer off. + 0 + + + INPUT + Mode 1: Output buffer off (high Z). Input buffer on. + +Other values, not supported. + 1 + + + + + DM_M + The GPIO Drive Mode for DM IO pad. + [5:3] + read-write + + + + + FLOW_CTL + Flow Control Register + 0xC + 32 + read-write + 0x0 + 0xFF + + + EP1_ERR_RESP + End Point 1 error response +0: do nothing (backward compatibility mode) +1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK + [0:0] + read-write + + + EP2_ERR_RESP + End Point 2 error response + [1:1] + read-write + + + EP3_ERR_RESP + End Point 3 error response + [2:2] + read-write + + + EP4_ERR_RESP + End Point 4 error response + [3:3] + read-write + + + EP5_ERR_RESP + End Point 5 error response + [4:4] + read-write + + + EP6_ERR_RESP + End Point 6 error response + [5:5] + read-write + + + EP7_ERR_RESP + End Point 7 error response + [6:6] + read-write + + + EP8_ERR_RESP + End Point 8 error response + [7:7] + read-write + + + + + LPM_CTL + LPM Control Register + 0x10 + 32 + read-write + 0x0 + 0x17 + + + LPM_EN + LPM enable +0: Disabled, LPM token will not get a response (backward compatibility mode) +1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) + A STALL will be sent if the bLinkState is not 0001b + A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below + [0:0] + read-write + + + LPM_ACK_RESP + LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request +0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode +1: a LPM token will get an ACK response and the device will go to the requested low power mode + [1:1] + read-write + + + NYET_EN + Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). +0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. +1: a LPM token will get a NYET response + [2:2] + read-write + + + SUB_RESP + Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. + [4:4] + read-write + + + + + LPM_STAT + LPM Status register + 0x14 + 32 + read-only + 0x0 + 0x1F + + + LPM_BESL + Best Effort Service Latency +This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. + [3:0] + read-only + + + LPM_REMOTEWAKE + 0: Device is prohibited from initiating a remote wake +1: Device is allow to wake the host + [4:4] + read-only + + + + + INTR_SIE + USB SOF, BUS RESET and EP0 Interrupt Status + 0x20 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR + Interrupt status for USB SOF + [0:0] + read-write + + + BUS_RESET_INTR + Interrupt status for BUS RESET + [1:1] + read-write + + + EP0_INTR + Interrupt status for EP0 + [2:2] + read-write + + + LPM_INTR + Interrupt status for LPM (Link Power Management, L1 entry) + [3:3] + read-write + + + RESUME_INTR + Interrupt status for Resume + [4:4] + read-write + + + + + INTR_SIE_SET + USB SOF, BUS RESET and EP0 Interrupt Set + 0x24 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + BUS_RESET_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EP0_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + LPM_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + RESUME_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + + + INTR_SIE_MASK + USB SOF, BUS RESET and EP0 Interrupt Mask + 0x28 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [0:0] + read-write + + + BUS_RESET_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [1:1] + read-write + + + EP0_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [2:2] + read-write + + + LPM_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [3:3] + read-write + + + RESUME_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [4:4] + read-write + + + + + INTR_SIE_MASKED + USB SOF, BUS RESET and EP0 Interrupt Masked + 0x2C + 32 + read-only + 0x0 + 0x1F + + + SOF_INTR_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + BUS_RESET_INTR_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EP0_INTR_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + LPM_INTR_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + RESUME_INTR_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + + + INTR_LVL_SEL + Select interrupt level for each interrupt source + 0x30 + 32 + read-write + 0x0 + 0xFFFFC3FF + + + SOF_LVL_SEL + USB SOF Interrupt level select + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + BUS_RESET_LVL_SEL + BUS RESET Interrupt level select + [3:2] + read-write + + + EP0_LVL_SEL + EP0 Interrupt level select + [5:4] + read-write + + + LPM_LVL_SEL + LPM Interrupt level select + [7:6] + read-write + + + RESUME_LVL_SEL + Resume Interrupt level select + [9:8] + read-write + + + ARB_EP_LVL_SEL + Arbiter Endpoint Interrupt level select + [15:14] + read-write + + + EP1_LVL_SEL + EP1 Interrupt level select + [17:16] + read-write + + + EP2_LVL_SEL + EP2 Interrupt level select + [19:18] + read-write + + + EP3_LVL_SEL + EP3 Interrupt level select + [21:20] + read-write + + + EP4_LVL_SEL + EP4 Interrupt level select + [23:22] + read-write + + + EP5_LVL_SEL + EP5 Interrupt level select + [25:24] + read-write + + + EP6_LVL_SEL + EP6 Interrupt level select + [27:26] + read-write + + + EP7_LVL_SEL + EP7 Interrupt level select + [29:28] + read-write + + + EP8_LVL_SEL + EP8 Interrupt level select + [31:30] + read-write + + + + + INTR_CAUSE_HI + High priority interrupt Cause register + 0x34 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_MED + Medium priority interrupt Cause register + 0x38 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_LO + Low priority interrupt Cause register + 0x3C + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + DFT_CTL + DFT control + 0x70 + 32 + read-write + 0x0 + 0x1F + + + DDFT_OUT_SEL + DDFT output select signal + [2:0] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + DP_SE + Single Ended output of DP + 1 + + + DM_SE + Single Ended output of DM + 2 + + + TXOE + Output Enable + 3 + + + RCV_DF + Differential Receiver output + 4 + + + GPIO_DP_OUT + GPIO output of DP + 5 + + + GPIO_DM_OUT + GPIO output of DM + 6 + + + + + DDFT_IN_SEL + DDFT input select signal + [4:3] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + GPIO_DP_IN + GPIO input of DP + 1 + + + GPIO_DM_IN + GPIO input of DM + 2 + + + + + + + + USBHOST + USB Host Controller + 0x00004000 + + HOST_CTL0 + Host Control 0 Register. + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + HOST + This bit selects an operating mode of this IP. +'0' : USB Device +'1' : USB Host +Notes: +- The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. +- This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. +- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. + * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. + * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. + * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. + [0:0] + read-write + + + ENABLE + This bit enables the operation of this IP. +'0' : Disable USB Host +'1' : Enable USB Host +Note: +- This bit doesn't affect the USB Device. + [31:31] + read-write + + + + + HOST_CTL1 + Host Control 1 Register. + 0x10 + 32 + read-write + 0x83 + 0x83 + + + CLKSEL + This bit selects the operating clock of USB Host. +'0' : Low-speed clock +'1' : Full-speed clock +Notes: +- This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- This bit must always be set to '1' in the USB Device mode. + [0:0] + read-write + + + USTP + This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. +'0' : Normal operating mode. +'1' : Stops the clock for the USB Host operating unit. +Notes: +- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. + [1:1] + read-write + + + RST + This bit resets the USB Host. +'0' : Normal operating mode. +'1' : USB Host is reset. +Notes: +- This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. + [7:7] + read-write + + + + + HOST_CTL2 + Host Control 2 Register. + 0x100 + 32 + read-write + 0x1 + 0xFF + + + RETRY + If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). +* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' +'0' : Doesn't retry token sending. +'1' : Retries token sending +Note: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + CANCEL + When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). +'0' : Continues a token. +'1' : Cancels a token. + [1:1] + read-write + + + SOFSTEP + If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. +If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. +'0' : An interrupt occurred due to the HOST_HFCOMP setting. +'1' : An interrupt occurred. +Notes: +- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. + [2:2] + read-write + + + ALIVE + This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. +'0' : SOF output. +'1' : SE0 output (Keep alive) + [3:3] + read-write + + + RSVD_4 + N/A + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-write + + + TTEST + N/A + [7:6] + read-write + + + + + HOST_ERR + Host Error Status Register. + 0x104 + 32 + read-write + 0x3 + 0xFF + + + HS + These flags indicate the status of a handshake packet to be sent or received. +These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +These bits are updated when sending or receiving has been ended. +Write '11' to set the status back to 'NULL', all other write values are ignored. +Note: +This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:0] + read-write + + + ACK + Acknowledge Packet + 0 + + + NAK + Non-Acknowledge Packet + 1 + + + STALL + Stall Packet + 2 + + + NULL + Null Packet + 3 + + + + + STUFF + If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No stuffing error. +'1' : Stuffing error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + TGERR + If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No toggle error. +'1' : Toggle error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:3] + read-write + + + CRC + If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No CRC error. +'1' : CRC error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + TOUT + If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No timeout. +'1' : Timeout has detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RERR + When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No receive error. +'1' : Maximum packet receive error detected. +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:6] + read-write + + + LSTSOF + If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. +'0' : SOF sent without error. +'1' : SOF error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + HOST_STATUS + Host Status Register. + 0x108 + 32 + read-write + 0xC2 + 0x1FF + + + CSTAT + When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. +'0' : Device is disconnected. +'1' : Device is connected. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [0:0] + read-only + + + TMODE + If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. +'0' : Low-speed. +'1' : Full-speed. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [1:1] + read-only + + + SUSP + If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +Set to '1' : Suspend. +Set '0' when this bit is '1' : Resume. +Other conditions : Holds the status. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. +- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). +- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. + [2:2] + read-write + + + SOFBUSY + When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. +'0' : The SOF timer is stopped. +'1' : The SOF timer is active. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). +- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. + [3:3] + read-write + + + URST + When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-only + + + RSTBUSY + This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. +'0' : USB Host isn't being reset. +'1' : USB Host is being reset. +Notes: +- If this bit is '1', the a token must not be executed. +- This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. + [6:6] + read-only + + + CLKSEL_ST + This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +'0' : Low speed +'1' : Full speed +Note: +- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [7:7] + read-only + + + HOST_ST + This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. +'0' : USB Device +'1' : USB Host +Notes: +- If this bit is different from the HOST bit, The execution of a token must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [8:8] + read-only + + + + + HOST_FCOMP + Host SOF Interrupt Frame Compare Register + 0x10C + 32 + read-write + 0x0 + 0xFF + + + FRAMECOMP + These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. +If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:0] + read-write + + + + + HOST_RTIMER + Host Retry Timer Setup Register + 0x110 + 32 + read-write + 0x0 + 0x3FFFF + + + RTIMER + These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. +If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. + [17:0] + read-write + + + + + HOST_ADDR + Host Address Register + 0x114 + 32 + read-write + 0x0 + 0x7F + + + ADDRESS + These bits are used to specify a token address. +Note: +- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:0] + read-write + + + + + HOST_EOF + Host EOF Setup Register + 0x118 + 32 + read-write + 0x0 + 0x3FFF + + + EOF + These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. +Setting example: MAXPKT = 64 bytes, full-speed mode + (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time + =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit + Therefore, set 0x2C9. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [13:0] + read-write + + + + + HOST_FRAME + Host Frame Setup Register + 0x11C + 32 + read-write + 0x0 + 0x7FF + + + FRAME + These bits are used to specify a frame number of SOF. +Notes: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. + [10:0] + read-write + + + + + HOST_TOKEN + Host Token Endpoint Register + 0x120 + 32 + read-write + 0x0 + 0x17F + + + ENDPT + These bits are used to specify an endpoint to send or receive data to or from the device. +Note: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:0] + read-write + + + TKNEN + These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The PRE packet isn't supported. +- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' +- Mode should be USB Host before writing data to this bit. +- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. +- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. +- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [6:4] + read-write + + + NONE + Sends no data. + 0 + + + SETUP + Sends SETUP token. + 1 + + + IN + Sends IN token. + 2 + + + OUT + Sends OUT token. + 3 + + + SOF + Sends SOF token. + 4 + + + ISO_IN + Sends Isochronous IN. + 5 + + + ISO_OUT + Sends Isochronous OUT. + 6 + + + RSV + N/A + 7 + + + + + TGGL + This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. +'0' : DATA0 +'1' : DATA1 +Notes: +- This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. + [8:8] + read-write + + + + + HOST_EP1_CTL + Host Endpoint 1 Control Register + 0x400 + 32 + read-write + 0x8100 + 0x9DFF + + + PKS1 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. +- If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, + [8:0] + read-write + + + NULLE + When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the packet transfer mode. +'1' : Sets the packet transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. + [15:15] + read-write + + + + + HOST_EP1_STATUS + Host Endpoint 1 Status Register + 0x404 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE1 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. +The indication range is from 0x000 to 0x100. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [8:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP1 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. +'0' : Not initiatialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP1_RW1_DR + Host Endpoint 1 Data 1-Byte Register + 0x408 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP1 for 1-byte data + [7:0] + read-write + + + + + HOST_EP1_RW2_DR + Host Endpoint 1 Data 2-Byte Register + 0x40C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP1 for 2-byte data + [15:0] + read-write + + + + + HOST_EP2_CTL + Host Endpoint 2 Control Register + 0x500 + 32 + read-write + 0x8040 + 0x9C7F + + + PKS2 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. +- If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. + [6:0] + read-write + + + NULLE + When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the automatic buffer transfer mode. +'1' : Sets the automatic buffer transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. + [15:15] + read-write + + + + + HOST_EP2_STATUS + Host Endpoint 2 Status Register + 0x504 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE2 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. +The indication range is from 0x000 to 0x40. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [6:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP2 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. +'0' : Not Initialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP2_RW1_DR + Host Endpoint 2 Data 1-Byte Register + 0x508 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP2 for 1-byte data. + [7:0] + read-write + + + + + HOST_EP2_RW2_DR + Host Endpoint 2 Data 2-Byte Register + 0x50C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP2 for 2 byte data. + [15:0] + read-write + + + + + HOST_LVL1_SEL + Host Interrupt Level 1 Selection Register + 0x800 + 32 + read-write + 0x0 + 0xFFFF + + + SOFIRQ_SEL + These bits assign SOFIRQ interrupt flag to selected interrupt signals. + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + DIRQ_SEL + These bits assign DIRQ interrupt flag to selected interrupt signals. + [3:2] + read-write + + + CNNIRQ_SEL + These bits assign CNNIRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + CMPIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [7:6] + read-write + + + URIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + RWKIRQ_SEL + These bits assign RWKIRQ interrupt flag to selected interrupt signals. + [11:10] + read-write + + + RSVD_13_12 + N/A + [13:12] + read-write + + + TCAN_SEL + These bits assign TCAN interrupt flag to selected interrupt signals. + [15:14] + read-write + + + + + HOST_LVL2_SEL + Host Interrupt Level 2 Selection Register + 0x804 + 32 + read-write + 0x0 + 0xFF0 + + + EP1_DRQ_SEL + These bits assign EP1_DRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + EP1_SPK_SEL + These bits assign EP1_SPK interrupt flag to selected interrupt signals. + [7:6] + read-write + + + EP2_DRQ_SEL + These bits assign EP2_DRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + EP2_SPK_SEL + These bits assign EP2_SPK interrupt flag to selected interrupt signals. + [11:10] + read-write + + + + + INTR_USBHOST_CAUSE_HI + Interrupt USB Host Cause High Register + 0x900 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_MED + Interrupt USB Host Cause Medium Register + 0x904 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_LO + Interrupt USB Host Cause Low Register + 0x908 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_HOST_EP_CAUSE_HI + Interrupt USB Host Endpoint Cause High Register + 0x920 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_MED + Interrupt USB Host Endpoint Cause Medium Register + 0x924 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_LO + Interrupt USB Host Endpoint Cause Low Register + 0x928 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_USBHOST + Interrupt USB Host Register + 0x940 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQ + If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Does not issue an interrupt request by starting a SOF token. +'1' : Issues an interrupt request by starting a SOF token. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + DIRQ + If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device disconnection. +'1' : Issues an interrupt request by detecting a device disconnection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:1] + read-write + + + CNNIRQ + If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device connection. +'1' : Issues an interrupt request by detecting a device connection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + CMPIRQ + If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by token completion. +'1' : Issues an interrupt request by token completion. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. +- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [3:3] + read-write + + + URIRQ + If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by USB bus resetting. +'1' : Issues an interrupt request by USB bus resetting. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + RWKIRQ + If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by restart. +'1' : Issues an interrupt request by restart. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCAN + If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. +'0' : Does not cancel token sending. +'1' : Cancels token sending. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + INTR_USBHOST_SET + Interrupt USB Host Set Register + 0x944 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQS + This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [0:0] + read-write + + + DIRQS + This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [1:1] + read-write + + + CNNIRQS + This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [2:2] + read-write + + + CMPIRQS + This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [3:3] + read-write + + + URIRQS + This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [4:4] + read-write + + + RWKIRQS + This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANS + This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. + [7:7] + read-write + + + + + INTR_USBHOST_MASK + Interrupt USB Host Mask Register + 0x948 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQM + This bit masks the interrupt by SOF flag. +'0' : Disables +'1' : Enables + [0:0] + read-write + + + DIRQM + This bit masks the interrupt by DIRQ flag. +'0' : Disables +'1' : Enables + [1:1] + read-write + + + CNNIRQM + This bit masks the interrupt by CNNIRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + CMPIRQM + This bit masks the interrupt by CMPIRQ flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + URIRQM + This bit masks the interrupt by URIRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + RWKIRQM + This bit masks the interrupt by RWKIRQ flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANM + This bit masks the interrupt by TCAN flag. +'0' : Disables +'1' : Enables + [7:7] + read-write + + + + + INTR_USBHOST_MASKED + Interrupt USB Host Masked Register + 0x94C + 32 + read-only + 0x0 + 0xFF + + + SOFIRQED + This bit indicates the interrupt by SOF flag. +'0' : Doesn't request the interrupt by SOF +'1' : Request the interrupt by SOF + [0:0] + read-only + + + DIRQED + This bit indicates the interrupt by DIRQ flag. +'0' : Doesn't request the interrupt by DIRQ +'1' : Request the interrupt by DIRQ + [1:1] + read-only + + + CNNIRQED + This bit indicates the interrupt by CNNIRQ flag. +'0' : Doesn't request the interrupt by CNNIRQ +'1' : Request the interrupt by CNNIRQ + [2:2] + read-only + + + CMPIRQED + This bit indicates the interrupt by CMPIRQ flag. +'0' : Doesn't request the interrupt by CMPIRQ +'1' : Request the interrupt by CMPIRQ + [3:3] + read-only + + + URIRQED + This bit indicates the interrupt by URIRQ flag. +'0' : Doesn't request the interrupt by URIRQ +'1' : Request the interrupt by URIRQ + [4:4] + read-only + + + RWKIRQED + This bit indicates the interrupt by RWKIRQ flag. +'0' : Doesn't request the interrupt by RWKIRQ +'1' : Request the interrupt by RWKIRQ + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCANED + This bit indicates the interrupt by TCAN flag. +'0' : Doesn't request the interrupt by TCAN +'1' : Request the interrupt by TCAN + [7:7] + read-only + + + + + INTR_HOST_EP + Interrupt USB Host Endpoint Register + 0xA00 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQ + This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [2:2] + read-write + + + EP1SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The EP1SPK bit is not set during data transfer in the OUT direction. + [3:3] + read-write + + + EP2DRQ + This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [4:4] + read-write + + + EP2SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The SPK bit is not set during data transfer in the OUT direction. + [5:5] + read-write + + + + + INTR_HOST_EP_SET + Interrupt USB Host Endpoint Set Register + 0xA04 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQS + This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. + [2:2] + read-write + + + EP1SPKS + This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. + [3:3] + read-write + + + EP2DRQS + This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. + [4:4] + read-write + + + EP2SPKS + This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. + [5:5] + read-write + + + + + INTR_HOST_EP_MASK + Interrupt USB Host Endpoint Mask Register + 0xA08 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQM + This bit masks the interrupt by EP1DRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + EP1SPKM + This bit masks the interrupt by EP1SPK flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + EP2DRQM + This bit masks the interrupt by EP2DRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + EP2SPKM + This bit masks the interrupt by EP2SPK flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + + + INTR_HOST_EP_MASKED + Interrupt USB Host Endpoint Masked Register + 0xA0C + 32 + read-only + 0x0 + 0x3C + + + EP1DRQED + This bit indicates the interrupt by EP1DRQ flag. +'0' : Doesn't request the interrupt by EP1DRQ +'1' : Request the interrupt by EP1DRQ + [2:2] + read-only + + + EP1SPKED + This bit indicates the interrupt by EP1SPK flag. +'0' : Doesn't request the interrupt by EP1SPK +'1' : Request the interrupt by EP1SPK + [3:3] + read-only + + + EP2DRQED + This bit indicates the interrupt by EP2DRQ flag. +'0' : Doesn't request the interrupt by EP2DRQ +'1' : Request the interrupt by EP2DRQ + [4:4] + read-only + + + EP2SPKED + This bit indicates the interrupt by EP2SPK flag. +'0' : Doesn't request the interrupt by EP2SPK +'1' : Request the interrupt by EP2SPK + [5:5] + read-only + + + + + HOST_DMA_ENBL + Host DMA Enable Register + 0xB00 + 32 + read-write + 0x0 + 0xC + + + DM_EP1DRQE + This bit enables DMA Request by EP1DRQ. +'0' : Disable +'1' : Enable + [2:2] + read-write + + + DM_EP2DRQE + This bit enables DMA Request by EP2DRQ. +'0' : Disable +'1' : Enable + [3:3] + read-write + + + + + HOST_EP1_BLK + Host Endpoint 1 Block Register + 0xB20 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') + [31:16] + read-write + + + + + HOST_EP2_BLK + Host Endpoint 2 Block Register + 0xB30 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') + [31:16] + read-write + + + + + + + + SMIF0 + Serial Memory Interface + SMIF + 0x40420000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x3000 + 0x81073001 + + + XIP_MODE + Mode of operation. + +Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. + [0:0] + read-write + + + MMIO_MODE + '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. + 0 + + + XIP_MODE + 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. + 1 + + + + + CLOCK_IF_RX_SEL + Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. +'0': 'spi_clk_out' (internal clock) +'1': !'spi_clk_out' (internal clock) +'2': 'spi_clk_in' (feedback clock) +'3': !'spi_clk_in' (feedback clock) + +Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. + [13:12] + read-write + + + DESELECT_DELAY + Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: +'0': 1 interface clock cycle. +'1': 2 interface clock cycles. +'2': 3 interface clock cycles. +'3': 4 interface clock cycles. +'4': 5 interface clock cycles. +'5': 6 interface clock cycles. +'6': 7 interface clock cycles. +'7': 8 interface clock cycles. + +During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. + [18:16] + read-write + + + BLOCK + Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. + +This field is not used for test controller accesses. + [24:24] + read-write + + + BUS_ERROR + 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). + 0 + + + WAIT_STATES + 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). + 1 + + + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. +'1': Enabled. + +Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + Cache, cryptography, XIP, device interface or any other logic busy in the IP: +'0': not busy +'1': busy +When BUSY is '0', the IP can be safely disabled without: +- the potential loss of transient write data. +- the potential risk of aborting an inflight SPI device interface transfer. +When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. + [31:31] + read-only + + + + + TX_CMD_FIFO_STATUS + Transmitter command FIFO status + 0x44 + 32 + read-only + 0x0 + 0x7 + + + USED3 + Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. + [2:0] + read-only + + + + + TX_CMD_FIFO_WR + Transmitter command FIFO write + 0x50 + 32 + write-only + 0x0 + 0xFFFFF + + + DATA20 + Command data. The higher two bits DATA[19:18] specify the specific command +'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. +- DATA[17:16] specifies the width of the data transfer: + - '0': 1 bit/cycle (single data transfer). + - '1': 2 bits/cycle (dual data transfer). + - '2': 4 bits/cycle (quad data transfer). + - '3': 8 bits/cycle (octal data transfer). +- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. +- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. + - '0': device deselected + - '1': device selected +- DATA[7:0] specifies the transmitted Byte. + +'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. + +'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. + +'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. +- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. + [19:0] + write-only + + + + + TX_DATA_FIFO_CTL + Transmitter data FIFO control + 0x80 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. + [2:0] + read-write + + + + + TX_DATA_FIFO_STATUS + Transmitter data FIFO status + 0x84 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_DATA_FIFO_WR1 + Transmitter data FIFO write + 0x90 + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + TX_DATA_FIFO_WR2 + Transmitter data FIFO write + 0x94 + 32 + write-only + 0x0 + 0xFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + + + TX_DATA_FIFO_WR4 + Transmitter data FIFO write + 0x98 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + DATA2 + TX data (written to TX data FIFO, third byte). + [23:16] + write-only + + + DATA3 + TX data (written to TX data FIFO, fourth byte). + [31:24] + write-only + + + + + RX_DATA_FIFO_CTL + Receiver data FIFO control + 0xC0 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. + [2:0] + read-write + + + + + RX_DATA_FIFO_STATUS + Receiver data FIFO status + 0xC4 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + RX_DATA_FIFO_RD1 + Receiver data FIFO read + 0xD0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + RX_DATA_FIFO_RD2 + Receiver data FIFO read + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + + + RX_DATA_FIFO_RD4 + Receiver data FIFO read + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + DATA2 + RX data (read from RX data FIFO, third byte). + [23:16] + read-only + + + DATA3 + RX data (read from RX data FIFO, fourth byte). + [31:24] + read-only + + + + + RX_DATA_FIFO_RD1_SILENT + Receiver data FIFO silent read + 0xE0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + SLOW_CA_CTL + Slow cache control + 0x100 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. + [25:24] + read-write + + + PREF_EN + Prefetch enable: +'0': Disabled. +'1': Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + ENABLED + Cache enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + SLOW_CA_CMD + Slow cache command + 0x108 + 32 + read-write + 0x0 + 0x1 + + + INV + Cache and prefetch buffer invalidation. +SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. +Note, +A write access will invalidate the prefetch buffer automatically in hardware. +A write access should invalidate both fast and slow caches, by firmware. +Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. + [0:0] + read-write + + + + + FAST_CA_CTL + Fast cache control + 0x180 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + See SLOW_CA_CTL.WAY. + [17:16] + read-write + + + SET_ADDR + See SLOW_CA_CTL.SET_ADDR. + [25:24] + read-write + + + PREF_EN + See SLOW_CA_CTL.PREF_EN. + [30:30] + read-write + + + ENABLED + See SLOW_CA_CTL.ENABLED. + [31:31] + read-write + + + + + FAST_CA_CMD + Fast cache command + 0x188 + 32 + read-write + 0x0 + 0x1 + + + INV + See SLOW_CA_CMD.INV. + [0:0] + read-write + + + + + CRYPTO_CMD + Cryptography Command + 0x200 + 32 + read-write + 0x0 + 0x1 + + + START + SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. + +The operation takes roughly 13 clk_hf clock cycles. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + + + CRYPTO_INPUT0 + Cryptography input 0 + 0x220 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT1 + Cryptography input 1 + 0x224 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT2 + Cryptography input 2 + 0x228 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT3 + Cryptography input 3 + 0x22C + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_KEY0 + Cryptography key 0 + 0x240 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY1 + Cryptography key 1 + 0x244 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY2 + Cryptography key 2 + 0x248 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY3 + Cryptography key 3 + 0x24C + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_OUTPUT0 + Cryptography output 0 + 0x260 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT1 + Cryptography output 1 + 0x264 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT2 + Cryptography output 2 + 0x268 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT3 + Cryptography output 3 + 0x26C + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. + [31:0] + read-write + + + + + INTR + Interrupt register + 0x7C0 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. + [0:0] + read-write + + + TR_RX_REQ + Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Activated in XIP mode, if: +- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. +- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. + +Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. + [5:5] + read-write + + + + + INTR_SET + Interrupt set register + 0x7C4 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x7C8 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x7CC + 32 + read-only + 0x0 + 0x3F + + + TR_TX_REQ + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TR_RX_REQ + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + XIP_ALIGNMENT_ERROR + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TX_CMD_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + TX_DATA_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + RX_DATA_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + 4 + 128 + DEVICE[%s] + Device (only used in XIP mode) + 0x00000800 + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80030101 + + + WR_EN + Write enable: +'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. +'1': write transfers are allowed to this device. + [0:0] + read-write + + + CRYPTO_EN + Cryptography on read/write accesses: +'0': disabled. +'1': enabled. + [8:8] + read-write + + + DATA_SEL + Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): +'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. +'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. +'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. +'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. + [17:16] + read-write + + + ENABLED + Device enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + ADDR + Device region base address + 0x8 + 32 + read-write + 0x0 + 0x0 + + + ADDR + Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. + +In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. + +The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. + [31:8] + read-write + + + + + MASK + Device region mask + 0xC + 32 + read-write + 0x0 + 0x0 + + + MASK + Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. + +The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. + +Note: a transfer request that is not in any device region results in an AHB-Lite bus error. + [31:8] + read-write + + + + + ADDR_CTL + Address control + 0x20 + 32 + read-write + 0x0 + 0x103 + + + SIZE2 + Specifies the size of the XIP device address in Bytes: +'0': 1 Byte address. +'1': 2 Byte address. +'2': 3 Byte address. +'3': 4 Byte address. +The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [1:0] + read-write + + + DIV2 + Specifies if the AHB-Lite bus transfer address is divided by 2 or not: +'0': No divide by 2. +'1': Divide by 2. + +This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [8:8] + read-write + + + + + RD_CMD_CTL + Read command control + 0x40 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of data transfer: +'0': 1 bit/cycle (single data transfer). +'1': 2 bits/cycle (dual data transfer). +'2': 4 bits/cycle (quad data transfer). +'3': 8 bits/cycle (octal data transfer). + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_ADDR_CTL + Read address control + 0x44 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + RD_MODE_CTL + Read mode control + 0x48 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DUMMY_CTL + Read dummy control + 0x4C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + +Note: this field specifies dummy cycles, not dummy Bytes! + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DATA_CTL + Read data control + 0x50 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_CMD_CTL + Write command control + 0x60 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_ADDR_CTL + Write address control + 0x64 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_MODE_CTL + Write mode control + 0x68 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DUMMY_CTL + Write dummy control + 0x6C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DATA_CTL + Write data control + 0x70 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + + + + SDHC0 + SD/eMMC Host Controller + SDHC + 0x40460000 + + 0 + 65536 + registers + + + + WRAP + MMIO at SDHC wrapper level + 0x00000000 + + CTL + Top level wrapper control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + IP Enable: +0: IP disabled, RAM in DeepSleep, SDHC_CORE regs are inaccessible (any attempts to access will result in AHB Error responses), IP is NOT held in reset but the clocks are gated +1: IP enabled, normal operation + [31:31] + read-write + + + + + + CORE + MMIO for Synopsys Mobile Storage Host Controller IP + 0x00001000 + + SDMASA_R + SDMA System Address register + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This +register contains the system memory address for an +SDMA transfer in the 32-bit addressing mode. When the +Host Controller stops an SDMA transfer, this register +points to the system address of the next contiguous data +position. It can be accessed only if no transaction is +executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the +Host Controller Version 4.10 specification, this register is +redefined as 32-bit Block Count. The Host Controller +decrements the block count of this register for every block +transfer and the data transfer stops when the count +reaches zero. This register must be accessed when no +transaction is executing. Reading this register during data +transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF - 4G - 1 Block +- ...... +- 0x0000_0002 - 2 Blocks +- 0x0000_0001 - 1 Block +- 0x0000_0000 - Stop Count +Note: +- When Host Version 4 Enable = 0, SDMA uses this register as system address and hence Auto CMD23 cannot be used with SDMA since this register is assigned for Auto CMD23 as 32-bit Block Count register. +-When Host Version 4 Enable = 1, SDMA uses ADMA system address register and this register is reassigned to 32-bit Block Count. This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. SDMA may use Auto CMD23 if 32-bit Block Count register is used. + [31:0] + read-write + + + + + BLOCKSIZE_R + Block Size register + 0x4 + 16 + read-write + 0x0 + 0x7FFF + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of +memory, it is set to 512 bytes. It can be accessed only if no +transaction is executing. Read operations during transfers +may return an invalid value, and write operations are +ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- ...... +- 0x1FF: 511 byte +- 0x200: 512 bytes +- ...... +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero +value for data transfer. + [11:0] + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system +memory. The SDMA transfer waits at every boundary +specified by these fields and the Host Controller generates +the DMA interrupt to request the Host Driver to update the +SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + [14:12] + read-write + + + + + BLOCKCOUNT_R + 16-bit Block Count register + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block +Count register is set to non-zero, the 16-bit Block Count +register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit +Block Count register is set to zero, the 32-bit Block Count +register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- ... - ... +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be +set to 0000h before programming the 32-bit block count +register when Auto CMD23 is enabled for non-DMA and +ADMA modes. + [15:0] + read-write + + + + + ARGUMENT_R + Argument register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ARGUMENT + Command Argument +These bits specify the SD/eMMC command argument that is +specified in bits 39-8 of the Command format. + [31:0] + read-write + + + + + XFER_MODE_R + Transfer Mode register + 0xC + 16 + read-write + 0x0 + 0x1FF + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a +DMA operation begins when the Host Driver writes to the +Command register. You can select one of the DMA modes by +using DMA Select in the Host Control 1 register. +Values: +- 0x1 (ENABLED): DMA Data transfer +- 0x0 (DISABLED): No data transfer or Non-DMA data +transfer + [0:0] + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is +relevant for multiple block transfers. If this bit is set to 0, the +Block Count register is disabled, which is useful in executing +an infinite transfer. The Host Driver must set this bit to 0 +when ADMA is used. When 16-bit Block Count register is used, the Host Driver can set this bit to 0 in ADMA2 mode to enable larger data transfer than the maximum of 65535 block counts supported by the 16-bit Block Count register. + [1:1] + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command +Disabled). +Values: +- 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +- 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +- 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +- 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Select + [3:2] + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. This +bit is set to 1 by the Host Driver to transfer data from the +SD/eMMC card to the Host Controller and it is set to 0 for all +other commands. +Values: +- 0x1 (READ): Read (Card to Host) +- 0x0 (WRITE): Write (Host to Card) + [4:4] + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer +commands using the DAT line. If this bit is set to 0, it is not +necessary to set the Block Count register. + [5:5] + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the +Response Error Check is selected. +Error statuses checked in R1: +- OUT_OF_RANGE +- ADDRESS_ERROR +- BLOCK_LEN_ERROR +- WP_VIOLATION +- CARD_IS_LOCKED +- COM_CRC_ERROR +- CARD_ECC_FAILED +- CC_ERROR +- ERROR +Response Flags checked in R5: +- COM_CRC_ERROR +- ERROR +- FUNCTION_NUMBER +- OUT_OF_RANGE +Values: +- 0x0 (RESP_R1): R1 (Memory) +- 0x1 (RESP_R5): R5 (SDIO) + [6:6] + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to +avoid overhead of response error check by Host driver. +Response types of only R1 and R5 can be checked by the +Controller. If the Host Controller checks the response error, +set this bit to 1 and set Response Interrupt Disable to 1. If an +error is detected, the Response Error interrupt is generated +in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any +response type other than R1 and R5. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + [7:7] + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to +avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the +Controller. +If Host Driver checks the response error, set this bit to 0 and +wait for Command Complete Interrupt and then check the +response register. +If the Host Controller checks the response error, set this bit +to 1 and set the Response Error Check Enable bit to 1. The +Command Complete Interrupt is disabled by this bit +regardless of the Command Complete Signal Enable. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + [8:8] + read-write + + + + + CMD_R + Command register + 0xE + 16 + read-write + 0x0 + 0x3FFF + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the +card. +Values: +- 0x0 (NO_RESP): No Response +- 0x1 (RESP_LEN_136): Response Length 136 +- 0x2 (RESP_LEN_48): Response Length 48 +- 0x3 (RESP_LEN_48B): Response Length 48; Check +Busy after response + [1:0] + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub +command. +Values: +- 0x0 (MAIN): Main Command +- 0x1 (SUB): Sub Command + [2:2] + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in +the response. If an error is detected, it is reported as a +Command CRC error. +Note: +- CRC Check enable must be set to 0 for the command +with no response, R3 response, and R4 response. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [3:3] + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in +the response to verify if it has the same value as the +command index. If the value is not the same, it is reported as +a Command Index error. +Note: +- Index Check enable must be set to 0 for the command +with no response, R2 response, R3 response and R4 +response. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [4:4] + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the +data is transferred using the DAT line. This bit is set to 0 in +the following instances: +- Command using the CMD line +- Command with no data transfer but using busy signal on +the DAT[0] line +- Resume Command +Values: +- 0x0 (NO_DATA): No Data Present +- 0x1 (DATA): Data Present + [5:5] + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or +reset CMD using CMD0/CMD52, CMD_TYPE field shall be +set to 0x3. +Values: +- 0x3 (ABORT_CMD): Abort +- 0x2 (RESUME_CMD): Resume +- 0x1 (SUSPEND_CMD): Suspend +- 0x0 (NORMAL_CMD): Normal + [7:6] + read-write + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified +in bits 45-40 of the Command Format. + [13:8] + read-write + + + + + RESP01_R + Response Register 0/1 + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the +Response Field) is updated in the RESP67_R register. + [31:0] + read-only + + + + + RESP23_R + Response Register 2/3 + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP23 + Command Response +These bits reflect 71-40 bits of the SD/eMMC Response + [31:0] + read-only + + + + + RESP45_R + Response Register 4/5 + 0x18 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP45 + Command Response +These bits reflect 103-72 bits of the Response Field. + [31:0] + read-only + + + + + RESP67_R + Response Register 6/7 + 0x1C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP67 + Command Response +These bits reflect bits 135-104 of SD/EMMC Response +Field. +Note: For Auto CMD, this register also reflects the 32-bit +response (bits 39-8 of the Response Field). + [31:0] + read-only + + + + + BUF_DATA_R + Buffer Data Port Register + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet +buffer. + [31:0] + read-write + + + + + PSTATE_REG + Present State Register + 0x24 + 32 + read-only + 0x0 + 0x1BFF0FF7 + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +- SD/eMMC mode: If this bit is set to 0, it indicates that the +CMD line is not in use and the Host controller can issue +an SD/eMMC command using the CMD line. This bit is +set when the command register is written. This bit is +cleared when the command response is received. This bit +is not cleared by the response of auto CMD12/23 but +cleared by the response of read/write command. +Values: +- 0x0 (READY): Host Controller is ready to issue a +command +- 0x1 (NOT_READY): Host Controller is not ready to issue +a command + [0:0] + read-only + + + CMD_INHIBIT_DAT + Command Inhibit (DAT) +This bit is applicable for SD/eMMC mode and is generated if +either DAT line active or Read transfer active is set to 1. If +this bit is set to 0, it indicates that the Host Controller can +issue subsequent SD/eMMC commands. +Values: +- 0x0 (READY): Can issue command which used DAT line +- 0x1 (NOT_READY): Cannot issue command which used +DAT line + [1:1] + read-only + + + DAT_LINE_ACTIVE + DAT Line Active (SD/eMMC Mode only) +This bit indicates whether one of the DAT lines on the +SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a +read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a +write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the +command executing busy is executing on an SD or eMMC +bus. +Values: +- 0x0 (INACTIVE): DAT Line Inactive +- 0x1 (ACTIVE): DAT Line Active + [2:2] + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from +errors and for debugging. These bits reflect the value of the +sd_dat_in (upper nibble) signal. + [7:4] + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for +SD/eMMC mode. +Values: +- 0x0 (INACTIVE): No valid data +- 0x1 (ACTIVE): Transferring data + [8:8] + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for +SD/eMMC mode. +Values: +- 0x0 (INACTIVE): No valid data +- 0x1 (ACTIVE): Transferring data + [9:9] + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space +is available for writing data. +Values: +- 0x0 (DISABLED): Write disable +- 0x1 (ENABLED): Write enable + [10:10] + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid +data exists in the Host buffer. +Values: +- 0x0 (DISABLED): Read disable +- 0x1 (ENABLED): Read enable + [11:11] + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The +Host Controller debounces this signal so that Host Driver +need not wait for it to stabilize. +Values: +- 0x0 (FALSE): Reset, Debouncing, or No card +- 0x1 (TRUE): Card Inserted + [16:16] + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A +card is not detected if this bit is set to 1 and the value of the +CARD_INSERTED bit is 0. +Values: +- 0x0 (FALSE): Reset or Debouncing +- 0x1 (TRUE): No Card or Inserted + [17:17] + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the +card_detect_n signal. +Values: +- 0x0 (FALSE): No card present +- 0x1 (TRUE): Card Present + [18:18] + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This +bit reflects the synchronized value of the card_write_prot +signal. +Values: +- 0x0 (FALSE): Write protected +- 0x1 (TRUE): Write enabled + [19:19] + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from +errors and for debugging. These bits reflect the value of the +sd_dat_in (lower nibble) signal. + [23:20] + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from +errors and for debugging. These bits reflect the value of the +sd_cmd_in signal. + [24:24] + read-only + + + HOST_REG_VOL + Host Regulator Voltage Stable +This bit is used to check whether the host regulator voltage is +stable for switching the voltage of UHS-I mode. This bit +reflects the synchronized value of the host_reg_vol_stable +signal. +Values: +- 0x0 (FALSE): Host Regulator Voltage is not stable +- 0x1 (TRUE): Host Regulator Voltage is stable + [25:25] + read-only + + + CMD_ISSU_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting +the command register due to an error except the Auto +CMD12 error. +Values: +- 0x0 (FALSE): No error for issuing a command +- 0x1 (TRUE): Command cannot be issued + [27:27] + read-only + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and +a sub command status. +Values: +- 0x0 (FALSE): Main Command Status +- 0x1 (TRUE): Sub Command Status + [28:28] + read-only + + + + + HOST_CTRL1_R + Host Control 1 Register + 0x28 + 8 + read-write + 0x0 + 0xFF + + + LED_CTRL + LED Control +This bit is used to caution the user not to remove the card +while the SD card is being accessed. The value is reflected +on the led_ctrl ouput. +Values: +- 0x0 (OFF): LED off +- 0x1 (ON): LED on + [0:0] + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of +the Host Controller. The Host Driver sets it to match the data +width of the SD/eMMC card. +Values: +- 0x1 (FOUR_BIT): 4-bit mode +- 0x0 (ONE_BIT): 1-bit mode + [1:1] + read-write + + + HIGH_SPEED_EN + High Speed Enable (SD/eMMC Mode only) +Before setting this bit, the Host Driver checks the High Speed +Support in the Capabilities register. +Note: SDHC always outputs the sd_cmd_out and +sd_dat_out lines at the rising edge of card clock +irrespective of this bit. +Values: +- 0x1 (HIGH_SPEED): High Speed mode +- 0x0 (NORMAL_SPEED): Normal Speed mode + [2:2] + read-write + + + DMA_SEL + N/A + [4:3] + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +- 0x1 (EIGHT_BIT): 8-bit Bus Width +- 0x0 (DEFAULT): Bus Width is selected by the Data +Transfer Width + [5:5] + read-write + + + CARD_DETECT_TEST_LVL + Card Detect Test Level +This bit is enabled while the Card Detect Signal Selection is +set to 1 and it indicates whether a card inserted or not. +Values: +- 0x1 (CARD_INSERTED): Card Inserted +- 0x0 (No_CARD): No Card + [6:6] + read-write + + + CARD_DETECT_SIG_SEL + Card Detect Signal Selection +This bit selects a source for card detection. When the source +for the card detection is switched, the interrupt must be +disabled during the switching period. +Values: +- 0x1 (CARD_DT_TEST_LEVEL): Card Detect Test Level +is selected (for test purpose) +- 0x0 (card_detect_n): card_detect_n signal is +selected (for normal use) + [7:7] + read-write + + + + + PWR_CTRL_R + Power Control Register + 0x29 + 8 + read-write + 0x0 + 0xF + + + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. This setting is +available on the card_if_pwr_en output so that it +can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus +Voltage Select bit. If the Host Controller detects a No Card +state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops +the SD Clock by clearing the SD_CLK_IN bit in the +CLK_CTRL_R register. +Values: +- 0x0 (OFF): Power off +- 0x1 (ON): Power on + [0:0] + read-write + + + SD_BUS_VOL_VDD1 + These bits are NON-operational (they can be written and read but they have no effect). In a generic HCI host these would select the card supply voltage. But, for the applications targeted for this block it is assumed that the card supply voltage is always fixed at the board level. If for some reason there is a variable power supply then that can be managed through normal GPIO programming separately. + [3:1] + read-write + + + + + BGAP_CTRL_R + Block Gap Control Register + 0x2A + 8 + read-write + 0x0 + 0xF + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions +at the next block gap for non-DMA, SDMA, and ADMA +transfers. +Values: +- 0x0 (XFER): Transfer +- 0x1 (STOP): Stop + [0:0] + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped +using the Stop At Block Gap Request. The Host Controller +automatically clears this bit when the transaction restarts. If +stop at block gap request is set to 1, any write to this bit is +ignored. +Values: +- 0x0 (NO_AFFECT): No Affect +- 0x1 (RESTART): Restart + [1:1] + read-write + + + RD_WAIT_CTRL + N/A + [2:2] + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is +used to select a sample point in the interrupt cycle. Setting to +1 enables interrupt detection at the block gap for a multiple +block transfer. +Values: +- 0x0 (DISABLE): Disabled +- 0x1 (ENABLE): Enabled + [3:3] + read-write + + + + + WUP_CTRL_R + Wakeup Control Register + 0x2B + 8 + read-write + 0x0 + 0x7 + + + WUP_CARD_INT + Wakeup Event Enable on SDIO Card Interrupt (through DAT[1]). +This bit enables wakeup event through an SDIO Card Interrupt +assertion in the Normal Interrupt Status register. This bit can +be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [0:0] + read-write + + + WUP_CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion +assertion in the Normal Interrupt Status register. FN_WUS +(Wake Up Support) in CIS does not affect this bit. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [1:1] + read-write + + + WUP_CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal +assertion in the Normal Interrupt Status register. For the +SDIO card, Wake Up Support (FN_WUS) in the Card +Information Structure (CIS) register does not affect this bit. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [2:2] + read-write + + + + + CLK_CTRL_R + Clock Control Register + 0x2C + 16 + read-write + 0x0 + 0xFFEF + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host +Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a +very low power state. Certain registers are not accessible when this bit is off. So, to be safe turn it on for any register access. +Values: +- 0x0 (FALSE): Stop +- 0x1 (TRUE): Oscillate + [0:0] + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability +twice after the Internal Clock Enable bit is set and after the +PLL Enable bit is set. This bit reflects the synchronized +value of the Internal Clock Stable signal after the Internal Clock +Enable bit is set to 1 and also reflects the synchronized +value of the Card Clock Stable signal after the PLL Enable bit is +set to 1. +Values: +- 0x0 (FALSE): Not Ready +- 0x1 (TRUE): Ready + [1:1] + read-only + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the clk_card output when set to 0. The +SDCLK Frequency Select bit can be changed when +this bit is set to 0. +Values: +- 0x0 (FALSE): Disable providing clk_card +- 0x1 (TRUE): Enable providing clk_card + [2:2] + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host +Version 4 Enable = 1). +Values: +- 0x0 (FALSE): PLL is in low power mode +- 0x1 (TRUE): PLL is enabled + [3:3] + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in +SDCLK Frequency Select. +Values: +- 0x0 (FALSE): Divided Clock Mode +- 0x1 (TRUE): Programmable Clock Mode + [5:5] + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK +Frequency Select control. + [7:6] + read-write + + + FREQ_SEL + SDCLK Frequency Select +These bits are used to select the frequency of the SDCLK +signal. +10-bit Divided Clock Mode: +- 0x3FF - 1/2046 Divided clock +- .......... +- N - 1/2N Divided Clock +- .......... +- 0x002 - 1/4 Divided Clock +- 0x001 - 1/2 Divided Clock +- 0x000 - Base clock (10MHz - 255 MHz) + [15:8] + read-write + + + + + TOUT_CTRL_R + Timeout Control Register + 0x2E + 8 + read-write + 0x0 + 0xF + + + TOUT_CNT + N/A + [3:0] + read-write + + + + + SW_RST_R + Software Reset Register + 0x2F + 8 + read-write + 0x0 + 0x7 + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the +card detection circuit. During its initialization, the Host Driver +sets this bit to 1 to reset the Host Controller. All registers are +reset except the capabilities register. If this bit is set to 1, the +Host Driver must issue reset command and reinitialize the +card. +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [0:0] + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able +to issue a command. This reset is effective only for a command +issuing circuit (including response error statuses related to +Command Inhibit (CMD) control) and does not affect the +data transfer circuit. Host Controller can continue data +transfer even after this reset is executed while handling +subcommand-response errors. +The following registers and bits are cleared by this bit: +- Present State register - Command Inhibit (CMD) bit +- Normal Interrupt Status register - Command Complete bit +- Error Interrupt Status - Response error statuses related +to Command Inhibit (CMD) bit +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [1:1] + read-write + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part +of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +- Buffer Data Port register +- Buffer is cleared and initialized. +- Present state register +- Buffer Read Enable +- Buffer Write Enable +- Read Transfer Active +- Write Transfer Active +- DAT Line Active +- Command Inhibit (DAT) +- Block Gap Control register +- Continue Request +- Stop At Block Gap Request +- Normal Interrupt status register +- Buffer Read Ready +- Buffer Write Ready +- DMA Interrupt +- Block Gap Event +- Transfer Complete +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [2:2] + read-write + + + + + NORMAL_INT_STAT_R + Normal Interrupt Status Register + 0x30 + 16 + read-write + 0x0 + 0xE1FF + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a +response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt +Disable in Transfer Mode Register is set to 1. +Values: +- 0x0 (FALSE): No command complete +- 0x1 (TRUE): Command Complete + [0:0] + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command +with status busy is completed. +Values: +- 0x0 (FALSE): Not complete +- 0x1 (TRUE): Command execution is completed + [1:1] + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at +block gap due to a Stop at Block Gap Request. +Values: +- 0x0 (FALSE): No Block Gap Event +- 0x1 (TRUE): Transaction stopped at block gap + [2:2] + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer +Boundary during transfer. In case of ADMA, by setting the Int +field in the descriptor table, the Host controller generates this +interrupt. This interrupt is not generated after a Transfer +Complete. +Values: +- 0x0 (FALSE): No DMA Interrupt +- 0x1 (TRUE): DMA Interrupt is generated + [3:3] + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +- 0x0 (FALSE): Not ready to write buffer +- 0x1 (TRUE): Ready to write buffer + [4:4] + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +- 0x0 (FALSE): Not ready to read buffer +- 0x1 (TRUE): Ready to read buffer + [5:5] + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State +register changes from 0 to 1. +Values: +- 0x0 (FALSE): Card state stable or Debouncing +- 0x1 (TRUE): Card Inserted + [6:6] + read-write + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State +register changes from 1 to 0. +Values: +- 0x0 (FALSE): Card state stable or Debouncing +- 0x1 (TRUE): Card Removed + [7:7] + read-write + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +- DAT[1] Interrupt Input for SD Mode +Values: +- 0x0 (FALSE): No Card Interrupt +- 0x1 (TRUE): Generate Card Interrupt + [8:8] + read-only + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 +and Response Type R1/R5 is set to 0 in Transfer Mode +register. This interrupt is used with response check function. +Values: +- 0x0 (FALSE): No Event +- 0x1 (TRUE): FX Event is detected + [13:13] + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event +has occurred in eMMC/SD mode. Read CQHCI's +CQIS/CRNQIS register for more details. In UHS-II Mode, +this bit is irrelevant. +Values: +- 0x0 (FALSE): No Event +- 0x1 (TRUE): Command Queuing Event is detected + [14:14] + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, +then this bit is set. +Values: +- 0x0 (FALSE): No Error +- 0x1 (TRUE): Error + [15:15] + read-only + + + + + ERROR_INT_STAT_R + Error Interrupt Status Register + 0x32 + 16 + read-write + 0x0 + 0x1FFF + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is +returned within 64 SD clock cycles from the end bit of the +command. If the Host Controller detects a CMD line conflict, +along with Command CRC Error bit, this bit is set to 1, +without waiting for 64 SD/eMMC card clock cycles. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Time out + [0:0] + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for +following two cases. +- If a response is returned and the Command Timeout +Error is set to 0 (indicating no timeout), this bit is set to 1 +when detecting a CRC error in the command response. +- The Host Controller detects a CMD line conflict by +monitoring the CMD line when a command is issued. If +the Host Controller drives the CMD line to 1 level, but +detects 0 level on the CMD line at the next SD clock +edge, then the Host Controller aborts the command (stop +driving CMD line) and set this bit to 1. The Command +Timeout Error is also set to 1 to distinguish a CMD line +conflict. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): CRC error generated + [1:1] + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command +response is 0 in SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): End Bit error generated + [2:2] + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the +command respons in SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [3:3] + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the +following timeout conditions: +- Busy timeout for R1b, R5b type +- Busy timeout after Write CRC status +- Write CRC Status timeout +- Read Data timeout +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Time out + [4:4] + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC +error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other +than 010 or when write CRC status timeout. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [5:5] + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 +at the end bit position of read data that uses the DAT line or +at the end bit position of the CRC status. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [6:6] + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control +register, the Host Controller is requested to supply power for +the SD Bus. If the Host Controller supports the Current Limit +function, it can be protected from an illegal card by stopping +power supply to the card in which case this bit indicates a +failure status. A reading of 1 for this bit means that the Host +Controller is not supplying power to the SD card due to some +failure. A reading of 0 for this bit means that the Host +Controller is supplying power and no error has occurred. The +Host Controller may require some sampling time to detect +the current limit. DWC_mshc Host Controller does not +support this function, this bit is always set to 0. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Power Fail + [7:7] + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in +SD/eMMC mode. This bit is set when detecting that any of +the bits D00 to D05 in Auto CMD Error Status register has +changed from 0 to 1. D07 is effective in case of Auto CMD12. +Auto CMD Error Status register is valid while this bit is set to +1 and may be cleared by clearing of this bit. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [8:8] + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during +ADMA-based data transfer. The error could be due to +following reasons: +- Error response received from System bus (Master I/F) +- ADMA3,ADMA2 Descriptors invalid +- CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the +ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects +an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that +an error has occurred in ST_FDS state. The Host Driver may +find that Valid bit is not set at the error descriptor. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [9:9] + read-write + + + TUNING_ERR + N/A + [10:10] + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check +function to avoid overhead of response error check by Host +Driver during DMA execution. If Response Error Check +Enable is set to 1 in the Transfer Mode register, Host +Controller Checks R1 or R5 response. If an error is detected +in a response, this bit is set to 1.This is applicable in +SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [11:11] + read-write + + + BOOT_ACK_ERR + Boot Acknowledgement Error +This bit is set when there is a timeout for boot +acknowledgement or when detecting boot ack status having +a value other than 010. This is applicable only when boot +acknowledgement is expected in eMMC mode. +In SD mode, this bit is irrelevant. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [12:12] + read-write + + + + + NORMAL_INT_STAT_EN_R + Normal Interrupt Status Enable Register + 0x34 + 16 + read-write + 0x0 + 0x7FFF + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt +request to the System. The Card Interrupt detection is +stopped when this bit is cleared and restarted when this bit is +set to 1. The Host Driver may clear the Card Interrupt Status +Enable before servicing the Card Interrupt and may set this +bit again after all interrupt requests from the card are cleared +to prevent inadvertent interrupts. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + INT_A_STAT_EN + N/A + [9:9] + read-write + + + INT_B_STAT_EN + N/A + [10:10] + read-write + + + INT_C_STAT_EN + N/A + [11:11] + read-write + + + RE_TUNE_EVENT_STAT_EN + N/A + [12:12] + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [13:13] + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + + + ERROR_INT_STAT_EN_R + Error Interrupt Status Enable Register + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode +only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + CMD_CRC_ERR_STAT_EN + ommand CRC Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [9:9] + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [10:10] + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [11:11] + read-write + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment +Error in Error Interrupt Status register +(ERROR_INT_STAT_R). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [12:12] + read-write + + + VENDOR_ERR_STAT_EN1 + N/A + [13:13] + read-write + + + VENDOR_ERR_STAT_EN2 + N/A + [14:14] + read-write + + + VENDOR_ERR_STAT_EN3 + N/A + [15:15] + read-write + + + + + NORMAL_INT_SIGNAL_EN_R + Normal Interrupt Signal Enable Register + 0x38 + 16 + read-write + 0x0 + 0x7FFF + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + INT_A_SIGNAL_EN + N/A + [9:9] + read-write + + + INT_B_SIGNAL_EN + N/A + [10:10] + read-write + + + INT_C_SIGNAL_EN + N/A + [11:11] + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + N/A + [12:12] + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [13:13] + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + + + ERROR_INT_SIGNAL_EN_R + Error Interrupt Signal Enable Register + 0x3A + 16 + read-write + 0x0 + 0xFFFF + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [3:3] + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [9:9] + read-write + + + TUNING_ERR_SIGNAL_EN + N/A + [10:10] + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [11:11] + read-write + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when +Boot Acknowledgement Error in Error Interrupt Status +register is set. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [12:12] + read-write + + + VENDOR_ERR_SIGNAL_EN1 + N/A + [13:13] + read-write + + + VENDOR_ERR_SIGNAL_EN2 + N/A + [14:14] + read-write + + + VENDOR_ERR_SIGNAL_EN3 + N/A + [15:15] + read-write + + + + + AUTO_CMD_STAT_R + Auto CMD Status Register + 0x3C + 16 + read-only + 0x0 + 0xBF + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a +command error, this bit is not set because it is not necessary +to issue an Auto CMD12. Setting this bit to 1 means that the +Host Controller cannot issue Auto CMD12 to stop multiple +memory block data transfer, due to some error. If this bit is +set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by +Auto CMD23. +Values: +- 0x1 (TRUE): Not Executed +- 0x0 (FALSE): Executed + [0:0] + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK +cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are +meaningless. +Values: +- 0x1 (TRUE): Time out +- 0x0 (FALSE): No Error + [1:1] + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command +response. +Values: +- 0x1 (TRUE): CRC Error Generated +- 0x0 (FALSE): No Error + [2:2] + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command +response is 0. +Values: +- 0x1 (TRUE): End Bit Error Generated +- 0x0 (FALSE): No Error + [3:3] + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response +to a command. +Values: +- 0x1 (TRUE): Error +- 0x0 (FALSE): No Error + [4:4] + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the +Transfer Mode register is set to 1 and an error is detected in +R1 response of either Auto CMD12 or CMD13. This status is +ignored if any bit between D00 to D04 is set to 1. +Values: +- 0x1 (TRUE): Error +- 0x0 (FALSE): No Error + [5:5] + read-only + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an +Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by +Auto CMD23. +Values: +- 0x1 (TRUE): Not Issued +- 0x0 (FALSE): No Error + [7:7] + read-only + + + + + HOST_CTRL2_R + Host Control 2 Register + 0x3E + 16 + read-write + 0x0 + 0xFDFF + + + UHS_MODE_SEL + N/A + [2:0] + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in SD UHS-I mode. Setting this bit from 0 to 1 starts changing the +signal voltage from 3.3V to 1.8V. Host Controller clears this +bit if switching to 1.8V signaling fails per protocol. The value is reflected on the io_volt_sel output which can then be used to change an external regulator to supply 1.8V instead of 3.3V on the VDDIO pin associated with the CLK/CMD/DAT signals. +Note: This bit must be set for all UHS-I speed modes +(SDR12/SDR25/SDR50/DDR50). +Values: +- 0x0 (V_3_3): 3.3V Signalling +- 0x1 (V_1_8): 1.8V Signalling + [3:3] + read-write + + + DRV_STRENGTH_SEL + Driver Strength Select +These bits are used to select the Host Controller output driver in +1.8V signaling UHS-I/eMMC speed modes. The value is reflected on the io_drive_strength[1:0] output. +- 0x0 (TYPEB): Driver TYPEB is selected +- 0x1 (TYPEA): Driver TYPEA is selected +- 0x2 (TYPEC): Driver TYPEC is selected +- 0x3 (TYPED): Driver TYPED is selected + [5:4] + read-write + + + EXEC_TUNING + N/A + [6:6] + read-write + + + SAMPLE_CLK_SEL + N/A + [7:7] + read-write + + + UHS2_IF_ENABLE + N/A + [8:8] + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or +26-bit. +Values: +- 0x0 (FALSE): 16-bit Data Length Mode +- 0x1 (TRUE): 26-bit Data Length Mode + [10:10] + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is +used to select Auto CMD23 or Auto CMD12 for ADMA3 data +transfer. +Values: +- 0x0 (FALSE): Auto CMD23 is disabled +- 0x1 (TRUE): Auto CMD23 is enabled + [11:11] + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or +Version 4 mode. +Functions of following fields are modified for Host Version 4 +mode: +- SDMA Address: SDMA uses ADMA System Address +(05Fh-058h) instead of SDMA System Address register +(003h-000h) +- ADMA2/ADMA3 selection: ADMA3 is selected by DMA +select in Host Control 1 register +- 32-bit Block Count: SDMA System Address register +(003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated +Descriptor Address registers and +Command Queuing registers (if applicable) while operating +in Host version less than 4 mode (Host Version 4 Enable = +0). +Values: +- 0x0 (FALSE): Version 3.00 compatible mode +- 0x1 (TRUE): Version 4 mode + [12:12] + read-write + + + ADDRESSING + N/A + [13:13] + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous +interrupts and Asynchronous Interrupt Support is set to 1 in +the Capabilities register. +Values: +- 0x0 (FALSE): Disabled +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + PRESET_VAL_ENABLE + N/A + [15:15] + read-write + + + + + CAPABILITIES1_R + Capabilities 1 Register - 0 to 31 + 0x40 + 32 + read-only + 0x276C6481 + 0xFFEFFFBF + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data +Timeout Error. The Timeout Clock unit defines the unit of +timeout clock frequency. It can be KHz or MHz. +- 0x00 - Get information through another method +- 0x01 - 1KHz / 1MHz +- 0x02 - 2KHz / 2MHz +- 0x03 - 3KHz / 3MHz +- ........... +- 0x3F - 63KHz / 63MHz + [5:0] + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to +detect Data TImeout Error. +Values: +- 0x0 (KHZ): KHz +- 0x1 (MHZ): MHz + [7:7] + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for +the SD Clock. The definition of these bits depend on the Host +Controller Version. +- 6-Bit Base Clock Frequency: This mode is supported by +the Host Controller version 1.00 and 2.00. The upper 2 +bits are not effective and are always 0. The unit values +are 1 MHz. The supported clock range is 10 MHz to 63 +MHz. +- 0x00 - Get information through another method +- 0x01 - 1 MHz +- 0x02 - 2 MHz +- ............. +- 0x3F - 63 MHz +- 0x40-0xFF - Not Supported +- 8-Bit Base Clock Frequency: This mode is supported by +the Host Controller version 3.00. The unit values are 1 +MHz. The supported clock range is 10 MHz to 255 MHz. +- 0x00 - Get information through another method +- 0x01 - 1 MHz +- 0x02 - 2 MHz +- ............ +- 0xFF - 255 MHz +If the frequency is 16.5 MHz, the larger value is set to +0001001b (17 MHz) because the Host Driver uses this value +to calculate the clock divider value and it does not exceed +the upper limit of the SD Clock frequency. If these bits are all +0, the Host system has to get information using a different +method. + [15:8] + read-only + + + MAX_BLK_LEN + N/A + [17:16] + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of +using an 8-bit bus width mode. This bit is not effective when +the Slot Type is set to 10b. +Values: +- 0x0 (FALSE): 8-bit Bus Width not Supported +- 0x1 (TRUE): 8-bit Bus Width Supported + [18:18] + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of +using ADMA2. +Values: +- 0x0 (FALSE): ADMA2 not Supported +- 0x1 (TRUE): ADMA2 Supported + [19:19] + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host +System supports High Speed mode and they can supply the +SD Clock frequency from 25 MHz to 50 MHz. +Values: +- 0x0 (FALSE): High Speed not Supported +- 0x1 (TRUE): High Speed Supported + [21:21] + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of +using SDMA to transfer data between the system memory +and the Host Controller directly. +Values: +- 0x0 (FALSE): SDMA not Supported +- 0x1 (TRUE): SDMA Supported + [22:22] + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports +Suspend/Resume functionality. If this bit is 0, the Host Driver +does not issue either Suspend or Resume commands +because the Suspend and Resume mechanism is not +supported. +Values: +- 0x0 (FALSE): Not Supported +- 0x1 (TRUE): Supported + [23:23] + read-only + + + VOLT_33 + Voltage Support 3.3V +Values: +- 0x0 (FALSE): 3.3V Not Supported +- 0x1 (TRUE): 3.3V Supported + [24:24] + read-only + + + VOLT_30 + Voltage Support 3.0V +Values: +- 0x0 (FALSE): 3.0V Not Supported +- 0x1 (TRUE): 3.0V Supported + [25:25] + read-only + + + VOLT_18 + Voltage Support 1.8V +Values: +- 0x0 (FALSE): 1.8V Not Supported +- 0x1 (TRUE): 1.8V Supported + [26:26] + read-only + + + SYS_ADDR_64_V4 + 64-bit System Address Support for V4 +This bit sets the Host Controller to support 64-bit System +Addressing of V4 mode. When this bit is set to 1, full or part +of 64-bit address must be used to decode the Host Controller +Registers so that Host Controller Registers can be placed +above system memory area. 64-bit address decode of Host +Controller registers is effective regardless of setting to 64-bit +Addressing in Host Control 2. +If this bit is set to 1, 64-bit DMA Addressing for version 4 is +enabled by setting Host Version 4 Enable +(HOST_VER4_ENABLE = 1) and by setting 64-bit +Addressing (ADDRESSING =1) in the Host Control 2 +register. SDMA can be used and ADMA2 uses 128-bit +Descriptor. +Values: +- 0x0 (FALSE): 64-bit System Address for V4 is Not +Supported +- 0x1 (TRUE): 64-bit System Address for V4 is Supported + [27:27] + read-only + + + SYS_ADDR_64_V3 + 64-bit System Address Support for V3 +This bit sets the Host controller to support 64-bit System +Addressing of V3 mode. +SDMA cannot be used in 64-bit Addressing in Version 3 +Mode. +If this bit is set to 1, 64-bit ADMA2 with using 96-bit +Descriptor can be enabled by setting Host Version 4 Enable +(HOST_VER4_ENABLE = 0) and DMA select (DMA_SEL = +11b). +Values: +- 0x0 (FALSE): 64-bit System Address for V3 is Not +Supported +- 0x1 (TRUE): 64-bit System Address for V3 is Supported + [28:28] + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +- 0x0 (FALSE): Asynchronous Interrupt Not Supported +- 0x1 (TRUE): Asynchronous Interrupt Supported + [29:29] + read-only + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host +System. +Values: +- 0x0 (REMOVABLE_SLOT): Removable Card Slot +- 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +- 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +- 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple +Embedded Devices + [31:30] + read-only + + + + + CAPABILITIES2_R + Capabilities Register - 32 to 63 + 0x44 + 32 + read-only + 0x8000077 + 0x18FFEF7F + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +Thsi bit indicates that SDR50 is supported. The bit 13 +(USE_TUNING_SDR50) indicates whether SDR50 requires +tuning or not. +Values: +- 0x0 (FALSE): SDR50 is not supported +- 0x1 (TRUE): SDR50 is supported + [0:0] + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +- 0x0 (FALSE): SDR104 is not supported +- 0x1 (TRUE): SDR104 is supported (NOT ACTUALLY SUPPORTED) + [1:1] + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +- 0x0 (FALSE): DDR50 is not supported +- 0x1 (TRUE): DDR50 is supported + [2:2] + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +- 0x0 (FALSE): UHS-II is not supported +- 0x1 (TRUE): UHS-II is supported + [3:3] + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type A is not supported +- 0x1 (TRUE): Driver Type A is supported + [4:4] + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type C is not supported +- 0x1 (TRUE): Driver Type C is supported + [5:5] + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type D is not supported +- 0x1 (TRUE): Driver Type D is supported + [6:6] + read-only + + + RETUNE_CNT + N/A + [11:8] + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +- 0x0 (ZERO): SDR50 does not require tuning +- 0x1 (ONE): SDR50 requires tuning + [13:13] + read-only + + + RE_TUNING_MODES + N/A + [15:14] + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable +clock generator. Setting these bits to 0 means that the Host +Controller does not support a programmable clock generator. +- 0x0: Clock Multiplier is not Supported +- 0x1: Clock Multiplier M = 2 +- 0x2: Clock Multiplier M = 3 +- ......... +- 0xFF: Clock Multiplier M = 256 + [23:16] + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of +using ADMA3. +Values: +- 0x0 (FALSE): ADMA3 not Supported +- 0x1 (TRUE): ADMA3 Supported + [27:27] + read-only + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +Values: +- 0x0 (FALSE): 1.8V VDD2 is not Supported +- 0x1 (TRUE): 1.8V VDD2 is Supported + [28:28] + read-only + + + + + CURR_CAPABILITIES1_R + Current Capabilities Register - 0 to 31 + 0x48 + 32 + read-only + 0x0 + 0xFFFFFF + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [7:0] + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [15:8] + read-only + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [23:16] + read-only + + + + + CURR_CAPABILITIES2_R + Maximum Current Capabilities Register - 32 to 63 + 0x4C + 32 + read-only + 0x0 + 0xFF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power +supply for the UHS-II card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [7:0] + read-only + + + + + FORCE_AUTO_CMD_STAT_R + Force Event Register for Auto CMD Error Status register + 0x50 + 16 + write-only + 0x0 + 0xBF + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +- 0x1 (TRUE): Auto CMD12 Not Executed Status is set +- 0x0 (FALSE): Not Affected + [0:0] + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +- 0x1 (TRUE): Auto CMD Timeout Error Status is set +- 0x0 (FALSE): Not Affected + [1:1] + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +- 0x1 (TRUE): Auto CMD CRC Error Status is set +- 0x0 (FALSE): Not Affected + [2:2] + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +- 0x1 (TRUE): Auto CMD End Bit Error Status is set +- 0x0 (FALSE): Not Affected + [3:3] + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +- 0x1 (TRUE): Auto CMD Index Error Status is set +- 0x0 (FALSE): Not Affected + [4:4] + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +- 0x1 (TRUE): Auto CMD Response Error Status is set +- 0x0 (FALSE): Not Affected + [5:5] + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +- 0x1 (TRUE): Command Not Issued By Auto CMD12 Error +Status is set +- 0x0 (FALSE): Not Affected + [7:7] + write-only + + + + + FORCE_ERROR_INT_STAT_R + Force Event Register for Error Interrupt Status + 0x52 + 16 + read-write + 0x0 + 0xFFFF + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command Timeout Error Status is set + [0:0] + read-write + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command CRC Error Status is set + [1:1] + read-write + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command End Bit Error Status is set + [2:2] + read-write + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command Index Error Status is set + [3:3] + read-write + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data Timeout Error Status is set + [4:4] + read-write + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data CRC Error Status is set + [5:5] + read-write + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data End Bit Error Status is set + [6:6] + read-write + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Current Limit Error Status is set + [7:7] + read-write + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Auto CMD Error Status is set + [8:8] + read-write + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): ADMA Error Status is set + [9:9] + read-write + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Tuning Error Status is set + [10:10] + read-write + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Response Error Status is set + [11:11] + read-write + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Boot ack Error Status is set + [12:12] + read-write + + + FORCE_VENDOR_ERR1 + N/A + [13:13] + read-write + + + FORCE_VENDOR_ERR2 + N/A + [14:14] + read-write + + + FORCE_VENDOR_ERR3 + N/A + [15:15] + read-write + + + + + ADMA_ERR_STAT_R + ADMA Error Status Register + 0x54 + 8 + read-only + 0x0 + 0x7 + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs +during ADMA data transfer. +Values: +- 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to +a location next to the error descriptor +- 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register +points to the error descriptor +- 0x2 (UNUSED): Never set this state +- 0x3 (ST_TFR): Transfer Data - SYS_ADR register points +to a location next to the error descriptor + [1:0] + read-only + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +- While the Block Count Enable is being set, the total data +length specified by the Descriptor table is different from +that specified by the Block Count and Block Length +- When the total data length cannot be divided by the block +length +Values: +- 0x0 (NO_ERR): No Error +- 0x1 (ERROR): Error + [2:2] + read-only + + + + + ADMA_SA_LOW_R + ADMA System Address Register - Low + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADMA_SA_LOW + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system +address. +- SDMA: If Host Version 4 Enable is set to 1, this register +stores the system address of the data location +- ADMA2: This register stores the byte address of the +executing command of the descriptor table +- ADMA3: This register is set by ADMA3. ADMA2 +increments the address of this register that points to the +next line, every time a Descriptor line is fetched. + [31:0] + read-write + + + + + ADMA_ID_LOW_R + ADMA3 Integrated Descriptor Address Register - Low + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADMA_ID_LOW + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated +Descriptor address. The start address of Integrated +Descriptor is set to these register bits. The ADMA3 fetches +one Descriptor Address and increments these bits to indicate +the next Descriptor address. + [31:0] + read-write + + + + + HOST_CNTRL_VERS_R + Host Controller Version + 0xFE + 16 + read-only + 0x5 + 0xFFFF + + + SPEC_VERSION_NUM + N/A + [7:0] + read-only + + + VENDOR_VERSION_NUM + N/A + [15:8] + read-only + + + + + CQVER + Command Queuing Version register + 0x180 + 32 + read-only + 0x510 + 0xFFF + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of +decimal point) in BCD format. + [3:0] + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of +decimal point) in BCD format. + [7:4] + read-only + + + EMMC_VER_MAJOR + This bit indicates the eMMC major version (1st digit left of +decimal point) in BCD format. + [11:8] + read-only + + + + + CQCAP + Command Queuing Capabilities register + 0x184 + 32 + read-only + 0x30C8 + 0x1000F3FF + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by +ITCFMUL. The Final clock frequency of actual timer clock is +calculated as ITCFVAL* ITCFMUL. + [9:0] + read-only + + + ITCFMUL + N/A + [15:12] + read-only + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports +cryptographic operations. +Values: +- 0x0 (FALSE): Crypto not Supported +- 0x1 (TRUE): Crypto Supported + [28:28] + read-only + + + + + CQCFG + Command Queuing Configuration register + 0x188 + 32 + read-write + 0x0 + 0x1103 + + + CQ_EN + Enable command queuing engine (CQE). +When CQE is disable, the software controls the eMMC bus +using the registers between the addresses 0x000 to 0x1FF. +Before the software writes to this bit, the software verifies +that the eMMC host controller is in idle state and there are no +ongoing commands or data transfers. When software wants +to exit command queuing mode, it clears all previous tasks (if +any) before setting this bit to 0. +Values: +- 0x1 (CQE_ENABLE): Enable command queuing +- 0x0 (CQE_DISABLE): Disable command queuing + [0:0] + read-write + + + CR_GENERAL_EN + N/A + [1:1] + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host +memory. This bit can only be configured when Command +Queuing Enable bit is 0 (command queuing is disabled). +Values: +- 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +- 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits + [8:8] + read-write + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor +or a direct-command descriptor. CQE uses this bit when a +task is issued in slot #31, to determine how to decode the +Task Descriptor. +Values: +- 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot +#31 is a DCMD Task Descriptor +- 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot +#31 is a data Transfer Task Descriptor + [12:12] + read-write + + + + + CQCTL + Command Queuing Control register + 0x18C + 32 + read-write + 0x0 + 0x101 + + + HALT + Halt request and resume +Values: +- 0x1 (HALT_CQE): Software writes 1 to this bit when it +wants to acquire software control over the eMMC bus and +to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command +(CMDQ_TASK_MGMT). When the software writes 1, CQE +completes the ongoing task (if any in progress). After the +task is completed and the CQE is in idle state, CQE does not +issue new commands and indicates to the software by +setting this bit to 1. The software can poll on this bit until it is +set to 1 and only then send commands on the eMMC bus. +- 0x0 (RESUME_CQE): Software writes 0 to this bit to exit +from the halt state and resume CQE activity. + [0:0] + read-write + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This +bit does not clear tasks in the device. The software has to +use the CMDQ_TASK_MGMT command to clear device's +queue. +Values: +- 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the +controller +- 0x0 (NO_EFFECT): Programming 0 has no effect + [8:8] + read-write + + + + + CQIS + Command Queuing Interrupt Status register + 0x190 + 32 + read-write + 0x0 + 0x3F + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when +halt bit in the CQCTL register transitions from 0 to 1 +indicating that the host controller has completed its current +ongoing task and has entered halt state. A value of 1 clears +this status bit. +Values: +- 0x1 (SET): HAC Interrupt is set +- 0x0 (NOTSET): HAC Interrupt is not set + [0:0] + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at +least one of the following conditions are met: +- A task is completed and the INT bit is set in its Task +Descriptor +- Interrupt caused by Interrupt Coalescing logic due to +timeout +- Interrupt Coalescing logic reached the configured +threshold +A value of 1 clears this status bit +Values: +- 0x1 (SET): TCC Interrupt is set +- 0x0 (NOTSET): TCC Interrupt is not set + [1:1] + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a +response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device +status bit fields that may trigger an interrupt and that are +masked. A value of 1 clears this status bit. +Values: +- 0x1 (SET): RED Interrupt is set +- 0x0 (NOTSET): RED Interrupt is not set + [2:2] + read-write + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a +task clear operation is completed by CQE. The completed +task clear operation is either an individual task clear (by +writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +- 0x1 (SET): TCL Interrupt is set +- 0x0 (NOTSET): TCL Interrupt is not set + [3:3] + read-write + + + GCE + N/A + [4:4] + read-write + + + ICCE + N/A + [5:5] + read-write + + + + + CQISE + Command Queuing Interrupt Status Enable register + 0x194 + 32 + read-write + 0x0 + 0x3F + + + HAC_STE + Halt complete interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + [0:0] + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + [1:1] + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.RED is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.RED is disabled + [2:2] + read-write + + + TCL_STE + Task cleared interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + [3:3] + read-write + + + GCE_STE + General Crypto Error interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.GCE is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.GCE is disabled + [4:4] + read-write + + + ICCE_STE + Invalid Crypto Configuration Error interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.ICCE is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.ICCE is disabled + [5:5] + read-write + + + + + CQISGE + Command Queuing Interrupt signal enable register + 0x198 + 32 + read-write + 0x0 + 0x3F + + + HAC_SGE + Halt complete interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal +generation is disabled + [0:0] + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal +generation is disabled + [1:1] + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal +generation is disabled + [2:2] + read-write + + + TCL_SGE + Task cleared interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal +generation is disabled + [3:3] + read-write + + + GCE_SGE + General Crypto Error interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.GCE interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.GCE interrupt signal +generation is disabled + [4:4] + read-write + + + ICCE_SGE + Invalid Crypto Configuration Error interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.ICCE interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.ICCE interrupt signal +generation is disabled + [5:5] + read-write + + + + + CQIC + Command Queuing Interrupt Coalescing register + 0x19C + 32 + read-write + 0x0 + 0x80119FFF + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time +allowed between the completion of a task on the bus and the +generation of an interrupt. +Timer Operation: The timer is reset by software during the +interrupt service routine. It starts running when the first data +transfer task with INT=0 is completed, after the timer was +reset. When the timer reaches the value configured in +ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock +whose frequency is specified in the Internal Timer Clock +Frequency field CQCAP register. +- 0x0: Timer is disabled. Timeout-based interrupt is not +generated +- 0x1: Timeout on 01x1024 cycles of timer clock frequency +- 0x2: Timeout on 02x1024 cycles of timer clock frequency +- ........ +- 0x7f: Timeout on 127x1024 cycles of timer clock +frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + [6:0] + read-write + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is +updated with the contents written on the same cycle. +Values: +- 0x1 (WEN_SET): Sets TOUT_VAL_WEN +- 0x0 (WEN_CLR): clears TOUT_VAL_WEN + [7:7] + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task +completions (only tasks with INT=0 in the Task Descriptor), +which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 +complete, they are counted by CQE. The counter is reset by +software during the interrupt service routine. The counter +stops counting when it reaches the value configured in +INTC_TH, and generates interrupt. +- 0x0: Interrupt coalescing feature disabled +- 0x1: Interrupt coalescing interrupt generated after 1 task +when INT=0 completes +- 0x2: Interrupt coalescing interrupt generated after 2 tasks +when INT=0 completes +- ........ +- 0x1f: Interrupt coalescing interrupt generated after 31 +tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set +during the same write operation. + [12:8] + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is +updated with the contents written on the same cycle. +Values: +- 0x1 (WEN_SET): Sets INTC_TH_WEN +- 0x0 (WEN_CLR): Clears INTC_TH_WEN + [15:15] + write-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and +counter are reset. +Values: +- 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer +and counter are reset +- 0x0 (NO_EFFECT): No Effect + [16:16] + write-only + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with +INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +- 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task +completion has been counted (INTC counter > 0) +- 0x0 (INTC_NO_TASK_COMP): INT0 Task completions +have not occurred since last counter reset (INTC counter +== 0) + [20:20] + read-only + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +- 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing +mechanism is active. Interrupts are counted and timed, +and coalesced interrupts are generated +- 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing +mechanism is disabled (Default). + [31:31] + read-write + + + + + CQTDLBA + Command Queuing Task Descriptor List Base Address register + 0x1A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of +the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor +size + Transfer Descriptor size) as configured by the host +driver. This address is set on 1 KB boundary. The lower 10 +bits of this register are set to 0 by the software and are +ignored by CQE. + [31:0] + read-write + + + + + CQTDBR + Command Queuing DoorBell register + 0x1A8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start +processing the task encoded in slot n of the TDL. Writing 0 +by the software does not have any impact on the hardware, +and does not change the value of the register bit. +CQE always processes tasks according to the order +submitted to the list by CQTDBR write transactions. CQE +processes Data Transfer tasks by reading the Task +Descriptor and sending QUEUED_TASK_PARAMS (CMD44) +and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when +enabled) by reading the Task Descriptor, and generating the +command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the +following events: +- A task execution is completed (with success or error). +- The task is cleared using CQTCLR register. +- All tasks are cleared using CQCTL register. +- CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch +submission) by writing 1 to multiple bits of this register in the +same transaction. In the case of batch submission, CQE +processes the tasks in order of the task index, starting with +the lowest index. If one or more tasks in the batch are +marked with QBR, the ordering of execution is based on said +processing order. + [31:0] + read-write + + + + + CQTCN + Command Queuing TaskClear Notification register + 0x1AC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Task-N has completed execution (with success +or errors) +- Bit-N(0): Task-N has not completed, could be pending or +not submitted. +On task completion, software may read this register to know +tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the +corresponding bits. + [31:0] + read-write + + + + + CQDQS + Device queue status register + 0x1B0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Device has marked task N as ready for +execution +- Bit-N(0): Task-N is not ready for execution. This task +could be pending in device or not submitted. +Host controller updates this register with response of the +Device Queue Status command. + [31:0] + read-only + + + + + CQDPT + Device pending tasks register + 0x1B4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Task-N has been successfully queued into the +device and is awaiting execution +- Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if +QUEUED_TASK_PARAMS (CMD44) and +QUEUED_TASK_ADDRESS (CMD45) were sent for this +specific task and if this task has not been executed. +The controller sets this bit after receiving a successful +response for CMD45. CQE clears this bit after the task has +completed execution. +Software reads this register in the task-discard procedure to +determine if the task is queued in the device. + [31:0] + read-only + + + + + CQTCLR + Command Queuing DoorBell register + 0x1B8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task +that the software has previously issued. +This bit can only be written when CQE is in Halt state as +indicated in CQCFG register Halt bit. When software writes 1 +to a bit in this register, CQE updates the value to 1, and +starts clearing the data structures related to the task. CQE +clears the bit fields (sets a value of 0) in CQTCLR and in +CQTDBR once the clear operation is complete. Software +must poll on the CQTCLR until it is cleared to verify that a +clear operation was done. + [31:0] + read-write + + + + + CQSSC1 + CQ Send Status Configuration 1 register + 0x1C0 + 32 + read-write + 0x11000 + 0xFFFFF + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when +using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the +device, but no data transfer is in progress. When a +SEND_QUEUE_STATUS response indicates that no task is +ready for execution, CQE counts the configured time until it +issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is +specified in the Internal Timer Clock Frequency field CQCAP +register. The minimum value is 0001h (1 clock period) and +the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz +clock frequency (period = 52.08 ns). If the setting in +CQSSC1.CIT is 1000h, the calculated polling period is +4096*52.08 ns= 213.33 ns. +Should be programmed only when CQCFG.CQ_EN is '0'. + [15:0] + read-write + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data +transfer is in progress. +A value of 'n' indicates that CQE sends status command on +the CMD line, during the transfer of data block BLOCK_CNTn, +on the data lines, where BLOCK_CNT is the number of +blocks in the current transaction. +- 0x0: SEND_QUEUE_STATUS (CMD13) command is not +sent during the transaction. Instead, it is sent only when +the data lines are idle. +- 0x1: SEND_QUEUE_STATUS command is to be sent +during the last block of the transaction. +- 0x2: SEND_QUEUE_STATUS command when last 2 +blocks are pending. +- 0x3: SEND_QUEUE_STATUS command when last 3 +blocks are pending. +- ........ +- 0xf: SEND_QUEUE_STATUS command when last 15 +blocks are pending. +Should be programmed only when CQCFG.CQ_EN is '0' + [19:16] + read-write + + + + + CQSSC2 + CQ Send Status Configuration 2 register + 0x1C4 + 32 + read-write + 0x0 + 0xFFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA +field in SEND_QUEUE_STATUS (CMD13) command +argument. +CQE copies this field to bits 31:16 of the argument when +transmitting SEND_ QUEUE_STATUS (CMD13) command. + [15:0] + read-write + + + + + CQCRDCT + Command response for direct command register + 0x1C8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command +generated by the last direct command (DCMD) task that was +sent. +Contents of this register are valid only after bit 31 of +CQTDBR register is cleared by the controller. + [31:0] + read-only + + + + + CQRMEM + Command response mode error mask register + 0x1D0 + 32 + read-write + 0xFDF9A080 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status +filed that is received in R1/R1b responses. +- 1: When a R1/R1b response is received, with a bit i in the +device status set, a RED interrupt is generated. +- 0: When a R1/R1b response is received, bit i in the device +status is ignored. +The reset value of this register is set to trigger an interrupt on +all 'Error' type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that +they are ignored by this logic. + [31:0] + read-write + + + + + CQTERRI + CQ Task Error Information register + 0x1D4 + 32 + read-only + 0x0 + 0x9F3F9F3F + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was +executed on the command line when the error occurred. + [5:0] + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on +the command line when the error occurred. + [12:8] + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a +command transaction was in progress. +Values: +- 0x1 (SET): Response-related error is detected. Check +contents of RESP_ERR_TASKID and +RESP_ERR_CMD_INDX fields +- 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID +and RESP_ERR_CMD_INDX + [15:15] + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was +executed and whose data transfer has errors. + [21:16] + read-only + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and +whose data transfer has errors. + [28:24] + read-only + + + TRANS_ERR_FIELDS_VALID + This bit is updated when an error is detected while a data +transfer transaction was in progress. +Values: +- 0x1 (SET): data transfer related error detected. Check +contents of TRANS_ERR_TASKID and +TRANS_ERR_CMD_INDX fields +- 0x0 (NOT_SET): Ignore contents of +TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX + [31:31] + read-only + + + + + CQCRI + CQ Command response index + 0x1D8 + 32 + read-only + 0x0 + 0x3F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command +response. Controller updates the value every time a +command response is received. + [5:0] + read-only + + + + + CQCRA + CQ Command response argument register + 0x1DC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command +response. Controller updates the value every time a +command response is received. + [31:0] + read-only + + + + + MSHC_VER_ID_R + MSHC version + 0x500 + 32 + read-only + 0x3137302A + 0xFFFFFFFF + + + MSHC_VER_ID + Current release number +This field indicates the Synopsys DesignWare Cores +DWC_mshc/DWC_mshc_lite current release number that is +read by an application. +For example, release number '1.60a' is represented in +ASCII as 0x313630. Lower 8 bits read from this register can +be ignored by the application. +An application reading this register in conjunction with the +MSHC_VER_TYPE_R register, gathers details of the current +release. + [31:0] + read-only + + + + + MSHC_VER_TYPE_R + MSHC version type + 0x504 + 32 + read-only + 0x67612A2A + 0xFFFFFFFF + + + MSHC_VER_TYPE + Current release type +This field indicates the Synopsys DesignWare Cores +DWC_mshc/DWC_mshc_lite current release type that is +read by an application. +For example, release type is 'ga' is represented in ASCII as +0x6761. Lower 16 bits read from this register can be ignored +by the application. +An application reading this register in conjunction with the +MSHC_VER_ID_R register, gathers details of the current +release. + [31:0] + read-only + + + + + MSHC_CTRL_R + MSHC Control register + 0x508 + 8 + read-write + 0x1 + 0x11 + + + CMD_CONFLICT_CHECK + Command conflict check +This bit enables command conflict check. +Note: DWC_mshc controller monitors the CMD line +whenever a command is issued and checks whether the +value driven on sd_cmd_out matches the value on +sd_cmd_in at next subsequent edge of cclk_tx to determine +command conflict error. This bit is cleared only if the feed +back delay (including IO Pad delay) is more than +(t_card_clk_period - t_setup), where t_setup is the setup +time of a flop in DWC_mshc. The I/O pad delay is consistent +across CMD and DATA lines, and it is within the value: +(2*t_card_clk_period - t_setup) +Values: +- 0x0 (DISABLE_CMD_CONFLICT_CHK): Disable +command conflict check +- 0x1 (CMD_CONFLICT_CHK_LAT1): Check for command +conflict after 1 card clock cycle + [0:0] + read-write + + + SW_CG_DIS + Internal clock gating disable control +This bit must be used to disable IP's internal clock gating +when required. when disabled clocks are not gated. Clocks +to the core (except hclk) must be stopped when +programming this bit. +Values: +- 0x0 (ENABLE): Internal clock gates are active and clock +gating is controlled internally +- 0x1 (DISABLE): Internal clock gating is disabled, clocks +are not gated internally + [4:4] + read-write + + + + + MBIU_CTRL_R + MBIU Control register + 0x510 + 8 + read-write + 0x1 + 0xF + + + UNDEFL_INCR_EN + Undefined INCR Burst +Controls generation of undefined length INCR transfer on +Master interface. +Values: +- 0x0 (FALSE): Undefined INCR type burst is the least +preferred burst on AHB Master I/F +- 0x1 (TRUE): Undefined INCR type burst is the most +preferred burst on AHB Master I/F + [0:0] + read-write + + + BURST_INCR4_EN + INCR4 Burst +Controls generation of INCR4 transfers on Master interface. +Values: +- 0x0 (FALSE): AHB INCR4 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR4 burst type can be generated on +Master I/F + [1:1] + read-write + + + BURST_INCR8_EN + INCR8 Burst +Controls generation of INCR8 transfers on Master interface. +Values: +- 0x0 (FALSE): AHB INCR8 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR8 burst type can be generated on +Master I/F + [2:2] + read-write + + + BURST_INCR16_EN + INCR16 Burst +Controls generation of INCR16 transfers on Master +interface. +Values: +- 0x0 (FALSE): AHB INCR16 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR16 burst type can be generated +on Master I/F + [3:3] + read-write + + + + + EMMC_CTRL_R + eMMC Control register + 0x52C + 16 + read-write + 0xC + 0x60F + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application +program this bit based on the card connected to SDHC. +Values: +- 0x1 (EMMC_CARD): Card connected to SDHC is an +eMMC card +- 0x0 (NON_EMMC_CARD): Card connected to SDHC is +a non-eMMC card + [0:0] + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in +eMMC mode. This is useful in bus testing (CMD19) for an +eMMC device. In bus testing, an eMMC card does not send +CRC status for a block, which may generate CRC error. This +CRC error can be masked using this bit during bus testing. +Values: +- 0x1 (DISABLE): DATA CRC check is disabled +- 0x0 (ENABLE): DATA CRC check is enabled + [1:1] + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the card_emmc_reset_n output of SDHC +Values: +- 0x1 (RST_DEASSERT): Reset to eMMC device is +deasserted +- 0x0 (RST_ASSERT): Reset to eMMC device asserted +(active low) + [2:2] + read-write + + + EMMC_RST_N_OE + Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n). +Values: +- 0x1 (ENABLE): OE for card_emmc_reset_n is 1 +- 0x0 (DISABLE): OE for card_emmc_reset_n is 0 + [3:3] + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the +many ready tasks for execution. +Values: +- 0x0 (PRI_REORDER_PLUS_FCFS): Priority based +reordering with FCFS to resolve equal priority tasks +- 0x1 (FCFS_ONLY): First come First serve, in the order of +DBR rings + [9:9] + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch +feature when set to 1. +Values: +- 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for +sucessive WRITE transfers and pipeline sucessive READ +transfers +- 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and +Pipeline for READ are disabled + [10:10] + read-write + + + + + BOOT_CTRL_R + eMMC Boot Control register + 0x52E + 16 + read-write + 0x0 + 0xF181 + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The +application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDHC clears this bit after the +boot transfer is completed or terminated. +Values: +- 0x1 (MAN_BOOT_EN): Mandatory boot enable +- 0x0 (MAN_BOOT_DIS): Mandatory boot disable + [0:0] + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +- 0x1 (TRUE): Validate Mandatory boot enable bit +- 0x0 (FALSE): Ignore Mandatory boot Enable bit + [7:7] + write-only + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDHC checks for boot acknowledge +start pattern of 0-1-0 during boot operation. This bit is +applicable for both mandatory and alternate boot mode. +Values: +- 0x1 (TRUE): Boot Ack enable +- 0x0 (FALSE): Boot Ack disable + [8:8] + read-write + + + BOOT_TOUT_CNT + N/A + [15:12] + read-write + + + + + GP_IN_R + General Purpose Input register + 0x530 + 32 + read-only + 0x0 + 0x1 + + + GP_IN + It reflects the value of gp_in ports. +NOT USED - ALWAYS READS 0 + [0:0] + read-only + + + + + GP_OUT_R + General Purpose Output register + 0x534 + 32 + read-write + 0x0 + 0x3FF + + + CARD_DETECT_EN + 0: Force card_detect_n input to 0 +1: Normal card_detect_n operation allowing card detection from a device pin + [0:0] + read-write + + + CARD_MECH_WRITE_PROT_EN + card_mech_write_prot, despite its name, is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#). Consider that in the following: +0: Force card_mech_write_prot input to 0 internally; this forces write protection to be active +1: Allow card_mech_write_prot to work normally per the device's pin state + [1:1] + read-write + + + LED_CTRL_OE + Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL: +0: disable OE associated with the led_ctrl output +1: enable OE associated with the led_ctrl output + [2:2] + read-write + + + CARD_CLOCK_OE + Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN: +0: disable OE to the clk_card output +1: enable OE to the clk_card output + [3:3] + read-write + + + CARD_IF_PWR_EN_OE + Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1: +0: disable OE to the card_if_pwr_en output +1: enable OE to the card_if_pwr_en output + [4:4] + read-write + + + IO_VOLT_SEL_OE + Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN: +0: disable OE to the io_volt_sel output +1: enable OE to the io_volt_sel output + [5:5] + read-write + + + CARD_CLOCK_OUT_DLY + N/A + [7:6] + read-write + + + CARD_CLOCK_IN_DLY + Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode: +00: SD Default Speed, SD SDR12, eMMC Legacy +01: SD SDR25, SD SDR50 +10: SD High Speed, eMMC High Speed SDR +11: SD DDR50, eMMC DDR + [9:8] + read-write + + + + + + + + SDHC1 + 0x40470000 + + + SCB0 + Serial Communications Block (SPI/UART/I2C) + SCB + 0x40600000 + + 0 + 65536 + registers + + + + CTRL + Generic control + 0x0 + 32 + read-write + 0x300000F + 0x83031F0F + + + OVS + N/A + [3:0] + read-write + + + EC_AM_MODE + Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field should be '0'. + [8:8] + read-write + + + EC_OP_MODE + Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). + +In UART mode this field should be '0'. + [9:9] + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field should be '0'. + [10:10] + read-write + + + BYTE_MODE + Determines the number of bits per FIFO data element: +'0': 16-bit FIFO data elements. +'1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. + [11:11] + read-write + + + CMD_RESP_MODE + Determines CMD_RESP mode of operation: +'0': CMD_RESP mode disabled. +'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). + [12:12] + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). + +In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. + +In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. + [16:16] + read-write + + + BLOCK + Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. + [17:17] + read-write + + + MODE + N/A + [25:24] + read-write + + + I2C + Inter-Integrated Circuits (I2C) mode. + 0 + + + SPI + Serial Peripheral Interface (SPI) mode. + 1 + + + UART + Universal Asynchronous Receiver/Transmitter (UART) mode. + 2 + + + + + ENABLED + IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: +- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL to enable IP, select the specific operation mode and oversampling factor. +When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + [31:31] + read-write + + + + + STATUS + Generic status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. + [0:0] + read-only + + + + + CMD_RESP_CTRL + Command/response control + 0x8 + 32 + read-write + 0x0 + 0x1FF01FF + + + BASE_RD_ADDR + I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. + [8:0] + read-write + + + BASE_WR_ADDR + I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. + [24:16] + read-write + + + + + CMD_RESP_STATUS + Command/response status + 0xC + 32 + read-only + 0x0 + 0x0 + + + CURR_RD_ADDR + I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [8:0] + read-only + + + CURR_WR_ADDR + I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [24:16] + read-only + + + CMD_RESP_EC_BUS_BUSY + Indicates whether there is an ongoing bus transfer to the IP. +'0': no ongoing bus transfer. +'1': ongoing bus transfer. + +For SPI, the field is '1' when the slave is selected. + +For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. + [30:30] + read-only + + + CMD_RESP_EC_BUSY + Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: +- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. + Note that this update lasts one I2C clock cycle, or two SPI clock cycles. + [31:31] + read-only + + + + + SPI_CTRL + SPI control + 0x20 + 32 + read-write + 0x3000000 + 0x8F010F3F + + + SSEL_CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. + +When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. + +When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames. + [0:0] + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. + +When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. + +When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. + [1:1] + read-write + + + CPHA + Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: +- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. +- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. + +In SPI Motorola submode, all four CPOL/CPHA modes are valid. +in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. +in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. + [2:2] + read-write + + + CPOL + Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: +- CPOL is '0': SCLK is '0' when not transmitting data. +- CPOL is '1': SCLK is '1' when not transmitting data. + [3:3] + read-write + + + LATE_MISO_SAMPLE + Changes the SCLK edge on which MISO is captured. Only used in master mode. + +When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). + +When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. + [4:4] + read-write + + + SCLK_CONTINUOUS + Only applicable in master mode. +'0': SCLK is generated, when the SPI master is enabled and data is transmitted. +'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. + [5:5] + read-write + + + SSEL_POLARITY0 + Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: +'0': slave select is low/'0' active. +'1': slave select is high/'1' active. +For Texas Instruments submode: +'0': high/'1' active precede/coincide pulse. +'1': low/'0' active precede/coincide pulse. + [8:8] + read-write + + + SSEL_POLARITY1 + Slave select polarity. + [9:9] + read-write + + + SSEL_POLARITY2 + Slave select polarity. + [10:10] + read-write + + + SSEL_POLARITY3 + Slave select polarity. + [11:11] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. +'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. +'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + SPI_MOTOROLA + SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 0 + + + SPI_TI + SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. + 1 + + + SPI_NS + SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 2 + + + + + SSEL + Selects one of the four incoming/outgoing SPI slave select signals: +- 0: Slave 0, SSEL[0]. +- 1: Slave 1, SSEL[1]. +- 2: Slave 2, SSEL[2]. +- 3: Slave 3, SSEL[3]. +The IP should be disabled when changes are made to this field. + [27:26] + read-write + + + MASTER_MODE + Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. + [31:31] + read-write + + + + + SPI_STATUS + SPI status + 0x24 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. + [0:0] + read-only + + + SPI_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. + [1:1] + read-only + + + CURR_EZ_ADDR + SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + UART_CTRL + UART control + 0x40 + 32 + read-write + 0x3000000 + 0x3010000 + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. + +This allows a SCB UART transmitter to communicate with its receiver counterpart. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + UART_STD + Standard UART submode. + 0 + + + UART_SMARTCARD + SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. + 1 + + + UART_IRDA + Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. + 2 + + + + + + + UART_TX_CTRL + UART transmitter control + 0x44 + 32 + read-write + 0x2 + 0x137 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware + [5:5] + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + [8:8] + read-write + + + + + UART_RX_CTRL + UART receiver control + 0x48 + 32 + read-write + 0xA0002 + 0xF3777 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + +Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. + [5:5] + read-write + + + POLARITY + Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + [6:6] + read-write + + + DROP_ON_PARITY_ERROR + Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). + [8:8] + read-write + + + DROP_ON_FRAME_ERROR + Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + [9:9] + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. + [10:10] + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [12:12] + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. + [13:13] + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. + [19:16] + read-write + + + + + UART_RX_STATUS + UART receiver status + 0x4C + 32 + read-only + 0x0 + 0x0 + + + BR_COUNTER + Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. + [11:0] + read-only + + + + + UART_FLOW_CTRL + UART flow control + 0x50 + 32 + read-write + 0x0 + 0x30100FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). + [7:0] + read-write + + + RTS_POLARITY + Polarity of the RTS output signal 'uart_rts_out': +'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. +'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. + +During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. + [16:16] + read-write + + + CTS_POLARITY + Polarity of the CTS input signal 'uart_cts_in': +'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. +'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. + [24:24] + read-write + + + CTS_ENABLED + Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: +'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. +'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. + +If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). + [25:25] + read-write + + + + + I2C_CTRL + I2C control + 0x60 + 32 + read-write + 0xFB88 + 0xC001FBFF + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. + [3:0] + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. + [7:4] + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. + [8:8] + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). + [9:9] + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. + [11:11] + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [12:12] + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [13:13] + read-write + + + S_NOT_READY_ADDR_NACK + For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: +- EC_AM is '0', EC_OP is '0' and non EZ mode. +Functionality is as follows: +- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + +For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): +- EC_AM is '1' and EC_OP is '0'. +- EC_AM is '1' and general call address match. +- EC_AM is '1' and non EZ mode. +Functionality is as follows: +- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). +- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. + [14:14] + read-write + + + S_NOT_READY_DATA_NACK + For internally clocked logic only. Only used when: +- non EZ mode. +Functionality is as follows: +- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + [15:15] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. + [16:16] + read-write + + + SLAVE_MODE + Slave mode enabled ('1') or not ('0'). + [30:30] + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. + [31:31] + read-write + + + + + I2C_STATUS + I2C status + 0x64 + 32 + read-only + 0x0 + 0x31 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). + +For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). + +For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). + [0:0] + read-only + + + I2C_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. + [1:1] + read-only + + + S_READ + I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. + [4:4] + read-only + + + M_READ + I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. + [5:5] + read-only + + + CURR_EZ_ADDR + I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + I2C_M_CMD + I2C master command + 0x68 + 32 + read-write + 0x0 + 0x1F + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. + [0:0] + read-write + + + M_START_ON_IDLE + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. + [1:1] + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + [2:2] + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + [3:3] + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. + I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. + [4:4] + read-write + + + + + I2C_S_CMD + I2C slave command + 0x6C + 32 + read-write + 0x0 + 0x3 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). + [0:0] + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. + [1:1] + read-write + + + + + I2C_CFG + I2C configuration + 0x70 + 32 + read-write + 0x2A1013 + 0x303F1313 + + + SDA_IN_FILT_TRIM + Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + +SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. +1: enable clock_scb_en, has no effect on ec_busy_pp +0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) + [1:0] + read-write + + + SDA_IN_FILT_SEL + Selection of 'i2c_sda_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [4:4] + read-write + + + SCL_IN_FILT_TRIM + Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [9:8] + read-write + + + SCL_IN_FILT_SEL + Selection of 'i2c_scl_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [12:12] + read-write + + + SDA_OUT_FILT0_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [17:16] + read-write + + + SDA_OUT_FILT1_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [19:18] + read-write + + + SDA_OUT_FILT2_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [21:20] + read-write + + + SDA_OUT_FILT_SEL + Selection of cumulative 'i2c_sda_out' filter delay: +'0': 0 ns. +'1': 50 ns (filter 0 enabled). +'2': 100 ns (filters 0 and 1 enabled). +'3': 150 ns (filters 0, 1 and 2 enabled). + [29:28] + read-write + + + + + TX_CTRL + Transmitter control + 0x200 + 32 + read-write + 0x107 + 0x1010F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + OPEN_DRAIN + Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. +'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. +'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). + +The open drain mode is supported for: +- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. +- UART mode, 'uart_tx' IO cell (SPI slave). +- SPI mode, 'spi_miso' IO cell. + [16:16] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control + 0x204 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + [17:17] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status + 0x208 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + [31:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write + 0x240 + 32 + write-only + 0x0 + 0xFFFF + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. + [15:0] + write-only + + + + + RX_CTRL + Receiver control + 0x300 + 32 + read-write + 0x107 + 0x30F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. + [9:9] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control + 0x304 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + [17:17] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status + 0x308 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + [31:24] + read-only + + + + + RX_MATCH + Slave address and mask + 0x310 + 32 + read-write + 0x0 + 0xFF00FF + + + ADDR + Slave device address. + +In UART multi-processor mode, all 8 bits are used. + +In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). + [7:0] + read-write + + + MASK + Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). + [23:16] + read-write + + + + + RX_FIFO_RD + Receiver FIFO read + 0x340 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read silent + 0x344 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + INTR_CAUSE + Active clocked interrupt signal + 0xE00 + 32 + read-only + 0x0 + 0x3F + + + M + Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. + [0:0] + read-only + + + S + Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. + [1:1] + read-only + + + TX + Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. + [2:2] + read-only + + + RX + Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. + [3:3] + read-only + + + I2C_EC + Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. + [4:4] + read-only + + + SPI_EC + Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. + [5:5] + read-only + + + + + INTR_I2C_EC + Externally clocked I2C interrupt request + 0xE80 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (I2C STOP). + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask + 0xE88 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_I2C_EC_MASKED + Externally clocked I2C interrupt masked + 0xE8C + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_SPI_EC + Externally clocked SPI interrupt request + 0xEC0 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (SPI deselection). + +Only available in EZ and CMD_RESP mode and when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask + 0xEC8 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked + 0xECC + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_M + Master interrupt request + 0xF00 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + [0:0] + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + [1:1] + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + [2:2] + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + [4:4] + read-write + + + I2C_BUS_ERROR + I2C master bus error (unexpected detection of START or STOP condition). + [8:8] + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. + [9:9] + read-write + + + + + INTR_M_SET + Master interrupt set request + 0xF04 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASK + Master interrupt mask + 0xF08 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASKED + Master interrupt masked request + 0xF0C + 32 + read-only + 0x0 + 0x317 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + + + INTR_S + Slave interrupt request + 0xF40 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [0:0] + read-write + + + I2C_NACK + I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). + [1:1] + read-write + + + I2C_ACK + I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). + [2:2] + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. + +In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). + [3:3] + read-write + + + I2C_STOP + I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. + [4:4] + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. + [5:5] + read-write + + + I2C_ADDR_MATCH + I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [6:6] + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [7:7] + read-write + + + I2C_BUS_ERROR + I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + SPI slave deselected after a write EZ SPI transfer occurred. + [9:9] + read-write + + + SPI_EZ_STOP + SPI slave deselected after any EZ SPI transfer occurred. + [10:10] + read-write + + + SPI_BUS_ERROR + SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [11:11] + read-write + + + + + INTR_S_SET + Slave interrupt set request + 0xF44 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASK + Slave interrupt mask + 0xF48 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASKED + Slave interrupt masked request + 0xF4C + 32 + read-only + 0x0 + 0xFFF + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_START + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + SPI_EZ_STOP + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + SPI_BUS_ERROR + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + INTR_TX + Transmitter interrupt request + 0xF80 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_FULL + TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries != FF_DATA_NR/2. +BYTE_MODE is '1': # entries != FF_DATA_NR. + +Only used in FIFO mode. + [1:1] + read-write + + + EMPTY + TX FIFO is empty; i.e. it has 0 entries. + +Only used in FIFO mode. + [4:4] + read-write + + + OVERFLOW + Attempt to write to a full TX FIFO. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + UART_NACK + UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. + [8:8] + read-write + + + UART_DONE + UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. + [9:9] + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + + + INTR_TX_SET + Transmitter interrupt set request + 0xF84 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASK + Transmitter interrupt mask + 0xF88 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASKED + Transmitter interrupt masked request + 0xF8C + 32 + read-only + 0x0 + 0x7F3 + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + UART_NACK + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + UART_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + INTR_RX + Receiver interrupt request + 0xFC0 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_EMPTY + RX FIFO is not empty. + +Only used in FIFO mode. + [2:2] + read-write + + + FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries == FF_DATA_NR/2. +BYTE_MODE is '1': # entries == FF_DATA_NR. + +Only used in FIFO mode. + [3:3] + read-write + + + OVERFLOW + Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty RX FIFO. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + FRAME_ERROR + Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: +Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. +Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. + +A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. + [8:8] + read-write + + + PARITY_ERROR + Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. + [9:9] + read-write + + + BAUD_DETECT + LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. + [11:11] + read-write + + + + + INTR_RX_SET + Receiver interrupt set request + 0xFC4 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt status register. + [2:2] + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt status register. + [3:3] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt status register. + [7:7] + read-write + + + FRAME_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [8:8] + read-write + + + PARITY_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [9:9] + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [10:10] + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [11:11] + read-write + + + + + INTR_RX_MASK + Receiver interrupt mask + 0xFC8 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + FRAME_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + PARITY_ERROR + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_RX_MASKED + Receiver interrupt masked request + 0xFCC + 32 + read-only + 0x0 + 0xFED + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + FULL + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + FRAME_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + PARITY_ERROR + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + BAUD_DETECT + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + BREAK_DETECT + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + + + SCB1 + 0x40610000 + + + SCB2 + 0x40620000 + + + SCB3 + 0x40630000 + + + SCB4 + 0x40640000 + + + SCB5 + 0x40650000 + + + SCB6 + 0x40660000 + + + SCB7 + 0x40670000 + + + SCB8 + 0x40680000 + + + SCB9 + 0x40690000 + + + SCB10 + 0x406A0000 + + + SCB11 + 0x406B0000 + + + SCB12 + 0x406C0000 + + + SAR + SAR ADC with Sequencer + 0x409D0000 + + 0 + 65536 + registers + + + + CTRL + Analog control register. + 0x0 + 32 + read-write + 0x10000000 + 0xFF3FEEF7 + + + PWR_CTRL_VREF + VREF buffer low power mode. + [2:0] + read-write + + + PWR_100 + full power (100 percent) (default), bypass cap, max clk_sar is 18MHz. + 0 + + + PWR_80 + 80 percent power + 1 + + + PWR_60 + 60 percent power + 2 + + + PWR_50 + 50 percent power + 3 + + + PWR_40 + 40 percent power + 4 + + + PWR_30 + 30 percent power + 5 + + + PWR_20 + 20 percent power + 6 + + + PWR_10 + 10 percent power + 7 + + + + + VREF_SEL + SARADC internal VREF selection. + [6:4] + read-write + + + VREF0 + VREF0 from PRB (VREF buffer on) + 0 + + + VREF1 + VREF1 from PRB (VREF buffer on) + 1 + + + VREF2 + VREF2 from PRB (VREF buffer on) + 2 + + + VREF_AROUTE + VREF from AROUTE (VREF buffer on) + 3 + + + VBGR + 1.024V from BandGap (VREF buffer on) + 4 + + + VREF_EXT + External precision Vref direct from a pin (low impedance path). + 5 + + + VDDA_DIV_2 + Vdda/2 (VREF buffer on) + 6 + + + VDDA + Vdda. + 7 + + + + + VREF_BYP_CAP_EN + VREF bypass cap enable for when VREF buffer is on + [7:7] + read-write + + + NEG_SEL + SARADC internal NEG selection for Single ended conversion + [11:9] + read-write + + + VSSA_KELVIN + NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high. + 0 + + + ART_VSSA + NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC + 1 + + + P1 + NEG input of SARADC is connected to P1 pin of SARMUX + 2 + + + P3 + NEG input of SARADC is connected to P3 pin of SARMUX + 3 + + + P5 + NEG input of SARADC is connected to P5 pin of SARMUX + 4 + + + P7 + NEG input of SARADC is connected to P7 pin of SARMUX + 5 + + + ACORE + NEG input of SARADC is connected to an ACORE in AROUTE + 6 + + + VREF + NEG input of SARADC is shorted with VREF input of SARADC. + 7 + + + + + SAR_HW_CTRL_NEGVREF + Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. + [13:13] + read-write + + + COMP_DLY + Set the comparator latch delay in accordance with SAR conversion rate + [15:14] + read-write + + + D2P5 + 2.5ns delay, use this for 2.5Msps + 0 + + + D4 + 4.0ns delay, use this for 2.0Msps + 1 + + + D10 + 10ns delay, use this for 1.5Msps + 2 + + + D12 + 12ns delay, use this for 1.0Msps or less + 3 + + + + + SPARE + Spare controls, not yet designated, for late changes done with an ECO + [19:16] + read-write + + + BOOSTPUMP_EN + deprecated + [20:20] + read-write + + + REFBUF_EN + For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. +Setting this bit is critical to proper function of switches inside SARREF block. + [21:21] + read-write + + + COMP_PWR + Comparator power mode. + [26:24] + read-write + + + P100 + Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz + 0 + + + P80 + N/A + 1 + + + P60 + Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz. + 2 + + + P50 + N/A + 3 + + + P40 + N/A + 4 + + + P30 + N/A + 5 + + + P20 + Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz + 6 + + + P10 + N/A + 7 + + + + + DEEPSLEEP_ON + - 0: SARMUX IP disabled off during DeepSleep power mode +- 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) + [27:27] + read-write + + + DSI_SYNC_CONFIG + - 0: bypass clock domain synchronization of the DSI config signals. +- 1: synchronize the DSI config signals to peripheral clock domain. + [28:28] + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) +- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations +- 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored + [29:29] + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) +- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations +- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX + [30:30] + read-write + + + ENABLED + - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgating) on write. +- 1: SAR IP enabled. + [31:31] + read-write + + + + + SAMPLE_CTRL + Sample control register. + 0x4 + 32 + read-write + 0x80008 + 0xDFCF01FE + + + LEFT_ALIGN + Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. + [1:1] + read-write + + + SINGLE_ENDED_SIGNED + Output data from a single ended conversion as a signed value + +If AVG_MODE = 1 (Interleaved averaging), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED. + [2:2] + read-write + + + UNSIGNED + Default: result data is unsigned (zero extended if needed) + 0 + + + SIGNED + result data is signed (sign extended if needed) + 1 + + + + + DIFFERENTIAL_SIGNED + Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 + +If AVG_MODE = 1 (Interleaved averaging), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED. + [3:3] + read-write + + + UNSIGNED + result data is unsigned (zero extended if needed) + 0 + + + SIGNED + Default: result data is signed (sign extended if needed) + 1 + + + + + AVG_CNT + Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. +- In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). +- In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). + [6:4] + read-write + + + AVG_SHIFT + Averaging shifting: after averaging the result is shifted right to fit in 12 bits. + [7:7] + read-write + + + AVG_MODE + Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. + [8:8] + read-write + + + ACCUNDUMP + Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged + 0 + + + INTERLEAVED + Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans. + 1 + + + + + CONTINUOUS + - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. +- 1: Continuously scan enabled channels, ignore triggers. + [16:16] + read-write + + + DSI_TRIGGER_EN + - 0: firmware trigger only: disable hardware trigger tr_sar_in. +- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). + [17:17] + read-write + + + DSI_TRIGGER_LEVEL + - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. +- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. + [18:18] + read-write + + + DSI_SYNC_TRIGGER + - 0: bypass clock domain synchronization of the trigger signal. +- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. + [19:19] + read-write + + + UAB_SCAN_MODE + Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored. + [22:22] + read-write + + + UNSCHEDULED + Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable. + 0 + + + SCHEDULED + Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. +This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator. + 1 + + + + + REPEAT_INVALID + For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: +- 0: use the last known valid sample for that channel and clear the NEWVALUE flag +- 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling) + [23:23] + read-write + + + VALID_SEL + Static UAB Valid select +0=UAB0 half 0 Valid output +1=UAB0 half 1 Valid output +2=UAB1 half 0 Valid output +3=UAB1 half 1 Valid output +4=UAB2 half 0 Valid output +5=UAB2 half 1 Valid output +6=UAB3 half 0 Valid output +7=UAB3 half 1 Valid output + [26:24] + read-write + + + VALID_SEL_EN + Enable static UAB Valid selection (override Hardware) + [27:27] + read-write + + + VALID_IGNORE + Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above + [28:28] + read-write + + + TRIGGER_OUT_EN + SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1). + [30:30] + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. + [31:31] + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x10 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. + [9:0] + read-write + + + SAMPLE_TIME1 + Sample time1 + [25:16] + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x14 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME2 + Sample time2 + [9:0] + read-write + + + SAMPLE_TIME3 + Sample time3 + [25:16] + read-write + + + + + RANGE_THRES + Global range detect threshold register. + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RANGE_LOW + Low threshold for range detect. + [15:0] + read-write + + + RANGE_HIGH + High threshold for range detect. + [31:16] + read-write + + + + + RANGE_COND + Global range detect mode register. + 0x1C + 32 + read-write + 0x0 + 0xC0000000 + + + RANGE_COND + Range condition select. + [31:30] + read-write + + + BELOW + result < RANGE_LOW + 0 + + + INSIDE + RANGE_LOW <= result < RANGE_HIGH + 1 + + + ABOVE + RANGE_HIGH <= result + 2 + + + OUTSIDE + result < RANGE_LOW || RANGE_HIGH <= result + 3 + + + + + + + CHAN_EN + Enable bits for the channels + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CHAN_EN + Channel enable. +- 0: the corresponding channel is disabled. +- 1: the corresponding channel is enabled, it will be included in the next scan. + [15:0] + read-write + + + + + START_CTRL + Start control register (firmware trigger). + 0x24 + 32 + read-write + 0x0 + 0x1 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. + [0:0] + read-write + + + + + 16 + 4 + CHAN_CONFIG[%s] + Channel configuration register. + 0x80 + 32 + read-write + 0x0 + 0x81773577 + + + POS_PIN_ADDR + Address of the pin to be sampled by this channel (connected to Vplus) + [2:0] + read-write + + + POS_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel (connected to Vplus) + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + DIFFERENTIAL_EN + Differential enable for this channel. +If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + NEG_PIN_ADDR + Address of the neg pin to be sampled by this channel. + [18:16] + read-write + + + NEG_PORT_ADDR + Address of the neg port that contains the pin to be sampled by this channel. + [22:20] + read-write + + + SARMUX + SARMUX pins. + 0 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + NEG_ADDR_EN + 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. + [24:24] + read-write + + + DSI_OUT_EN + DSI data output enable for this channel. +- 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. +- 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. + [31:31] + read-write + + + + + 16 + 4 + CHAN_WORK[%s] + Channel working data register + 0x100 + 32 + read-only + 0x0 + 0x88000000 + + + WORK + SAR conversion working data of the channel. The data is written here right after sampling this channel. + [15:0] + read-only + + + CHAN_WORK_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register + [27:27] + read-only + + + CHAN_WORK_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register + [31:31] + read-only + + + + + 16 + 4 + CHAN_RESULT[%s] + Channel result data register + 0x180 + 32 + read-only + 0x0 + 0xE8000000 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + [15:0] + read-only + + + CHAN_RESULT_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register + [27:27] + read-only + + + SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_SATURATE_INTR register + [29:29] + read-only + + + RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_RANGE_INTR register + [30:30] + read-only + + + CHAN_RESULT_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register + [31:31] + read-only + + + + + CHAN_WORK_UPDATED + Channel working data register 'updated' bits + 0x200 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_UPDATED + If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_RESULT_UPDATED + Channel result data register 'updated' bits + 0x204 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_UPDATED + If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_WORK_NEWVALUE + Channel working data register 'new value' bits + 0x208 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_NEWVALUE + If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + CHAN_RESULT_NEWVALUE + Channel result data register 'new value' bits + 0x20C + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_NEWVALUE + If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + INTR + Interrupt request register. + 0x210 + 32 + read-write + 0x0 + 0xFF + + + EOS_INTR + End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. + [0:0] + read-write + + + OVERFLOW_INTR + Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. + [1:1] + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [2:2] + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [3:3] + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. + [4:4] + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [5:5] + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [6:6] + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit. + [7:7] + read-write + + + + + INTR_SET + Interrupt set request register + 0x214 + 32 + read-write + 0x0 + 0xFF + + + EOS_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask register. + 0x218 + 32 + read-write + 0x0 + 0xFF + + + EOS_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_MASK + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x21C + 32 + read-only + 0x0 + 0xFF + + + EOS_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + OVERFLOW_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + FW_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + DSI_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + INJ_EOC_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + INJ_SATURATE_MASKED + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + INJ_RANGE_MASKED + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + INJ_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + + + SATURATE_INTR + Saturate interrupt request register. + 0x220 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_INTR + Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [15:0] + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x224 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register. + 0x228 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x22C + 32 + read-only + 0x0 + 0xFFFF + + + SATURATE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + RANGE_INTR + Range detect interrupt request register. + 0x230 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_INTR + Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [15:0] + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x234 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register. + 0x238 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x23C + 32 + read-only + 0x0 + 0xFFFF + + + RANGE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + INTR_CAUSE + Interrupt cause register + 0x240 + 32 + read-only + 0x0 + 0xC00000FF + + + EOS_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [0:0] + read-only + + + OVERFLOW_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [1:1] + read-only + + + FW_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [2:2] + read-only + + + DSI_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [3:3] + read-only + + + INJ_EOC_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [4:4] + read-only + + + INJ_SATURATE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [5:5] + read-only + + + INJ_RANGE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [6:6] + read-only + + + INJ_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [7:7] + read-only + + + SATURATE_MASKED_RED + Reduction OR of all SAR_SATURATION_INTR_MASKED bits + [30:30] + read-only + + + RANGE_MASKED_RED + Reduction OR of all SAR_RANGE_INTR_MASKED bits + [31:31] + read-only + + + + + INJ_CHAN_CONFIG + Injection channel configuration register. + 0x280 + 32 + read-write + 0x0 + 0xC0003577 + + + INJ_PIN_ADDR + Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. + [2:0] + read-write + + + INJ_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel. + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT + AROUTE virtual port + 6 + + + SARMUX_VIRT + SARMUX virtual port + 7 + + + + + INJ_DIFFERENTIAL_EN + Differential enable for this channel. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + INJ_AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + INJ_SAMPLE_TIME_SEL + Injection sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + INJ_TAILGATING + Injection channel tailgating. +- 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set if the SAR is not busy. If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan. +- 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. + [30:30] + read-write + + + INJ_START_EN + Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. + [31:31] + read-write + + + + + INJ_RESULT + Injection channel result register + 0x290 + 32 + read-only + 0x0 + 0xF8000000 + + + INJ_RESULT + SAR conversion result of the channel. + [15:0] + read-only + + + INJ_NEWVALUE + The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit) + [27:27] + read-only + + + INJ_COLLISION_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [28:28] + read-only + + + INJ_SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [29:29] + read-only + + + INJ_RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [30:30] + read-only + + + INJ_EOC_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [31:31] + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x2A0 + 32 + read-only + 0x0 + 0xC000001F + + + CUR_CHAN + current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. + [4:0] + read-only + + + SW_VREF_NEG + the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). + [30:30] + read-only + + + BUSY + If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. + [31:31] + read-only + + + + + AVG_STAT + Current averaging status (for debug) + 0x2A4 + 32 + read-only + 0x0 + 0xFF8FFFFF + + + CUR_AVG_ACCU + the current value of the averaging accumulator + [19:0] + read-only + + + INTRLV_BUSY + If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. +This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. + [23:23] + read-only + + + CUR_AVG_CNT + the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. + [31:24] + read-only + + + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x300 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit. + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit. + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit. + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit. + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit. + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit. + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit. + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit. + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit. + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit. + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit. + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit. + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit. + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit. + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit. + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit. + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit. + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit. + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit. + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit. + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit. + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit. + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit. + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit. + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit. + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit. + [29:29] + read-write + + + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x304 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [29:29] + read-write + + + + + MUX_SWITCH_DS_CTRL + SARMUX switch DSI control + 0x340 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_DS_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_DS_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_DS_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_DS_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_DS_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_DS_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_DS_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_DS_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_DS_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_DS_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_DS_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_DS_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_DS_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_DS_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_SQ_CTRL + SARMUX switch Sar Sequencer control + 0x344 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_SQ_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_SQ_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_SQ_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_SQ_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_SQ_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_SQ_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_SQ_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_SQ_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_SQ_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_SQ_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_SQ_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_SQ_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_SQ_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_SQ_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x348 + 32 + read-only + 0x0 + 0x3FFFFFF + + + MUX_FW_P0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [0:0] + read-only + + + MUX_FW_P1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [1:1] + read-only + + + MUX_FW_P2_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [2:2] + read-only + + + MUX_FW_P3_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [3:3] + read-only + + + MUX_FW_P4_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [4:4] + read-only + + + MUX_FW_P5_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [5:5] + read-only + + + MUX_FW_P6_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [6:6] + read-only + + + MUX_FW_P7_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [7:7] + read-only + + + MUX_FW_P0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [8:8] + read-only + + + MUX_FW_P1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [9:9] + read-only + + + MUX_FW_P2_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [10:10] + read-only + + + MUX_FW_P3_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [11:11] + read-only + + + MUX_FW_P4_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [12:12] + read-only + + + MUX_FW_P5_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [13:13] + read-only + + + MUX_FW_P6_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [14:14] + read-only + + + MUX_FW_P7_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [15:15] + read-only + + + MUX_FW_VSSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [16:16] + read-only + + + MUX_FW_TEMP_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [17:17] + read-only + + + MUX_FW_AMUXBUSA_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [18:18] + read-only + + + MUX_FW_AMUXBUSB_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [19:19] + read-only + + + MUX_FW_AMUXBUSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [20:20] + read-only + + + MUX_FW_AMUXBUSB_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [21:21] + read-only + + + MUX_FW_SARBUS0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [22:22] + read-only + + + MUX_FW_SARBUS1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [23:23] + read-only + + + MUX_FW_SARBUS0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [24:24] + read-only + + + MUX_FW_SARBUS1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [25:25] + read-only + + + + + ANA_TRIM0 + Analog trim register. + 0xF00 + 32 + read-write + 0x0 + 0x3F + + + CAP_TRIM + Attenuation cap trimming + [4:0] + read-write + + + TRIMUNIT + Attenuation cap trimming + [5:5] + read-write + + + + + ANA_TRIM1 + Analog trim register. + 0xF04 + 32 + read-write + 0x0 + 0x3F + + + SAR_REF_BUF_TRIM + SAR Reference buffer trim + [5:0] + read-write + + + + + + + PASS + PASS top-level MMIO (DSABv2, INTR) + 0x409F0000 + + 0 + 65536 + registers + + + + INTR_CAUSE + Interrupt cause register + 0x0 + 32 + read-only + 0x0 + 0xFF + + + CTB0_INT + CTB0 interrupt pending + [0:0] + read-only + + + CTB1_INT + CTB1 interrupt pending + [1:1] + read-only + + + CTB2_INT + CTB2 interrupt pending + [2:2] + read-only + + + CTB3_INT + CTB3 interrupt pending + [3:3] + read-only + + + CTDAC0_INT + CTDAC0 interrupt pending + [4:4] + read-only + + + CTDAC1_INT + CTDAC1 interrupt pending + [5:5] + read-only + + + CTDAC2_INT + CTDAC2 interrupt pending + [6:6] + read-only + + + CTDAC3_INT + CTDAC3 interrupt pending + [7:7] + read-only + + + + + AREF + AREF configuration + 0x00000E00 + + AREF_CTRL + global AREF control + 0x0 + 32 + read-write + 0x0 + 0xF039FFFD + + + AREF_MODE + Control bit to trade off AREF settling and noise performance + [0:0] + read-write + + + NORMAL + Nominal noise normal startup mode (meets normal mode settling and noise specifications) + 0 + + + FAST_START + High noise fast startup mode (meets fast mode settling and noise specifications) + 1 + + + + + AREF_BIAS_SCALE + BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) +0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) +1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) +2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) +3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) + [3:2] + read-write + + + AREF_RMB + AREF control signals (RMB). + +Bit 0: Manual VBG startup circuit enable + 0: normal VBG startup circuit operation + 1: VBG startup circuit is forced 'always on' + +Bit 1: Manual disable of IPTAT2 DAC + 0: normal IPTAT2 DAC operation + 1: PTAT2 DAC is disabled while VBG startup is active + +Bit 2: Manual enable of VBG offset correction DAC + 0: normal VBG offset correction DAC operation + 1: VBG offset correction DAC is enabled while VBG startup is active + [6:4] + read-write + + + CTB_IPTAT_SCALE + CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). +0: 1uA +1: 100nA + [7:7] + read-write + + + CTB_IPTAT_REDIRECT + Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). +0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT +1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT + +*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. + [15:8] + read-write + + + IZTAT_SEL + iztat current select control + [16:16] + read-write + + + SRSS + Use 250nA IZTAT from SRSS + 0 + + + LOCAL + Use locally generated 250nA + 1 + + + + + CLOCK_PUMP_PERI_SEL + CTBm charge pump clock source select. This field has nothing to do with the AREF. +0: Use the dedicated pump clock from SRSS (default) +1: Use one of the CLK_PERI dividers + [19:19] + read-write + + + VREF_SEL + bandgap voltage select control + [21:20] + read-write + + + SRSS + Use 0.8V Vref from SRSS + 0 + + + LOCAL + Use locally generated Vref + 1 + + + EXTERNAL + Use externally supplied Vref (aref_ext_vref) + 2 + + + + + DEEPSLEEP_MODE + AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) + [29:28] + read-write + + + OFF + All blocks 'OFF' in DeepSleep + 0 + + + IPTAT + IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) + 1 + + + IPTAT_IZTAT + IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) + +*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep + 2 + + + IPTAT_IZTAT_VREF + IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. + 3 + + + + + DEEPSLEEP_ON + - 0: AREF IP disabled/off during DeepSleep power mode +- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + Disable AREF + [31:31] + read-write + + + + + + VREF_TRIM0 + VREF Trim bits + 0xF00 + 32 + read-write + 0x0 + 0xFF + + + VREF_ABS_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM1 + VREF Trim bits + 0xF04 + 32 + read-write + 0x0 + 0xFF + + + VREF_TEMPCO_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM2 + VREF Trim bits + 0xF08 + 32 + read-write + 0x0 + 0xFF + + + VREF_CURV_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM3 + VREF Trim bits + 0xF0C + 32 + read-write + 0x0 + 0xF + + + VREF_ATTEN_TRIM + Obsolete + [3:0] + read-write + + + + + IZTAT_TRIM0 + IZTAT Trim bits + 0xF10 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_ABS_TRIM + N/A + [7:0] + read-write + + + + + IZTAT_TRIM1 + IZTAT Trim bits + 0xF14 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_TC_TRIM + IZTAT temperature correction trim (RMB) +0x00 : No IZTAT temperature correction +0xFF : Maximum IZTAT temperature correction + +As this is a Risk Mitigation Register, it should be loaded with 0x08. + [7:0] + read-write + + + + + IPTAT_TRIM0 + IPTAT Trim bits + 0xF18 + 32 + read-write + 0x0 + 0xFF + + + IPTAT_CORE_TRIM + IPTAT trim +0x0 : Minimum IPTAT current (~150nA at room) +0xF : Maximum IPTAT current (~350nA at room) + [3:0] + read-write + + + IPTAT_CTBM_TRIM + CTMB PTAT Current Trim +0x0 : Minimum CTMB IPTAT Current (~875nA) +0xF : Maximum CTMB IPTAT Current (~1.1uA) + [7:4] + read-write + + + + + ICTAT_TRIM0 + ICTAT Trim bits + 0xF1C + 32 + read-write + 0x0 + 0xF + + + ICTAT_TRIM + ICTAT trim +0x00 : Minimum ICTAT current (~150nA at room) +0x0F : Maximum ICTAT current (~350nA at room) + [3:0] + read-write + + + + + + + PDM0 + PDM registers + PDM + 0x40A00000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x20808 + 0x80030F0F + + + PGA_R + Right channel PGA gain: ++1.5dB/step, -12dB ~ +10.5dB +'0': -12 dB +'1': -10.5 dB +... +'15' +10.5 dB +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R) + [3:0] + read-write + + + PGA_L + Left channel PGA gain: ++1.5dB/step, -12dB ~ +10.5dB +'0': -12 dB +'1': -10.5 dB +... +'15': +10.5 dB +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L) + [11:8] + read-write + + + SOFT_MUTE + Soft mute function to mute the volume smoothly +'0': Disabled. +'1': Enabled. +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE) + [16:16] + read-write + + + STEP_SEL + Set fine gain step for smooth PGA or Soft-Mute attenuation transition. +'0': 0.13dB +'1': 0.26dB +(Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP) + [17:17] + read-write + + + ENABLED + Enables the PDM component: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CLOCK_CTL + Clock control + 0x10 + 32 + read-write + 0x200310 + 0x7F0F33 + + + CLK_CLOCK_DIV + PDM CLK (FPDM_CLK) (1st divider): +This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. + +Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider. + [1:0] + read-write + + + DIVBY1 + Divide by 1 + 0 + + + DIVBY2 + Divide by 2 (no 50 percent duty cycle) + 1 + + + DIVBY3 + Divide by 3 (no 50 percent duty cycle) + 2 + + + DIVBY4 + Divide by 4 (no 50 percent duty cycle) + 3 + + + + + MCLKQ_CLOCK_DIV + MCLKQ divider (2nd divider) + +(Note: These bits are connected to +AR36U12.PDM_CORE2_CFG.DIV_MCLKQ) + [5:4] + read-write + + + DIVBY1 + Divide by 1 + 0 + + + DIVBY2 + Divide by 2 (no 50 percent duty cycle) + 1 + + + DIVBY3 + Divide by 3 (no 50 percent duty cycle) + 2 + + + DIVBY4 + Divide by 4 (no 50 percent duty cycle) + 3 + + + + + CKO_CLOCK_DIV + PDM CKO (FPDM_CKO) clock divider (3rd divider): +FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1) + +Note: To configure '0' to this field is prohibited. +(Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. ) +(Note: These bits are connected to +AR36U12.PDM_CORE_CFG.MCLKDIV) + [11:8] + read-write + + + SINC_RATE + SINC Decimation Rate. For details, see the data sheet provided by Archband. +Oversampling Ratio = Decimation Rate = 2 X SINC_RATE +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE) + [22:16] + read-write + + + + + MODE_CTL + Mode control + 0x14 + 32 + read-write + 0x1B000103 + 0x1F070707 + + + PCM_CH_SET + Specifies PCM output channels as mono or stereo: + +(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET) + [1:0] + read-write + + + DISABLED + Channel disabled + 0 + + + MONO_L + Mono left channel enable + 1 + + + MONO_R + Mono right channel enable + 2 + + + STEREO + Stereo channel enable + 3 + + + + + SWAP_LR + Input data L/R channel swap: +'1': Right/Left channel recording swap +'0': No Swap +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP) + [2:2] + read-write + + + S_CYCLES + Set time step for gain change during PGA or soft mute operation in +number of 1/a sampling rate. +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES) + [10:8] + read-write + + + STEP_NUM64 + 64steps + 0 + + + STEP_NUM96 + 96steps + 1 + + + STEP_NUM128 + 128steps + 2 + + + STEP_NUM160 + 160steps + 3 + + + STEP_NUM192 + 192steps + 4 + + + STEP_NUM256 + 256steps + 5 + + + STEP_NUM384 + 384steps + 6 + + + STEP_NUM512 + 512steps + 7 + + + + + CKO_DELAY + Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock: + +(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY) + [18:16] + read-write + + + ADV3 + CLK_IS is 3*PDM_CLK period early + 0 + + + ADV2 + CLK_IS is 2*PDM_CLK period early + 1 + + + ADV1 + CLK_IS is 1*PDM_CLK period early + 2 + + + NO_DELAY + CLK_IS is the same as PDM_CKO + 3 + + + DLY1 + CLK_IS is 1*PDM_CLK period late + 4 + + + DLY2 + CLK_IS is 2*PDM_CLK period late + 5 + + + DLY3 + CLK_IS is 3*PDM_CLK period late + 6 + + + DLY4 + CLK_IS is 4*PDM_CLK period late + 7 + + + + + HPF_GAIN + Adjust high pass filter coefficients. +H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ] +(Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN) + [27:24] + read-write + + + HPF_EN_N + Enable high pass filter (active low) +'1': Disabled. +'0': Enabled. +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD) + [28:28] + read-write + + + + + DATA_CTL + Data control + 0x18 + 32 + read-write + 0x0 + 0x103 + + + WORD_LEN + PCM Word Length in number of bits: + +(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL) + [1:0] + read-write + + + BIT_LEN16 + 16-bit + 0 + + + BIT_LEN18 + 18-bit + 1 + + + BIT_LEN20 + 20-bit + 2 + + + BIT_LEN24 + 24-bit + 3 + + + + + BIT_EXTENSION + When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. +'0': Extended by '0' +'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') + [8:8] + read-write + + + + + CMD + Command + 0x20 + 32 + read-write + 0x0 + 0x1 + + + STREAM_EN + Enable data streaming flow: +'0': Disabled. +'1': Enabled. +(Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN) + [0:0] + read-write + + + + + TR_CTL + Trigger control + 0x40 + 32 + read-write + 0x0 + 0x10000 + + + RX_REQ_EN + Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + RX_FIFO_CTL + RX FIFO control + 0x300 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. +Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3'). + [7:0] + read-write + + + CLEAR + When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes. + [17:17] + read-write + + + + + RX_FIFO_STATUS + RX FIFO status + 0x304 + 32 + read-only + 0x0 + 0xFFFF00FF + + + USED + Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty. + [7:0] + read-only + + + RD_PTR + RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes. + [31:24] + read-only + + + + + RX_FIFO_RD + RX FIFO read + 0x308 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. +Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + RX FIFO silent read + 0x30C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. +Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. + [31:0] + read-only + + + + + INTR + Interrupt register + 0xF00 + 32 + read-write + 0x0 + 0x650000 + + + RX_TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL. + [16:16] + read-write + + + RX_NOT_EMPTY + RX FIFO is not empty. + [18:18] + read-write + + + RX_OVERFLOW + Attempt to write to a full RX FIFO + [21:21] + read-write + + + RX_UNDERFLOW + Attempt to read from an empty RX FIFO + [22:22] + read-write + + + + + INTR_SET + Interrupt set register + 0xF04 + 32 + read-write + 0x0 + 0x650000 + + + RX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [22:22] + read-write + + + + + INTR_MASK + Interrupt mask register + 0xF08 + 32 + read-write + 0x0 + 0x650000 + + + RX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [22:22] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0xF0C + 32 + read-only + 0x0 + 0x650000 + + + RX_TRIGGER + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + RX_NOT_EMPTY + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + RX_OVERFLOW + Logical and of corresponding request and mask bits. + [21:21] + read-only + + + RX_UNDERFLOW + Logical and of corresponding request and mask bits. + [22:22] + read-only + + + + + + + I2S0 + I2S registers + I2S + 0x40A10000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + TX_ENABLED + Enables the I2S TX component: +'0': Disabled. +'1': Enabled. + [30:30] + read-write + + + RX_ENABLED + Enables the I2S RX component: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CLOCK_CTL + Clock control + 0x10 + 32 + read-write + 0x0 + 0x13F + + + CLOCK_DIV + Frequency divisor for generating I2S clock frequency. +The selected clock with CLOCK_SEL is divided by this. +'0': Bypass +'1': 2 x +'2': 3 x +'3': 4 x +... +'62': 63 x +'63': 64 x + [5:0] + read-write + + + CLOCK_SEL + Selects clock to be used by I2S: +'0': Internal clock ('clk_audio_i2s') +'1': External clock ('clk_i2s_if') + [8:8] + read-write + + + + + CMD + Command + 0x20 + 32 + read-write + 0x0 + 0x10101 + + + TX_START + Transmitter enable: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + TX_PAUSE + Pause enable: +'0': Disabled (TX FIFO data is sent over I2S). +'1': Enabled ('0' data is sent over I2S, instead of TX FIFO data). + [8:8] + read-write + + + RX_START + Receiver enable: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + TR_CTL + Trigger control + 0x40 + 32 + read-write + 0x0 + 0x10001 + + + TX_REQ_EN + Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + RX_REQ_EN + Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + TX_CTL + Transmitter control + 0x80 + 32 + read-write + 0x440510 + 0x37737F8 + + + B_CLOCK_INV + Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. +When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'. + +1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge +2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1) +3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge +4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3) + +(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. +Note: When Master mode, must be '0'. +(Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV) + [3:3] + read-write + + + FALLING_EDGE_TX + SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0 + 0 + + + RISING_EDGE_TX + SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0 + 1 + + + + + CH_NR + Specifies number of channels per frame: + +Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. +(Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET) + [6:4] + read-write + + + CH_NUM1 + 1 channel + 0 + + + CH_NUM2 + 2 channels + 1 + + + CH_NUM3 + 3 channels + 2 + + + CH_NUM4 + 4 channels + 3 + + + CH_NUM5 + 5 channels + 4 + + + CH_NUM6 + 6 channels + 5 + + + CH_NUM7 + 7 channels + 6 + + + CH_NUM8 + 8 channels + 7 + + + + + MS + Set interface in master or slave mode: + +(Note: This bit is connected to AR38U12.TX_CFG.TX_MS) + [7:7] + read-write + + + SLAVE + Slave + 0 + + + MASTER + Master + 1 + + + + + I2S_MODE + Select I2S, left-justified or TDM: + +(Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE) + [9:8] + read-write + + + LEFT_JUSTIFIED + Left Justified + 0 + + + I2S + I2S mode + 1 + + + TDM_A + TDM mode A, the 1st Channel align to WSO +Rising Edge + 2 + + + TDM_B + TDM mode B, the 1st Channel align to WSO +Rising edge with1 SCK Delay + 3 + + + + + WS_PULSE + Set WS pulse width in TDM mode: + +(Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) +Note: When not TDM mode, must be '1'. + [10:10] + read-write + + + SCK_PERIOD + Pulse width is 1 SCK period + 0 + + + CH_LENGTH + Pulse width is 1 channel length + 1 + + + + + OVHDATA + Set overhead value: +'0': Set to '0' +'1': Set to '1' +(Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA) + [12:12] + read-write + + + WD_EN + Set watchdog for 'tx_ws_in': +'0': Disabled. +'1': Enabled. + [13:13] + read-write + + + CH_LEN + Channel length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- When TDM mode, must be 32-bit length to this field. +(Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN) + [18:16] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + WORD_LEN + Word length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- Don't configure this field as beyond Channel length. +(Note: These bits are connected to AR38U12.TX_CFG.TX_IWL) + [22:20] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + SCKO_POL + TX master bit clock polarity. +When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. +'0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge +'1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge + [24:24] + read-write + + + SCKI_POL + TX slave bit clock polarity. +When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details. + [25:25] + read-write + + + + + TX_WATCHDOG + Transmitter watchdog + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WD_COUNTER + Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. + [31:0] + read-write + + + + + RX_CTL + Receiver control + 0xA0 + 32 + read-write + 0x440510 + 0x3F727F8 + + + B_CLOCK_INV + Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. +When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'. + +1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge +2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1) +3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge +4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3) + +(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. +Note: When Slave mode, must be '0'. +(Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV) + [3:3] + read-write + + + RISING_EDGE_RX + SDI received at SCK rising edge when RX_CTL.SCKO_POL=0 + 0 + + + FALLING_EDGE_RX + SDI received at SCK falling edge when RX_CTL.SCKO_POL=0 + 1 + + + + + CH_NR + Specifies number of channels per frame: + +Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. +(Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET) + [6:4] + read-write + + + CH_NUM1 + 1 channel + 0 + + + CH_NUM2 + 2 channels + 1 + + + CH_NUM3 + 3 channels + 2 + + + CH_NUM4 + 4 channels + 3 + + + CH_NUM5 + 5 channels + 4 + + + CH_NUM6 + 6 channels + 5 + + + CH_NUM7 + 7 channels + 6 + + + CH_NUM8 + 8 channels + 7 + + + + + MS + Set interface in master or slave mode: + +(Note: This bit is connected to AR38U12.TX_CFG.RX_MS) + [7:7] + read-write + + + SLAVE + Slave + 0 + + + MASTER + Master + 1 + + + + + I2S_MODE + Select I2S, left-justified or TDM: + +(Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE) + [9:8] + read-write + + + LEFT_JUSTIFIED + Left Justified + 0 + + + I2S + I2S mode + 1 + + + TDM_A + TDM mode A, the 1st Channel align to WSO +Rising Edge + 2 + + + TDM_B + TDM mode B, the 1st Channel align to WSO +Rising edge with1 SCK Delay + 3 + + + + + WS_PULSE + Set WS pulse width in TDM mode: + +(Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) +Note: When not TDM mode, must be '1'. + [10:10] + read-write + + + SCK_PERIOD + Pulse width is 1 SCK period + 0 + + + CH_LENGTH + Pulse width is 1 channel length + 1 + + + + + WD_EN + Set watchdog for 'rx_ws_in' +'0': Disabled. +'1': Enabled. + [13:13] + read-write + + + CH_LEN + Channel length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- When TDM mode, must be 32-bit length to this field. +(Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN) + [18:16] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + WORD_LEN + Word length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- Don't configure this field as beyond Channel length. +(Note: These bits are connected to AR38U12.RX_CFG.RX_IWL) + [22:20] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + BIT_EXTENSION + When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. +'0': Extended by '0' +'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') + [23:23] + read-write + + + SCKO_POL + RX master bit clock polarity. +When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details. + [24:24] + read-write + + + SCKI_POL + RX slave bit clock polarity. +When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting. +'0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge +'1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge + [25:25] + read-write + + + + + RX_WATCHDOG + Receiver watchdog + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WD_COUNTER + Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. + [31:0] + read-write + + + + + TX_FIFO_CTL + TX FIFO control + 0x200 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. + [7:0] + read-write + + + CLEAR + When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes. + [17:17] + read-write + + + + + TX_FIFO_STATUS + TX FIFO status + 0x204 + 32 + read-only + 0x0 + 0xFFFF01FF + + + USED + Number of entries in the TX FIFO. The field value is in the range [0, 256]. + [8:0] + read-only + + + RD_PTR + TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes. + [31:24] + read-only + + + + + TX_FIFO_WR + TX FIFO write + 0x208 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA + Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. +Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'. + [31:0] + write-only + + + + + RX_FIFO_CTL + RX FIFO control + 0x300 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. +Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)]. + [7:0] + read-write + + + CLEAR + When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee. + [17:17] + read-write + + + + + RX_FIFO_STATUS + RX FIFO status + 0x304 + 32 + read-only + 0x0 + 0xFFFF01FF + + + USED + Number of entries in the RX FIFO. The field value is in the range [0, 256]. + [8:0] + read-only + + + RD_PTR + RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes. + [31:24] + read-only + + + + + RX_FIFO_RD + RX FIFO read + 0x308 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. +Notes: + - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. + - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + RX FIFO silent read + 0x30C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. +Notes: + - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. + - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. + [31:0] + read-only + + + + + INTR + Interrupt register + 0xF00 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL. + [0:0] + read-write + + + TX_NOT_FULL + TX FIFO is not full. + [1:1] + read-write + + + TX_EMPTY + TX FIFO is empty; i.e. it has 0 entries. + [4:4] + read-write + + + TX_OVERFLOW + Attempt to write to a full TX FIFO. + [5:5] + read-write + + + TX_UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'. + [6:6] + read-write + + + TX_WD + Triggers (sets to '1') when the Tx watchdog event occurs. + [8:8] + read-write + + + RX_TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL. + [16:16] + read-write + + + RX_NOT_EMPTY + RX FIFO is not empty. + [18:18] + read-write + + + RX_FULL + RX FIFO is full. + [19:19] + read-write + + + RX_OVERFLOW + Attempt to write to a full RX FIFO. + [21:21] + read-write + + + RX_UNDERFLOW + Attempt to read from an empty RX FIFO. + [22:22] + read-write + + + RX_WD + Triggers (sets to '1') when the Rx watchdog event occurs. + [24:24] + read-write + + + + + INTR_SET + Interrupt set register + 0xF04 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + TX_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + TX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + TX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + TX_WD + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + RX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FULL + Write with '1' to set corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [22:22] + read-write + + + RX_WD + Write with '1' to set corresponding bit in interrupt request register. + [24:24] + read-write + + + + + INTR_MASK + Interrupt mask register + 0xF08 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + TX_EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + TX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + TX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + TX_WD + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + RX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FULL + Mask bit for corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [22:22] + read-write + + + RX_WD + Mask bit for corresponding bit in interrupt request register. + [24:24] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0xF0C + 32 + read-only + 0x0 + 0x16D0173 + + + TX_TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TX_NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + TX_EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + TX_OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + TX_UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + TX_WD + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + RX_TRIGGER + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + RX_NOT_EMPTY + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + RX_FULL + Logical and of corresponding request and mask bits. + [19:19] + read-only + + + RX_OVERFLOW + Logical and of corresponding request and mask bits. + [21:21] + read-only + + + RX_UNDERFLOW + Logical and of corresponding request and mask bits. + [22:22] + read-only + + + RX_WD + Logical and of corresponding request and mask bits. + [24:24] + read-only + + + + + + + I2S1 + 0x40A11000 + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_03.svd b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_03.svd new file mode 100644 index 0000000000..6736965708 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_03.svd @@ -0,0 +1,44886 @@ + + + + Cypress Semiconductor + Cypress + psoc6_03 + PSoC6_03 + 1.0 + PSoC6_03 + Copyright 2016-2021 Cypress Semiconductor Corporation\n + SPDX-License-Identifier: Apache-2.0\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + CM4 + r0p1 + little + true + true + 1 + 3 + 0 + + 8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERI + Peripheral interconnect + 0x40000000 + + 0 + 65536 + registers + + + + TIMEOUT_CTL + Timeout control + 0x200 + 32 + read-write + 0xFFFF + 0xFFFF + + + TIMEOUT + This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). +'0x0000'-'0xfffe': Number of clock cycles. +'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. + [15:0] + read-write + + + + + TR_CMD + Trigger command + 0x220 + 32 + read-write + 0x0 + 0xE0001FFF + + + TR_SEL + Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. + [7:0] + read-write + + + GROUP_SEL + Specifies the trigger group: +'0'-'15': trigger multiplexer groups. +'16'-'31': trigger 1-to-1 groups. + [12:8] + read-write + + + TR_EDGE + Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. +'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. + [29:29] + read-write + + + OUT_SEL + Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. +'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. +'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. + +Note: this field is not used for trigger 1-to-1 groups. + [30:30] + read-write + + + ACTIVATE + SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. + +Note: when ACTIVATE is '1', SW should not modify the other register fields. + [31:31] + read-write + + + + + DIV_CMD + Divider command + 0x400 + 32 + read-write + 0x3FF03FF + 0xC3FF03FF + + + DIV_SEL + (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. + [7:0] + read-write + + + TYPE_SEL + Specifies the divider type of the divider on which the command is performed: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + PA_DIV_SEL + (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. + +If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. + [23:16] + read-write + + + PA_TYPE_SEL + Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [25:24] + read-write + + + DISABLE + Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. + +The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. + [30:30] + read-write + + + ENABLE + Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the DIV_CMD.DISABLE field. +1: Configure the divider's DIV_XXX_CTL register. +2: Enable the divider using the DIV_CMD_ENABLE field. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. + +The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. + +The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. + [31:31] + read-write + + + + + 256 + 4 + CLOCK_CTL[%s] + Clock control + 0xC00 + 32 + read-write + 0x3FF + 0x3FF + + + DIV_SEL + Specifies one of the dividers of the divider type specified by TYPE_SEL. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. + +When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. + [7:0] + read-write + + + TYPE_SEL + Specifies divider type: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + + + 256 + 4 + DIV_8_CTL[%s] + Divider control (for 8.0 divider) + 0x1000 + 32 + read-write + 0x0 + 0xFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT8_DIV + Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 256]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + 256 + 4 + DIV_16_CTL[%s] + Divider control (for 16.0 divider) + 0x1400 + 32 + read-write + 0x0 + 0xFFFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 256 + 4 + DIV_16_5_CTL[%s] + Divider control (for 16.5 divider) + 0x1800 + 32 + read-write + 0x0 + 0xFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. + +For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 255 + 4 + DIV_24_5_CTL[%s] + Divider control (for 24.5 divider) + 0x1C00 + 32 + read-write + 0x0 + 0xFFFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT24_DIV + Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. + +For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [31:8] + read-write + + + + + ECC_CTL + ECC control + 0x2000 + 32 + read-write + 0x10000 + 0xFF0507FF + + + WORD_ADDR + Specifies the word address where the parity is injected. +- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [10:0] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_INJ_EN + Enable error injection for PERI protection structure SRAM. +When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. + [18:18] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:24] + read-write + + + + + 10 + 32 + GR[%s] + Peripheral group structure + 0x00004000 + + CLOCK_CTL + Clock control + 0x0 + 32 + read-write + 0x0 + 0xFF00 + + + INT8_DIV + Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + SL_CTL + Slave control + 0x10 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ENABLED_0 + Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [0:0] + read-write + + + ENABLED_1 + Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [1:1] + read-write + + + ENABLED_2 + N/A + [2:2] + read-write + + + ENABLED_3 + N/A + [3:3] + read-write + + + ENABLED_4 + N/A + [4:4] + read-write + + + ENABLED_5 + N/A + [5:5] + read-write + + + ENABLED_6 + N/A + [6:6] + read-write + + + ENABLED_7 + N/A + [7:7] + read-write + + + ENABLED_8 + N/A + [8:8] + read-write + + + ENABLED_9 + N/A + [9:9] + read-write + + + ENABLED_10 + N/A + [10:10] + read-write + + + ENABLED_11 + N/A + [11:11] + read-write + + + ENABLED_12 + N/A + [12:12] + read-write + + + ENABLED_13 + N/A + [13:13] + read-write + + + ENABLED_14 + N/A + [14:14] + read-write + + + ENABLED_15 + N/A + [15:15] + read-write + + + DISABLED_0 + Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. + [16:16] + read-write + + + DISABLED_1 + N/A + [17:17] + read-write + + + DISABLED_2 + N/A + [18:18] + read-write + + + DISABLED_3 + N/A + [19:19] + read-write + + + DISABLED_4 + N/A + [20:20] + read-write + + + DISABLED_5 + N/A + [21:21] + read-write + + + DISABLED_6 + N/A + [22:22] + read-write + + + DISABLED_7 + N/A + [23:23] + read-write + + + DISABLED_8 + N/A + [24:24] + read-write + + + DISABLED_9 + N/A + [25:25] + read-write + + + DISABLED_10 + N/A + [26:26] + read-write + + + DISABLED_11 + N/A + [27:27] + read-write + + + DISABLED_12 + N/A + [28:28] + read-write + + + DISABLED_13 + N/A + [29:29] + read-write + + + DISABLED_14 + N/A + [30:30] + read-write + + + DISABLED_15 + N/A + [31:31] + read-write + + + + + + 11 + 1024 + TR_GR[%s] + Trigger group + 0x00008000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x13FF + + + TR_SEL + Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. + [7:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + 8 + 1024 + TR_1TO1_GR[%s] + Trigger 1-to-1 group + 0x0000C000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x1301 + + + TR_SEL + Specifies input trigger: +'0'': constant signal level '0'. +'1': input trigger. + [0:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + + + PERI_MS + Peripheral interconnect, master interface + 0x40010000 + + 0 + 65536 + registers + + + + 8 + 64 + PPU_PR[%s] + Programmable protection structure pair + 0x00000000 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-write + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-write + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + 221 + 64 + PPU_FX[%s] + Fixed protection structure pair + 0x00000800 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFC + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-only + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-only + 0x80000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-only + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-only + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + + + CPUSS + CPU subsystem (CPUSS) + 0x40200000 + + 0 + 65536 + registers + + + ioss_interrupts_gpio_0 + GPIO Port Interrupt #0 + 0 + + + ioss_interrupts_gpio_2 + GPIO Port Interrupt #2 + 2 + + + ioss_interrupts_gpio_3 + GPIO Port Interrupt #3 + 3 + + + ioss_interrupts_gpio_5 + GPIO Port Interrupt #5 + 5 + + + ioss_interrupts_gpio_6 + GPIO Port Interrupt #6 + 6 + + + ioss_interrupts_gpio_7 + GPIO Port Interrupt #7 + 7 + + + ioss_interrupts_gpio_8 + GPIO Port Interrupt #8 + 8 + + + ioss_interrupts_gpio_9 + GPIO Port Interrupt #9 + 9 + + + ioss_interrupts_gpio_10 + GPIO Port Interrupt #10 + 10 + + + ioss_interrupts_gpio_11 + GPIO Port Interrupt #11 + 11 + + + ioss_interrupts_gpio_12 + GPIO Port Interrupt #12 + 12 + + + ioss_interrupts_gpio_14 + GPIO Port Interrupt #14 + 14 + + + ioss_interrupt_gpio + GPIO All Ports + 15 + + + ioss_interrupt_vdd + GPIO Supply Detect Interrupt + 16 + + + lpcomp_interrupt + Low Power Comparator Interrupt + 17 + + + scb_6_interrupt + Serial Communication Block #6 (DeepSleep capable) + 18 + + + srss_interrupt_mcwdt_0 + Multi Counter Watchdog Timer interrupt + 19 + + + srss_interrupt_mcwdt_1 + Multi Counter Watchdog Timer interrupt + 20 + + + srss_interrupt_backup + Backup domain interrupt + 21 + + + srss_interrupt + Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + 22 + + + cpuss_interrupts_ipc_0 + CPUSS Inter Process Communication Interrupt #0 + 23 + + + cpuss_interrupts_ipc_1 + CPUSS Inter Process Communication Interrupt #1 + 24 + + + cpuss_interrupts_ipc_2 + CPUSS Inter Process Communication Interrupt #2 + 25 + + + cpuss_interrupts_ipc_3 + CPUSS Inter Process Communication Interrupt #3 + 26 + + + cpuss_interrupts_ipc_4 + CPUSS Inter Process Communication Interrupt #4 + 27 + + + cpuss_interrupts_ipc_5 + CPUSS Inter Process Communication Interrupt #5 + 28 + + + cpuss_interrupts_ipc_6 + CPUSS Inter Process Communication Interrupt #6 + 29 + + + cpuss_interrupts_ipc_7 + CPUSS Inter Process Communication Interrupt #7 + 30 + + + cpuss_interrupts_ipc_8 + CPUSS Inter Process Communication Interrupt #8 + 31 + + + cpuss_interrupts_ipc_9 + CPUSS Inter Process Communication Interrupt #9 + 32 + + + cpuss_interrupts_ipc_10 + CPUSS Inter Process Communication Interrupt #10 + 33 + + + cpuss_interrupts_ipc_11 + CPUSS Inter Process Communication Interrupt #11 + 34 + + + cpuss_interrupts_ipc_12 + CPUSS Inter Process Communication Interrupt #12 + 35 + + + cpuss_interrupts_ipc_13 + CPUSS Inter Process Communication Interrupt #13 + 36 + + + cpuss_interrupts_ipc_14 + CPUSS Inter Process Communication Interrupt #14 + 37 + + + cpuss_interrupts_ipc_15 + CPUSS Inter Process Communication Interrupt #15 + 38 + + + scb_0_interrupt + Serial Communication Block #0 + 39 + + + scb_1_interrupt + Serial Communication Block #1 + 40 + + + scb_2_interrupt + Serial Communication Block #2 + 41 + + + scb_3_interrupt + Serial Communication Block #3 + 42 + + + scb_4_interrupt + Serial Communication Block #4 + 43 + + + scb_5_interrupt + Serial Communication Block #5 + 44 + + + csd_interrupt + CSD (Capsense) interrupt + 51 + + + cpuss_interrupts_dmac_0 + CPUSS DMAC, Channel #0 + 52 + + + cpuss_interrupts_dmac_1 + CPUSS DMAC, Channel #1 + 53 + + + cpuss_interrupts_dw0_0 + CPUSS DataWire #0, Channel #0 + 56 + + + cpuss_interrupts_dw0_1 + CPUSS DataWire #0, Channel #1 + 57 + + + cpuss_interrupts_dw0_2 + CPUSS DataWire #0, Channel #2 + 58 + + + cpuss_interrupts_dw0_3 + CPUSS DataWire #0, Channel #3 + 59 + + + cpuss_interrupts_dw0_4 + CPUSS DataWire #0, Channel #4 + 60 + + + cpuss_interrupts_dw0_5 + CPUSS DataWire #0, Channel #5 + 61 + + + cpuss_interrupts_dw0_6 + CPUSS DataWire #0, Channel #6 + 62 + + + cpuss_interrupts_dw0_7 + CPUSS DataWire #0, Channel #7 + 63 + + + cpuss_interrupts_dw0_8 + CPUSS DataWire #0, Channel #8 + 64 + + + cpuss_interrupts_dw0_9 + CPUSS DataWire #0, Channel #9 + 65 + + + cpuss_interrupts_dw0_10 + CPUSS DataWire #0, Channel #10 + 66 + + + cpuss_interrupts_dw0_11 + CPUSS DataWire #0, Channel #11 + 67 + + + cpuss_interrupts_dw0_12 + CPUSS DataWire #0, Channel #12 + 68 + + + cpuss_interrupts_dw0_13 + CPUSS DataWire #0, Channel #13 + 69 + + + cpuss_interrupts_dw0_14 + CPUSS DataWire #0, Channel #14 + 70 + + + cpuss_interrupts_dw0_15 + CPUSS DataWire #0, Channel #15 + 71 + + + cpuss_interrupts_dw0_16 + CPUSS DataWire #0, Channel #16 + 72 + + + cpuss_interrupts_dw0_17 + CPUSS DataWire #0, Channel #17 + 73 + + + cpuss_interrupts_dw0_18 + CPUSS DataWire #0, Channel #18 + 74 + + + cpuss_interrupts_dw0_19 + CPUSS DataWire #0, Channel #19 + 75 + + + cpuss_interrupts_dw0_20 + CPUSS DataWire #0, Channel #20 + 76 + + + cpuss_interrupts_dw0_21 + CPUSS DataWire #0, Channel #21 + 77 + + + cpuss_interrupts_dw0_22 + CPUSS DataWire #0, Channel #22 + 78 + + + cpuss_interrupts_dw0_23 + CPUSS DataWire #0, Channel #23 + 79 + + + cpuss_interrupts_dw0_24 + CPUSS DataWire #0, Channel #24 + 80 + + + cpuss_interrupts_dw0_25 + CPUSS DataWire #0, Channel #25 + 81 + + + cpuss_interrupts_dw0_26 + CPUSS DataWire #0, Channel #26 + 82 + + + cpuss_interrupts_dw0_27 + CPUSS DataWire #0, Channel #27 + 83 + + + cpuss_interrupts_dw0_28 + CPUSS DataWire #0, Channel #28 + 84 + + + cpuss_interrupts_dw1_0 + CPUSS DataWire #1, Channel #0 + 85 + + + cpuss_interrupts_dw1_1 + CPUSS DataWire #1, Channel #1 + 86 + + + cpuss_interrupts_dw1_2 + CPUSS DataWire #1, Channel #2 + 87 + + + cpuss_interrupts_dw1_3 + CPUSS DataWire #1, Channel #3 + 88 + + + cpuss_interrupts_dw1_4 + CPUSS DataWire #1, Channel #4 + 89 + + + cpuss_interrupts_dw1_5 + CPUSS DataWire #1, Channel #5 + 90 + + + cpuss_interrupts_dw1_6 + CPUSS DataWire #1, Channel #6 + 91 + + + cpuss_interrupts_dw1_7 + CPUSS DataWire #1, Channel #7 + 92 + + + cpuss_interrupts_dw1_8 + CPUSS DataWire #1, Channel #8 + 93 + + + cpuss_interrupts_dw1_9 + CPUSS DataWire #1, Channel #9 + 94 + + + cpuss_interrupts_dw1_10 + CPUSS DataWire #1, Channel #10 + 95 + + + cpuss_interrupts_dw1_11 + CPUSS DataWire #1, Channel #11 + 96 + + + cpuss_interrupts_dw1_12 + CPUSS DataWire #1, Channel #12 + 97 + + + cpuss_interrupts_dw1_13 + CPUSS DataWire #1, Channel #13 + 98 + + + cpuss_interrupts_dw1_14 + CPUSS DataWire #1, Channel #14 + 99 + + + cpuss_interrupts_dw1_15 + CPUSS DataWire #1, Channel #15 + 100 + + + cpuss_interrupts_dw1_16 + CPUSS DataWire #1, Channel #16 + 101 + + + cpuss_interrupts_dw1_17 + CPUSS DataWire #1, Channel #17 + 102 + + + cpuss_interrupts_dw1_18 + CPUSS DataWire #1, Channel #18 + 103 + + + cpuss_interrupts_dw1_19 + CPUSS DataWire #1, Channel #19 + 104 + + + cpuss_interrupts_dw1_20 + CPUSS DataWire #1, Channel #20 + 105 + + + cpuss_interrupts_dw1_21 + CPUSS DataWire #1, Channel #21 + 106 + + + cpuss_interrupts_dw1_22 + CPUSS DataWire #1, Channel #22 + 107 + + + cpuss_interrupts_dw1_23 + CPUSS DataWire #1, Channel #23 + 108 + + + cpuss_interrupts_dw1_24 + CPUSS DataWire #1, Channel #24 + 109 + + + cpuss_interrupts_dw1_25 + CPUSS DataWire #1, Channel #25 + 110 + + + cpuss_interrupts_dw1_26 + CPUSS DataWire #1, Channel #26 + 111 + + + cpuss_interrupts_dw1_27 + CPUSS DataWire #1, Channel #27 + 112 + + + cpuss_interrupts_dw1_28 + CPUSS DataWire #1, Channel #28 + 113 + + + cpuss_interrupts_fault_0 + CPUSS Fault Structure Interrupt #0 + 114 + + + cpuss_interrupts_fault_1 + CPUSS Fault Structure Interrupt #1 + 115 + + + cpuss_interrupt_crypto + CRYPTO Accelerator Interrupt + 116 + + + cpuss_interrupt_fm + FLASH Macro Interrupt + 117 + + + cpuss_interrupts_cm4_fp + Floating Point operation fault + 118 + + + cpuss_interrupts_cm0_cti_0 + CM0+ CTI #0 + 119 + + + cpuss_interrupts_cm0_cti_1 + CM0+ CTI #1 + 120 + + + cpuss_interrupts_cm4_cti_0 + CM4 CTI #0 + 121 + + + cpuss_interrupts_cm4_cti_1 + CM4 CTI #1 + 122 + + + tcpwm_0_interrupts_0 + TCPWM #0, Counter #0 + 123 + + + tcpwm_0_interrupts_1 + TCPWM #0, Counter #1 + 124 + + + tcpwm_0_interrupts_2 + TCPWM #0, Counter #2 + 125 + + + tcpwm_0_interrupts_3 + TCPWM #0, Counter #3 + 126 + + + tcpwm_1_interrupts_0 + TCPWM #1, Counter #0 + 131 + + + tcpwm_1_interrupts_1 + TCPWM #1, Counter #1 + 132 + + + tcpwm_1_interrupts_2 + TCPWM #1, Counter #2 + 133 + + + tcpwm_1_interrupts_3 + TCPWM #1, Counter #3 + 134 + + + tcpwm_1_interrupts_4 + TCPWM #1, Counter #4 + 135 + + + tcpwm_1_interrupts_5 + TCPWM #1, Counter #5 + 136 + + + tcpwm_1_interrupts_6 + TCPWM #1, Counter #6 + 137 + + + tcpwm_1_interrupts_7 + TCPWM #1, Counter #7 + 138 + + + pass_interrupt_sar + SAR ADC interrupt + 155 + + + smif_interrupt + Serial Memory Interface interrupt + 160 + + + usb_interrupt_hi + USB Interrupt + 161 + + + usb_interrupt_med + USB Interrupt + 162 + + + usb_interrupt_lo + USB Interrupt + 163 + + + sdhc_0_interrupt_wakeup + SDIO wakeup interrupt for mxsdhc + 164 + + + sdhc_0_interrupt_general + Consolidated interrupt for mxsdhc for everything else + 165 + + + canfd_0_interrupt0 + Can #0, Consolidated interrupt #0 + 168 + + + canfd_0_interrupts0_0 + CAN #0, Interrupt #0, Channel #0 + 169 + + + canfd_0_interrupts1_0 + CAN #0, Interrupt #1, Channel #0 + 170 + + + cpuss_interrupts_dw1_29 + CPUSS DataWire #1, Channel #29 + 171 + + + cpuss_interrupts_dw1_30 + CPUSS DataWire #1, Channel #30 + 172 + + + cpuss_interrupts_dw1_31 + CPUSS DataWire #1, Channel #31 + 173 + + + + IDENTITY + Identity + 0x0 + 32 + read-only + 0x0 + 0x0 + + + P + This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. + [0:0] + read-only + + + NS + This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. + [1:1] + read-only + + + PC + This field specifies the protection context of the transfer that reads the register. + [7:4] + read-only + + + MS + This field specifies the bus master identifier of the transfer that reads the register. + [11:8] + read-only + + + + + CM4_STATUS + CM4 status + 0x4 + 32 + read-only + 0x13 + 0x13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + + + CM4_CLOCK_CTL + CM4 clock control + 0x8 + 32 + read-write + 0x0 + 0xFF00 + + + FAST_INT_DIV + Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM4_CTL + CM4 control + 0xC + 32 + read-write + 0x0 + 0x9F000000 + + + IOC_MASK + CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. + +Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. + +Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. + [24:24] + read-write + + + DZC_MASK + CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [25:25] + read-write + + + OFC_MASK + CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [26:26] + read-write + + + UFC_MASK + CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [27:27] + read-write + + + IXC_MASK + CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. + [28:28] + read-write + + + IDC_MASK + CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. + [31:31] + read-write + + + + + CM4_INT0_STATUS + CM4 interrupt 0 status + 0x100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 0. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT1_STATUS + CM4 interrupt 1 status + 0x104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT2_STATUS + CM4 interrupt 2 status + 0x108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT3_STATUS + CM4 interrupt 3 status + 0x10C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT4_STATUS + CM4 interrupt 4 status + 0x110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT5_STATUS + CM4 interrupt 5 status + 0x114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT6_STATUS + CM4 interrupt 6 status + 0x118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT7_STATUS + CM4 interrupt 7 status + 0x11C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_VECTOR_TABLE_BASE + CM4 vector table base + 0x200 + 32 + read-write + 0x0 + 0xFFFFFC00 + + + ADDR22 + Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. + +Note: the CM4 vector table is at an address that is a 1024 B multiple. + [31:10] + read-write + + + + + 4 + 4 + CM4_NMI_CTL[%s] + CM4 NMI control + 0x240 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + UDB_PWR_CTL + UDB power control + 0x300 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for UDBs + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RESET + See CM4_PWR_CTL + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + UDB_PWR_DELAY_CTL + UDB power control + 0x304 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CTL + CM0+ control + 0x1000 + 32 + read-write + 0xFA050002 + 0xFFFF0003 + + + SLV_STALL + Processor debug access control: +'0': Access. +'1': Stall access. + +This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. + [0:0] + read-write + + + ENABLED + Processor enable: +'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. +'1': Enabled. +Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). + +Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). + [1:1] + read-write + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_STATUS + CM0+ status + 0x1004 + 32 + read-only + 0x0 + 0x3 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + + + CM0_CLOCK_CTL + CM0+ clock control + 0x1008 + 32 + read-write + 0x0 + 0xFF00FF00 + + + SLOW_INT_DIV + Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + PERI_INT_DIV + Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + +Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. + [31:24] + read-write + + + + + CM0_INT0_STATUS + CM0+ interrupt 0 status + 0x1100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 0. + +Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). + +The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. + [9:0] + read-only + + + SYSTEM_INT_VALID + Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. + [31:31] + read-only + + + + + CM0_INT1_STATUS + CM0+ interrupt 1 status + 0x1104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT2_STATUS + CM0+ interrupt 2 status + 0x1108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT3_STATUS + CM0+ interrupt 3 status + 0x110C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT4_STATUS + CM0+ interrupt 4 status + 0x1110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT5_STATUS + CM0+ interrupt 5 status + 0x1114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT6_STATUS + CM0+ interrupt 6 status + 0x1118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT7_STATUS + CM0+ interrupt 7 status + 0x111C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_VECTOR_TABLE_BASE + CM0+ vector table base + 0x1120 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. + +Note: the CM0+ vector table is at an address that is a 256 B multiple. + [31:8] + read-write + + + + + 4 + 4 + CM0_NMI_CTL[%s] + CM0+ NMI control + 0x1140 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + CM4_PWR_CTL + CM4 power control + 0x1200 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Switch CM4 off +Power off, clock off, isolate, reset and no retain. + 0 + + + RESET + Reset CM4 +Clock off, no isolated, no retain and reset. + +Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. + 1 + + + RETAINED + Put CM4 in Retained mode +This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. +Power off, clock off, isolate, no reset and retain. + 2 + + + ENABLED + Switch CM4 on. +Power on, clock on, no isolate, no reset and no retain. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM4_PWR_DELAY_CTL + CM4 power control + 0x1204 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + RAM0_CTL0 + RAM 0 control + 0x1300 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_AUTO_CORRECT + HW ECC autocorrect functionality: +'0': Disabled. +'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. + [17:17] + read-write + + + ECC_INJ_EN + Enable error injection for system SRAM 0. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. + [18:18] + read-write + + + + + RAM0_STATUS + RAM 0 status + 0x1304 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. +'0': Write buffer NOT empty. +'1': Write buffer empty. + +Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). + [0:0] + read-only + + + + + 16 + 4 + RAM0_PWR_MACRO_CTL[%s] + RAM 0 power control + 0x1340 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + SRAM Power mode. + [1:0] + read-write + + + OFF + Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. + 0 + + + RSVD + undefined + 1 + + + RETAINED + Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. +The SRAM contents will be retained in DeepSleep system power mode. + 2 + + + ENABLED + Enable SRAM for regular operation. +The SRAM contents will be retained in DeepSleep system power mode. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + RAM1_CTL0 + RAM 1 control + 0x1380 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM1_STATUS + RAM 1 status + 0x1384 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM1_PWR_CTL + RAM 1 power control + 0x1388 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM2_CTL0 + RAM 2 control + 0x13A0 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM2_STATUS + RAM 2 status + 0x13A4 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM2_PWR_CTL + RAM 2 power control + 0x13A8 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM_PWR_DELAY_CTL + Power up delay used for all SRAM power domains + 0x13C0 + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles (clk_slow) delay needed after power domain power up + [9:0] + read-write + + + + + ROM_CTL + ROM control + 0x13C4 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + +Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. +ROM_CTL.SLOW_WS = '0' when clk_hf <=100 MHz. +ROM_CTL.SLOW_WS = '1' when 100MHz < clk_hf <=clk_hf_max. +Note: clk_hf_max depends on the target device. Refer datasheet. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. +ROM_CTL.FAST_WS = '0' when clk_hf <= clk_hf_max. + [9:8] + read-write + + + + + ECC_CTL + ECC control + 0x13C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. +This field needs to be written with the offset address within the memory, divided by 4. +For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. + [24:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + PRODUCT_ID + Product identifier and version (same as CoreSight RomTables) + 0x1400 + 32 + read-only + 0x0 + 0xFFF + + + FAMILY_ID + Family ID. Common ID for a product family. + [11:0] + read-only + + + MAJOR_REV + Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) + [19:16] + read-only + + + MINOR_REV + Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) + [23:20] + read-only + + + + + DP_STATUS + Debug port status + 0x1410 + 32 + read-only + 0x4 + 0x7 + + + SWJ_CONNECTED + Specifies if the SWJ debug port is connected; i.e. debug host interface is active: +'0': Not connected/not active. +'1': Connected/active. + [0:0] + read-only + + + SWJ_DEBUG_EN + Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: +'0': Disabled. +'1': Enabled. + [1:1] + read-only + + + SWJ_JTAG_SEL + Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). +'0': SWD selected. +'1': JTAG selected. + [2:2] + read-only + + + + + AP_CTL + Access port control + 0x1414 + 32 + read-write + 0x0 + 0x70007 + + + CM0_ENABLE + Enables the CM0 AP interface: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + CM4_ENABLE + Enables the CM4 AP interface: +'0': Disabled. +'1': Enabled. + [1:1] + read-write + + + SYS_ENABLE + Enables the system AP interface: +'0': Disabled. +'1': Enabled. + [2:2] + read-write + + + CM0_DISABLE + Disables the CM0 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. + [16:16] + read-write + + + CM4_DISABLE + Disables the CM4 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. + [17:17] + read-write + + + SYS_DISABLE + Disables the system AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. + [18:18] + read-write + + + + + BUFF_CTL + Buffer control + 0x1500 + 32 + read-write + 0x1 + 0x1 + + + WRITE_BUFF + Specifies if write transfer can be buffered in the bus infrastructure bridges: +'0': Write transfers are not buffered, independent of the transfer's bufferable attribute. +'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. + [0:0] + read-write + + + + + SYSTICK_CTL + SysTick timer control + 0x1600 + 32 + read-write + 0x40000147 + 0xC3FFFFFF + + + TENMS + Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. + [23:0] + read-write + + + CLOCK_SOURCE + Specifies an external clock source: +'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). +'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. +o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. +'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). + +Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. +Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. + [25:24] + read-write + + + SKEW + Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: +'0': Precise. +'1': Imprecise. + [30:30] + read-write + + + NOREF + Specifies if an external clock source is provided: +'0': An external clock source is provided. +'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. + [31:31] + read-write + + + + + MBIST_STAT + Memory BIST status + 0x1704 + 32 + read-only + 0x0 + 0x3 + + + SFP_READY + Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. + [0:0] + read-only + + + SFP_FAIL + Report status of the BIST run, only valid if SFP_READY=1 + [1:1] + read-only + + + + + CAL_SUP_SET + Calibration support set and read + 0x1800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read without side effect, write 1 to set + [31:0] + read-write + + + + + CAL_SUP_CLR + Calibration support clear and reset + 0x1804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read side effect: when read all bits are cleared, write 1 to clear a specific bit +Note: no exception for the debug host, it also causes the read side effect + [31:0] + read-write + + + + + CM0_PC_CTL + CM0+ protection context control + 0x2000 + 32 + read-write + 0x0 + 0xF + + + VALID + Valid fields for the protection context handler CM0_PCi_HANDLER registers: +Bit 0: Valid field for CM0_PC0_HANDLER. +Bit 1: Valid field for CM0_PC1_HANDLER. +Bit 2: Valid field for CM0_PC2_HANDLER. +Bit 3: Valid field for CM0_PC3_HANDLER. + [3:0] + read-write + + + + + CM0_PC0_HANDLER + CM0+ protection context 0 handler + 0x2040 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. + [31:0] + read-write + + + + + CM0_PC1_HANDLER + CM0+ protection context 1 handler + 0x2044 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 1 handler. + [31:0] + read-write + + + + + CM0_PC2_HANDLER + CM0+ protection context 2 handler + 0x2048 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 2 handler. + [31:0] + read-write + + + + + CM0_PC3_HANDLER + CM0+ protection context 3 handler + 0x204C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 3 handler. + [31:0] + read-write + + + + + PROTECTION + Protection status + 0x20C4 + 32 + read-write + 0x0 + 0x7 + + + STATE + Protection state: +'0': UNKNOWN. +'1': VIRGIN. +'2': NORMAL. +'3': SECURE. +'4': DEAD. + +The following state transitions are allowed (and enforced by HW): +- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD +- NORMAL => DEAD +- SECURE => DEAD +An attempt to make a NOT allowed state transition will NOT affect this register field. + [2:0] + read-write + + + + + TRIM_ROM_CTL + ROM trim control + 0x2100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + TRIM_RAM_CTL + RAM trim control + 0x2104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + 1023 + 4 + CM0_SYSTEM_INT_CTL[%s] + CM0+ system interrupt control + 0x8000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. + +Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. + [2:0] + read-write + + + CPU_INT_VALID + Interrupt enable: +'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. +'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. + +Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. + [31:31] + read-write + + + + + 1023 + 4 + CM4_SYSTEM_INT_CTL[%s] + CM4 system interrupt control + 0xA000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + N/A + [2:0] + read-write + + + CPU_INT_VALID + N/A + [31:31] + read-write + + + + + + + FAULT + Fault structures + 0x40210000 + + 0 + 65536 + registers + + + + 2 + 256 + STRUCT[%s] + Fault structure + 0x00000000 + + CTL + Fault control + 0x0 + 32 + read-write + 0x0 + 0x7 + + + TR_EN + Trigger output enable: +'0': Disabled. The trigger output 'tr_fault' is '0'. +'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). + [0:0] + read-write + + + OUT_EN + IO output signal enable: +'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. +'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. + [1:1] + read-write + + + RESET_REQ_EN + Reset request enable: +'0': Disabled. +'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). + +The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. + [2:2] + read-write + + + + + STATUS + Fault status + 0xC + 32 + read-write + 0x0 + 0x80000000 + + + IDX + The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. + +Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. + [6:0] + read-write + + + VALID + Valid indication: +'0': Invalid. +'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. + +Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. + +An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: +- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. + +Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) + [31:31] + read-write + + + + + 4 + 4 + DATA[%s] + Fault data + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + Captured fault source data. + +Note: the DATA registers can only be written when STATUS.VALID is '0'. + +Note: the fault source index STATUS.IDX specifies the format of the DATA registers. + [31:0] + read-write + + + + + PENDING0 + Fault pending 0 + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: CM0 MPU. +Bit 1: CRYPTO MPU. +Bit 2: DW 0 MPU. +Bit 3: DW 1 MPU. +Bit 4: DMA controller MPU. +... +Bit 15: DAP MPU. +Bit 16: CM4 system bus MPU. +Bit 17: CM4 code bus MPU (for non FLASH controller accesses). +Bit 18: CM4 code bus MPU (for FLASH controller accesses). + [31:0] + read-only + + + + + PENDING1 + Fault pending 1 + 0x44 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: Peripheral group 0 PPU. +Bit 1: Peripheral group 1 PPU. +Bit 2: Peripheral group 2 PPU. +Bit 3: Peripheral group 3 PPU. +Bit 4: Peripheral group 4 PPU. +Bit 5: Peripheral group 5 PPU. +Bit 6: Peripheral group 6 PPU. +Bit 7: Peripheral group 7 PPU. +... +Bit 15: Peripheral group 15 PPU. + +Bit 16 - 31: See STATUS register. + [31:0] + read-only + + + + + PENDING2 + Fault pending 2 + 0x48 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0 - 31: See STATUS register. + [31:0] + read-only + + + + + MASK0 + Fault mask 0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 31 to 0. + [31:0] + read-write + + + + + MASK1 + Fault mask 1 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 63 to 32. + [31:0] + read-write + + + + + MASK2 + Fault mask 2 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 95 to 64. + [31:0] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1 + + + FAULT + This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: +- STATUS.VALID is set to '1'. +- STATUS.IDX specifies the fault source index. +- DATA0 through DATA3 captures the fault source data. + +SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1 + + + FAULT + SW writes a '1' to this field to set the corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1 + + + FAULT + Mask bit for corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1 + + + FAULT + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + IPC + IPC + 0x40220000 + + 0 + 65536 + registers + + + + 16 + 32 + STRUCT[%s] + IPC structure + 0x00000000 + + ACQUIRE + IPC acquire + 0x0 + 32 + read-only + 0x0 + 0x80000000 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the access that successfully acquired the lock. + [0:0] + read-only + + + NS + Secure/non-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the access that successfully acquired the lock. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + SUCCESS + Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): +'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. +'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. + +Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). + [31:31] + read-only + + + + + RELEASE + IPC release + 0x4 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_RELEASE + Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. + +SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + NOTIFY + IPC notification + 0x8 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_NOTIFY + This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. + +SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + DATA0 + IPC data 0 + 0xC + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + DATA1 + IPC data 1 + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + LOCK_STATUS + IPC lock status + 0x1C + 32 + read-only + 0x0 + 0x80000000 + + + P + This field specifies the user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + This field specifies the secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + ACQUIRED + Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. + [31:31] + read-only + + + + + + 16 + 32 + INTR_STRUCT[%s] + IPC interrupt structure + 0x00001000 + + INTR + Interrupt + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [15:0] + read-write + + + NOTIFY + These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [31:16] + read-write + + + + + INTR_SET + Interrupt set + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + SW writes a '1' to this field to set the corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASK + Interrupt mask + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + Mask bit for corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RELEASE + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + NOTIFY + Logical and of corresponding INTR and INTR_MASK fields. + [31:16] + read-only + + + + + + + + PROT + Protection + 0x40230000 + + 0 + 65536 + registers + + + + SMPU + SMPU + 0x00000000 + + MS0_CTL + Master 0 protection context control + 0x0 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + Privileged setting ('0': user mode; '1': privileged mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. +The default/reset field value provides privileged mode access capabilities. + [0:0] + read-write + + + NS + Security setting ('0': secure mode; '1': non-secure mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. +Note that the default/reset field value provides non-secure mode access capabilities to all masters. + [1:1] + read-write + + + PRIO + Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). + +Notes: +The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). +The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). +Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. + [9:8] + read-write + + + PC_MASK_0 + Protection context mask for protection context '0'. This field is a constant '0': +- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. + [16:16] + read-only + + + PC_MASK_15_TO_1 + Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': +- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. +- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. + +Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). + [31:17] + read-write + + + + + MS1_CTL + Master 1 protection context control + 0x4 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS2_CTL + Master 2 protection context control + 0x8 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS3_CTL + Master 3 protection context control + 0xC + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS4_CTL + Master 4 protection context control + 0x10 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS5_CTL + Master 5 protection context control + 0x14 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS6_CTL + Master 6 protection context control + 0x18 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS7_CTL + Master 7 protection context control + 0x1C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS8_CTL + Master 8 protection context control + 0x20 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS9_CTL + Master 9 protection context control + 0x24 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS10_CTL + Master 10 protection context control + 0x28 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS11_CTL + Master 11 protection context control + 0x2C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS12_CTL + Master 12 protection context control + 0x30 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS13_CTL + Master 13 protection context control + 0x34 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS14_CTL + Master 14 protection context control + 0x38 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS15_CTL + Master 15 protection context control + 0x3C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + 16 + 64 + SMPU_STRUCT[%s] + SMPU structure + 0x00002000 + + ADDR0 + SMPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + SMPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x100 + 0x80000100 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + SMPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + SMPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'7': 256 B region (8 32 B subregions) + +Note: this field is read-only. + [28:24] + read-only + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + [31:31] + read-write + + + + + + + 16 + 1024 + MPU[%s] + MPU + 0x00004000 + + MS_CTL + Master control + 0x0 + 32 + read-write + 0x0 + 0xF000F + + + PC + Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). + +The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: +* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: + IF (the new PC is the same as MS_CTL.PC) + PC is not affected; PC_SAVED is not affected. + ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) + An AHB-Lite bus error is generated for the exception handler fetch; + PC is not affected; PC_SAVED is not affected. + ELSE + PC = 'new PC'; PC_SAVED = PC (push operation). +* On entry of any other exception/interrupt handler: + PC = PC_SAVED; PC_SAVED is not affected (pop operation). + +Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. + +Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. + [3:0] + read-write + + + PC_SAVED + Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. + +Note: this field is ONLY used by the CM0+. + [19:16] + read-write + + + + + 127 + 4 + MS_CTL_READ_MIR[%s] + Master control read mirror + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + PC + Read-only mirror of MS_CTL.PC + [3:0] + read-only + + + PC_SAVED + Read-only mirror of MS_CTL.PC_SAVED + [19:16] + read-only + + + + + 8 + 32 + MPU_STRUCT[%s] + MPU structure + 0x00000200 + + ADDR + MPU region address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT + MPU region attrributes + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + + + + + FLASHC + Flash controller + 0x40240000 + + 0 + 65536 + registers + + + + FLASH_CTL + Control + 0x0 + 32 + read-write + 0x110000 + 0x77330F + + + MAIN_WS + FLASH macro main interface wait states: +'0': 0 wait states. +... +'15': 15 wait states + [3:0] + read-write + + + MAIN_MAP + Specifies mapping of FLASH macro main array. +0: Mapping A. +1: Mapping B. + +This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). + [8:8] + read-write + + + WORK_MAP + Specifies mapping of FLASH macro work array. +0: Mapping A. +1: Mapping B. + +This field is only used when WORK_BANK_MODE is '1' (dual bank mode). + [9:9] + read-write + + + MAIN_BANK_MODE + Specifies bank mode of FLASH macro main array. +0: Single bank mode. +1: Dual bank mode. + [12:12] + read-write + + + WORK_BANK_MODE + Specifies bank mode of FLASH macro work array. +0: Single bank mode. +1: Dual bank mode. + [13:13] + read-write + + + MAIN_ECC_EN + Enable ECC checking for FLASH main interface: +0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [16:16] + read-write + + + MAIN_ECC_INJ_EN + Enable error injection for FLASH main interface. +When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [17:17] + read-write + + + MAIN_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro main interface internal error. +- FLASH macro main interface non-recoverable ECC error. +- FLASH macro main interface recoverable ECC error. +- FLASH macro main interface memory hole error. + [18:18] + read-write + + + WORK_ECC_EN + Enable ECC checking for FLASH work interface: +0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [20:20] + read-write + + + WORK_ECC_INJ_EN + Enable error injection for FLASH work interface. +When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [21:21] + read-write + + + WORK_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro work interface internal error. +- FLASH macro work interface non-recoverable ECC error. +- FLASH macro work interface recoverable ECC error. +- FLASH macro work interface memory hole error. + [22:22] + read-write + + + + + FLASH_PWR_CTL + Flash power control + 0x4 + 32 + read-write + 0x3 + 0x3 + + + ENABLE + Controls 'enable' pin of the Flash memory. + [0:0] + read-write + + + ENABLE_HV + Controls 'enable_hv' pin of the Flash memory. + [1:1] + read-write + + + + + FLASH_CMD + Command + 0x8 + 32 + read-write + 0x0 + 0x3 + + + INV + Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. + [0:0] + read-write + + + BUFF_INV + Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. + +Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. + [1:1] + read-write + + + + + ECC_CTL + ECC control + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. +- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). +- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). + [23:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. +- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. +- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. +- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. + [31:24] + read-write + + + + + FM_SRAM_ECC_CTL0 + eCT Flash SRAM ECC control 0 + 0x2B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ECC_INJ_DATA + 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. + [31:0] + read-write + + + + + FM_SRAM_ECC_CTL1 + eCT Flash SRAM ECC control 1 + 0x2B4 + 32 + read-write + 0x0 + 0x7F + + + ECC_INJ_PARITY + 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. + [6:0] + read-write + + + + + FM_SRAM_ECC_CTL2 + eCT Flash SRAM ECC control 2 + 0x2B8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CORRECTED_DATA + 32-bit corrected data output of the ECC syndrome logic. + [31:0] + read-only + + + + + FM_SRAM_ECC_CTL3 + eCT Flash SRAM ECC control 3 + 0x2BC + 32 + read-write + 0x1 + 0x111 + + + ECC_ENABLE + ECC generation/check enable for eCT Flash SRAM memory. + [0:0] + read-write + + + ECC_INJ_EN + eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: +1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. +2. Set the ECC_INJ_EN bit to '1'. +3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. +4. Check the corrected data in FM_SRAM_ECC_CTL2. +5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if +corrupted data was written in step 1). +6. If not finished, start over at 1 with different data. + [4:4] + read-write + + + ECC_TEST_FAIL + Status of ECC test. +1 : ECC test failed because eCT Flash macro is busy and using the SRAM. +0: ECC was performed. + [8:8] + read-only + + + + + CM0_CA_CTL0 + CM0+ cache control + 0x400 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + Enable ECC checking for cache accesses: +0: Disabled. +1: Enabled. + [0:0] + read-write + + + RAM_ECC_INJ_EN + Enable error injection for cache. +When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. + [1:1] + read-write + + + WAY + Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. + [26:24] + read-write + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + CA_EN + Cache enable: +0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). +1: Enabled. + [31:31] + read-write + + + + + CM0_CA_CTL1 + CM0+ cache control + 0x404 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM0 cache. +The following sequnece should be followed for turning OFF/ON the cache SRAM. +Turn OFF sequence: +a) Write CM0_CA_CTL0 to disable cache. +b) Write CM0_CA_CTL1 to turn OFF cache SRAM. +Turn ON sequence: +a) Write CM0_CA_CTL1 to turn ON cache SRAM. +b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. +c) Write CM0_CA_CTL0 to enable cache. + [1:0] + read-write + + + OFF + Power OFF the CM0 cache SRAM. + 0 + + + RSVD + Undefined + 1 + + + RETAINED + Put CM0 cache SRAM in retained mode. + 2 + + + ENABLED + Enable/Turn ON the CM0 cache SRAM. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_CA_CTL2 + CM0+ cache control + 0x408 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CA_STATUS0 + CM0+ cache status 0 + 0x440 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS1 + CM0+ cache status 1 + 0x444 + 32 + read-only + 0x0 + 0x0 + + + TAG + Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS2 + CM0+ cache status 2 + 0x448 + 32 + read-only + 0x0 + 0x0 + + + LRU + Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): +Bit 5: 0_LRU_1: way 0 less recently used than way 1. +Bit 4: 0_LRU_2. +Bit 3: 0_LRU_3. +Bit 2: 1_LRU_2. +Bit 1: 1_LRU_3. +Bit 0: 2_LRU_3. + [5:0] + read-only + + + + + CM0_STATUS + CM0+ interface status + 0x460 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CM4_CA_CTL0 + CM4 cache control + 0x480 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + See CM0_CA_CTL. + [0:0] + read-write + + + RAM_ECC_INJ_EN + See CM0_CA_CTL. + [1:1] + read-write + + + WAY + See CM0_CA_CTL. + [17:16] + read-write + + + SET_ADDR + See CM0_CA_CTL. + [26:24] + read-write + + + PREF_EN + See CM0_CA_CTL. + [30:30] + read-write + + + CA_EN + See CM0_CA_CTL. + [31:31] + read-write + + + + + CM4_CA_CTL1 + CM4 cache control + 0x484 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. + [1:0] + read-write + + + OFF + See CM0_CA_CTL1 + 0 + + + RSVD + Undefined + 1 + + + RETAINED + See CM0_CA_CTL1 + 2 + + + ENABLED + See CM0_CA_CTL1 + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM4_CA_CTL2 + CM4 cache control + 0x488 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM4_CA_STATUS0 + CM4 cache status 0 + 0x4C0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + See CM0_CA_STATUS0. + [31:0] + read-only + + + + + CM4_CA_STATUS1 + CM4 cache status 1 + 0x4C4 + 32 + read-only + 0x0 + 0x0 + + + TAG + See CM0_CA_STATUS1. + [31:0] + read-only + + + + + CM4_CA_STATUS2 + CM4 cache status 2 + 0x4C8 + 32 + read-only + 0x0 + 0x0 + + + LRU + See CM0_CA_STATUS2. + [5:0] + read-only + + + + + CM4_STATUS + CM4 interface status + 0x4E0 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM4_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CRYPTO_BUFF_CTL + Cryptography buffer control + 0x500 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. +A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. +For eCT work Flash, prefetch will not be done. + [30:30] + read-write + + + + + DW0_BUFF_CTL + Datawire 0 buffer control + 0x580 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DW1_BUFF_CTL + Datawire 1 buffer control + 0x600 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DMAC_BUFF_CTL + DMA controller buffer control + 0x680 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS0_BUFF_CTL + External master 0 buffer control + 0x700 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS1_BUFF_CTL + External master 1 buffer control + 0x780 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + FM_CTL + Flash Macro Registers + 0x0000F000 + + FM_CTL + Flash macro control + 0x0 + 32 + read-write + 0x0 + 0x37F030F + + + FM_MODE + Requires (IF_SEL|WR_EN)=1 +Flash macro mode selection + [3:0] + read-write + + + FM_SEQ + Requires (IF_SEL|WR_EN)=1 +Flash macro sequence selection + [9:8] + read-write + + + DAA_MUX_SEL + Direct memory cell access address. + [22:16] + read-write + + + IF_SEL + Interface selection. Specifies the interface that is used for flash memory read operations: +0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. +1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. +Note: IF_SEL and WR_EN cannot be changed at the same time + [24:24] + read-write + + + WR_EN + 0: normal mode +1: Fm Write Enable +Note: IF_SEL and WR_EN cannot be changed at the same time + [25:25] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x1800 + 0xFFFFFFFF + + + TIMER_ENABLED + This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires +0: timer not running +1: Timer is enabled and not expired yet + [0:0] + read-only + + + HV_REGS_ISOLATED + Indicates the isolation status at HV trim and redundancy registers inputs +0: Not isolated, writing permitted +1: isolated writing disabled + [1:1] + read-only + + + ILLEGAL_HVOP + Indicates a bulk, sector erase, program has been requested when axa=1 +0: no error +1: illegal HV operation error + [2:2] + read-only + + + TURBO_N + After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. +Used in the testchip boot only as an 'FM READY' flag. +0: turbo mode +1: normal mode + [3:3] + read-only + + + WR_EN_MON + FM_CTL.WR_EN bit after being synchronized in clk_r domain + [4:4] + read-only + + + IF_SEL_MON + FM_CTL.IF_SEL bit after being synchronized in clk_r domain + [5:5] + read-only + + + TIMER_STATUS + The actual timer state sync-ed in clk_c domain: +0: timer is not running: +1: timer is running; + [6:6] + read-only + + + R_GRANT_DELAY_STATUS + 0: R_GRANT_DELAY timer is not running +1: R_GRANT_DELAY timer is running + [7:7] + read-only + + + FM_BUSY + 0': FM not busy +1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. + [8:8] + read-only + + + FM_READY + 0: FM not ready +1: FM ready + [9:9] + read-only + + + POS_PUMP_VLO + POS pump VLO + [10:10] + read-only + + + NEG_PUMP_VHI + NEG pump VHI + [11:11] + read-only + + + RWW + FM Type (Read While Write or Not Read While Write): +0: Non RWW FM Type +1: RWW FM Type + [12:12] + read-only + + + MAX_DOUT_WIDTH + Internal memory core max data out size +(number of data out bits per column): +0: x128 bits +1: x256 bits + [13:13] + read-only + + + SECTOR0_SR + 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. +1: Sector 0 contains special rows + [14:14] + read-only + + + RESET_MM + Test_only, internal node: mpcon reset_mm + [15:15] + read-only + + + ROW_ODD + Test_only, internal node: mpcon row_odd + [16:16] + read-only + + + ROW_EVEN + Test_only, internal node: mpcon row_even + [17:17] + read-only + + + HVOP_SUB_SECTOR_N + Test_only, internal node: mpcon bk_subb + [18:18] + read-only + + + HVOP_SECTOR + Test_only, internal node: mpcon bk_sec + [19:19] + read-only + + + HVOP_BULK_ALL + Test_only, internal node: mpcon bk_all + [20:20] + read-only + + + CBUS_RA_MATCH + Test_only, internal node: mpcon ra match + [21:21] + read-only + + + CBUS_RED_ROW_EN + Test_only, internal node: mpcon red_row_en + [22:22] + read-only + + + RQ_ERROR + Test_only, internal node: rq_error sync-de in clk_c domain + [23:23] + read-only + + + PUMP_PDAC + Test_only, internal node: regif pdac outputs to pos pump + [27:24] + read-only + + + PUMP_NDAC + Test_only, internal node: regif ndac outputs to pos pump + [31:28] + read-only + + + + + FM_ADDR + Flash macro address + 0x8 + 32 + read-write + 0x0 + 0x1FFFFFF + + + RA + Row address. + [15:0] + read-write + + + BA + Bank address. + [23:16] + read-write + + + AXA + Auxiliary address field: +0: regular flash memory. +1: supervisory flash memory. + [24:24] + read-write + + + + + BOOKMARK + Bookmark register - keeps the current FW HV seq + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BOOKMARK + Used by FW. Keeps the Current HV cycle sequence + [31:0] + read-write + + + + + GEOMETRY + Regular flash geometry + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1): +0: 1 row +1: 2 rows +2: 3 rows +... +'65535': 65536 rows + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1): +0: 1 bank +1: 2 banks +... +'255': 256 banks + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +3: 128 Bytes + +The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2): +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +15: 32768 Bytes + +The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. + [31:28] + read-only + + + + + GEOMETRY_SUPERVISORY + Supervisory flash geometry + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. + [31:28] + read-only + + + + + ANA_CTL0 + Analog control 0 + 0x18 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + MDAC + Trimming of the output margin Voltage as a function of Vpos and Vneg. + [7:0] + read-write + + + CSLDAC + Trimming of common source line DAC. + [10:8] + read-write + + + FLIP_AMUXBUS_AB + Flips amuxbusa and amuxbusb +0: amuxbusa, amuxbusb +1: amuxbusb, amuxbusb + [11:11] + read-write + + + NDAC_MIN + NDAC staircase min value + [15:12] + read-write + + + PDAC_MIN + PDAC staircase min value + [19:16] + read-write + + + SCALE_PRG_SEQ01 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [21:20] + read-write + + + SCALE_PRG_SEQ12 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [23:22] + read-write + + + SCALE_PRG_SEQ23 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [25:24] + read-write + + + SCALE_SEQ30 + PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [27:26] + read-write + + + SCALE_PRG_PEON + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [29:28] + read-write + + + SCALE_PRG_PEOFF + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [31:30] + read-write + + + + + ANA_CTL1 + Analog control 1 + 0x1C + 32 + read-write + 0xD32FAFA + 0xFFFFFFFF + + + NDAC_MAX + Ndac Max Value.Trimming of negative pump output Voltage. + [3:0] + read-write + + + NDAC_STEP + Ndac step increment + [7:4] + read-write + + + PDAC_MAX + Pdac Max Value.Trimming of positive pump output Voltage: + [11:8] + read-write + + + PDAC_STEP + Pdac step increment + [15:12] + read-write + + + NPDAC_STEP_TIME + Ndac/Pdac step duration: (1uS .. 255uS) * 8 +When = 0 N/PDAC_MAX control the pumps + [23:16] + read-write + + + NPDAC_ZERO_TIME + Ndac/Pdac LO duration: (1uS .. 255uS) * 8 +When 0, N/PDAC don't return to 0 + [31:24] + read-write + + + + + WAIT_CTL + Wait State control + 0x28 + 32 + read-write + 0x30B09 + 0x3F070F0F + + + WAIT_FM_MEM_RD + Number of C interface wait cycles (on 'clk_c') for a read from the memory + [3:0] + read-write + + + WAIT_FM_HV_RD + Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. +Common for reading HV Page Latches and the DATA_COMP_RESULT bit + [11:8] + read-write + + + WAIT_FM_HV_WR + Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. + [18:16] + read-write + + + FM_RWW_MODE + 00: Full CBUS MODE +01: RWW +10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration + [25:24] + read-write + + + LV_SPARE_1 + Spare register + [26:26] + read-write + + + DRMM + 0: Normal +1: Test mode to enable Margin mode for 2 rows at a time + [27:27] + read-write + + + MBA + 0: Normal +1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). + [28:28] + read-write + + + PL_SOFT_SET_EN + Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API + [29:29] + read-write + + + + + TIMER_CLK_CTL + Timer prescaler (clk_t to timer clock frequency divider) + 0x34 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TIMER_CLOCK_FREQ + Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. +Equal to the frequency in MHz of the timer clock 'clk_t'. +Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' +Max clk_t frequency = 100MHz. +This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table + [7:0] + read-write + + + RGRANT_DELAY_PRG_PEON + PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_PRG_PEOFF + PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_PRG_SEQ01 + PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + TIMER_CTL + Timer control + 0x38 + 32 + read-write + 0x4000001 + 0xE700FFFF + + + PERIOD + Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. + [14:0] + read-write + + + SCALE + Timer tick scale: +0: 1 microsecond. +1: 100 microseconds. + [15:15] + read-write + + + AUTO_SEQUENCE + 1': Starts1 the HV automatic sequencing +Cleared by HW + [24:24] + read-write + + + PRE_PROG + 1 during pre-program operation + [25:25] + read-write + + + PRE_PROG_CSL + 0: CSL lines driven by CSL_DAC +1: CSL lines driven by VNEG_G + [26:26] + read-write + + + PUMP_EN + Pump enable: +0: disabled +1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). +SW sets this field to '1' to generate a single PE pulse. +HW clears this field when timer is expired. + [29:29] + read-write + + + ACLK_EN + ACLK enable (generates a single cycle pulse for the FM): +0: disabled +1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. + [30:30] + read-write + + + TIMER_EN + Timer enable: +0: disabled +1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. + [31:31] + read-write + + + + + ACLK_CTL + MPCON clock + 0x3C + 32 + write-only + 0x0 + 0x1 + + + ACLK_GEN + A write to this register generates the clock pulse for HV control registers (mpcon outputs) + [0:0] + write-only + + + + + INTR + Interrupt + 0x40 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x44 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x48 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x4C + 32 + read-only + 0x0 + 0x1 + + + TIMER_EXPIRED + Logical and of corresponding request and mask fields. + [0:0] + read-only + + + + + CAL_CTL0 + Cal control BG LO trim bits + 0x50 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_LO_HV + LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_LO_HV + LO Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control + [15:13] + read-write + + + ICREF_TC_TRIM_LO_HV + LO Bandgap Current Temperature Compensation trim control + [18:16] + read-write + + + IPREF_TRIMA_LO_HV + Adds 100-150nA boost on IPREF_LO + [19:19] + read-write + + + + + CAL_CTL1 + Cal control BG HI trim bits + 0x54 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_HI_HV + HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_HI_HV + HI Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [15:13] + read-write + + + ICREF_TC_TRIM_HI_HV + HI Bandgap Current Temperature Compensation trim control. + [18:16] + read-write + + + IPREF_TRIMA_HI_HV + Adds 100-150nA boost on IPREF_HI + [19:19] + read-write + + + + + CAL_CTL2 + Cal control BG LO&HI trim bits + 0x58 + 32 + read-write + 0x7BE10 + 0xFFFFF + + + ICREF_TRIM_LO_HV + LO Bandgap Current trim control. + [4:0] + read-write + + + ICREF_TRIM_HI_HV + HI Bandgap Current trim control. + [9:5] + read-write + + + IPREF_TRIM_LO_HV + LO Bandgap IPTAT trim control. + [14:10] + read-write + + + IPREF_TRIM_HI_HV + HI Bandgap IPTAT trim control. + [19:15] + read-write + + + + + CAL_CTL3 + Cal control osc trim bits, idac, sdac, itim + 0x5C + 32 + read-write + 0x2004 + 0xFFFFF + + + OSC_TRIM_HV + Flash macro pump clock trim control. + [3:0] + read-write + + + OSC_RANGE_TRIM_HV + 0: Oscillator High Frequency Range +1: Oscillator Low Frequency range + [4:4] + read-write + + + VPROT_ACT_HV + Forces VPROT in active mode all the time + [5:5] + read-write + + + IPREF_TC_HV + 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA +1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA + [6:6] + read-write + + + VREF_SEL_HV + Voltage reference: +0: internal bandgap reference +1: external voltage reference + [7:7] + read-write + + + IREF_SEL_HV + Current reference: +0: internal current reference +1: external current reference + [8:8] + read-write + + + REG_ACT_HV + 0: VBST regulator will operate in active/standby mode based on control signal. +1: Forces the VBST regulator in active mode all the time + [9:9] + read-write + + + FDIV_TRIM_HV + FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. +Following are the clock frequencies seen by doubler +00: F = 1MHz +01: F = 0.5MHz +10: F = 2MHz +11: F = 4MHz + [11:10] + read-write + + + VDDHI_HV + 0: vdd < 2.3V +1: vdd >= 2.3V +'0' setting can used for vdd > 2.3V also, but with a current penalty. + [12:12] + read-write + + + TURBO_PULSEW_HV + Turbo pulse width trim (Typical) +00: 40 us +01: 20 us +10: 15 us +11: 8 us + [14:13] + read-write + + + BGLO_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable LO Bandgap + [15:15] + read-write + + + BGHI_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable HI Bandgap +When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active + [16:16] + read-write + + + CL_ISO_DIS_HV + 0: The internal logic controls the CL isolation +1: Forces CL bypass + [17:17] + read-write + + + R_GRANT_EN_HV + 0: r_grant handshake disabled, r_grant always 1. +1: r_grand handshake enabled + [18:18] + read-write + + + LP_ULP_SW_HV + LP<-->ULP switch for trim signals: +0: LP +1: ULP + [19:19] + read-write + + + + + CAL_CTL4 + Cal Control Vlim, SA, fdiv, reg_act + 0x60 + 32 + read-write + 0x12AE0 + 0xFFFFF + + + VLIM_TRIM_ULP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_ULP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_ULP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_ULP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_ULP_HV + 00: Default : delay 1ns +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_ULP_HV + N/A + [15:15] + read-write + + + READY_RESTART_N_HV + Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. + [16:16] + read-write + + + VBST_S_DIS_HV + 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. +1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. + [17:17] + read-write + + + AUTO_HVPULSE_HV + 0: HV Pulse controlled by FW +1: HV Pulse controlled by Hardware + [18:18] + read-write + + + UGB_EN_HV + UGB enable in TM control + [19:19] + read-write + + + + + CAL_CTL5 + Cal control + 0x64 + 32 + read-write + 0x2AE0 + 0xFFFFF + + + VLIM_TRIM_LP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_LP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_LP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_LP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_LP_HV + 00: Delayed by 1us +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_LP_HV + N/A + [15:15] + read-write + + + SPARE52_HV + N/A + [17:16] + read-write + + + AMUX_SEL_HV + Amux Select in AMUX_UGB +00: Bypass UGB for both amuxbusa and amuxbusb +01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. +10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. +11: UGB Calibrate mode + [19:18] + read-write + + + + + CAL_CTL6 + SA trim LP/ULP + 0x68 + 32 + read-write + 0x36F7F + 0xFFFFF + + + SA_CTL_TRIM_T1_ULP_HV + clk_trk delay + [0:0] + read-write + + + SA_CTL_TRIM_T4_ULP_HV + SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) + [3:1] + read-write + + + SA_CTL_TRIM_T5_ULP_HV + SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) + [6:4] + read-write + + + SA_CTL_TRIM_T6_ULP_HV + SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) + [8:7] + read-write + + + SA_CTL_TRIM_T8_ULP_HV + saen3 pulse width trim (Current trim) + [9:9] + read-write + + + SA_CTL_TRIM_T1_LP_HV + clk_trk delay + [10:10] + read-write + + + SA_CTL_TRIM_T4_LP_HV + SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) + [13:11] + read-write + + + SA_CTL_TRIM_T5_LP_HV + SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) + [16:14] + read-write + + + SA_CTL_TRIM_T6_LP_HV + SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) + [18:17] + read-write + + + SA_CTL_TRIM_T8_LP_HV + saen3 pulse width trim (Current trim) + [19:19] + read-write + + + + + CAL_CTL7 + Cal control + 0x6C + 32 + read-write + 0x0 + 0xFFFFF + + + ERSX8_CLK_SEL_HV + Clock frequency into the ersx8 shift register block +00: Oscillator clock +01: Oscillator clock / 2 +10: Oscillator clock / 4 +11: Oscillator clock + [1:0] + read-write + + + FM_ACTIVE_HV + 0: Normal operation +1: Forces FM SYS in active mode + [2:2] + read-write + + + TURBO_EXT_HV + 0: Normal operation +1: Uses external turbo pulse + [3:3] + read-write + + + NPDAC_HWCTL_DIS_HV + 0': ndac, pdac staircase hardware controlled +1: ndac, pdac staircase disabled. Enables FW control. + [4:4] + read-write + + + FM_READY_DIS_HV + 0': fm ready is enabled +1: fm ready is disabled (fm_ready is always '1') + [5:5] + read-write + + + ERSX8_EN_ALL_HV + 0': Staggered turn on/off of GWL +1: GWL are turned on/off at the same time (old FM legacy) + [6:6] + read-write + + + DISABLE_LOAD_ONCE_HV + 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. +1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. + [7:7] + read-write + + + SPARE7_HV + N/A + [9:8] + read-write + + + SPARE7_ULP_HV + N/A + [14:10] + read-write + + + SPARE7_LP_HV + N/A + [19:15] + read-write + + + + + RED_CTL01 + Redundancy Control normal sectors 0,1 + 0x80 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_0 + Bad Row Pair Address for Sector 0 + [7:0] + read-write + + + RED_EN_0 + 1: Redundancy Enable for Sector 0 + [8:8] + read-write + + + RED_ADDR_1 + Bad Row Pair Address for Sector 1 + [23:16] + read-write + + + RED_EN_1 + 1: Redundancy Enable for Sector 1 + [24:24] + read-write + + + + + RED_CTL23 + Redundancy Control normal sectors 2,3 + 0x84 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_2 + Bad Row Pair Address for Sector 2 + [7:0] + read-write + + + RED_EN_2 + 1: Redundancy Enable for Sector 2 + [8:8] + read-write + + + RED_ADDR_3 + Bad Row Pair Address for Sector 3 + [23:16] + read-write + + + RED_EN_3 + 1: Redundancy Enable for Sector 3 + [24:24] + read-write + + + + + RED_CTL45 + Redundancy Control normal sectors 4,5 + 0x88 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_4 + Bad Row Pair Address for Sector 4 + [7:0] + read-write + + + RED_EN_4 + 1: Redundancy Enable for Sector 4 + [8:8] + read-write + + + RED_ADDR_5 + Bad Row Pair Address for Sector 5 + [23:16] + read-write + + + RED_EN_5 + 1: Redundancy Enable for Sector 5 + [24:24] + read-write + + + + + RED_CTL67 + Redundancy Control normal sectors 6,7 + 0x8C + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_6 + Bad Row Pair Address for Sector 6 + [7:0] + read-write + + + RED_EN_6 + 1: Redundancy Enable for Sector 6 + [8:8] + read-write + + + RED_ADDR_7 + Bad Row Pair Address for Sector 7 + [23:16] + read-write + + + RED_EN_7 + 1: Redundancy Enable for Sector 7 + [24:24] + read-write + + + + + RED_CTL_SM01 + Redundancy Control special sectors 0,1 + 0x90 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_SM0 + Bad Row Pair Address for Special Sector 0 + [7:0] + read-write + + + RED_EN_SM0 + Redundancy Enable for Special Sector 0 + [8:8] + read-write + + + RED_ADDR_SM1 + Bad Row Pair Address for Special Sector 1 + [23:16] + read-write + + + RED_EN_SM1 + Redundancy Enable for Special Sector 1 + [24:24] + read-write + + + + + RGRANT_DELAY_PRG + R-grant delay for program + 0x98 + 32 + read-write + 0x1000000 + 0x8FFFFFFF + + + RGRANT_DELAY_PRG_SEQ12 + PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_PRG_SEQ23 + PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_SEQ30 + PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_CLK + Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay +The value of this field is the integer result of 'clk_t frequency / 8'. +Example: for clk_t=100 this field is INT(100/8) =12. +This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table + [27:24] + read-write + + + HV_PARAMS_LOADED + 0: HV Pulse common params not loaded +1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 + [31:31] + read-write + + + + + PW_SEQ12 + HV Pulse Delay for seq 1&2 pre + 0xA0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ1 + Seq1 delay + [15:0] + read-write + + + PW_SEQ2_PRE + Seq2 pre delay + [31:16] + read-write + + + + + PW_SEQ23 + HV Pulse Delay for seq2 post & seq3 + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ2_POST + Seq2 post delay + [15:0] + read-write + + + PW_SEQ3 + Seq3 delay + [31:16] + read-write + + + + + RGRANT_SCALE_ERS + R-grant delay scale for erase + 0xA8 + 32 + read-write + 0x0 + 0xFFFF03FF + + + SCALE_ERS_SEQ01 + ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [1:0] + read-write + + + SCALE_ERS_SEQ12 + ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [3:2] + read-write + + + SCALE_ERS_SEQ23 + ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [5:4] + read-write + + + SCALE_ERS_PEON + ERASE: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [7:6] + read-write + + + SCALE_ERS_PEOFF + ERASE: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [9:8] + read-write + + + RGRANT_DELAY_ERS_PEON + ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_ERS_PEOFF + ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + RGRANT_DELAY_ERS + R-grant delay for erase + 0xAC + 32 + read-write + 0x0 + 0xFFFFFF + + + RGRANT_DELAY_ERS_SEQ01 + ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_ERS_SEQ12 + ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_ERS_SEQ23 + ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + + + FM_PL_WRDATA_ALL + Flash macro write page latches all + 0x7FC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Write all high Voltage page latches with the same 32-bit data in a single write cycle +Read always returns 0. + [31:0] + read-write + + + + + 256 + 4 + FM_PL_DATA[%s] + Flash macro Page Latches data + 0x800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Four page latch Bytes +When reading the page latches it requires FM_CTL.IF_SEL to be '1' +Note: the high Voltage page latches are readable for test mode functionality. + [31:0] + read-write + + + + + 256 + 4 + FM_MEM_DATA[%s] + Flash macro memory sense amplifier and column decoder data + 0xC00 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: +- IF_SEL is 0: data as specified by the R interface address +- IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. + [31:0] + read-only + + + + + + + + SRSS + SRSS Core Registers + 0x40260000 + + 0 + 65536 + registers + + + + PWR_CTL + Power Mode Control + 0x0 + 32 + read-write + 0x0 + 0xFFFC0033 + + + POWER_MODE + Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. + [1:0] + read-only + + + RESET + System is resetting. + 0 + + + ACTIVE + At least one CPU is running. + 1 + + + SLEEP + No CPUs are running. Peripherals may be running. + 2 + + + DEEPSLEEP + Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. + 3 + + + + + DEBUG_SESSION + Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) + [4:4] + read-only + + + NO_SESSION + No debug session active + 0 + + + SESSION_ACTIVE + Debug session is active. Power modes behave differently to keep the debug session active, and current consumption may be higher than datasheet specification. + 1 + + + + + LPM_READY + Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. +1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. + [5:5] + read-only + + + IREF_LPMODE + Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Current reference generator operates in normal mode. +1: Current reference generator operates in low power mode. Response time is reduced to save current. + [18:18] + read-write + + + VREFBUF_OK + Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. + [19:19] + read-only + + + DPSLP_REG_DIS + Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: DeepSleep Regulator is on. +1: DeepSleep Regulator is off. + [20:20] + read-write + + + RET_REG_DIS + Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Retention Regulator is on. +1: Retention Regulator is off. + [21:21] + read-write + + + NWELL_REG_DIS + Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Nwell Regulator is on. +1: Nwell Regulator is off. + [22:22] + read-write + + + LINREG_DIS + Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear regulator is on. +1: Linear regulator is off. + [23:23] + read-write + + + LINREG_LPMODE + Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear Regulator operates in normal mode. +1: Linear Regulator operates in low power mode. Load current capability is reduced, and firmware must ensure the current is kept within the limit for this operating mode. + [24:24] + read-write + + + PORBOD_LPMODE + Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: POR/BOD circuits operate in normal mode. +1: POR/BOD circuits operate in low power mode. Response time is reduced to save current. + [25:25] + read-write + + + BGREF_LPMODE + Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Bandgap Voltage and Current Reference operates in normal mode. +1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current. The Active Reference may be disabled using ACT_REF_DIS=0. + [26:26] + read-write + + + PLL_LS_BYPASS + Bypass level shifter inside the PLL. +0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. +1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. + [27:27] + read-write + + + VREFBUF_LPMODE + Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. +0: Voltage Reference Buffer operates in normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current. + [28:28] + read-write + + + VREFBUF_DIS + Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. + [29:29] + read-write + + + ACT_REF_DIS + Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Reference is enabled +1: Active Reference is disabled + [30:30] + read-write + + + ACT_REF_OK + Indicates that the normal mode of the Active Reference is ready. + [31:31] + read-only + + + + + PWR_HIBERNATE + HIBERNATE Mode Register + 0x4 + 32 + read-write + 0x0 + 0xCFFEFFFF + + + TOKEN + Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. + [7:0] + read-write + + + UNLOCK + This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. + [15:8] + read-write + + + FREEZE + Controls whether mode and state of GPIOs and SIOs in the system are frozen. This is intended to be used as part of the HIBERNATE entry and exit sequences. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. + [17:17] + read-write + + + MASK_HIBALARM + When set, HIBERNATE will wakeup for a RTC interrupt + [18:18] + read-write + + + MASK_HIBWDT + When set, HIBERNATE will wakeup if WDT matches + [19:19] + read-write + + + POLARITY_HIBPIN + Each bit sets the active polarity of the corresponding wakeup pin. +0: Pin input of 0 will wakeup the part from HIBERNATE +1: Pin input of 1 will wakeup the part from HIBERNATE + [23:20] + read-write + + + MASK_HIBPIN + When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the HIBERNATE wakeup pins. + [27:24] + read-write + + + HIBERNATE_DISABLE + Hibernate disable bit. +0: Normal operation, HIBERNATE works as described +1: Further writes to this register are ignored +Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. + [30:30] + read-write + + + HIBERNATE + Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. + [31:31] + read-write + + + + + PWR_LVD_CTL + Low Voltage Detector (LVD) Configuration Register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + HVLVD1_TRIPSEL + Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. +0: rise=1.225V (nom), fall=1.2V (nom) +1: rise=1.425V (nom), fall=1.4V (nom) +2: rise=1.625V (nom), fall=1.6V (nom) +3: rise=1.825V (nom), fall=1.8V (nom) +4: rise=2.025V (nom), fall=2V (nom) +5: rise=2.125V (nom), fall=2.1V (nom) +6: rise=2.225V (nom), fall=2.2V (nom) +7: rise=2.325V (nom), fall=2.3V (nom) +8: rise=2.425V (nom), fall=2.4V (nom) +9: rise=2.525V (nom), fall=2.5V (nom) +10: rise=2.625V (nom), fall=2.6V (nom) +11: rise=2.725V (nom), fall=2.7V (nom) +12: rise=2.825V (nom), fall=2.8V (nom) +13: rise=2.925V (nom), fall=2.9V (nom) +14: rise=3.025V (nom), fall=3.0V (nom) +15: rise=3.125V (nom), fall=3.1V (nom) + [3:0] + read-write + + + HVLVD1_SRCSEL + Source selection for HVLVD1 + [6:4] + read-write + + + VDDD + Select VDDD + 0 + + + AMUXBUSA + Select AMUXBUSA (VDDD branch) + 1 + + + RSVD + N/A + 2 + + + VDDIO + N/A + 3 + + + AMUXBUSB + Select AMUXBUSB (VDDD branch) + 4 + + + + + HVLVD1_EN + Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. + [7:7] + read-write + + + + + PWR_BUCK_CTL + Buck Control Register + 0x14 + 32 + read-write + 0x5 + 0xC0000007 + + + BUCK_OUT1_SEL + Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 0.85V +1: 0.875V +2: 0.90V +3: 0.95V +4: 1.05V +5: 1.10V +6: 1.15V +7: 1.20V + [2:0] + read-write + + + BUCK_EN + Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. + [30:30] + read-write + + + BUCK_OUT1_EN + Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. + [31:31] + read-write + + + + + PWR_BUCK_CTL2 + Buck Control Register 2 + 0x18 + 32 + read-write + 0x0 + 0xC0000007 + + + BUCK_OUT2_SEL + Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 1.15V +1: 1.20V +2: 1.25V +3: 1.30V +4: 1.35V +5: 1.40V +6: 1.45V +7: 1.50V + [2:0] + read-write + + + BUCK_OUT2_HW_SEL + Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. + [30:30] + read-write + + + BUCK_OUT2_EN + Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. + [31:31] + read-write + + + + + PWR_LVD_STATUS + Low Voltage Detector (LVD) Status Register + 0x1C + 32 + read-only + 0x0 + 0x1 + + + HVLVD1_OK + HVLVD1 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + 16 + 4 + PWR_HIB_DATA[%s] + HIBERNATE Data Register + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HIB_DATA + Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. + [31:0] + read-write + + + + + WDT_CTL + Watchdog Counter Control Register + 0x180 + 32 + read-write + 0xC0000001 + 0xC0000001 + + + WDT_EN + Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. + [0:0] + read-write + + + WDT_LOCK + Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. +Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + WDT_CNT + Watchdog Counter Count Register + 0x184 + 32 + read-write + 0x0 + 0xFFFF + + + COUNTER + Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. + [15:0] + read-write + + + + + WDT_MATCH + Watchdog Counter Match Register + 0x188 + 32 + read-write + 0x1000 + 0xFFFFF + + + MATCH + Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). + [15:0] + read-write + + + IGNORE_BITS + The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. + [19:16] + read-write + + + + + 2 + 64 + MCWDT_STRUCT[%s] + Multi-Counter Watchdog Timer + MCWDT_STRUCT + 0x00000200 + + MCWDT_CNTLOW + Multi-Counter Watchdog Sub-counters 0/1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR0 + Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. + [15:0] + read-write + + + WDT_CTR1 + Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:16] + read-write + + + + + MCWDT_CNTHIGH + Multi-Counter Watchdog Sub-counter 2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR2 + Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:0] + read-write + + + + + MCWDT_MATCH + Multi-Counter Watchdog Counter Match Register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_MATCH0 + Match value for sub-counter 0 of this MCWDT + [15:0] + read-write + + + WDT_MATCH1 + Match value for sub-counter 1 of this MCWDT + [31:16] + read-write + + + + + MCWDT_CONFIG + Multi-Counter Watchdog Counter Configuration + 0x10 + 32 + read-write + 0x0 + 0x1F010F0F + + + WDT_MODE0 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). + [1:0] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR0 + Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. + [2:2] + read-write + + + WDT_CASCADE0_1 + Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. +0: Independent counters +1: Cascaded counters + [3:3] + read-write + + + WDT_MODE1 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). + [9:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR1 + Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. + [10:10] + read-write + + + WDT_CASCADE1_2 + Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. +0: Independent counters +1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. + [11:11] + read-write + + + WDT_MODE2 + Watchdog Counter 2 Mode. + [16:16] + read-write + + + NOTHING + Free running counter with no interrupt requests + 0 + + + INT + Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). + 1 + + + + + WDT_BITS2 + Bit to observe for WDT_INT2: +0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) +... +31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) + [28:24] + read-write + + + + + MCWDT_CTL + Multi-Counter Watchdog Counter Control + 0x14 + 32 + read-write + 0x0 + 0xB0B0B + + + WDT_ENABLE0 + Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [0:0] + read-write + + + WDT_ENABLED0 + Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. + [1:1] + read-only + + + WDT_RESET0 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [3:3] + read-write + + + WDT_ENABLE1 + Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [8:8] + read-write + + + WDT_ENABLED1 + Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. + [9:9] + read-only + + + WDT_RESET1 + Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [11:11] + read-write + + + WDT_ENABLE2 + Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [16:16] + read-write + + + WDT_ENABLED2 + Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. + [17:17] + read-only + + + WDT_RESET2 + Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [19:19] + read-write + + + + + MCWDT_INTR + Multi-Counter Watchdog Counter Interrupt Register + 0x18 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. + [0:0] + read-write + + + MCWDT_INT1 + MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. + [1:1] + read-write + + + MCWDT_INT2 + MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. + [2:2] + read-write + + + + + MCWDT_INTR_SET + Multi-Counter Watchdog Counter Interrupt Set Register + 0x1C + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Set interrupt for MCWDT_INT0 + [0:0] + read-write + + + MCWDT_INT1 + Set interrupt for MCWDT_INT1 + [1:1] + read-write + + + MCWDT_INT2 + Set interrupt for MCWDT_INT2 + [2:2] + read-write + + + + + MCWDT_INTR_MASK + Multi-Counter Watchdog Counter Interrupt Mask Register + 0x20 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Mask for sub-counter 0 + [0:0] + read-write + + + MCWDT_INT1 + Mask for sub-counter 1 + [1:1] + read-write + + + MCWDT_INT2 + Mask for sub-counter 2 + [2:2] + read-write + + + + + MCWDT_INTR_MASKED + Multi-Counter Watchdog Counter Interrupt Masked Register + 0x24 + 32 + read-only + 0x0 + 0x7 + + + MCWDT_INT0 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + MCWDT_INT1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + MCWDT_INT2 + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + MCWDT_LOCK + Multi-Counter Watchdog Counter Lock Register + 0x28 + 32 + read-write + 0x0 + 0xC0000000 + + + MCWDT_LOCK + Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + + 16 + 4 + CLK_DSI_SELECT[%s] + Clock DSI Select Register + 0x300 + 32 + read-write + 0x0 + 0x1F + + + DSI_MUX + Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. + [4:0] + read-write + + + DSI_OUT0 + DSI0 - dsi_out[0] + 0 + + + DSI_OUT1 + DSI1 - dsi_out[1] + 1 + + + DSI_OUT2 + DSI2 - dsi_out[2] + 2 + + + DSI_OUT3 + DSI3 - dsi_out[3] + 3 + + + DSI_OUT4 + DSI4 - dsi_out[4] + 4 + + + DSI_OUT5 + DSI5 - dsi_out[5] + 5 + + + DSI_OUT6 + DSI6 - dsi_out[6] + 6 + + + DSI_OUT7 + DSI7 - dsi_out[7] + 7 + + + DSI_OUT8 + DSI8 - dsi_out[8] + 8 + + + DSI_OUT9 + DSI9 - dsi_out[9] + 9 + + + DSI_OUT10 + DSI10 - dsi_out[10] + 10 + + + DSI_OUT11 + DSI11 - dsi_out[11] + 11 + + + DSI_OUT12 + DSI12 - dsi_out[12] + 12 + + + DSI_OUT13 + DSI13 - dsi_out[13] + 13 + + + DSI_OUT14 + DSI14 - dsi_out[14] + 14 + + + DSI_OUT15 + DSI15 - dsi_out[15] + 15 + + + ILO + ILO - Internal Low-speed Oscillator + 16 + + + WCO + WCO - Watch-Crystal Oscillator + 17 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock + 18 + + + PILO + PILO - Precision Internal Low-speed Oscillator + 19 + + + + + + + 16 + 4 + CLK_PATH_SELECT[%s] + Clock Path Select Register + 0x340 + 32 + read-write + 0x0 + 0x7 + + + PATH_MUX + Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + DSI_MUX + DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. + 4 + + + + + + + 16 + 4 + CLK_ROOT_SELECT[%s] + Clock Root Select Register + 0x380 + 32 + read-write + 0x0 + 0x8000003F + + + ROOT_MUX + Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [3:0] + read-write + + + PATH0 + Select PATH0 (can be configured for FLL) + 0 + + + PATH1 + Select PATH1 (can be configured for PLL0, if available in the product) + 1 + + + PATH2 + Select PATH2 (can be configured for PLL1, if available in the product) + 2 + + + PATH3 + Select PATH3 (can be configured for PLL2, if available in the product) + 3 + + + PATH4 + Select PATH4 (can be configured for PLL3, if available in the product) + 4 + + + PATH5 + Select PATH5 (can be configured for PLL4, if available in the product) + 5 + + + PATH6 + Select PATH6 (can be configured for PLL5, if available in the product) + 6 + + + PATH7 + Select PATH7 (can be configured for PLL6, if available in the product) + 7 + + + PATH8 + Select PATH8 (can be configured for PLL7, if available in the product) + 8 + + + PATH9 + Select PATH9 (can be configured for PLL8, if available in the product) + 9 + + + PATH10 + Select PATH10 (can be configured for PLL9, if available in the product) + 10 + + + PATH11 + Select PATH11 (can be configured for PLL10, if available in the product) + 11 + + + PATH12 + Select PATH12 (can be configured for PLL11, if available in the product) + 12 + + + PATH13 + Select PATH13 (can be configured for PLL12, if available in the product) + 13 + + + PATH14 + Select PATH14 (can be configured for PLL13, if available in the product) + 14 + + + PATH15 + Select PATH15 (can be configured for PLL14, if available in the product) + 15 + + + + + ROOT_DIV + Selects predivider value for this clock root and DSI input. + [5:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + + + ENABLE + Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. + [31:31] + read-write + + + + + CLK_SELECT + Clock selection register + 0x500 + 32 + read-write + 0x0 + 0xFF03 + + + LFCLK_SEL + Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. + [1:0] + read-write + + + ILO + ILO - Internal Low-speed Oscillator + 0 + + + WCO + WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). + 1 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock. Capability is product-specific + 2 + + + PILO + PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. + 3 + + + + + PUMP_SEL + Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. + [11:8] + read-write + + + PUMP_DIV + Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. + [14:12] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + + + PUMP_ENABLE + Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: +1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. +2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. +3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. + [15:15] + read-write + + + + + CLK_TIMER_CTL + Timer Clock Control Register + 0x504 + 32 + read-write + 0x70000 + 0x80FF0301 + + + TIMER_SEL + Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. + [0:0] + read-write + + + IMO + IMO - Internal Main Oscillator + 0 + + + HF0_DIV + Select the output of the predivider configured by TIMER_HF0_DIV. + 1 + + + + + TIMER_HF0_DIV + Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. + [9:8] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. + 0 + + + DIV_BY_2 + Divide HFCLK0 by 2. + 1 + + + DIV_BY_4 + Divide HFCLK0 by 4. + 2 + + + DIV_BY_8 + Divide HFCLK0 by 8. + 3 + + + + + TIMER_DIV + Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. + [23:16] + read-write + + + ENABLE + Enable for TIMERCLK. +0: TIMERCLK is off +1: TIMERCLK is enabled + [31:31] + read-write + + + + + CLK_ILO_CONFIG + ILO Configuration + 0x50C + 32 + read-write + 0x80000000 + 0x80000001 + + + ILO_BACKUP + If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. +0: ILO turns off at XRES/BOD event or HIBERNATE entry. +1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. + [0:0] + read-write + + + ENABLE + Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. + [31:31] + read-write + + + + + CLK_IMO_CONFIG + IMO Configuration + 0x510 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLE + Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if CLK_MFO_CONFIG.DPSLP_ENABLE==0. + [31:31] + read-write + + + + + CLK_OUTPUT_FAST + Fast Clock Output Select Register + 0x514 + 32 + read-write + 0x0 + 0xFFF0FFF + + + FAST_SEL0 + Select signal for fast clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL0 + Selects the clock path chosen by PATH_SEL0 field + 5 + + + HFCLK_SEL0 + Selects the output of the HFCLK_SEL0 mux + 6 + + + SLOW_SEL0 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 + 7 + + + + + PATH_SEL0 + Selects a clock path to use in fast clock output #0 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [7:4] + read-write + + + HFCLK_SEL0 + Selects a HFCLK tree for use in fast clock output #0 + [11:8] + read-write + + + FAST_SEL1 + Select signal for fast clock output #1 + [19:16] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL1 + Selects the clock path chosen by PATH_SEL1 field + 5 + + + HFCLK_SEL1 + Selects the output of the HFCLK_SEL1 mux + 6 + + + SLOW_SEL1 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 + 7 + + + + + PATH_SEL1 + Selects a clock path to use in fast clock output #1 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [23:20] + read-write + + + HFCLK_SEL1 + Selects a HFCLK tree for use in fast clock output #1 logic + [27:24] + read-write + + + + + CLK_OUTPUT_SLOW + Slow Clock Output Select Register + 0x518 + 32 + read-write + 0x0 + 0xFF + + + SLOW_SEL0 + Select signal for slow clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + SLOW_SEL1 + Select signal for slow clock output #1 + [7:4] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + + + CLK_CAL_CNT1 + Clock Calibration Counter 1 + 0x51C + 32 + read-write + 0x80000000 + 0x80FFFFFF + + + CAL_COUNTER1 + Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. + [23:0] + read-write + + + CAL_COUNTER_DONE + Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up + [31:31] + read-only + + + + + CLK_CAL_CNT2 + Clock Calibration Counter 2 + 0x520 + 32 + read-only + 0x0 + 0xFFFFFF + + + CAL_COUNTER2 + Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) + [23:0] + read-only + + + + + CLK_ECO_CONFIG + ECO Configuration Register + 0x52C + 32 + read-write + 0x2 + 0x80000002 + + + AGC_EN + Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. + [1:1] + read-write + + + ECO_EN + Master enable for ECO oscillator. + [31:31] + read-write + + + + + CLK_ECO_STATUS + ECO Status Register + 0x530 + 32 + read-only + 0x0 + 0x3 + + + ECO_OK + Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. + [0:0] + read-only + + + ECO_READY + Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. + [1:1] + read-only + + + + + CLK_PILO_CONFIG + Precision ILO Configuration Register + 0x53C + 32 + read-write + 0x80 + 0xE00003FF + + + PILO_FFREQ + Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. + [9:0] + read-write + + + PILO_CLK_EN + Enable the PILO clock output. See PILO_EN field for required sequencing. + [29:29] + read-write + + + PILO_RESET_N + Reset the PILO. See PILO_EN field for required sequencing. + [30:30] + read-write + + + PILO_EN + Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. + [31:31] + read-write + + + + + CLK_MF_SELECT + Medium Frequency Clock Select Register + 0x544 + 32 + read-write + 0x0 + 0x8000FF07 + + + MFCLK_SEL + Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior. + [2:0] + read-write + + + MFO + MFO - medium frequency oscillator + 0 + + + + + MFCLK_DIV + Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1, 256]. Do not change this setting while ENABLE==1. + [15:8] + read-write + + + ENABLE + Enable for MFCLK (clk_mf). + [31:31] + read-write + + + + + CLK_MFO_CONFIG + MFO Configuration Register + 0x548 + 32 + read-write + 0x80000000 + 0xC0000000 + + + DPSLP_ENABLE + Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1: +0: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup; +1: MFO is kept enabled throughout DEEPSLEEP + [30:30] + read-write + + + ENABLE + Enable for MFO. + [31:31] + read-write + + + + + CLK_FLL_CONFIG + FLL Configuration Register + 0x580 + 32 + read-write + 0x1000000 + 0x8103FFFF + + + FLL_MULT + Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). + +Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) + [17:0] + read-write + + + FLL_OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: no division +1: divide by 2 + [24:24] + read-write + + + FLL_ENABLE + Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. + +To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. + +To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. + +Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. + +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_CONFIG2 + FLL Configuration Register 2 + 0x584 + 32 + read-write + 0x20001 + 0x1FF1FFF + + + FLL_REF_DIV + Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +8191: divide by 8191 + [12:0] + read-write + + + LOCK_TOL + Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. +0: tolerate error of 1 count value +1: tolerate error of 2 count values +... +511: tolerate error of 512 count values + [24:16] + read-write + + + + + CLK_FLL_CONFIG3 + FLL Configuration Register 3 + 0x588 + 32 + read-write + 0x2800 + 0x301FFFFF + + + FLL_LF_IGAIN + FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [3:0] + read-write + + + FLL_LF_PGAIN + FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [7:4] + read-write + + + SETTLING_COUNT + Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. +0: no settling time +1: wait one reference clock cycle +... +8191: wait 8191 reference clock cycles + [20:8] + read-write + + + BYPASS_SEL + Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. + [29:28] + read-write + + + AUTO + N/A + 0 + + + AUTO1 + N/A + 1 + + + FLL_REF + Select FLL reference input (bypass mode). Ignores lock indicator + 2 + + + FLL_OUT + Select FLL output. Ignores lock indicator. + 3 + + + + + + + CLK_FLL_CONFIG4 + FLL Configuration Register 4 + 0x58C + 32 + read-write + 0xFF + 0xC1FF07FF + + + CCO_LIMIT + Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) + [7:0] + read-write + + + CCO_RANGE + Frequency range of CCO + [10:8] + read-write + + + RANGE0 + Target frequency is in range [48, 64) MHz + 0 + + + RANGE1 + Target frequency is in range [64, 85) MHz + 1 + + + RANGE2 + Target frequency is in range [85, 113) MHz + 2 + + + RANGE3 + Target frequency is in range [113, 150) MHz + 3 + + + RANGE4 + Target frequency is in range [150, 200] MHz + 4 + + + + + CCO_FREQ + CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. + [24:16] + read-write + + + CCO_HW_UPDATE_DIS + Disable CCO frequency update by FLL hardware +0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. +1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. + [30:30] + read-write + + + CCO_ENABLE + Enable the CCO. It is required to enable the CCO before using the FLL. +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_STATUS + FLL Status Register + 0x590 + 32 + read-write + 0x0 + 0x7 + + + LOCKED + FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. + [0:0] + read-only + + + UNLOCK_OCCURRED + N/A + [1:1] + read-write + + + CCO_READY + This indicates that the CCO is internally settled and ready to use. + [2:2] + read-only + + + + + 15 + 4 + CLK_PLL_CONFIG[%s] + PLL Configuration Register + 0x600 + 32 + read-write + 0x20116 + 0xB81F1F7F + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-21: illegal (undefined behavior) +22: divide by 22 +... +112: divide by 112 +>112: illegal (undefined behavior) + [6:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +20: divide by 20 +others: illegal (undefined behavior) + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + PLL_LF_MODE + VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. +0: VCO frequency is [200MHz, 400MHz] +1: VCO frequency is [170MHz, 200MHz) + [27:27] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. + 0 + + + AUTO1 + Same as AUTO + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. + +Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled +1: Block is enabled + [31:31] + read-write + + + + + 15 + 4 + CLK_PLL_STATUS[%s] + PLL Status Register + 0x640 + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + SRSS_INTR + SRSS Interrupt Register + 0x700 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. + [0:0] + read-write + + + HVLVD1 + Interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Clock calibration counter is done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_SET + SRSS Interrupt Set Register + 0x704 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Set interrupt for low voltage detector WDT_MATCH + [0:0] + read-write + + + HVLVD1 + Set interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_MASK + SRSS Interrupt Mask Register + 0x708 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. + [0:0] + read-write + + + HVLVD1 + Mask for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Mask for clock calibration done + [5:5] + read-write + + + + + SRSS_INTR_MASKED + SRSS Interrupt Masked Register + 0x70C + 32 + read-only + 0x0 + 0x23 + + + WDT_MATCH + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + HVLVD1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CLK_CAL + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + SRSS_INTR_CFG + SRSS Interrupt Configuration Register + 0x710 + 32 + read-write + 0x0 + 0x3 + + + HVLVD1_EDGE_SEL + Sets which edge(s) will trigger an IRQ for HVLVD1 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + + + RES_CAUSE + Reset Cause Observation Register + 0x800 + 32 + read-write + 0x0 + 0x1FF + + + RESET_WDT + A basic WatchDog Timer (WDT) reset has occurred since last power cycle. + [0:0] + read-write + + + RESET_ACT_FAULT + Fault logging system requested a reset from its Active logic. + [1:1] + read-write + + + RESET_DPSLP_FAULT + Fault logging system requested a reset from its DeepSleep logic. + [2:2] + read-write + + + RESET_CSV_WCO_LOSS + Clock supervision logic requested a reset due to loss of a watch-crystal clock. + [3:3] + read-write + + + RESET_SOFT + A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. + [4:4] + read-write + + + RESET_MCWDT0 + Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. + [5:5] + read-write + + + RESET_MCWDT1 + Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. + [6:6] + read-write + + + RESET_MCWDT2 + Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. + [7:7] + read-write + + + RESET_MCWDT3 + Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. + [8:8] + read-write + + + + + RES_CAUSE2 + Reset Cause Observation Register 2 + 0x804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESET_CSV_HF_LOSS + Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [15:0] + read-write + + + RESET_CSV_HF_FREQ + Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [31:16] + read-write + + + + + PWR_TRIM_REF_CTL + Reference Trim Register + 0x7F00 + 32 + read-write + 0x70F00000 + 0xF1FF5FFF + + + ACT_REF_TCTRIM + Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [3:0] + read-write + + + ACT_REF_ITRIM + Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [7:4] + read-write + + + ACT_REF_ABSTRIM + Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [12:8] + read-write + + + ACT_REF_IBOOST + Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: normal operation +others: risk mitigation + [14:14] + read-write + + + DPSLP_REF_TCTRIM + DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [19:16] + read-write + + + DPSLP_REF_ABSTRIM + DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [24:20] + read-write + + + DPSLP_REF_ITRIM + DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:28] + read-write + + + + + PWR_TRIM_BODOVP_CTL + BOD/OVP Trim Register + 0x7F04 + 32 + read-write + 0x40D04 + 0xFDFF7 + + + HVPORBOD_TRIPSEL + HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [2:0] + read-write + + + HVPORBOD_OFSTRIM + HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [6:4] + read-write + + + HVPORBOD_ITRIM + HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [9:7] + read-write + + + LVPORBOD_TRIPSEL + LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [12:10] + read-write + + + LVPORBOD_OFSTRIM + LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [16:14] + read-write + + + LVPORBOD_ITRIM + LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [19:17] + read-write + + + + + CLK_TRIM_CCO_CTL + CCO Trim Register + 0x7F08 + 32 + read-write + 0xA7000020 + 0xBF00003F + + + CCO_RCSTRIM + CCO reference current source trim. + [5:0] + read-write + + + CCO_STABLE_CNT + Terminal count for the stabilization counter from CCO_ENABLE until stable. + [29:24] + read-write + + + ENABLE_CNT + Enables the automatic stabilization counter. + [31:31] + read-write + + + + + CLK_TRIM_CCO_CTL2 + CCO Trim Register 2 + 0x7F0C + 32 + read-write + 0x884110 + 0x1FFFFFF + + + CCO_FCTRIM1 + CCO frequency 1st range calibration + [4:0] + read-write + + + CCO_FCTRIM2 + CCO frequency 2nd range calibration + [9:5] + read-write + + + CCO_FCTRIM3 + CCO frequency 3rd range calibration + [14:10] + read-write + + + CCO_FCTRIM4 + CCO frequency 4th range calibration + [19:15] + read-write + + + CCO_FCTRIM5 + CCO frequency 5th range calibration + [24:20] + read-write + + + + + PWR_TRIM_WAKE_CTL + Wakeup Trim Register + 0x7F30 + 32 + read-write + 0x0 + 0xFF + + + WAKE_DELAY + Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. + [7:0] + read-write + + + + + PWR_TRIM_LVD_CTL + LVD Trim Register + 0xFF10 + 32 + read-write + 0x20 + 0x77 + + + HVLVD1_OFSTRIM + HVLVD1 offset trim + [2:0] + read-write + + + HVLVD1_ITRIM + HVLVD1 current trim + [6:4] + read-write + + + + + CLK_TRIM_ILO_CTL + ILO Trim Register + 0xFF18 + 32 + read-write + 0x2C + 0x3F + + + ILO_FTRIM + ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + + + PWR_TRIM_PWRSYS_CTL + Power System Trim Register + 0xFF1C + 32 + read-write + 0x17 + 0x1F + + + ACT_REG_TRIM + Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: +5'h07: 900mV (nominal) +5'h17: 1100mV (nominal) + [4:0] + read-write + + + ACT_REG_BOOST + Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: +2'b00: 50uA +2'b01: 100uA +2'b10: 150uA +2'b11: 200uA + +The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. +50mA chip: 2'b00 (default); +100mA chip: 2'b00 (default); +150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); +200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); +250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); +300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); + +This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:30] + read-write + + + + + CLK_TRIM_ECO_CTL + ECO Trim Register + 0xFF20 + 32 + read-write + 0x1F0003 + 0x3F3FF7 + + + WDTRIM + Watch Dog Trim - Delta voltage below steady state level +0x0 - 50mV +0x1 - 75mV +0x2 - 100mV +0x3 - 125mV +0x4 - 150mV +0x5 - 175mV +0x6 - 200mV +0x7 - 225mV + [2:0] + read-write + + + ATRIM + Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. +0x0 - 150mV +0x1 - 175mV +0x2 - 200mV +0x3 - 225mV +0x4 - 250mV +0x5 - 275mV +0x6 - 300mV +0x7 - 325mV +0x8 - 350mV +0x9 - 375mV +0xA - 400mV +0xB - 425mV +0xC - 450mV +0xD - 475mV +0xE - 500mV +0xF - 525mV + [7:4] + read-write + + + FTRIM + Filter Trim - 3rd harmonic oscillation + [9:8] + read-write + + + RTRIM + Feedback resistor Trim + [11:10] + read-write + + + GTRIM + Gain Trim - Startup time + [13:12] + read-write + + + ITRIM + Current Trim + [21:16] + read-write + + + + + CLK_TRIM_PILO_CTL + PILO Trim Register + 0xFF24 + 32 + read-write + 0x108500F + 0x7DFF703F + + + PILO_CFREQ + Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. + [5:0] + read-write + + + PILO_OSC_TRIM + Trim for current in oscillator block. + [14:12] + read-write + + + PILO_COMP_TRIM + Trim for comparator bias current. + [17:16] + read-write + + + PILO_NBIAS_TRIM + Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier + [19:18] + read-write + + + PILO_RES_TRIM + Trim for beta-multiplier branch current + [24:20] + read-write + + + PILO_ISLOPE_TRIM + Trim for beta-multiplier current slope + [27:26] + read-write + + + PILO_VTDIFF_TRIM + Trim for VT-DIFF output (internal power supply) + [30:28] + read-write + + + + + CLK_TRIM_PILO_CTL2 + PILO Trim Register 2 + 0xFF28 + 32 + read-write + 0xDA10E0 + 0xFF1FFF + + + PILO_VREF_TRIM + Trim for voltage reference + [7:0] + read-write + + + PILO_IREFBM_TRIM + Trim for beta-multiplier current reference + [12:8] + read-write + + + PILO_IREF_TRIM + Trim for current reference + [23:16] + read-write + + + + + CLK_TRIM_PILO_CTL3 + PILO Trim Register 3 + 0xFF2C + 32 + read-write + 0x4800 + 0xFFFF + + + PILO_ENGOPT + Engineering options for PILO circuits +0: Short vdda to vpwr +1: Beta:mult current change +2: Iref generation Ptat current addition +3: Disable current path in secondary Beta:mult startup circuit +4: Double oscillator current +5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block +6: Spare +7: Ptat component increase in Iref +8: vpwr_rc and vpwr_dig_rc shorting testmode +9: Switch b/w psub connection for cascode nfet for vref generation +10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. +15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. + [15:0] + read-write + + + + + + + BACKUP + SRSS Backup Domain + 0x40270000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFF0F3308 + + + WCO_EN + Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. +After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. + [3:3] + read-write + + + CLK_SEL + Clock select for BAK clock + [9:8] + read-write + + + WCO + Watch-crystal oscillator input. + 0 + + + ALTBAK + This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. + 1 + + + + + PRESCALER + N/A + [13:12] + read-write + + + WCO_BYPASS + Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. +0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. +1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. + [16:16] + read-write + + + VDDBAK_CTL + Controls the behavior of the switch that generates vddbak from vbackup or vddd. +0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. +1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. + [18:17] + read-write + + + VBACKUP_MEAS + Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. + [19:19] + read-write + + + EN_CHARGE_KEY + When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. + [31:24] + read-write + + + + + RTC_RW + RTC Read Write register + 0x8 + 32 + read-write + 0x0 + 0x3 + + + READ + Read bit +When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. +Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. + [0:0] + read-write + + + WRITE + Write bit +Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. +The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. +Only user RTC registers that were written to will get copied, others will not be affected. +When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). +When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. +Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. + [1:1] + read-write + + + + + CAL_CTL + Oscillator calibration for absolute frequency + 0xC + 32 + read-write + 0x0 + 0x8000007F + + + CALIB_VAL + Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). +Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) + +Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. + [5:0] + read-write + + + CALIB_SIGN + Calibration sign: +0= Negative sign: remove pulses (it takes more clock ticks to count one second) +1= Positive sign: add pulses (it takes less clock ticks to count one second) + [6:6] + read-write + + + CAL_OUT + Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. + [31:31] + read-write + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x0 + 0x5 + + + RTC_BUSY + pending RTC write + [0:0] + read-only + + + WCO_OK + Indicates that output has transitioned. + [2:2] + read-only + + + + + RTC_TIME + Calendar Seconds, Minutes, Hours, Day of Week + 0x14 + 32 + read-write + 0x0 + 0x77F7F7F + + + RTC_SEC + Calendar seconds in BCD, 0-59 + [6:0] + read-write + + + RTC_MIN + Calendar minutes in BCD, 0-59 + [14:8] + read-write + + + RTC_HOUR + Calendar hours in BCD, value depending on 12/24HR mode +0=24HR: [21:16]=0-23 +1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 + [21:16] + read-write + + + CTRL_12HR + Select 12/24HR mode: 1=12HR, 0=24HR + [22:22] + read-write + + + RTC_DAY + Calendar Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + + + RTC_DATE + Calendar Day of Month, Month, Year + 0x18 + 32 + read-write + 0x0 + 0xFF1F3F + + + RTC_DATE + Calendar Day of the Month in BCD, 1-31 +Automatic Leap Year Correction + [5:0] + read-write + + + RTC_MON + Calendar Month in BCD, 1-12 + [12:8] + read-write + + + RTC_YEAR + Calendar year in BCD, 0-99 + [23:16] + read-write + + + + + ALM1_TIME + Alarm 1 Seconds, Minute, Hours, Day of Week + 0x1C + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM1_DATE + Alarm 1 Day of Month, Month + 0x20 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 1. +0: Alarm 1 is disabled. Fields for date and time are ignored. +1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + ALM2_TIME + Alarm 2 Seconds, Minute, Hours, Day of Week + 0x24 + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM2_DATE + Alarm 2 Day of Month, Month + 0x28 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 2. +0: Alarm 2 is disabled. Fields for date and time are ignored. +1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x2C + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Alarm 1 Interrupt + [0:0] + read-write + + + ALARM2 + Alarm 2 Interrupt + [1:1] + read-write + + + CENTURY + Century overflow interrupt + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x30 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x34 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x38 + 32 + read-only + 0x0 + 0x7 + + + ALARM1 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + ALARM2 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CENTURY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + OSCCNT + 32kHz oscillator counter + 0x3C + 32 + read-only + 0x0 + 0xFF + + + CNT32KHZ + 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. + [7:0] + read-only + + + + + TICKS + 128Hz tick counter + 0x40 + 32 + read-only + 0x0 + 0x3F + + + CNT128HZ + 128Hz counter (msb=2Hz) +When SECONDS is written this field will be reset. + [5:0] + read-only + + + + + PMIC_CTL + PMIC control register + 0x44 + 32 + read-write + 0xA0000000 + 0xE001FF00 + + + UNLOCK + This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. + [15:8] + read-write + + + POLARITY + N/A + [16:16] + read-write + + + PMIC_EN_OUTEN + Output enable for the output driver in the PMIC_EN pad. +0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present +1: Output pad is enabled for PMIC_EN pin. + [29:29] + read-write + + + PMIC_ALWAYSEN + Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. +0: Normal operation, PMIC_EN and PMIC_OUTEN work as described +1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. +Note: This bit is a write-once bit until the next backup reset. + [30:30] + read-write + + + PMIC_EN + Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. + [31:31] + read-write + + + + + RESET + Backup reset register + 0x48 + 32 + read-write + 0x0 + 0x80000000 + + + RESET + Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. + [31:31] + read-write + + + + + 64 + 4 + BREG[%s] + Backup register region + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BREG + Backup memory that contains application-specific data. Memory is retained on vbackup supply. + [31:0] + read-write + + + + + TRIM + Trim Register + 0xFF00 + 32 + read-write + 0x0 + 0x3F + + + TRIM + WCO trim + [5:0] + read-write + + + + + + + DW0 + Datawire Controller + DW + 0x40280000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x1 + 0x80000003 + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + ECC_INJ_EN + Enable parity injection for SRAM. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. + [1:1] + read-write + + + ENABLED + IP enable: +'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0xF0000000 + + + P + Active channel, user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + Active channel, secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + B + Active channel, non-bufferable/bufferable access control: +'0': non-bufferable +'1': bufferable. + [2:2] + read-only + + + PC + Active channel protection context. + [7:4] + read-only + + + PRIO + Active channel priority. + [9:8] + read-only + + + PREEMPTABLE + Active channel preemptable. + [11:11] + read-only + + + CH_IDX + Active channel index. + [24:16] + read-only + + + STATE + State of the DW controller. +'0': Default/inactive state. +'1': Loading descriptor. +'2': Loading data element from source location. +'3': Storing data element to destination location. +'4': CRC functionality (only used for CRC transfer descriptor type). +'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. +'6': Error. + [30:28] + read-only + + + ACTIVE + Active channel present: +'0': No. +'1': Yes. + [31:31] + read-only + + + + + ACT_DESCR_CTL + Active descriptor control + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-only + + + + + ACT_DESCR_SRC + Active descriptor source + 0x24 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_SRC of the currently active descriptor. + +Base address of source location. + [31:0] + read-only + + + + + ACT_DESCR_DST + Active descriptor destination + 0x28 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_DST of the currently active descriptor. + +Base address of destination location. + +Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. + [31:0] + read-only + + + + + ACT_DESCR_X_CTL + Active descriptor X loop control + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_X_CTL of the currently active descriptor. + +[11:0] SRC_X_INCR +Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + +[23:12] DST_X_INCR +Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + +Note: this field is not used for CRC transfer descriptors and must be set to '0'. + +[31:24] X_COUNT +Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For a single transfer descriptor type, descriptor will not have X_CTL. + [31:0] + read-only + + + + + ACT_DESCR_Y_CTL + Active descriptor Y loop control + 0x34 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_Y_CTL of the currently active descriptor. + +[11:0] SRC_Y_INCR +Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[23:12] DST_Y_INCR +Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[31:24] Y_COUNT +Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. + [31:0] + read-only + + + + + ACT_DESCR_NEXT_PTR + Active descriptor next pointer + 0x38 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Copy of DESCR_NEXT_PTR of the currently active descriptor. + +[31:2] ADDR +Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + ACT_SRC + Active source + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SRC_ADDR + Current address of source location. + [31:0] + read-only + + + + + ACT_DST + Active destination + 0x44 + 32 + read-only + 0x0 + 0x0 + + + DST_ADDR + Current address of destination location. + [31:0] + read-only + + + + + ECC_CTL + ECC control + 0x80 + 32 + read-write + 0x0 + 0xFE0003FF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [9:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + CRC_CTL + CRC control + 0x100 + 32 + read-write + 0x0 + 0x101 + + + DATA_REVERSE + Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): +'0': Most significant bit (bit 1) first. +'1': Least significant bit (bit 0) first. + [0:0] + read-write + + + REM_REVERSE + Specifies whether the remainder is bit reversed (reversal is performed after XORing): +'0': No. +'1': Yes. + [8:8] + read-write + + + + + CRC_DATA_CTL + CRC data control + 0x110 + 32 + read-write + 0x0 + 0xFF + + + DATA_XOR + Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. + [7:0] + read-write + + + + + CRC_POL_CTL + CRC polynomial control + 0x120 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POLYNOMIAL + CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: +- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). +- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). +- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). + [31:0] + read-write + + + + + CRC_LFSR_CTL + CRC LFSR control + 0x130 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LFSR32 + State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. + +The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. + +Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). + [31:0] + read-write + + + + + CRC_REM_CTL + CRC remainder control + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REM_XOR + Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. + [31:0] + read-write + + + + + CRC_REM_RESULT + CRC remainder result + 0x148 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REM + Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: +'0': the more significant bits (bit 31 and down) contain the remainder. +'1': the less significant bits (bit 0 and up) contain the remainder. + +Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. + [31:0] + read-only + + + + + 32 + 64 + CH_STRUCT[%s] + DW channel structure + 0x00008000 + + CH_CTL + Channel control + 0x0 + 32 + read-write + 0x0 + 0x80000300 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). + [9:8] + read-write + + + PREEMPTABLE + Specifies if the channel is preemptable. +'0': Not preemptable. +'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. + [11:11] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). + [31:31] + read-write + + + + + CH_STATUS + Channel status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + INTR_CAUSE + Specifies the source of the interrupt cause: +'0': No interrupt generated +'1': Interrupt based on transfer complettion configuration based on INTR_TYPE +'2': Source transfer bus error +'3': Destination transfer bus error +'4': Source address misalignment +'5': Destination address misalignment +'6': Current descriptor pointer is null +'7': Active channel is disabled +'8': Descriptor bus error +'9'-'15': Not used. + +For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). + [3:0] + read-only + + + PENDING + Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). + [31:31] + read-only + + + + + CH_IDX + Channel current indices + 0x8 + 32 + read-write + 0x0 + 0x0 + + + X_IDX + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [7:0] + read-write + + + Y_IDX + Specifies the Y loop index, with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [15:8] + read-write + + + + + CH_CURR_PTR + Channel current descriptor pointer + 0xC + 32 + read-write + 0x0 + 0x0 + + + ADDR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. + [31:2] + read-write + + + + + INTR + Interrupt + 0x10 + 32 + read-write + 0x0 + 0x1 + + + CH + Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x14 + 32 + read-write + 0x0 + 0x1 + + + CH + Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x18 + 32 + read-write + 0x0 + 0x1 + + + CH + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x1C + 32 + read-only + 0x0 + 0x1 + + + CH + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + SRAM_DATA0 + SRAM data 0 + 0x20 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + SRAM_DATA1 + SRAM data 1 + 0x24 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + TR_CMD + Channel software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + + + + DW1 + 0x40290000 + + + DMAC + DMAC + 0x402A0000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + ACTIVE + Active channels + 0x8 + 32 + read-only + 0x0 + 0xFF + + + ACTIVE + Specifies active channels; i.e. enabled channels whose trigger got activated. + [7:0] + read-only + + + + + 2 + 256 + CH[%s] + DMA controller channel + 0x00001000 + + CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x800003F7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. +A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. + [9:8] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' when an error interrupt cause is activated. + [31:31] + read-write + + + + + IDX + Channel current indices + 0x10 + 32 + read-only + 0x0 + 0x0 + + + X + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor. + [15:0] + read-only + + + Y + Specifies the Y loop index, with Y_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor.. + [31:16] + read-only + + + + + SRC + Channel current source address + 0x14 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of source location. + [31:0] + read-only + + + + + DST + Channel current destination address + 0x18 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of destination location. + [31:0] + read-only + + + + + CURR + Channel current descriptor pointer + 0x20 + 32 + read-write + 0x0 + 0x0 + + + PTR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + [31:2] + read-write + + + + + TR_CMD + Channle software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + DESCR_STATUS + Channel descriptor status + 0x40 + 32 + read-only + 0x0 + 0x80000000 + + + VALID + Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. + [31:31] + read-only + + + + + DESCR_CTL + Channel descriptor control + 0x60 + 32 + read-only + 0x0 + 0x0 + + + WAIT_FOR_DEACT + Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. +'0': Do not wait for trigger de-activation (for pulse sensitive triggers). +'1': Wait for up to 4 cycles. +'2': Wait for up to 16 cycles. +'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. + [1:0] + read-only + + + INTR_TYPE + Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): +'0': An interrupt is generated after a single transfer. +'1': An interrupt is generated after a single 1D transfer or a memory copy transfer +- If the descriptor type is 'single', the interrupt is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. +'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). +'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [3:2] + read-only + + + TR_OUT_TYPE + Specifies when an output trigger is generated: +'0': An output trigger is generated after a single transfer. +'1': An output trigger is generated after a single 1D transfer or a memory copy transfer. +- If the descriptor type is 'single', the output trigger is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. +'2': An output trigger is generated after the execution of the current descriptor. +'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [5:4] + read-only + + + TR_IN_TYPE + Specifies the input trigger type (not to be confused with the descriptor type): +'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. +'1': A trigger results in the execution of a single 1D transfer. +- If the descriptor type is 'single', the trigger results in the execution of a single transfer. +- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. +'2': A trigger results in the execution of the current descriptor. +'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. + [7:6] + read-only + + + DATA_PREFETCH + Source data prefetch: +'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. +'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. + +Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. + [8:8] + read-only + + + DATA_SIZE + Specifies the data element size: +'0': Byte (8 bits). +'1': Halfword (16 bits). +'2': Word (32 bits). +DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: +- DATA is 8 bit, SRC is 8 bit, DST is 8 bit. +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. +- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). +- DATA is 16 bit, SRC is 16 bit, DST is 16 bit. +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. +- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). +- DATA is 32 bit, SRC is 32 bit, DST is 32 bit. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. + [17:16] + read-only + + + CH_DISABLE + Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): +'0': Channel is not disabled. +'1': Channel is disabled. + [24:24] + read-only + + + SRC_TRANSFER_SIZE + Specifies the bus transfer size to the source location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [26:26] + read-only + + + DST_TRANSFER_SIZE + Specifies the bus transfer size to the destination location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [27:27] + read-only + + + DESCR_TYPE + Specifies the descriptor type (not to be confused with the trigger type): +'0': Single transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. +'1': 1D transfer. +The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. +'2': 2D transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. +'3': Memory copy. +The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. +'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. +'5'-'7': Undefined. + +After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. + [30:28] + read-only + + + + + DESCR_SRC + Channel descriptor source + 0x64 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of source location. + [31:0] + read-only + + + + + DESCR_DST + Channel descriptor destination + 0x68 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of destination location. + [31:0] + read-only + + + + + DESCR_X_SIZE + Channel descriptor X size + 0x6C + 32 + read-only + 0x0 + 0x0 + + + X_COUNT + Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + +For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. + [15:0] + read-only + + + + + DESCR_X_INCR + Channel descriptor X increment + 0x70 + 32 + read-only + 0x0 + 0x0 + + + SRC_X + Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + [15:0] + read-only + + + DST_X + Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + [31:16] + read-only + + + + + DESCR_Y_SIZE + Channel descriptor Y size + 0x74 + 32 + read-only + 0x0 + 0x0 + + + Y_COUNT + Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + [15:0] + read-only + + + + + DESCR_Y_INCR + Channel descriptor Y increment + 0x78 + 32 + read-only + 0x0 + 0x0 + + + SRC_Y + Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [15:0] + read-only + + + DST_Y + Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [31:16] + read-only + + + + + DESCR_NEXT + Channel descriptor next pointer + 0x7C + 32 + read-only + 0x0 + 0x0 + + + PTR + Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + INTR + Interrupt + 0x80 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. + [0:0] + read-write + + + SRC_BUS_ERROR + Activated (set to '1') on a bus error for a load from the source. + [1:1] + read-write + + + DST_BUS_ERROR + Activated (set to '1') on a bus error for a store to the destination. + [2:2] + read-write + + + SRC_MISAL + Activated (set to '1') on a misalignment of the source address. + [3:3] + read-write + + + DST_MISAL + Activated (set to '1') on a misalignment of the destination address. + [4:4] + read-write + + + CURR_PTR_NULL + Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. + [6:6] + read-write + + + DESCR_BUS_ERROR + Activated (set to '1') on a bus error for a load of the descriptor. + [7:7] + read-write + + + + + INTR_SET + Interrupt set + 0x84 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). + [0:0] + read-write + + + SRC_BUS_ERROR + Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). + [1:1] + read-write + + + DST_BUS_ERROR + Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). + [2:2] + read-write + + + SRC_MISAL + Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). + [3:3] + read-write + + + DST_MISAL + Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). + [4:4] + read-write + + + CURR_PTR_NULL + Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). + [6:6] + read-write + + + DESCR_BUS_ERROR + Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask + 0x88 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Mask for INTR.COMPLETION interrupt. + [0:0] + read-write + + + SRC_BUS_ERROR + Mask for INTR.SRC_BUS_ERROR interrupt. + [1:1] + read-write + + + DST_BUS_ERROR + Mask for INTR.DST_BUS_ERROR interrupt. + [2:2] + read-write + + + SRC_MISAL + Mask for INTR.SRC_MISAL interrupt. + [3:3] + read-write + + + DST_MISAL + Mask for INTR.DST_MISAL interrupt. + [4:4] + read-write + + + CURR_PTR_NULL + Mask for INTR.CURR_PTR_NULL interrupt. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Mask for INTR.ACTIVE_CH_DISABLED interrupt. + [6:6] + read-write + + + DESCR_BUS_ERROR + Mask for INTR.DESCR_BUS_ERROR interrupt. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x8C + 32 + read-only + 0x0 + 0xFF + + + COMPLETION + Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. + [0:0] + read-only + + + SRC_BUS_ERROR + Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. + [1:1] + read-only + + + DST_BUS_ERROR + Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. + [2:2] + read-only + + + SRC_MISAL + Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. + [3:3] + read-only + + + DST_MISAL + Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. + [4:4] + read-only + + + CURR_PTR_NULL + Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. + [5:5] + read-only + + + ACTIVE_CH_DISABLED + Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. + [6:6] + read-only + + + DESCR_BUS_ERROR + Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. + [7:7] + read-only + + + + + + + + EFUSE + EFUSE MXS40 registers + 0x402C0000 + + 0 + 128 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + + + CMD + Command + 0x10 + 32 + read-write + 0x1 + 0x800F1F71 + + + BIT_DATA + Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. + [0:0] + read-write + + + BIT_ADDR + Bit address. This field specifies a bit within a Byte. + [6:4] + read-write + + + BYTE_ADDR + Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). + [12:8] + read-write + + + MACRO_ADDR + Macro address. This field specifies an eFUSE macro. + [19:16] + read-write + + + START + FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. + +Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. + +Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. + +Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. + [31:31] + read-write + + + + + SEQ_DEFAULT + Sequencer Default value + 0x20 + 32 + read-write + 0x1D0000 + 0x7F0000 + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + + + SEQ_READ_CTL_0 + Sequencer read control 0 + 0x40 + 32 + read-write + 0x80560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_1 + Sequencer read control 1 + 0x44 + 32 + read-write + 0x540004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_2 + Sequencer read control 2 + 0x48 + 32 + read-write + 0x560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_3 + Sequencer read control 3 + 0x4C + 32 + read-write + 0x540003 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_4 + Sequencer read control 4 + 0x50 + 32 + read-write + 0x80150001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_5 + Sequencer read control 5 + 0x54 + 32 + read-write + 0x310004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_0 + Sequencer program control 0 + 0x60 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_1 + Sequencer program control 1 + 0x64 + 32 + read-write + 0x220020 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_2 + Sequencer program control 2 + 0x68 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_3 + Sequencer program control 3 + 0x6C + 32 + read-write + 0x310005 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_4 + Sequencer program control 4 + 0x70 + 32 + read-write + 0x80350006 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_5 + Sequencer program control 5 + 0x74 + 32 + read-write + 0x803D0019 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + + + HSIOM + High Speed IO Matrix (HSIOM) + 0x40300000 + + 0 + 16384 + registers + + + + 15 + 16 + PRT[%s] + HSIOM port registers + 0x00000000 + + PORT_SEL0 + Port selection 0 + 0x0 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO0_SEL + Selects connection for IO pin 0 route. + [4:0] + read-write + + + GPIO + GPIO controls 'out' + 0 + + + GPIO_DSI + GPIO controls 'out', DSI controls 'output enable' + 1 + + + DSI_DSI + DSI controls 'out' and 'output enable' + 2 + + + DSI_GPIO + DSI controls 'out', GPIO controls 'output enable' + 3 + + + AMUXA + Analog mux bus A + 4 + + + AMUXB + Analog mux bus B + 5 + + + AMUXA_DSI + Analog mux bus A, DSI control + 6 + + + AMUXB_DSI + Analog mux bus B, DSI control + 7 + + + ACT_0 + Active functionality 0 + 8 + + + ACT_1 + Active functionality 1 + 9 + + + ACT_2 + Active functionality 2 + 10 + + + ACT_3 + Active functionality 3 + 11 + + + DS_0 + DeepSleep functionality 0 + 12 + + + DS_1 + DeepSleep functionality 1 + 13 + + + DS_2 + DeepSleep functionality 2 + 14 + + + DS_3 + DeepSleep functionality 3 + 15 + + + ACT_4 + Active functionality 4 + 16 + + + ACT_5 + Active functionality 5 + 17 + + + ACT_6 + Active functionality 6 + 18 + + + ACT_7 + Active functionality 7 + 19 + + + ACT_8 + Active functionality 8 + 20 + + + ACT_9 + Active functionality 9 + 21 + + + ACT_10 + Active functionality 10 + 22 + + + ACT_11 + Active functionality 11 + 23 + + + ACT_12 + Active functionality 12 + 24 + + + ACT_13 + Active functionality 13 + 25 + + + ACT_14 + Active functionality 14 + 26 + + + ACT_15 + Active functionality 15 + 27 + + + DS_4 + DeepSleep functionality 4 + 28 + + + DS_5 + DeepSleep functionality 5 + 29 + + + DS_6 + DeepSleep functionality 6 + 30 + + + DS_7 + DeepSleep functionality 7 + 31 + + + + + IO1_SEL + Selects connection for IO pin 1 route. + [12:8] + read-write + + + IO2_SEL + Selects connection for IO pin 2 route. + [20:16] + read-write + + + IO3_SEL + Selects connection for IO pin 3 route. + [28:24] + read-write + + + + + PORT_SEL1 + Port selection 1 + 0x4 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO4_SEL + Selects connection for IO pin 4 route. +See PORT_SEL0 for connection details. + [4:0] + read-write + + + IO5_SEL + Selects connection for IO pin 5 route. + [12:8] + read-write + + + IO6_SEL + Selects connection for IO pin 6 route. + [20:16] + read-write + + + IO7_SEL + Selects connection for IO pin 7 route. + [28:24] + read-write + + + + + + 64 + 4 + AMUX_SPLIT_CTL[%s] + AMUX splitter cell control + 0x2000 + 32 + read-write + 0x0 + 0x77 + + + SWITCH_AA_SL + T-switch control for Left AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [0:0] + read-write + + + SWITCH_AA_SR + T-switch control for Right AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [1:1] + read-write + + + SWITCH_AA_S0 + T-switch control for AMUXBUSA vssa/ground switch: +'0': switch open. +'1': switch closed. + [2:2] + read-write + + + SWITCH_BB_SL + T-switch control for Left AMUXBUSB switch. + [4:4] + read-write + + + SWITCH_BB_SR + T-switch control for Right AMUXBUSB switch. + [5:5] + read-write + + + SWITCH_BB_S0 + T-switch control for AMUXBUSB vssa/ground switch. + [6:6] + read-write + + + + + MONITOR_CTL_0 + Power/Ground Monitor cell control 0 + 0x2200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_1 + Power/Ground Monitor cell control 1 + 0x2204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_2 + Power/Ground Monitor cell control 2 + 0x2208 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_3 + Power/Ground Monitor cell control 3 + 0x220C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + ALT_JTAG_EN + Alternate JTAG IF selection register + 0x2240 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + Provides the selection for alternate JTAG IF connectivity. +0: Primary JTAG interface is selected +1: Secondary (alternate) JTAG interface is selected. + +This connectivity works ONLY in ACTIVE mode. + [31:31] + read-write + + + + + + + GPIO + GPIO port control/configuration + 0x40310000 + + 0 + 65536 + registers + + + + 15 + 128 + PRT[%s] + GPIO port registers + 0x00000000 + + OUT + Port output data register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO output data for pin 0 +'0': Output state set to '0' +'1': Output state set to '1' + [0:0] + read-write + + + OUT1 + IO output data for pin 1 + [1:1] + read-write + + + OUT2 + IO output data for pin 2 + [2:2] + read-write + + + OUT3 + IO output data for pin 3 + [3:3] + read-write + + + OUT4 + IO output data for pin 4 + [4:4] + read-write + + + OUT5 + IO output data for pin 5 + [5:5] + read-write + + + OUT6 + IO output data for pin 6 + [6:6] + read-write + + + OUT7 + IO output data for pin 7 + [7:7] + read-write + + + + + OUT_CLR + Port output data clear register + 0x4 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO clear output for pin 0: +'0': Output state not affected. +'1': Output state set to '0'. + [0:0] + read-write + + + OUT1 + IO clear output for pin 1 + [1:1] + read-write + + + OUT2 + IO clear output for pin 2 + [2:2] + read-write + + + OUT3 + IO clear output for pin 3 + [3:3] + read-write + + + OUT4 + IO clear output for pin 4 + [4:4] + read-write + + + OUT5 + IO clear output for pin 5 + [5:5] + read-write + + + OUT6 + IO clear output for pin 6 + [6:6] + read-write + + + OUT7 + IO clear output for pin 7 + [7:7] + read-write + + + + + OUT_SET + Port output data set register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO set output for pin 0: +'0': Output state not affected. +'1': Output state set to '1'. + [0:0] + read-write + + + OUT1 + IO set output for pin 1 + [1:1] + read-write + + + OUT2 + IO set output for pin 2 + [2:2] + read-write + + + OUT3 + IO set output for pin 3 + [3:3] + read-write + + + OUT4 + IO set output for pin 4 + [4:4] + read-write + + + OUT5 + IO set output for pin 5 + [5:5] + read-write + + + OUT6 + IO set output for pin 6 + [6:6] + read-write + + + OUT7 + IO set output for pin 7 + [7:7] + read-write + + + + + OUT_INV + Port output data invert register + 0xC + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO invert output for pin 0: +'0': Output state not affected. +'1': Output state inverted ('0' => '1', '1' => '0'). + [0:0] + read-write + + + OUT1 + IO invert output for pin 1 + [1:1] + read-write + + + OUT2 + IO invert output for pin 2 + [2:2] + read-write + + + OUT3 + IO invert output for pin 3 + [3:3] + read-write + + + OUT4 + IO invert output for pin 4 + [4:4] + read-write + + + OUT5 + IO invert output for pin 5 + [5:5] + read-write + + + OUT6 + IO invert output for pin 6 + [6:6] + read-write + + + OUT7 + IO invert output for pin 7 + [7:7] + read-write + + + + + IN + Port input state register + 0x10 + 32 + read-only + 0x0 + 0x1FF + + + IN0 + IO pin state for pin 0 +'0': Low logic level present on pin. +'1': High logic level present on pin. +On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. + [0:0] + read-only + + + IN1 + IO pin state for pin 1 + [1:1] + read-only + + + IN2 + IO pin state for pin 2 + [2:2] + read-only + + + IN3 + IO pin state for pin 3 + [3:3] + read-only + + + IN4 + IO pin state for pin 4 + [4:4] + read-only + + + IN5 + IO pin state for pin 5 + [5:5] + read-only + + + IN6 + IO pin state for pin 6 + [6:6] + read-only + + + IN7 + IO pin state for pin 7 + [7:7] + read-only + + + FLT_IN + Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. + [8:8] + read-only + + + + + INTR + Port interrupt status register + 0x14 + 32 + read-write + 0x0 + 0x1FF01FF + + + EDGE0 + Edge detect for IO pin 0 +'0': No edge was detected on pin. +'1': An edge was detected on pin. + [0:0] + read-write + + + EDGE1 + Edge detect for IO pin 1 + [1:1] + read-write + + + EDGE2 + Edge detect for IO pin 2 + [2:2] + read-write + + + EDGE3 + Edge detect for IO pin 3 + [3:3] + read-write + + + EDGE4 + Edge detect for IO pin 4 + [4:4] + read-write + + + EDGE5 + Edge detect for IO pin 5 + [5:5] + read-write + + + EDGE6 + Edge detect for IO pin 6 + [6:6] + read-write + + + EDGE7 + Edge detect for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Edge detected on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + IN_IN0 + IO pin state for pin 0 + [16:16] + read-only + + + IN_IN1 + IO pin state for pin 1 + [17:17] + read-only + + + IN_IN2 + IO pin state for pin 2 + [18:18] + read-only + + + IN_IN3 + IO pin state for pin 3 + [19:19] + read-only + + + IN_IN4 + IO pin state for pin 4 + [20:20] + read-only + + + IN_IN5 + IO pin state for pin 5 + [21:21] + read-only + + + IN_IN6 + IO pin state for pin 6 + [22:22] + read-only + + + IN_IN7 + IO pin state for pin 7 + [23:23] + read-only + + + FLT_IN_IN + Filtered pin state for pin selected by INTR_CFG.FLT_SEL + [24:24] + read-only + + + + + INTR_MASK + Port interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Masks edge interrupt on IO pin 0 +'0': Pin interrupt forwarding disabled +'1': Pin interrupt forwarding enabled + [0:0] + read-write + + + EDGE1 + Masks edge interrupt on IO pin 1 + [1:1] + read-write + + + EDGE2 + Masks edge interrupt on IO pin 2 + [2:2] + read-write + + + EDGE3 + Masks edge interrupt on IO pin 3 + [3:3] + read-write + + + EDGE4 + Masks edge interrupt on IO pin 4 + [4:4] + read-write + + + EDGE5 + Masks edge interrupt on IO pin 5 + [5:5] + read-write + + + EDGE6 + Masks edge interrupt on IO pin 6 + [6:6] + read-write + + + EDGE7 + Masks edge interrupt on IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_MASKED + Port interrupt masked status register + 0x1C + 32 + read-only + 0x0 + 0x1FF + + + EDGE0 + Edge detected AND masked on IO pin 0 +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [0:0] + read-only + + + EDGE1 + Edge detected and masked on IO pin 1 + [1:1] + read-only + + + EDGE2 + Edge detected and masked on IO pin 2 + [2:2] + read-only + + + EDGE3 + Edge detected and masked on IO pin 3 + [3:3] + read-only + + + EDGE4 + Edge detected and masked on IO pin 4 + [4:4] + read-only + + + EDGE5 + Edge detected and masked on IO pin 5 + [5:5] + read-only + + + EDGE6 + Edge detected and masked on IO pin 6 + [6:6] + read-only + + + EDGE7 + Edge detected and masked on IO pin 7 + [7:7] + read-only + + + FLT_EDGE + Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-only + + + + + INTR_SET + Port interrupt set register + 0x20 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Sets edge detect interrupt for IO pin 0 +'0': Interrupt state not affected +'1': Interrupt set + [0:0] + read-write + + + EDGE1 + Sets edge detect interrupt for IO pin 1 + [1:1] + read-write + + + EDGE2 + Sets edge detect interrupt for IO pin 2 + [2:2] + read-write + + + EDGE3 + Sets edge detect interrupt for IO pin 3 + [3:3] + read-write + + + EDGE4 + Sets edge detect interrupt for IO pin 4 + [4:4] + read-write + + + EDGE5 + Sets edge detect interrupt for IO pin 5 + [5:5] + read-write + + + EDGE6 + Sets edge detect interrupt for IO pin 6 + [6:6] + read-write + + + EDGE7 + Sets edge detect interrupt for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_CFG + Port interrupt configuration register + 0x40 + 32 + read-write + 0x0 + 0x1FFFFF + + + EDGE0_SEL + Sets which edge will trigger an IRQ for IO pin 0 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + EDGE1_SEL + Sets which edge will trigger an IRQ for IO pin 1 + [3:2] + read-write + + + EDGE2_SEL + Sets which edge will trigger an IRQ for IO pin 2 + [5:4] + read-write + + + EDGE3_SEL + Sets which edge will trigger an IRQ for IO pin 3 + [7:6] + read-write + + + EDGE4_SEL + Sets which edge will trigger an IRQ for IO pin 4 + [9:8] + read-write + + + EDGE5_SEL + Sets which edge will trigger an IRQ for IO pin 5 + [11:10] + read-write + + + EDGE6_SEL + Sets which edge will trigger an IRQ for IO pin 6 + [13:12] + read-write + + + EDGE7_SEL + Sets which edge will trigger an IRQ for IO pin 7 + [15:14] + read-write + + + FLT_EDGE_SEL + Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + FLT_SEL + Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. + [20:18] + read-write + + + + + CFG + Port configuration register + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DRIVE_MODE0 + The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [2:0] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Weak/resistive pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull up + D_OUT = '1': Weak/resistive pull up + 2 + + + PULLDOWN + Resistive pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': High Impedance +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 4 + + + OD_DRIVESHIGH + Open drain, drives high + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': High Impedance + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 5 + + + STRONG + Strong D_OUTput buffer + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 6 + + + PULLUP_DOWN + Pull up or pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = '0': + GPIO_DSI_OUT = '0': Weak/resistive pull down + GPIO_DSI_OUT = '1': Weak/resistive pull up +where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull up + 7 + + + + + IN_EN0 + Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. +'0': Input buffer disabled +'1': Input buffer enabled + [3:3] + read-write + + + DRIVE_MODE1 + The GPIO drive mode for IO pin 1 + [6:4] + read-write + + + IN_EN1 + Enables the input buffer for IO pin 1 + [7:7] + read-write + + + DRIVE_MODE2 + The GPIO drive mode for IO pin 2 + [10:8] + read-write + + + IN_EN2 + Enables the input buffer for IO pin 2 + [11:11] + read-write + + + DRIVE_MODE3 + The GPIO drive mode for IO pin 3 + [14:12] + read-write + + + IN_EN3 + Enables the input buffer for IO pin 3 + [15:15] + read-write + + + DRIVE_MODE4 + The GPIO drive mode for IO pin4 + [18:16] + read-write + + + IN_EN4 + Enables the input buffer for IO pin 4 + [19:19] + read-write + + + DRIVE_MODE5 + The GPIO drive mode for IO pin 5 + [22:20] + read-write + + + IN_EN5 + Enables the input buffer for IO pin 5 + [23:23] + read-write + + + DRIVE_MODE6 + The GPIO drive mode for IO pin 6 + [26:24] + read-write + + + IN_EN6 + Enables the input buffer for IO pin 6 + [27:27] + read-write + + + DRIVE_MODE7 + The GPIO drive mode for IO pin 7 + [30:28] + read-write + + + IN_EN7 + Enables the input buffer for IO pin 7 + [31:31] + read-write + + + + + CFG_IN + Port input buffer configuration register + 0x48 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_0 + Configures the pin 0 input buffer mode (trip points and hysteresis) + [0:0] + read-write + + + CMOS + PSoC 6:: Input buffer compatible with CMOS and I2C interfaces +Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 0 + + + TTL + PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces +Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 1 + + + + + VTRIP_SEL1_0 + Configures the pin 1 input buffer mode (trip points and hysteresis) + [1:1] + read-write + + + VTRIP_SEL2_0 + Configures the pin 2 input buffer mode (trip points and hysteresis) + [2:2] + read-write + + + VTRIP_SEL3_0 + Configures the pin 3 input buffer mode (trip points and hysteresis) + [3:3] + read-write + + + VTRIP_SEL4_0 + Configures the pin 4 input buffer mode (trip points and hysteresis) + [4:4] + read-write + + + VTRIP_SEL5_0 + Configures the pin 5 input buffer mode (trip points and hysteresis) + [5:5] + read-write + + + VTRIP_SEL6_0 + Configures the pin 6 input buffer mode (trip points and hysteresis) + [6:6] + read-write + + + VTRIP_SEL7_0 + Configures the pin 7 input buffer mode (trip points and hysteresis) + [7:7] + read-write + + + + + CFG_OUT + Port output buffer configuration register + 0x4C + 32 + read-write + 0x0 + 0xFFFF00FF + + + SLOW0 + Enables slow slew rate for IO pin 0 +'0': Fast slew rate +'1': Slow slew rate + [0:0] + read-write + + + SLOW1 + Enables slow slew rate for IO pin 1 + [1:1] + read-write + + + SLOW2 + Enables slow slew rate for IO pin 2 + [2:2] + read-write + + + SLOW3 + Enables slow slew rate for IO pin 3 + [3:3] + read-write + + + SLOW4 + Enables slow slew rate for IO pin 4 + [4:4] + read-write + + + SLOW5 + Enables slow slew rate for IO pin 5 + [5:5] + read-write + + + SLOW6 + Enables slow slew rate for IO pin 6 + [6:6] + read-write + + + SLOW7 + Enables slow slew rate for IO pin 7 + [7:7] + read-write + + + DRIVE_SEL0 + Sets the GPIO drive strength for IO pin 0 + [17:16] + read-write + + + DRIVE_SEL_ZERO + Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +Traveo II:_GPIO_SMC: GPIO_SMC default mode. +Traveo II:_HSIO_STD: HSIO default mode. +PSoC 6: GPIO cells and HSIO_STD cells: Full drive strength: GPIO drives current at its max rated spec. + 0 + + + DRIVE_SEL_ONE + Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +Traveo II:_GPIO_SMC: GPIO full drive strength. +Traveo II:_HSIO_STD: GPIO full drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec + 1 + + + DRIVE_SEL_TWO + Traveo II: GPIO_STD/GPIO_ENH: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec. +Traveo II:_GPIO_SMC: GPIO 1/2 drive strength. +Traveo II:_HSIO_STD: GPIO 1/2 drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/4 drive strength. GPIO drives current at 1/4 of its max rated spec. + 2 + + + DRIVE_SEL_THREE + Traveo II: GPIO_STD/GPIO_ENH: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec. +Traveo II:_GPIO_SMC: GPIO 1/4 drive strength. +Traveo II:_HSIO_STD: GPIO 1/4 drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/8 drive strength. GPIO drives current at 1/8 of its max rated spec. + 3 + + + + + DRIVE_SEL1 + Sets the GPIO drive strength for IO pin 1 + [19:18] + read-write + + + DRIVE_SEL2 + Sets the GPIO drive strength for IO pin 2 + [21:20] + read-write + + + DRIVE_SEL3 + Sets the GPIO drive strength for IO pin 3 + [23:22] + read-write + + + DRIVE_SEL4 + Sets the GPIO drive strength for IO pin 4 + [25:24] + read-write + + + DRIVE_SEL5 + Sets the GPIO drive strength for IO pin 5 + [27:26] + read-write + + + DRIVE_SEL6 + Sets the GPIO drive strength for IO pin 6 + [29:28] + read-write + + + DRIVE_SEL7 + Sets the GPIO drive strength for IO pin 7 + [31:30] + read-write + + + + + CFG_SIO + Port SIO configuration register + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VREG_EN01 + Selects the output buffer mode: +'0': Unregulated output buffer +'1': Regulated output buffer +The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. + [0:0] + read-write + + + IBUF_SEL01 + Selects the input buffer mode: +0: Singled ended input buffer +1: Differential input buffer + [1:1] + read-write + + + VTRIP_SEL01 + Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): +'0': Input buffer functions as a CMOS input buffer. +'1': Input buffer functions as a TTL input buffer. +In differential input buffer mode (IBUF_SEL = '1') +'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) +'1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) + [2:2] + read-write + + + VREF_SEL01 + Selects reference voltage (Vref) trip-point of the input buffer: +'0': Trip-point reference from pin_ref +'1': Trip-point reference of SRSS internal reference Vref (1.2 V) +'2': Trip-point reference of AMUXBUS_A +'3': Trip-point reference of AMUXBUS_B + [4:3] + read-write + + + VOH_SEL01 + Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). +'0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V +'1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V +'2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V +'3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V +'4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V +'5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V +'6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V +'7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V +Note: The upper value on Voh is limited to Vddio - 400mV + [7:5] + read-write + + + VREG_EN23 + See corresponding definition for IO pins 0 and 1 + [8:8] + read-write + + + IBUF_SEL23 + See corresponding definition for IO pins 0 and 1 + [9:9] + read-write + + + VTRIP_SEL23 + See corresponding definition for IO pins 0 and 1 + [10:10] + read-write + + + VREF_SEL23 + See corresponding definition for IO pins 0 and 1 + [12:11] + read-write + + + VOH_SEL23 + See corresponding definition for IO pins 0 and 1 + [15:13] + read-write + + + VREG_EN45 + See corresponding definition for IO pins 0 and 1 + [16:16] + read-write + + + IBUF_SEL45 + See corresponding definition for IO pins 0 and 1 + [17:17] + read-write + + + VTRIP_SEL45 + See corresponding definition for IO pins 0 and 1 + [18:18] + read-write + + + VREF_SEL45 + See corresponding definition for IO pins 0 and 1 + [20:19] + read-write + + + VOH_SEL45 + See corresponding definition for IO pins 0 and 1 + [23:21] + read-write + + + VREG_EN67 + See corresponding definition for IO pins 0 and 1 + [24:24] + read-write + + + IBUF_SEL67 + See corresponding definition for IO pins 0 and 1 + [25:25] + read-write + + + VTRIP_SEL67 + See corresponding definition for IO pins 0 and 1 + [26:26] + read-write + + + VREF_SEL67 + See corresponding definition for IO pins 0 and 1 + [28:27] + read-write + + + VOH_SEL67 + See corresponding definition for IO pins 0 and 1 + [31:29] + read-write + + + + + CFG_IN_AUTOLVL + Port input buffer AUTOLVL configuration register + 0x58 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_1 + Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: +{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: +0,0: CMOS +0,1: TTL +1,0: input buffer is compatible with automotive. +1,1: input buffer is compatible with automotvie + [0:0] + read-write + + + CMOS_OR_TTL + Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. + 0 + + + AUTO + Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. + 1 + + + + + VTRIP_SEL1_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [1:1] + read-write + + + VTRIP_SEL2_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [2:2] + read-write + + + VTRIP_SEL3_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [3:3] + read-write + + + VTRIP_SEL4_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [4:4] + read-write + + + VTRIP_SEL5_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [5:5] + read-write + + + VTRIP_SEL6_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [6:6] + read-write + + + VTRIP_SEL7_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [7:7] + read-write + + + + + + INTR_CAUSE0 + Interrupt port cause register 0 + 0x4000 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE1 + Interrupt port cause register 1 + 0x4004 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE2 + Interrupt port cause register 2 + 0x4008 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE3 + Interrupt port cause register 3 + 0x400C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + VDD_ACTIVE + Extern power supply detection register + 0x4010 + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. +'0': Supply is not present +'1': Supply is present + +When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. +For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: +0: vbackup, +1: vddio_0, +2: vddio_1, +3: vddio_a, +4: vddio_r, +5: vddusb' + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) + [31:31] + read-only + + + + + VDD_INTR + Supply detection interrupt register + 0x4014 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply state change detected. +'0': No change to supply detected +'1': Change to supply detected + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. + [31:31] + read-write + + + + + VDD_INTR_MASK + Supply detection interrupt mask register + 0x4018 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Masks supply interrupt on VDDIO. +'0': VDDIO interrupt forwarding disabled +'1': VDDIO interrupt forwarding enabled + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + VDD_INTR_MASKED + Supply detection interrupt masked register + 0x401C + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply transition detected AND masked +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-only + + + + + VDD_INTR_SET + Supply detection interrupt set register + 0x4020 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Sets supply interrupt. +'0': Interrupt state not affected +'1': Interrupt set + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + + + SMARTIO + Programmable IO configuration + 0x40320000 + + 0 + 65536 + registers + + + + 10 + 256 + PRT[%s] + Programmable IO port registers + 0x00000000 + + CTL + Control register + 0x0 + 32 + read-write + 0x2001400 + 0x82001F00 + + + BYPASS + Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. +'0': No bypass (programmable SMARTIO fabric is exposed). +'1': Bypass (programmable SMARTIOIO fabric is hidden). + [7:0] + read-write + + + CLOCK_SRC + Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: +'0': io_data_in[0]/'1'. +... +'7': io_data_in[7]/'1'. +'8': chip_data[0]/'1'. +... +'15': chip_data[7]/'1'. +'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. +'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. +'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. +'31': asynchronous mode/'1'. Select this when clockless operation is configured. + +NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. + [12:8] + read-write + + + HLD_OVR + IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: +'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). +'1': The SMARTIO controls the IO cel hold override functionality: +- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. +- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). + [24:24] + read-write + + + PIPELINE_EN + Enable for pipeline register: +'0': Disabled (register is bypassed). +'1': Enabled. + [25:25] + read-write + + + ENABLED + Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: +'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. + +If the IP is disabled: +- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. +- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. + +'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. + [31:31] + read-write + + + + + SYNC_CTL + Synchronization control register + 0x10 + 32 + read-write + 0x0 + 0x0 + + + IO_SYNC_EN + Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. +'0': No synchronization. +'1': Synchronization. + [7:0] + read-write + + + CHIP_SYNC_EN + Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. +'0': No synchronization. +'1': Synchronization. + [15:8] + read-write + + + + + 8 + 4 + LUT_SEL[%s] + LUT component input selection + 0x20 + 32 + read-write + 0x0 + 0x0 + + + LUT_TR0_SEL + LUT input signal 'tr0_in' source selection: +'0': Data unit output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [3:0] + read-write + + + LUT_TR1_SEL + LUT input signal 'tr1_in' source selection: +'0': LUT 0 output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [11:8] + read-write + + + LUT_TR2_SEL + LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. + [19:16] + read-write + + + + + 8 + 4 + LUT_CTL[%s] + LUT component control register + 0x40 + 32 + read-write + 0x0 + 0x0 + + + LUT + LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). + [7:0] + read-write + + + LUT_OPC + LUT opcode specifies the LUT operation: +'0': Combinatoral output, no feedback. + tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. +'1': Combinatorial output, feedback. + tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. +On clock: + lut_reg <= tr_in2. +'2': Sequential output, no feedback. + temp = LUT[{tr2_in, tr1_in, tr0_in}]. + tr_out = lut_reg. +On clock: + lut_reg <= temp. +'3': Register with asynchronous set and reset. + tr_out = lut_reg. + enable = (tr2_in ^ LUT[4]) | LUT[5]. + set = enable & (tr1_in ^ LUT[2]) & LUT[3]. + clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. +Asynchronously (no clock required): + lut_reg <= if (clr) '0' else if (set) '1' + [9:8] + read-write + + + + + DU_SEL + Data unit component input selection + 0xC0 + 32 + read-write + 0x0 + 0x0 + + + DU_TR0_SEL + Data unit input signal 'tr0_in' source selection: +'0': Constant '0'. +'1': Constant '1'. +'2': Data unit output. +'10-3': LUT 7 - 0 outputs. +Otherwise: Undefined. + [3:0] + read-write + + + DU_TR1_SEL + Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. + [11:8] + read-write + + + DU_TR2_SEL + Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. + [19:16] + read-write + + + DU_DATA0_SEL + Data unit input data 'data0_in' source selection: +'0': Constant '0'. +'1': chip_data[7:0]. +'2': io_data_in[7:0]. +'3': DATA.DATA MMIO register field. + [25:24] + read-write + + + DU_DATA1_SEL + Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. + [29:28] + read-write + + + + + DU_CTL + Data unit component control register + 0xC4 + 32 + read-write + 0x0 + 0x0 + + + DU_SIZE + Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. + [2:0] + read-write + + + DU_OPC + Data unit opcode specifies the data unit operation: +'1': INCR +'2': DECR +'3': INCR_WRAP +'4': DECR_WRAP +'5': INCR_DECR +'6': INCR_DECR_WRAP +'7': ROR +'8': SHR +'9': AND_OR +'10': SHR_MAJ3 +'11': SHR_EQL. +Otherwise: Undefined. + [11:8] + read-write + + + + + DATA + Data register + 0xF0 + 32 + read-write + 0x0 + 0x0 + + + DATA + Data unit input data source. + [7:0] + read-write + + + + + + + + LPCOMP + Low Power Comparators + 0x40350000 + + 0 + 65536 + registers + + + + CONFIG + LPCOMP Configuration Register + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + LPREF_EN + Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. + [30:30] + read-write + + + ENABLED + - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) +- 1: IP enabled + [31:31] + read-write + + + + + STATUS + LPCOMP Status Register + 0x4 + 32 + read-only + 0x0 + 0x10001 + + + OUT0 + Current output value of the comparator 0. + [0:0] + read-only + + + OUT1 + Current output value of the comparator 1. + [16:16] + read-only + + + + + INTR + LPCOMP Interrupt request register + 0x10 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + LPCOMP Interrupt set register + 0x14 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + LPCOMP Interrupt request mask + 0x18 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + LPCOMP Interrupt request masked + 0x1C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + CMP0_CTRL + Comparator 0 control Register + 0x40 + 32 + read-write + 0x0 + 0xCE3 + + + MODE0 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST0 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE0 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS0 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL0 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP0_SW + Comparator 0 switch control + 0x50 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + Comparator 0 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP0_AP0 + Comparator 0 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP0_BP0 + Comparator 0 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP0_IN0 + Comparator 0 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP0_AN0 + Comparator 0 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP0_BN0 + Comparator 0 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP0_VN0 + Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP0_SW_CLEAR + Comparator 0 switch control clear + 0x54 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + see corresponding bit in CMP0_SW + [0:0] + read-write + + + CMP0_AP0 + see corresponding bit in CMP0_SW + [1:1] + read-write + + + CMP0_BP0 + see corresponding bit in CMP0_SW + [2:2] + read-write + + + CMP0_IN0 + see corresponding bit in CMP0_SW + [4:4] + read-write + + + CMP0_AN0 + see corresponding bit in CMP0_SW + [5:5] + read-write + + + CMP0_BN0 + see corresponding bit in CMP0_SW + [6:6] + read-write + + + CMP0_VN0 + see corresponding bit in CMP0_SW + [7:7] + read-write + + + + + CMP1_CTRL + Comparator 1 control Register + 0x80 + 32 + read-write + 0x0 + 0xCE3 + + + MODE1 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST1 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE1 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS1 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL1 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP1_SW + Comparator 1 switch control + 0x90 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + Comparator 1 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP1_AP1 + Comparator 1 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP1_BP1 + Comparator 1 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP1_IN1 + Comparator 1 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP1_AN1 + Comparator 1 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP1_BN1 + Comparator 1 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP1_VN1 + Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP1_SW_CLEAR + Comparator 1 switch control clear + 0x94 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + see corresponding bit in CMP1_SW + [0:0] + read-write + + + CMP1_AP1 + see corresponding bit in CMP1_SW + [1:1] + read-write + + + CMP1_BP1 + see corresponding bit in CMP1_SW + [2:2] + read-write + + + CMP1_IN1 + see corresponding bit in CMP1_SW + [4:4] + read-write + + + CMP1_AN1 + see corresponding bit in CMP1_SW + [5:5] + read-write + + + CMP1_BN1 + see corresponding bit in CMP1_SW + [6:6] + read-write + + + CMP1_VN1 + see corresponding bit in CMP1_SW + [7:7] + read-write + + + + + + + CSD0 + Capsense Controller + CSD + 0x40360000 + + 0 + 4096 + registers + + + + CONFIG + Configuration and Control + 0x0 + 32 + read-write + 0x4000000 + 0xCF0E1DF1 + + + IREF_SEL + Select Iref supply. + [0:0] + read-write + + + IREF_SRSS + select SRSS Iref (default) + 0 + + + IREF_PASS + select PASS.AREF Iref, only available if PASS IP is on the chip. + 1 + + + + + FILTER_DELAY + This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on. +When set to 0 the digital filter is off. When set to any other value the ignoring will last for FILTER_DELAY clk_csd cycles after the start of each measurement and from the first comparator trip to the end of each measurement. + [8:4] + read-write + + + SHIELD_DELAY + Selects the delay by which csd_shield is delayed relative to csd_sense. + [11:10] + read-write + + + OFF + Delay line is off, csd_shield=csd_sense + 0 + + + D5NS + Introduces a 5ns delay (typ) + 1 + + + D10NS + Introduces a 10ns delay (typ) + 2 + + + D20NS + Introduces a 20ns delay (typ) + 3 + + + + + SENSE_EN + Enables the sense modulator output. +0: all switches, static or dynamic, are open and IDAC in CSD mode is off +1: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer. + [12:12] + read-write + + + FULL_WAVE + Enables full wave cap sensing mode + [17:17] + read-write + + + HALFWAVE + Half Wave mode (normal). +In this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change. + 0 + + + FULLWAVE + Full Wave mode. +In this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips. + 1 + + + + + MUTUAL_CAP + Enables mutual cap sensing mode + [18:18] + read-write + + + SELFCAP + Self-cap mode (configure sense line as CSD_SENSE) + 0 + + + MUTUALCAP + Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense. + 1 + + + + + CSX_DUAL_CNT + Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUTUAL_CAP=0 + [19:19] + read-write + + + ONE + Use one counter for both phases (source and sink). + 0 + + + TWO + Use two counters, separate count for when csd_sense is high and when csd_sense is low. + 1 + + + + + DSI_COUNT_SEL + Select what to output on the dsi_count bus. + [24:24] + read-write + + + CSD_RESULT + depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially. + 0 + + + ADC_RESULT + output ADC_RES.VIN_CNT on the dsi_count bus + 1 + + + + + DSI_SAMPLE_EN + Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER. + [25:25] + read-write + + + SAMPLE_SYNC + Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1). + [26:26] + read-write + + + DSI_SENSE_EN + Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals. + [27:27] + read-write + + + LP_MODE + Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP): +0: High Power mode +1: Low Power mode + [30:30] + read-write + + + ENABLE + Master enable of the CSDv2 IP. Must be set to 1 for any CSDv2, ADC or IDAC operation to function. +When 0 all analog components will be off and all switches will be open. + [31:31] + read-write + + + + + SPARE + Spare MMIO + 0x4 + 32 + read-write + 0x0 + 0xF + + + SPARE + Spare MMIO + [3:0] + read-write + + + + + STATUS + Status Register + 0x80 + 32 + read-only + 0x0 + 0xE + + + CSD_SENSE + Signal used to drive the Cs switches. + [1:1] + read-only + + + HSCMP_OUT + Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized) + [2:2] + read-only + + + C_LT_VREF + Vin < Vref + 0 + + + C_GT_VREF + Vin > Vref + 1 + + + + + CSDCMP_OUT + Output of main sensing comparator (synchronized) + [3:3] + read-only + + + + + STAT_SEQ + Current Sequencer status + 0x84 + 32 + read-only + 0x0 + 0x70007 + + + SEQ_STATE + CSD sequencer state + [2:0] + read-only + + + ADC_STATE + ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) + [18:16] + read-only + + + + + STAT_CNTS + Current status counts + 0x88 + 32 + read-only + 0x0 + 0xFFFF + + + NUM_CONV + Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) + [15:0] + read-only + + + + + STAT_HCNT + Current count of the HSCMP counter + 0x8C + 32 + read-only + 0x0 + 0xFFFF + + + CNT + Current value of HSCMP counter + [15:0] + read-only + + + + + RESULT_VAL1 + Result CSD/CSX accumulation counter value 1 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFF + + + VALUE + Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. + [15:0] + read-only + + + BAD_CONVS + Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. + [23:16] + read-only + + + + + RESULT_VAL2 + Result CSX accumulation counter value 2 + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + VALUE + Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. + [15:0] + read-only + + + + + ADC_RES + ADC measurement + 0xE0 + 32 + read-only + 0x0 + 0xC001FFFF + + + VIN_CNT + Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. + [15:0] + read-only + + + HSCMP_POL + Polarity used for IDACB for this last ADC result, 0= source, 1= sink + [16:16] + read-only + + + ADC_OVERFLOW + This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. + [30:30] + read-only + + + ADC_ABORT + This flag is set when the ADC sequencer was aborted before tripping HSCMP. + [31:31] + read-only + + + + + INTR + CSD Interrupt Request Register + 0xF0 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + A normal sample is complete + [1:1] + read-write + + + INIT + Coarse initialization complete or Sample initialization complete (the latter is typically ignored) + [2:2] + read-write + + + ADC_RES + ADC Result ready + [8:8] + read-write + + + + + INTR_SET + CSD Interrupt set register + 0xF4 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASK + CSD Interrupt mask register + 0xF8 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASKED + CSD Interrupt masked register + 0xFC + 32 + read-only + 0x0 + 0x106 + + + SAMPLE + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + INIT + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + ADC_RES + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + + + HSCMP + High Speed Comparator configuration + 0x180 + 32 + read-write + 0x0 + 0x80000011 + + + HSCMP_EN + High Speed Comparator enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + HSCMP_INVERT + Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT + [4:4] + read-write + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + AMBUF + Reference Generator configuration + 0x184 + 32 + read-write + 0x0 + 0x3 + + + PWR_MODE + Amux buffer power level + [1:0] + read-write + + + OFF + Disable buffer + 0 + + + NORM + On, normal or low power level depending on CONFIG.LP_MODE. + 1 + + + HI + On, high or low power level depending on CONFIG.LP_MODE. + 2 + + + + + + + REFGEN + Reference Generator configuration + 0x188 + 32 + read-write + 0x0 + 0x9F1F71 + + + REFGEN_EN + Reference Generator Enable + [0:0] + read-write + + + OFF + Disable Reference Generator + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + BYPASS + Bypass selected input reference unbuffered to Vrefhi + [4:4] + read-write + + + VDDA_EN + Close Vdda switch to top of resistor string (or Vrefhi?) + [5:5] + read-write + + + RES_EN + Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) + [6:6] + read-write + + + GAIN + Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) + [12:8] + read-write + + + VREFLO_SEL + Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) + [20:16] + read-write + + + VREFLO_INT + Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). + [23:23] + read-write + + + + + CSDCMP + CSD Comparator configuration + 0x18C + 32 + read-write + 0x0 + 0xB0000331 + + + CSDCMP_EN + CSD Comparator Enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + POLARITY_SEL + Select which IDAC polarity to use to detect CSDCMP triggering + [5:4] + read-write + + + IDACA_POL + Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX + 0 + + + IDACB_POL + Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) + 1 + + + DUAL_POL + Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case + 2 + + + + + CMP_PHASE + Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). + [9:8] + read-write + + + FULL + Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + Comparator is active during Phi1 only. Currently no known use-case. + 1 + + + PHI2 + Comparator is active during Phi2 only. Intended usage: CSD Low EMI. + 2 + + + PHI1_2 + Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. + 3 + + + + + CMP_MODE + Select which signal to output on dsi_sample_out. + [28:28] + read-write + + + CSD + CSD mode: output the filtered sample signal on dsi_sample_out + 0 + + + GP + General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. + 1 + + + + + FEEDBACK_MODE + This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. + [29:29] + read-write + + + FLOP + Use feedback from sampling flip-flop (used in most modes). + 0 + + + COMP + Use feedback from comparator directly (used in single Cmod mutual cap sensing only) + 1 + + + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + SW_RES + Switch Resistance configuration + 0x1F0 + 32 + read-write + 0x0 + 0xF00FF + + + RES_HCAV + Select resistance or low EMI (slow ramp) for the HCAV switch + [1:0] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + LOWEMI + Low EMI (slow ramp: 3 switches closed by fixed delay line) + 3 + + + + + RES_HCAG + Select resistance or low EMI for the corresponding switch + [3:2] + read-write + + + RES_HCBV + Select resistance or low EMI for the corresponding switch + [5:4] + read-write + + + RES_HCBG + Select resistance or low EMI for the corresponding switch + [7:6] + read-write + + + RES_F1PM + Select resistance for the corresponding switch + [17:16] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + RSVD + N/A + 3 + + + + + RES_F2PT + Select resistance for the corresponding switch + [19:18] + read-write + + + + + SENSE_PERIOD + Sense clock period + 0x200 + 32 + read-write + 0xC000000 + 0xFF70FFF + + + SENSE_DIV + The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . +Note this is the base divider, clock dithering may change the actual period length. +Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. +In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. + [11:0] + read-write + + + LFSR_SIZE + Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. + [18:16] + read-write + + + OFF + Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) + 0 + + + 6B + 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) + 1 + + + 7B + 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) + 2 + + + 9B + 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) + 3 + + + 10B + 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) + 4 + + + 8B + 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) + 5 + + + 12B + 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) + 6 + + + + + LFSR_SCALE + Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. +The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). +Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. + [23:20] + read-write + + + LFSR_CLEAR + When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. +Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. + [24:24] + read-write + + + SEL_LFSR_MSB + Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. + [25:25] + read-write + + + LFSR_BITS + Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. +Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. + [27:26] + read-write + + + 2B + use 2 bits: range = [-2,1] + 0 + + + 3B + use 3 bits: range = [-4,3] + 1 + + + 4B + use 4 bits: range = [-8,7] + 2 + + + 5B + use 5 bits: range = [-16,15] (default) + 3 + + + + + + + SENSE_DUTY + Sense clock duty cycle + 0x204 + 32 + read-write + 0x0 + 0xD0FFF + + + SENSE_WIDTH + Defines the length of the first phase of the sense clock in clk_csd cycles. +A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. +Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. + [11:0] + read-write + + + SENSE_POL + Polarity of the sense clock +0 = start with low phase (typical for regular negative transfer CSD) +1 = start with high phase + [16:16] + read-write + + + OVERLAP_PHI1 + NonOverlap or not for Phi1 (csd_sense=0). +0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. +1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. + [18:18] + read-write + + + OVERLAP_PHI2 + Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). + [19:19] + read-write + + + + + SW_HS_P_SEL + HSCMP Pos input switch Waveform selection + 0x280 + 32 + read-write + 0x0 + 0x11111111 + + + SW_HMPM + Set HMPM switch +0: static open +1: static closed + [0:0] + read-write + + + SW_HMPT + Set corresponding switch + [4:4] + read-write + + + SW_HMPS + Set corresponding switch + [8:8] + read-write + + + SW_HMMA + Set corresponding switch + [12:12] + read-write + + + SW_HMMB + Set corresponding switch + [16:16] + read-write + + + SW_HMCA + Set corresponding switch + [20:20] + read-write + + + SW_HMCB + Set corresponding switch + [24:24] + read-write + + + SW_HMRH + Set corresponding switch + [28:28] + read-write + + + + + SW_HS_N_SEL + HSCMP Neg input switch Waveform selection + 0x284 + 32 + read-write + 0x0 + 0x77110000 + + + SW_HCCC + Set corresponding switch + [16:16] + read-write + + + SW_HCCD + Set corresponding switch + [20:20] + read-write + + + SW_HCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_HCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_SHIELD_SEL + Shielding switches Waveform selection + 0x288 + 32 + read-write + 0x0 + 0x117777 + + + SW_HCAV + N/A + [2:0] + read-write + + + SW_HCAG + Select waveform for corresponding switch + [6:4] + read-write + + + SW_HCBV + N/A + [10:8] + read-write + + + SW_HCBG + Select waveform for corresponding switch, using csd_shield as base + [14:12] + read-write + + + SW_HCCV + Set corresponding switch + [16:16] + read-write + + + SW_HCCG + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_AMUXBUF_SEL + Amuxbuffer switches Waveform selection + 0x290 + 32 + read-write + 0x0 + 0x11171110 + + + SW_IRBY + Set corresponding switch + [4:4] + read-write + + + SW_IRLB + Set corresponding switch + [8:8] + read-write + + + SW_ICA + Set corresponding switch + [12:12] + read-write + + + SW_ICB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_IRLI + Set corresponding switch + [20:20] + read-write + + + SW_IRH + Set corresponding switch + [24:24] + read-write + + + SW_IRL + Set corresponding switch + [28:28] + read-write + + + + + SW_BYP_SEL + AMUXBUS bypass switches Waveform selection + 0x294 + 32 + read-write + 0x0 + 0x111000 + + + SW_BYA + Set corresponding switch + [12:12] + read-write + + + SW_BYB + Set corresponding switch + [16:16] + read-write + + + SW_CBCC + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_CMP_P_SEL + CSDCMP Pos Switch Waveform selection + 0x2A0 + 32 + read-write + 0x0 + 0x1111777 + + + SW_SFPM + Select waveform for corresponding switch + [2:0] + read-write + + + SW_SFPT + Select waveform for corresponding switch + [6:4] + read-write + + + SW_SFPS + Select waveform for corresponding switch + [10:8] + read-write + + + SW_SFMA + Set corresponding switch + [12:12] + read-write + + + SW_SFMB + Set corresponding switch + [16:16] + read-write + + + SW_SFCA + Set corresponding switch + [20:20] + read-write + + + SW_SFCB + Set corresponding switch + [24:24] + read-write + + + + + SW_CMP_N_SEL + CSDCMP Neg Switch Waveform selection + 0x2A4 + 32 + read-write + 0x0 + 0x77000000 + + + SW_SCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_SCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_REFGEN_SEL + Reference Generator Switch Waveform selection + 0x2A8 + 32 + read-write + 0x0 + 0x11110011 + + + SW_IAIB + Set corresponding switch + [0:0] + read-write + + + SW_IBCB + Set corresponding switch + [4:4] + read-write + + + SW_SGMB + Set corresponding switch + [16:16] + read-write + + + SW_SGRP + Set corresponding switch + [20:20] + read-write + + + SW_SGRE + Set corresponding switch + [24:24] + read-write + + + SW_SGR + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_MOD_SEL + Full Wave Cmod Switch Waveform selection + 0x2B0 + 32 + read-write + 0x0 + 0x11170701 + + + SW_F1PM + Set corresponding switch + [0:0] + read-write + + + SW_F1MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F1CA + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C1CC + Set corresponding switch + [20:20] + read-write + + + SW_C1CD + Set corresponding switch + [24:24] + read-write + + + SW_C1F1 + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_TANK_SEL + Full Wave Csh_tank Switch Waveform selection + 0x2B4 + 32 + read-write + 0x0 + 0x11177710 + + + SW_F2PT + Set corresponding switch + [4:4] + read-write + + + SW_F2MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F2CA + Select waveform for corresponding switch + [14:12] + read-write + + + SW_F2CB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C2CC + Set corresponding switch + [20:20] + read-write + + + SW_C2CD + Set corresponding switch + [24:24] + read-write + + + SW_C2F2 + Set corresponding switch + [28:28] + read-write + + + + + SW_DSI_SEL + DSI output switch control Waveform selection + 0x2C0 + 32 + read-write + 0x0 + 0xFF + + + DSI_CSH_TANK + Select waveform for dsi_csh_tank output signal +0: static open +1: static closed +2: phi1 +3: phi2 +4: phi1 & HSCMP +5: phi2 & HSCMP +6: HSCMP // ignores phi1/2 +7: !sense // = phi1 but ignores OVERLAP_PHI1 + +8: phi1_delay // phi1 delayed with shield delay +9: phi2_delay // phi2 delayed with shield delay + +10: !phi1 +11: !phi2 +12: !(phi1 & HSCMP) +13: !(phi2 & HSCMP) +14: !HSCMP // ignores phi1/2 +15: sense // = phi2 but ignores OVERLAP_PHI2 + [3:0] + read-write + + + DSI_CMOD + Select waveform for dsi_cmod output signal + [7:4] + read-write + + + + + IO_SEL + IO output control Waveform selection + 0x2D0 + 32 + read-write + 0x0 + 0xFFFF0FF + + + CSD_TX_OUT + Select waveform for csd_tx_out output signal + [3:0] + read-write + + + CSD_TX_OUT_EN + Select waveform for csd_tx_out_en output signal + [7:4] + read-write + + + CSD_TX_AMUXB_EN + Select waveform for csd_tx_amuxb_en output signal + [15:12] + read-write + + + CSD_TX_N_OUT + Select waveform for csd_tx_n_out output signal + [19:16] + read-write + + + CSD_TX_N_OUT_EN + Select waveform for csd_tx_n_out_en output signal + [23:20] + read-write + + + CSD_TX_N_AMUXA_EN + Select waveform for csd_tx_n_amuxa_en output signal + [27:24] + read-write + + + + + SEQ_TIME + Sequencer Timing + 0x300 + 32 + read-write + 0x0 + 0xFF + + + AZ_TIME + Define Auto-Zero time in csd_sense cycles -1. + [7:0] + read-write + + + + + SEQ_INIT_CNT + Sequencer Initial conversion and sample counts + 0x310 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. + [15:0] + read-write + + + + + SEQ_NORM_CNT + Sequencer Normal conversion and sample counts + 0x314 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. +Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). +Note for CSDv1 Sample window size = PERIOD + [15:0] + read-write + + + + + ADC_CTL + ADC Control + 0x320 + 32 + read-write + 0x0 + 0x300FF + + + ADC_TIME + ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 + [7:0] + read-write + + + ADC_MODE + Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state + [17:16] + read-write + + + OFF + No ADC measurement + 0 + + + VREF_CNT + Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB + 1 + + + VREF_BY2_CNT + Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) + 2 + + + VIN_CNT + Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. + 3 + + + + + + + SEQ_START + Sequencer start + 0x340 + 32 + read-write + 0x0 + 0x31B + + + START + Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). + [0:0] + read-write + + + SEQ_MODE + 0 = regular CSD scan + optional ADC +1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. + [1:1] + read-write + + + ABORT + When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. + [3:3] + read-write + + + DSI_START_EN + When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. + [4:4] + read-write + + + AZ0_SKIP + When set the AutoZero_0 state will be skipped + [8:8] + read-write + + + AZ1_SKIP + When set the AutoZero_1 state will be skipped + [9:9] + read-write + + + + + IDACA + IDACA Configuration + 0x400 + 32 + read-write + 0x0 + 0x3EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_MODE==CSD also mixed with the CSD configuration and operation. However in mutual cap mode with one IDAC (config.mutual_cap=1 & config.csx_dual_idac=0) the polarity of the IDAC is controlled by csd_sense. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + Balancing mode: only applies to legs configured as CSD. + [11:10] + read-write + + + FULL + enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking. + 1 + + + PHI2 + enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or dual IDAC CSX or Full-Wave. + 2 + + + PHI1_2 + enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave. + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled). +0: no DSI control + IDACA_POLARITY = IDACA.POLARITY + IDACA_LEG1_EN = IDACA.LEG1_EN + IDACA_LEG2_EN = IDACA.LEG2_EN +1: Mix MMIO with DSI control + IDACA_POLARITY = IDACA.POLARITY EXOR dsi_idaca_pol + IDACA_LEG1_EN = IDACA.LEG1_EN AND dsi_idaca_leg1_en + IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSA + [25:25] + read-write + + + + + IDACB + IDACB Configuration + 0x500 + 32 + read-write + 0x0 + 0x7EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_EN==1 and LEG1_MODE==CSD also mixed with the CSD configuration and operation. In mutual cap mode however (see config.mutual_cap) the polarity of the IDAC is controlled by csd_sense. If LEG3_EN=1 (the other two legs must be off) then the ADC sequencer controls the IDACB polarity, optionally mixed with DSI. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + same as corresponding IDACA Balancing mode + [11:10] + read-write + + + FULL + same as corresponding IDACA Balancing mode + 0 + + + PHI1 + same as corresponding IDACA Balancing mode + 1 + + + PHI2 + same as corresponding IDACA Balancing mode + 2 + + + PHI1_2 + same as corresponding IDACA Balancing mode + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG1_MODE + 0 + + + GP + same as corresponding IDACA.LEG1_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG1_MODE + 2 + + + CSD + same as corresponding IDACA.LEG1_MODE + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG2_MODE + 0 + + + GP + same as corresponding IDACA.LEG2_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG2_MODE + 2 + + + CSD + same as corresponding IDACA.LEG2_MODE + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled) +0: no DSI control + IDACB_POLARITY = IDACB.POLARITY + IDACB_LEG1_EN = IDACB.LEG1_EN + IDACB_LEG2_EN = IDACB.LEG2_EN + IDACB_LEG3_EN = IDACB.LEG3_EN +1: Mix MMIO with DSI control + IDACB_POLARITY = IDACB.POLARITY EXOR dsi_idacb_pol + IDACB_LEG1_EN = IDACB.LEG1_EN AND dsi_idacb_leg1_en + IDACB_LEG2_EN = IDACB.LEG2_EN AND dsi_idacb_leg2_en + IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSB or CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSB or CSDBUSA + [25:25] + read-write + + + LEG3_EN + output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit is set both other legs should be off. +Note that leg3 can only be used for ADC mode, not GP mode. Which means that leg3 can only be on when the ADC Sequencer is in the ADC_measure or Calib_measure state. In those states leg3 is controlled by the ADC configuration and the HSCMP output. In addition this leg3 enable bit can optionally be mixed with DSI (see DSI_CTRL_EN). +When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer. + [26:26] + read-write + + + + + + + TCPWM0 + Timer/Counter/PWM + TCPWM + 0x40380000 + + 0 + 65536 + registers + + + + CTRL + TCPWM control register + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Counter enables for counters 0 up to CNT_NR-1. +'0': counter disabled. +'1': counter enabled. +Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: +- the associated counter triggers in the CMD register are set to '0'. +- the counter's interrupt cause fields in counter's INTR register. +- the counter's status fields in counter's STATUS register.. +- the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). +- the counter's line outputs ('line_out' and 'line_compl_out'). +In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. + [31:0] + read-write + + + + + CTRL_CLR + TCPWM control clear register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Alias of CTRL that only allows disabling of counters. A write access: +'0': Does nothing. +'1': Clears respective COUNTER_ENABLED field. + +A read access returns CTRL.COUNTER_ENABLED. + [31:0] + read-write + + + + + CTRL_SET + TCPWM control set register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_ENABLED + Alias of CTRL that only allows enabling of counters. A write access: +'0': Does nothing. +'1': Sets respective COUNTER_ENABLED field. + +A read access returns CTRL.COUNTER_ENABLED. + [31:0] + read-write + + + + + CMD_CAPTURE + TCPWM capture command register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_CAPTURE + Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. + [31:0] + read-write + + + + + CMD_RELOAD + TCPWM reload command register + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_RELOAD + Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + CMD_STOP + TCPWM stop command register + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_STOP + Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + CMD_START + TCPWM start command register + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER_START + Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. + [31:0] + read-write + + + + + INTR_CAUSE + TCPWM Counter interrupt cause register + 0x1C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNTER_INT + Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. + [31:0] + read-only + + + + + 8 + 64 + CNT[%s] + Timer/Counter/PWM Counter Module + 0x00000100 + + CTRL + Counter control register + 0x0 + 32 + read-write + 0x0 + 0x737FF0F + + + AUTO_RELOAD_CC + Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. +Timer mode: +'0': never switch. +'1': switch on a compare match event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [0:0] + read-write + + + AUTO_RELOAD_PERIOD + Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + [1:1] + read-write + + + PWM_SYNC_KILL + Specifies asynchronous/synchronous kill behavior: +'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. +'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. + +This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. + [2:2] + read-write + + + PWM_STOP_ON_KILL + Specifies whether the counter stops on a kill events: +'0': kill event does NOT stop counter. +'1': kill event stops counter. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [3:3] + read-write + + + GENERIC + Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. + [15:8] + read-write + + + UP_DOWN_MODE + Determines counter direction. + [17:16] + read-write + + + COUNT_UP + Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. + 0 + + + COUNT_DOWN + Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 1 + + + COUNT_UPDN1 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 2 + + + COUNT_UPDN2 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). + 3 + + + + + ONE_SHOT + When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. + [18:18] + read-write + + + QUADRATURE_MODE + In QUAD mode selects quadrature encoding mode (X1/X2/X4). +In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1]. + [21:20] + read-write + + + X1 + X1 encoding (QUAD mode) + 0 + + + X2 + X2 encoding (QUAD mode) + 1 + + + X4 + X4 encoding (QUAD mode) + 2 + + + + + MODE + Counter mode. + [26:24] + read-write + + + TIMER + Timer mode + 0 + + + CAPTURE + Capture mode + 2 + + + QUAD + Quadrature encoding mode + 3 + + + PWM + Pulse width modulation (PWM) mode + 4 + + + PWM_DT + PWM with deadtime insertion mode + 5 + + + PWM_PR + Pseudo random pulse width modulation + 6 + + + + + + + STATUS + Counter status register + 0x4 + 32 + read-only + 0x0 + 0x8000FF01 + + + DOWN + When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. + [0:0] + read-only + + + GENERIC + Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. + [15:8] + read-only + + + RUNNING + When '0', the counter is NOT running. When '1', the counter is running. + [31:31] + read-only + + + + + COUNTER + Counter count register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER + 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. + [31:0] + read-write + + + + + CC + Counter compare/capture register + 0xC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC_BUFF + Counter buffered compare/capture register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC register. + [31:0] + read-write + + + + + PERIOD + Counter period register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. + [31:0] + read-write + + + + + PERIOD_BUFF + Counter buffered period register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Additional buffer for counter PERIOD register. + [31:0] + read-write + + + + + TR_CTRL0 + Counter trigger control register 0 + 0x20 + 32 + read-write + 0x10 + 0xFFFFF + + + CAPTURE_SEL + Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. + [3:0] + read-write + + + COUNT_SEL + Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. + [7:4] + read-write + + + RELOAD_SEL + Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint). + [11:8] + read-write + + + STOP_SEL + Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. + [15:12] + read-write + + + START_SEL + Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). + [19:16] + read-write + + + + + TR_CTRL1 + Counter trigger control register 1 + 0x24 + 32 + read-write + 0x3FF + 0x3FF + + + CAPTURE_EDGE + A capture event will copy the counter value into the CC register. + [1:0] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + COUNT_EDGE + A counter event will increase or decrease the counter by '1'. + [3:2] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + RELOAD_EDGE + A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. + [5:4] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + STOP_EDGE + A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. + [7:6] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + START_EDGE + A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. + [9:8] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + BOTH_EDGES + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + + + TR_CTRL2 + Counter trigger control register 2 + 0x28 + 32 + read-write + 0x3F + 0x3F + + + CC_MATCH_MODE + Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. +To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. + [1:0] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + OVERFLOW_MODE + Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. + [3:2] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + UNDERFLOW_MODE + Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. + [5:4] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + + + INTR + Interrupt request register + 0x30 + 32 + read-write + 0x0 + 0x3 + + + TC + Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. + [0:0] + read-write + + + CC_MATCH + Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + Interrupt set request register + 0x34 + 32 + read-write + 0x0 + 0x3 + + + TC + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + CC_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x38 + 32 + read-write + 0x0 + 0x3 + + + TC + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + CC_MATCH + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x3C + 32 + read-only + 0x0 + 0x3 + + + TC + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CC_MATCH + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + + + + TCPWM1 + 0x40390000 + + + LCD0 + LCD Controller Block + LCD + 0x403B0000 + + 0 + 65536 + registers + + + + ID + ID & Revision + 0x0 + 32 + read-only + 0x2F0F0 + 0xFFFFFFFF + + + ID + the ID of LCD controller peripheral is 0xF0F0 + [15:0] + read-only + + + REVISION + the version number is 0x0002 + [31:16] + read-only + + + + + DIVIDER + LCD Divider Register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SUBFR_DIV + Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. + [15:0] + read-write + + + DEAD_DIV + Length of the dead time period in cycles. When set to zero, no dead time period exists. + [31:16] + read-write + + + + + CONTROL + LCD Configuration Register + 0x8 + 32 + read-write + 0x0 + 0x80000FFF + + + LS_EN + Low speed (LS) generator enable +1: enable +0: disable + [0:0] + read-write + + + HS_EN + High speed (HS) generator enable +1: enable +0: disable + [1:1] + read-write + + + LCD_MODE + HS/LS Mode selection + [2:2] + read-write + + + LS + Select Low Speed Generator (Works in Active, Sleep and DeepSleep power modes). Low speed clock (clk_lf) or middle speed clock (clk_mf) can be selected for Low Speed Generator. + 0 + + + HS + Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). + 1 + + + + + TYPE + LCD driving waveform type configuration. + [3:3] + read-write + + + TYPE_A + Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. + 0 + + + TYPE_B + Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). + 1 + + + + + OP_MODE + Driving mode configuration + [4:4] + read-write + + + PWM + PWM Mode + 0 + + + CORRELATION + Digital Correlation Mode + 1 + + + + + BIAS + PWM bias selection + [6:5] + read-write + + + HALF + 1/2 Bias + 0 + + + THIRD + 1/3 Bias + 1 + + + FOURTH + 1/4 Bias + 2 + + + FIFTH + 1/5 Bias + 3 + + + + + CLOCK_LS_SEL + Low speed (LS) generator clock source selection +1: select clk_mf +0: select clk_lf + [7:7] + read-write + + + COM_NUM + The number of COM connections minus 2. So: +0: 2 COM's +1: 3 COM's +... +13: 15 COM's +14: 16 COM's +15: undefined + [11:8] + read-write + + + LS_EN_STAT + LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. +The following procedure should be followed to disable the LS generator: +1. If LS_EN=0 we are done. Exit the procedure. +2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. +3. Set LS_EN=0. +4. Wait until LS_EN_STAT=0. + [31:31] + read-only + + + + + 8 + 4 + DATA0[%s] + LCD Pin Data Registers + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA1[%s] + LCD Pin Data Registers + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA2[%s] + LCD Pin Data Registers + 0x300 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA3[%s] + LCD Pin Data Registers + 0x400 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). + [31:0] + read-write + + + + + + + USBFS0 + USB Host and Device Controller + USBFS + 0x403F0000 + + 0 + 65536 + registers + + + + USBDEV + USB Device + 0x00000000 + + 8 + 4 + EP0_DR[%s] + Control End point EP0 Data Register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + DATA_BYTE + This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. + [7:0] + read-write + + + + + CR0 + USB control 0 Register + 0x20 + 32 + read-write + 0x0 + 0xFF + + + DEVICE_ADDRESS + These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. +If USB bus reset is detected, these bits are initialized. + [6:0] + read-write + + + USB_ENABLE + This bit enables the device to respond to USB traffic. +If USB bus reset is detected, this bit is cleared. +Note: +When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. + [7:7] + read-write + + + + + CR1 + USB control 1 Register + 0x24 + 32 + read-write + 0x0 + 0xF + + + REG_ENABLE + This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. + [0:0] + read-write + + + ENABLE_LOCK + This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. + [1:1] + read-write + + + BUS_ACTIVITY + The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High +value until firmware clears it. + [2:2] + read-write + + + RSVD_3 + N/A + [3:3] + read-write + + + + + SIE_EP_INT_EN + USB SIE Data Endpoints Interrupt Enable Register + 0x28 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + SIE_EP_INT_SR + USB SIE Data Endpoint Interrupt Status + 0x2C + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-write + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-write + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-write + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-write + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-write + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-write + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-write + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-write + + + + + SIE_EP1_CNT0 + Non-control endpoint count register + 0x30 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP1_CNT1 + Non-control endpoint count register + 0x34 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP1_CR0 + Non-control endpoint's control Register + 0x38 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + USBIO_CR0 + USBIO Control 0 Register + 0x40 + 32 + read-write + 0x0 + 0xE0 + + + RD + Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. +If D+=D- (SE0), this value is undefined. + [0:0] + read-only + + + DIFF_LOW + D+ < D- (K state) + 0 + + + DIFF_HIGH + D+ > D- (J state) + 1 + + + + + TD + Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. + [5:5] + read-write + + + DIFF_K + Force USB K state (D+ is low D- is high). + 0 + + + DIFF_J + Force USB J state (D+ is high D- is low). + 1 + + + + + TSE0 + Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. + [6:6] + read-write + + + TEN + USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually +transmitting is to force a resume state on the bus. + [7:7] + read-write + + + + + USBIO_CR2 + USBIO control 2 Register + 0x44 + 32 + read-write + 0x0 + 0xFF + + + RSVD_5_0 + N/A + [5:0] + read-only + + + TEST_PKT + This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. + [6:6] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + + + USBIO_CR1 + USBIO control 1 Register + 0x48 + 32 + read-write + 0x20 + 0x20 + + + DMO + This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. +This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. +This bit is valid if USB Device. + [0:0] + read-only + + + DPO + This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. +This bit displays the output value of D+ pin when USB transmits SE0 or data. +This bit is valid if USB Device. + [1:1] + read-only + + + RSVD_2 + N/A + [2:2] + read-write + + + IOMODE + This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. + [5:5] + read-write + + + + + DYN_RECONFIG + USB Dynamic reconfiguration register + 0x50 + 32 + read-write + 0x0 + 0x1F + + + DYN_CONFIG_EN + This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. +Use 0 for EP1, 1 for EP2, etc. + [0:0] + read-write + + + DYN_RECONFIG_EPNO + These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. + [3:1] + read-write + + + DYN_RECONFIG_RDY_STS + This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. + [4:4] + read-only + + + + + SOF0 + Start Of Frame Register + 0x60 + 32 + read-only + 0x0 + 0xFF + + + FRAME_NUMBER + It has the lower 8 bits [7:0] of the SOF frame number. + [7:0] + read-only + + + + + SOF1 + Start Of Frame Register + 0x64 + 32 + read-only + 0x0 + 0x7 + + + FRAME_NUMBER_MSB + It has the upper 3 bits [10:8] of the SOF frame number. + [2:0] + read-only + + + + + SIE_EP2_CNT0 + Non-control endpoint count register + 0x70 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP2_CNT1 + Non-control endpoint count register + 0x74 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP2_CR0 + Non-control endpoint's control Register + 0x78 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + OSCLK_DR0 + Oscillator lock data register 0 + 0x80 + 32 + read-only + 0x0 + 0x0 + + + ADDER + These bits return the lower 8 bits of the oscillator locking circuits adder output. + [7:0] + read-only + + + + + OSCLK_DR1 + Oscillator lock data register 1 + 0x84 + 32 + read-only + 0x0 + 0x0 + + + ADDER_MSB + These bits return the upper 7 bits of the oscillator locking circuits adder output. + [6:0] + read-only + + + + + EP0_CR + Endpoint0 control Register + 0xA0 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + OUT_RCVD + When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. + [5:5] + read-write + + + IN_RCVD + When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. + [6:6] + read-write + + + SETUP_RCVD + When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. + [7:7] + read-write + + + + + EP0_CNT + Endpoint0 count Register + 0xA4 + 32 + read-write + 0x0 + 0xCF + + + BYTE_COUNT + These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. + [3:0] + read-write + + + DATA_VALID + This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT0 + Non-control endpoint count register + 0xB0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT1 + Non-control endpoint count register + 0xB4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP3_CR0 + Non-control endpoint's control Register + 0xB8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP4_CNT0 + Non-control endpoint count register + 0xF0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP4_CNT1 + Non-control endpoint count register + 0xF4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP4_CR0 + Non-control endpoint's control Register + 0xF8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP5_CNT0 + Non-control endpoint count register + 0x130 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP5_CNT1 + Non-control endpoint count register + 0x134 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP5_CR0 + Non-control endpoint's control Register + 0x138 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP6_CNT0 + Non-control endpoint count register + 0x170 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP6_CNT1 + Non-control endpoint count register + 0x174 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP6_CR0 + Non-control endpoint's control Register + 0x178 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP7_CNT0 + Non-control endpoint count register + 0x1B0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP7_CNT1 + Non-control endpoint count register + 0x1B4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP7_CR0 + Non-control endpoint's control Register + 0x1B8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP8_CNT0 + Non-control endpoint count register + 0x1F0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP8_CNT1 + Non-control endpoint count register + 0x1F4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP8_CR0 + Non-control endpoint's control Register + 0x1F8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + ARB_EP1_CFG + Endpoint Configuration Register *1 + 0x200 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP1_INT_EN + Endpoint Interrupt Enable Register *1 + 0x204 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP1_SR + Endpoint Interrupt Enable Register *1 + 0x208 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW1_WA + Endpoint Write Address value *1, *2 + 0x210 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW1_WA_MSB + Endpoint Write Address value *1, *2 + 0x214 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW1_RA + Endpoint Read Address value *1, *2 + 0x218 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW1_RA_MSB + Endpoint Read Address value *1, *2 + 0x21C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW1_DR + Endpoint Data Register + 0x220 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUF_SIZE + Dedicated Endpoint Buffer Size Register *1 + 0x230 + 32 + read-write + 0x0 + 0xFF + + + IN_BUF + Buffer size for IN Endpoints. + [3:0] + read-write + + + OUT_BUF + Buffer size for OUT Endpoints. + [7:4] + read-write + + + + + EP_ACTIVE + Endpoint Active Indication Register *1 + 0x238 + 32 + read-write + 0x0 + 0xFF + + + EP1_ACT + Indicates that Endpoint is currently active. + [0:0] + read-write + + + EP2_ACT + Indicates that Endpoint is currently active. + [1:1] + read-write + + + EP3_ACT + Indicates that Endpoint is currently active. + [2:2] + read-write + + + EP4_ACT + Indicates that Endpoint is currently active. + [3:3] + read-write + + + EP5_ACT + Indicates that Endpoint is currently active. + [4:4] + read-write + + + EP6_ACT + Indicates that Endpoint is currently active. + [5:5] + read-write + + + EP7_ACT + Indicates that Endpoint is currently active. + [6:6] + read-write + + + EP8_ACT + Indicates that Endpoint is currently active. + [7:7] + read-write + + + + + EP_TYPE + Endpoint Type (IN/OUT) Indication *1 + 0x23C + 32 + read-write + 0x0 + 0xFF + + + EP1_TYP + Endpoint Type Indication. + [0:0] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP2_TYP + Endpoint Type Indication. + [1:1] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP3_TYP + Endpoint Type Indication. + [2:2] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP4_TYP + Endpoint Type Indication. + [3:3] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP5_TYP + Endpoint Type Indication. + [4:4] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP6_TYP + Endpoint Type Indication. + [5:5] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP7_TYP + Endpoint Type Indication. + [6:6] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP8_TYP + Endpoint Type Indication. + [7:7] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + + + ARB_EP2_CFG + Endpoint Configuration Register *1 + 0x240 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP2_INT_EN + Endpoint Interrupt Enable Register *1 + 0x244 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP2_SR + Endpoint Interrupt Enable Register *1 + 0x248 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW2_WA + Endpoint Write Address value *1, *2 + 0x250 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW2_WA_MSB + Endpoint Write Address value *1, *2 + 0x254 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW2_RA + Endpoint Read Address value *1, *2 + 0x258 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW2_RA_MSB + Endpoint Read Address value *1, *2 + 0x25C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW2_DR + Endpoint Data Register + 0x260 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_CFG + Arbiter Configuration Register *1 + 0x270 + 32 + read-write + 0x0 + 0xF0 + + + AUTO_MEM + Enables Auto Memory Configuration. Manual memory configuration by default. + [4:4] + read-write + + + DMA_CFG + DMA Access Configuration. + [6:5] + read-write + + + DMA_NONE + No DMA + 0 + + + DMA_MANUAL + Manual DMA + 1 + + + DMA_AUTO + Auto DMA + 2 + + + + + CFG_CMP + Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. + [7:7] + read-write + + + + + USB_CLK_EN + USB Block Clock Enable Register + 0x274 + 32 + read-write + 0x0 + 0x1 + + + CSR_CLK_EN + Clock Enable for Core Logic clocked by AHB bus clock + [0:0] + read-write + + + + + ARB_INT_EN + Arbiter Interrupt Enable *1 + 0x278 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + ARB_INT_SR + Arbiter Interrupt Status *1 + 0x27C + 32 + read-only + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-only + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-only + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-only + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-only + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-only + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-only + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-only + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-only + + + + + ARB_EP3_CFG + Endpoint Configuration Register *1 + 0x280 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP3_INT_EN + Endpoint Interrupt Enable Register *1 + 0x284 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP3_SR + Endpoint Interrupt Enable Register *1 + 0x288 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW3_WA + Endpoint Write Address value *1, *2 + 0x290 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW3_WA_MSB + Endpoint Write Address value *1, *2 + 0x294 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW3_RA + Endpoint Read Address value *1, *2 + 0x298 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW3_RA_MSB + Endpoint Read Address value *1, *2 + 0x29C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW3_DR + Endpoint Data Register + 0x2A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + CWA + Common Area Write Address *1 + 0x2B0 + 32 + read-write + 0x0 + 0xFF + + + CWA + Write Address for Common Area + [7:0] + read-write + + + + + CWA_MSB + Endpoint Read Address value *1 + 0x2B4 + 32 + read-write + 0x0 + 0x1 + + + CWA_MSB + Write Address for Common Area + [0:0] + read-write + + + + + ARB_EP4_CFG + Endpoint Configuration Register *1 + 0x2C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP4_INT_EN + Endpoint Interrupt Enable Register *1 + 0x2C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP4_SR + Endpoint Interrupt Enable Register *1 + 0x2C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW4_WA + Endpoint Write Address value *1, *2 + 0x2D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW4_WA_MSB + Endpoint Write Address value *1, *2 + 0x2D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW4_RA + Endpoint Read Address value *1, *2 + 0x2D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW4_RA_MSB + Endpoint Read Address value *1, *2 + 0x2DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW4_DR + Endpoint Data Register + 0x2E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + DMA_THRES + DMA Burst / Threshold Configuration + 0x2F0 + 32 + read-write + 0x0 + 0xFF + + + DMA_THS + DMA Threshold count + [7:0] + read-write + + + + + DMA_THRES_MSB + DMA Burst / Threshold Configuration + 0x2F4 + 32 + read-write + 0x0 + 0x1 + + + DMA_THS_MSB + DMA Threshold count + [0:0] + read-write + + + + + ARB_EP5_CFG + Endpoint Configuration Register *1 + 0x300 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP5_INT_EN + Endpoint Interrupt Enable Register *1 + 0x304 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP5_SR + Endpoint Interrupt Enable Register *1 + 0x308 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW5_WA + Endpoint Write Address value *1, *2 + 0x310 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW5_WA_MSB + Endpoint Write Address value *1, *2 + 0x314 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW5_RA + Endpoint Read Address value *1, *2 + 0x318 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW5_RA_MSB + Endpoint Read Address value *1, *2 + 0x31C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW5_DR + Endpoint Data Register + 0x320 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUS_RST_CNT + Bus Reset Count Register + 0x330 + 32 + read-write + 0xA + 0xF + + + BUS_RST_CNT + Bus Reset Count Length + [3:0] + read-write + + + + + ARB_EP6_CFG + Endpoint Configuration Register *1 + 0x340 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP6_INT_EN + Endpoint Interrupt Enable Register *1 + 0x344 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP6_SR + Endpoint Interrupt Enable Register *1 + 0x348 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW6_WA + Endpoint Write Address value *1, *2 + 0x350 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW6_WA_MSB + Endpoint Write Address value *1, *2 + 0x354 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW6_RA + Endpoint Read Address value *1, *2 + 0x358 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW6_RA_MSB + Endpoint Read Address value *1, *2 + 0x35C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW6_DR + Endpoint Data Register + 0x360 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP7_CFG + Endpoint Configuration Register *1 + 0x380 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP7_INT_EN + Endpoint Interrupt Enable Register *1 + 0x384 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP7_SR + Endpoint Interrupt Enable Register *1 + 0x388 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW7_WA + Endpoint Write Address value *1, *2 + 0x390 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW7_WA_MSB + Endpoint Write Address value *1, *2 + 0x394 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW7_RA + Endpoint Read Address value *1, *2 + 0x398 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW7_RA_MSB + Endpoint Read Address value *1, *2 + 0x39C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW7_DR + Endpoint Data Register + 0x3A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP8_CFG + Endpoint Configuration Register *1 + 0x3C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP8_INT_EN + Endpoint Interrupt Enable Register *1 + 0x3C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP8_SR + Endpoint Interrupt Enable Register *1 + 0x3C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW8_WA + Endpoint Write Address value *1, *2 + 0x3D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW8_WA_MSB + Endpoint Write Address value *1, *2 + 0x3D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW8_RA + Endpoint Read Address value *1, *2 + 0x3D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW8_RA_MSB + Endpoint Read Address value *1, *2 + 0x3DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW8_DR + Endpoint Data Register + 0x3E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + 512 + 4 + MEM_DATA[%s] + DATA + 0x400 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + SOF16 + Start Of Frame Register + 0x1060 + 32 + read-only + 0x0 + 0x7FF + + + FRAME_NUMBER16 + The frame number (11b) + [10:0] + read-only + + + + + OSCLK_DR16 + Oscillator lock data register + 0x1080 + 32 + read-only + 0x0 + 0x0 + + + ADDER16 + These bits return the oscillator locking circuits adder output. + [14:0] + read-only + + + + + ARB_RW1_WA16 + Endpoint Write Address value *3 + 0x1210 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW1_RA16 + Endpoint Read Address value *3 + 0x1218 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW1_DR16 + Endpoint Data Register + 0x1220 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW2_WA16 + Endpoint Write Address value *3 + 0x1250 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW2_RA16 + Endpoint Read Address value *3 + 0x1258 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW2_DR16 + Endpoint Data Register + 0x1260 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW3_WA16 + Endpoint Write Address value *3 + 0x1290 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW3_RA16 + Endpoint Read Address value *3 + 0x1298 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW3_DR16 + Endpoint Data Register + 0x12A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + CWA16 + Common Area Write Address + 0x12B0 + 32 + read-write + 0x0 + 0x1FF + + + CWA16 + Write Address for Common Area + [8:0] + read-write + + + + + ARB_RW4_WA16 + Endpoint Write Address value *3 + 0x12D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW4_RA16 + Endpoint Read Address value *3 + 0x12D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW4_DR16 + Endpoint Data Register + 0x12E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + DMA_THRES16 + DMA Burst / Threshold Configuration + 0x12F0 + 32 + read-write + 0x0 + 0x1FF + + + DMA_THS16 + DMA Threshold count + [8:0] + read-write + + + + + ARB_RW5_WA16 + Endpoint Write Address value *3 + 0x1310 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW5_RA16 + Endpoint Read Address value *3 + 0x1318 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW5_DR16 + Endpoint Data Register + 0x1320 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW6_WA16 + Endpoint Write Address value *3 + 0x1350 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW6_RA16 + Endpoint Read Address value *3 + 0x1358 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW6_DR16 + Endpoint Data Register + 0x1360 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW7_WA16 + Endpoint Write Address value *3 + 0x1390 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW7_RA16 + Endpoint Read Address value *3 + 0x1398 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW7_DR16 + Endpoint Data Register + 0x13A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW8_WA16 + Endpoint Write Address value *3 + 0x13D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW8_RA16 + Endpoint Read Address value *3 + 0x13D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW8_DR16 + Endpoint Data Register + 0x13E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + + USBLPM + USB Device LPM and PHY Test + 0x00002000 + + POWER_CTL + Power Control Register + 0x0 + 32 + read-write + 0x0 + 0x303F0004 + + + SUSPEND + Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). +Note: +- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. + [2:2] + read-write + + + DP_UP_EN + Enables the pull up on the DP. +'0' : Disable. +'1' : Enable. + [16:16] + read-write + + + DP_BIG + Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DP. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DP + [17:17] + read-write + + + DP_DOWN_EN + Enables the ~15k pull down on the DP. + [18:18] + read-write + + + DM_UP_EN + Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. +'0' : Disable. +'1' : Enable. + [19:19] + read-write + + + DM_BIG + Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DM. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DM + [20:20] + read-write + + + DM_DOWN_EN + Enables the ~15k pull down on the DP. + [21:21] + read-write + + + ENABLE_DPO + Enables the single ended receiver on D+. + [28:28] + read-write + + + ENABLE_DMO + Enables the signle ended receiver on D-. + [29:29] + read-write + + + + + USBIO_CTL + USB IO Control Register + 0x8 + 32 + read-write + 0x0 + 0x3F + + + DM_P + The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. + [2:0] + read-write + + + OFF + Mode 0: Output buffer off (high Z). Input buffer off. + 0 + + + INPUT + Mode 1: Output buffer off (high Z). Input buffer on. + +Other values, not supported. + 1 + + + + + DM_M + The GPIO Drive Mode for DM IO pad. + [5:3] + read-write + + + + + FLOW_CTL + Flow Control Register + 0xC + 32 + read-write + 0x0 + 0xFF + + + EP1_ERR_RESP + End Point 1 error response +0: do nothing (backward compatibility mode) +1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK + [0:0] + read-write + + + EP2_ERR_RESP + End Point 2 error response + [1:1] + read-write + + + EP3_ERR_RESP + End Point 3 error response + [2:2] + read-write + + + EP4_ERR_RESP + End Point 4 error response + [3:3] + read-write + + + EP5_ERR_RESP + End Point 5 error response + [4:4] + read-write + + + EP6_ERR_RESP + End Point 6 error response + [5:5] + read-write + + + EP7_ERR_RESP + End Point 7 error response + [6:6] + read-write + + + EP8_ERR_RESP + End Point 8 error response + [7:7] + read-write + + + + + LPM_CTL + LPM Control Register + 0x10 + 32 + read-write + 0x0 + 0x17 + + + LPM_EN + LPM enable +0: Disabled, LPM token will not get a response (backward compatibility mode) +1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) + A STALL will be sent if the bLinkState is not 0001b + A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below + [0:0] + read-write + + + LPM_ACK_RESP + LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request +0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode +1: a LPM token will get an ACK response and the device will go to the requested low power mode + [1:1] + read-write + + + NYET_EN + Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). +0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. +1: a LPM token will get a NYET response + [2:2] + read-write + + + SUB_RESP + Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. + [4:4] + read-write + + + + + LPM_STAT + LPM Status register + 0x14 + 32 + read-only + 0x0 + 0x1F + + + LPM_BESL + Best Effort Service Latency +This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. + [3:0] + read-only + + + LPM_REMOTEWAKE + 0: Device is prohibited from initiating a remote wake +1: Device is allow to wake the host + [4:4] + read-only + + + + + INTR_SIE + USB SOF, BUS RESET and EP0 Interrupt Status + 0x20 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR + Interrupt status for USB SOF + [0:0] + read-write + + + BUS_RESET_INTR + Interrupt status for BUS RESET + [1:1] + read-write + + + EP0_INTR + Interrupt status for EP0 + [2:2] + read-write + + + LPM_INTR + Interrupt status for LPM (Link Power Management, L1 entry) + [3:3] + read-write + + + RESUME_INTR + Interrupt status for Resume + [4:4] + read-write + + + + + INTR_SIE_SET + USB SOF, BUS RESET and EP0 Interrupt Set + 0x24 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + BUS_RESET_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EP0_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + LPM_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + RESUME_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + + + INTR_SIE_MASK + USB SOF, BUS RESET and EP0 Interrupt Mask + 0x28 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [0:0] + read-write + + + BUS_RESET_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [1:1] + read-write + + + EP0_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [2:2] + read-write + + + LPM_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [3:3] + read-write + + + RESUME_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [4:4] + read-write + + + + + INTR_SIE_MASKED + USB SOF, BUS RESET and EP0 Interrupt Masked + 0x2C + 32 + read-only + 0x0 + 0x1F + + + SOF_INTR_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + BUS_RESET_INTR_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EP0_INTR_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + LPM_INTR_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + RESUME_INTR_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + + + INTR_LVL_SEL + Select interrupt level for each interrupt source + 0x30 + 32 + read-write + 0x0 + 0xFFFFC3FF + + + SOF_LVL_SEL + USB SOF Interrupt level select + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + BUS_RESET_LVL_SEL + BUS RESET Interrupt level select + [3:2] + read-write + + + EP0_LVL_SEL + EP0 Interrupt level select + [5:4] + read-write + + + LPM_LVL_SEL + LPM Interrupt level select + [7:6] + read-write + + + RESUME_LVL_SEL + Resume Interrupt level select + [9:8] + read-write + + + ARB_EP_LVL_SEL + Arbiter Endpoint Interrupt level select + [15:14] + read-write + + + EP1_LVL_SEL + EP1 Interrupt level select + [17:16] + read-write + + + EP2_LVL_SEL + EP2 Interrupt level select + [19:18] + read-write + + + EP3_LVL_SEL + EP3 Interrupt level select + [21:20] + read-write + + + EP4_LVL_SEL + EP4 Interrupt level select + [23:22] + read-write + + + EP5_LVL_SEL + EP5 Interrupt level select + [25:24] + read-write + + + EP6_LVL_SEL + EP6 Interrupt level select + [27:26] + read-write + + + EP7_LVL_SEL + EP7 Interrupt level select + [29:28] + read-write + + + EP8_LVL_SEL + EP8 Interrupt level select + [31:30] + read-write + + + + + INTR_CAUSE_HI + High priority interrupt Cause register + 0x34 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_MED + Medium priority interrupt Cause register + 0x38 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_LO + Low priority interrupt Cause register + 0x3C + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + DFT_CTL + DFT control + 0x70 + 32 + read-write + 0x0 + 0x1F + + + DDFT_OUT_SEL + DDFT output select signal + [2:0] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + DP_SE + Single Ended output of DP + 1 + + + DM_SE + Single Ended output of DM + 2 + + + TXOE + Output Enable + 3 + + + RCV_DF + Differential Receiver output + 4 + + + GPIO_DP_OUT + GPIO output of DP + 5 + + + GPIO_DM_OUT + GPIO output of DM + 6 + + + + + DDFT_IN_SEL + DDFT input select signal + [4:3] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + GPIO_DP_IN + GPIO input of DP + 1 + + + GPIO_DM_IN + GPIO input of DM + 2 + + + + + + + + USBHOST + USB Host Controller + 0x00004000 + + HOST_CTL0 + Host Control 0 Register. + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + HOST + This bit selects an operating mode of this IP. +'0' : USB Device +'1' : USB Host +Notes: +- The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. +- This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. +- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. + * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. + * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. + * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. + [0:0] + read-write + + + ENABLE + This bit enables the operation of this IP. +'0' : Disable USB Host +'1' : Enable USB Host +Note: +- This bit doesn't affect the USB Device. + [31:31] + read-write + + + + + HOST_CTL1 + Host Control 1 Register. + 0x10 + 32 + read-write + 0x83 + 0x83 + + + CLKSEL + This bit selects the operating clock of USB Host. +'0' : Low-speed clock +'1' : Full-speed clock +Notes: +- This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- This bit must always be set to '1' in the USB Device mode. + [0:0] + read-write + + + USTP + This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. +'0' : Normal operating mode. +'1' : Stops the clock for the USB Host operating unit. +Notes: +- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. + [1:1] + read-write + + + RST + This bit resets the USB Host. +'0' : Normal operating mode. +'1' : USB Host is reset. +Notes: +- This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. + [7:7] + read-write + + + + + HOST_CTL2 + Host Control 2 Register. + 0x100 + 32 + read-write + 0x1 + 0xFF + + + RETRY + If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). +* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' +'0' : Doesn't retry token sending. +'1' : Retries token sending +Note: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + CANCEL + When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). +'0' : Continues a token. +'1' : Cancels a token. + [1:1] + read-write + + + SOFSTEP + If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. +If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. +'0' : An interrupt occurred due to the HOST_HFCOMP setting. +'1' : An interrupt occurred. +Notes: +- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. + [2:2] + read-write + + + ALIVE + This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. +'0' : SOF output. +'1' : SE0 output (Keep alive) + [3:3] + read-write + + + RSVD_4 + N/A + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-write + + + TTEST + N/A + [7:6] + read-write + + + + + HOST_ERR + Host Error Status Register. + 0x104 + 32 + read-write + 0x3 + 0xFF + + + HS + These flags indicate the status of a handshake packet to be sent or received. +These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +These bits are updated when sending or receiving has been ended. +Write '11' to set the status back to 'NULL', all other write values are ignored. +Note: +This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:0] + read-write + + + ACK + Acknowledge Packet + 0 + + + NAK + Non-Acknowledge Packet + 1 + + + STALL + Stall Packet + 2 + + + NULL + Null Packet + 3 + + + + + STUFF + If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No stuffing error. +'1' : Stuffing error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + TGERR + If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No toggle error. +'1' : Toggle error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:3] + read-write + + + CRC + If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No CRC error. +'1' : CRC error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + TOUT + If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No timeout. +'1' : Timeout has detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RERR + When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No receive error. +'1' : Maximum packet receive error detected. +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:6] + read-write + + + LSTSOF + If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. +'0' : SOF sent without error. +'1' : SOF error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + HOST_STATUS + Host Status Register. + 0x108 + 32 + read-write + 0xC2 + 0x1FF + + + CSTAT + When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. +'0' : Device is disconnected. +'1' : Device is connected. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [0:0] + read-only + + + TMODE + If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. +'0' : Low-speed. +'1' : Full-speed. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [1:1] + read-only + + + SUSP + If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +Set to '1' : Suspend. +Set '0' when this bit is '1' : Resume. +Other conditions : Holds the status. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. +- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). +- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. + [2:2] + read-write + + + SOFBUSY + When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. +'0' : The SOF timer is stopped. +'1' : The SOF timer is active. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). +- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. + [3:3] + read-write + + + URST + When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-only + + + RSTBUSY + This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. +'0' : USB Host isn't being reset. +'1' : USB Host is being reset. +Notes: +- If this bit is '1', the a token must not be executed. +- This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. + [6:6] + read-only + + + CLKSEL_ST + This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +'0' : Low speed +'1' : Full speed +Note: +- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [7:7] + read-only + + + HOST_ST + This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. +'0' : USB Device +'1' : USB Host +Notes: +- If this bit is different from the HOST bit, The execution of a token must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [8:8] + read-only + + + + + HOST_FCOMP + Host SOF Interrupt Frame Compare Register + 0x10C + 32 + read-write + 0x0 + 0xFF + + + FRAMECOMP + These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. +If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:0] + read-write + + + + + HOST_RTIMER + Host Retry Timer Setup Register + 0x110 + 32 + read-write + 0x0 + 0x3FFFF + + + RTIMER + These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. +If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. + [17:0] + read-write + + + + + HOST_ADDR + Host Address Register + 0x114 + 32 + read-write + 0x0 + 0x7F + + + ADDRESS + These bits are used to specify a token address. +Note: +- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:0] + read-write + + + + + HOST_EOF + Host EOF Setup Register + 0x118 + 32 + read-write + 0x0 + 0x3FFF + + + EOF + These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. +Setting example: MAXPKT = 64 bytes, full-speed mode + (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time + =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit + Therefore, set 0x2C9. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [13:0] + read-write + + + + + HOST_FRAME + Host Frame Setup Register + 0x11C + 32 + read-write + 0x0 + 0x7FF + + + FRAME + These bits are used to specify a frame number of SOF. +Notes: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. + [10:0] + read-write + + + + + HOST_TOKEN + Host Token Endpoint Register + 0x120 + 32 + read-write + 0x0 + 0x17F + + + ENDPT + These bits are used to specify an endpoint to send or receive data to or from the device. +Note: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:0] + read-write + + + TKNEN + These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The PRE packet isn't supported. +- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' +- Mode should be USB Host before writing data to this bit. +- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. +- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. +- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [6:4] + read-write + + + NONE + Sends no data. + 0 + + + SETUP + Sends SETUP token. + 1 + + + IN + Sends IN token. + 2 + + + OUT + Sends OUT token. + 3 + + + SOF + Sends SOF token. + 4 + + + ISO_IN + Sends Isochronous IN. + 5 + + + ISO_OUT + Sends Isochronous OUT. + 6 + + + RSV + N/A + 7 + + + + + TGGL + This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. +'0' : DATA0 +'1' : DATA1 +Notes: +- This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. + [8:8] + read-write + + + + + HOST_EP1_CTL + Host Endpoint 1 Control Register + 0x400 + 32 + read-write + 0x8100 + 0x9DFF + + + PKS1 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. +- If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, + [8:0] + read-write + + + NULLE + When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the packet transfer mode. +'1' : Sets the packet transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. + [15:15] + read-write + + + + + HOST_EP1_STATUS + Host Endpoint 1 Status Register + 0x404 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE1 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. +The indication range is from 0x000 to 0x100. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [8:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP1 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. +'0' : Not initiatialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP1_RW1_DR + Host Endpoint 1 Data 1-Byte Register + 0x408 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP1 for 1-byte data + [7:0] + read-write + + + + + HOST_EP1_RW2_DR + Host Endpoint 1 Data 2-Byte Register + 0x40C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP1 for 2-byte data + [15:0] + read-write + + + + + HOST_EP2_CTL + Host Endpoint 2 Control Register + 0x500 + 32 + read-write + 0x8040 + 0x9C7F + + + PKS2 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. +- If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. + [6:0] + read-write + + + NULLE + When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the automatic buffer transfer mode. +'1' : Sets the automatic buffer transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. + [15:15] + read-write + + + + + HOST_EP2_STATUS + Host Endpoint 2 Status Register + 0x504 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE2 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. +The indication range is from 0x000 to 0x40. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [6:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP2 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. +'0' : Not Initialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP2_RW1_DR + Host Endpoint 2 Data 1-Byte Register + 0x508 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP2 for 1-byte data. + [7:0] + read-write + + + + + HOST_EP2_RW2_DR + Host Endpoint 2 Data 2-Byte Register + 0x50C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP2 for 2 byte data. + [15:0] + read-write + + + + + HOST_LVL1_SEL + Host Interrupt Level 1 Selection Register + 0x800 + 32 + read-write + 0x0 + 0xFFFF + + + SOFIRQ_SEL + These bits assign SOFIRQ interrupt flag to selected interrupt signals. + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + DIRQ_SEL + These bits assign DIRQ interrupt flag to selected interrupt signals. + [3:2] + read-write + + + CNNIRQ_SEL + These bits assign CNNIRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + CMPIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [7:6] + read-write + + + URIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + RWKIRQ_SEL + These bits assign RWKIRQ interrupt flag to selected interrupt signals. + [11:10] + read-write + + + RSVD_13_12 + N/A + [13:12] + read-write + + + TCAN_SEL + These bits assign TCAN interrupt flag to selected interrupt signals. + [15:14] + read-write + + + + + HOST_LVL2_SEL + Host Interrupt Level 2 Selection Register + 0x804 + 32 + read-write + 0x0 + 0xFF0 + + + EP1_DRQ_SEL + These bits assign EP1_DRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + EP1_SPK_SEL + These bits assign EP1_SPK interrupt flag to selected interrupt signals. + [7:6] + read-write + + + EP2_DRQ_SEL + These bits assign EP2_DRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + EP2_SPK_SEL + These bits assign EP2_SPK interrupt flag to selected interrupt signals. + [11:10] + read-write + + + + + INTR_USBHOST_CAUSE_HI + Interrupt USB Host Cause High Register + 0x900 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_MED + Interrupt USB Host Cause Medium Register + 0x904 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_LO + Interrupt USB Host Cause Low Register + 0x908 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_HOST_EP_CAUSE_HI + Interrupt USB Host Endpoint Cause High Register + 0x920 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_MED + Interrupt USB Host Endpoint Cause Medium Register + 0x924 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_LO + Interrupt USB Host Endpoint Cause Low Register + 0x928 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_USBHOST + Interrupt USB Host Register + 0x940 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQ + If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Does not issue an interrupt request by starting a SOF token. +'1' : Issues an interrupt request by starting a SOF token. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + DIRQ + If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device disconnection. +'1' : Issues an interrupt request by detecting a device disconnection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:1] + read-write + + + CNNIRQ + If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device connection. +'1' : Issues an interrupt request by detecting a device connection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + CMPIRQ + If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by token completion. +'1' : Issues an interrupt request by token completion. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. +- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [3:3] + read-write + + + URIRQ + If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by USB bus resetting. +'1' : Issues an interrupt request by USB bus resetting. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + RWKIRQ + If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by restart. +'1' : Issues an interrupt request by restart. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCAN + If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. +'0' : Does not cancel token sending. +'1' : Cancels token sending. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + INTR_USBHOST_SET + Interrupt USB Host Set Register + 0x944 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQS + This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [0:0] + read-write + + + DIRQS + This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [1:1] + read-write + + + CNNIRQS + This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [2:2] + read-write + + + CMPIRQS + This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [3:3] + read-write + + + URIRQS + This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [4:4] + read-write + + + RWKIRQS + This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANS + This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. + [7:7] + read-write + + + + + INTR_USBHOST_MASK + Interrupt USB Host Mask Register + 0x948 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQM + This bit masks the interrupt by SOF flag. +'0' : Disables +'1' : Enables + [0:0] + read-write + + + DIRQM + This bit masks the interrupt by DIRQ flag. +'0' : Disables +'1' : Enables + [1:1] + read-write + + + CNNIRQM + This bit masks the interrupt by CNNIRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + CMPIRQM + This bit masks the interrupt by CMPIRQ flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + URIRQM + This bit masks the interrupt by URIRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + RWKIRQM + This bit masks the interrupt by RWKIRQ flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANM + This bit masks the interrupt by TCAN flag. +'0' : Disables +'1' : Enables + [7:7] + read-write + + + + + INTR_USBHOST_MASKED + Interrupt USB Host Masked Register + 0x94C + 32 + read-only + 0x0 + 0xFF + + + SOFIRQED + This bit indicates the interrupt by SOF flag. +'0' : Doesn't request the interrupt by SOF +'1' : Request the interrupt by SOF + [0:0] + read-only + + + DIRQED + This bit indicates the interrupt by DIRQ flag. +'0' : Doesn't request the interrupt by DIRQ +'1' : Request the interrupt by DIRQ + [1:1] + read-only + + + CNNIRQED + This bit indicates the interrupt by CNNIRQ flag. +'0' : Doesn't request the interrupt by CNNIRQ +'1' : Request the interrupt by CNNIRQ + [2:2] + read-only + + + CMPIRQED + This bit indicates the interrupt by CMPIRQ flag. +'0' : Doesn't request the interrupt by CMPIRQ +'1' : Request the interrupt by CMPIRQ + [3:3] + read-only + + + URIRQED + This bit indicates the interrupt by URIRQ flag. +'0' : Doesn't request the interrupt by URIRQ +'1' : Request the interrupt by URIRQ + [4:4] + read-only + + + RWKIRQED + This bit indicates the interrupt by RWKIRQ flag. +'0' : Doesn't request the interrupt by RWKIRQ +'1' : Request the interrupt by RWKIRQ + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCANED + This bit indicates the interrupt by TCAN flag. +'0' : Doesn't request the interrupt by TCAN +'1' : Request the interrupt by TCAN + [7:7] + read-only + + + + + INTR_HOST_EP + Interrupt USB Host Endpoint Register + 0xA00 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQ + This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [2:2] + read-write + + + EP1SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The EP1SPK bit is not set during data transfer in the OUT direction. + [3:3] + read-write + + + EP2DRQ + This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [4:4] + read-write + + + EP2SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The SPK bit is not set during data transfer in the OUT direction. + [5:5] + read-write + + + + + INTR_HOST_EP_SET + Interrupt USB Host Endpoint Set Register + 0xA04 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQS + This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. + [2:2] + read-write + + + EP1SPKS + This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. + [3:3] + read-write + + + EP2DRQS + This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. + [4:4] + read-write + + + EP2SPKS + This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. + [5:5] + read-write + + + + + INTR_HOST_EP_MASK + Interrupt USB Host Endpoint Mask Register + 0xA08 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQM + This bit masks the interrupt by EP1DRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + EP1SPKM + This bit masks the interrupt by EP1SPK flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + EP2DRQM + This bit masks the interrupt by EP2DRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + EP2SPKM + This bit masks the interrupt by EP2SPK flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + + + INTR_HOST_EP_MASKED + Interrupt USB Host Endpoint Masked Register + 0xA0C + 32 + read-only + 0x0 + 0x3C + + + EP1DRQED + This bit indicates the interrupt by EP1DRQ flag. +'0' : Doesn't request the interrupt by EP1DRQ +'1' : Request the interrupt by EP1DRQ + [2:2] + read-only + + + EP1SPKED + This bit indicates the interrupt by EP1SPK flag. +'0' : Doesn't request the interrupt by EP1SPK +'1' : Request the interrupt by EP1SPK + [3:3] + read-only + + + EP2DRQED + This bit indicates the interrupt by EP2DRQ flag. +'0' : Doesn't request the interrupt by EP2DRQ +'1' : Request the interrupt by EP2DRQ + [4:4] + read-only + + + EP2SPKED + This bit indicates the interrupt by EP2SPK flag. +'0' : Doesn't request the interrupt by EP2SPK +'1' : Request the interrupt by EP2SPK + [5:5] + read-only + + + + + HOST_DMA_ENBL + Host DMA Enable Register + 0xB00 + 32 + read-write + 0x0 + 0xC + + + DM_EP1DRQE + This bit enables DMA Request by EP1DRQ. +'0' : Disable +'1' : Enable + [2:2] + read-write + + + DM_EP2DRQE + This bit enables DMA Request by EP2DRQ. +'0' : Disable +'1' : Enable + [3:3] + read-write + + + + + HOST_EP1_BLK + Host Endpoint 1 Block Register + 0xB20 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') + [31:16] + read-write + + + + + HOST_EP2_BLK + Host Endpoint 2 Block Register + 0xB30 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') + [31:16] + read-write + + + + + + + + SMIF0 + Serial Memory Interface + SMIF + 0x40420000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x3000 + 0x81073001 + + + XIP_MODE + Mode of operation. + +Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. + [0:0] + read-write + + + MMIO_MODE + '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. + 0 + + + XIP_MODE + 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. + 1 + + + + + CLOCK_IF_RX_SEL + Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. +'0': 'spi_clk_out' (internal clock) +'1': !'spi_clk_out' (internal clock) +'2': 'spi_clk_in' (feedback clock) +'3': !'spi_clk_in' (feedback clock) + +Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. + [13:12] + read-write + + + DESELECT_DELAY + Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: +'0': 1 interface clock cycle. +'1': 2 interface clock cycles. +'2': 3 interface clock cycles. +'3': 4 interface clock cycles. +'4': 5 interface clock cycles. +'5': 6 interface clock cycles. +'6': 7 interface clock cycles. +'7': 8 interface clock cycles. + +During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. + [18:16] + read-write + + + BLOCK + Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. + +This field is not used for test controller accesses. + [24:24] + read-write + + + BUS_ERROR + 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). + 0 + + + WAIT_STATES + 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). + 1 + + + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. +'1': Enabled. + +Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + Cache, cryptography, XIP, device interface or any other logic busy in the IP: +'0': not busy +'1': busy +When BUSY is '0', the IP can be safely disabled without: +- the potential loss of transient write data. +- the potential risk of aborting an inflight SPI device interface transfer. +When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. + [31:31] + read-only + + + + + TX_CMD_FIFO_STATUS + Transmitter command FIFO status + 0x44 + 32 + read-only + 0x0 + 0x7 + + + USED3 + Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. + [2:0] + read-only + + + + + TX_CMD_FIFO_WR + Transmitter command FIFO write + 0x50 + 32 + write-only + 0x0 + 0xFFFFF + + + DATA20 + Command data. The higher two bits DATA[19:18] specify the specific command +'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. +- DATA[17:16] specifies the width of the data transfer: + - '0': 1 bit/cycle (single data transfer). + - '1': 2 bits/cycle (dual data transfer). + - '2': 4 bits/cycle (quad data transfer). + - '3': 8 bits/cycle (octal data transfer). +- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. +- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. + - '0': device deselected + - '1': device selected +- DATA[7:0] specifies the transmitted Byte. + +'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. + +'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. + +'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. +- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. + [19:0] + write-only + + + + + TX_DATA_FIFO_CTL + Transmitter data FIFO control + 0x80 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. + [2:0] + read-write + + + + + TX_DATA_FIFO_STATUS + Transmitter data FIFO status + 0x84 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_DATA_FIFO_WR1 + Transmitter data FIFO write + 0x90 + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + TX_DATA_FIFO_WR2 + Transmitter data FIFO write + 0x94 + 32 + write-only + 0x0 + 0xFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + + + TX_DATA_FIFO_WR4 + Transmitter data FIFO write + 0x98 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + DATA2 + TX data (written to TX data FIFO, third byte). + [23:16] + write-only + + + DATA3 + TX data (written to TX data FIFO, fourth byte). + [31:24] + write-only + + + + + RX_DATA_FIFO_CTL + Receiver data FIFO control + 0xC0 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. + [2:0] + read-write + + + + + RX_DATA_FIFO_STATUS + Receiver data FIFO status + 0xC4 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + RX_DATA_FIFO_RD1 + Receiver data FIFO read + 0xD0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + RX_DATA_FIFO_RD2 + Receiver data FIFO read + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + + + RX_DATA_FIFO_RD4 + Receiver data FIFO read + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + DATA2 + RX data (read from RX data FIFO, third byte). + [23:16] + read-only + + + DATA3 + RX data (read from RX data FIFO, fourth byte). + [31:24] + read-only + + + + + RX_DATA_FIFO_RD1_SILENT + Receiver data FIFO silent read + 0xE0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + SLOW_CA_CTL + Slow cache control + 0x100 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. + [25:24] + read-write + + + PREF_EN + Prefetch enable: +'0': Disabled. +'1': Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + ENABLED + Cache enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + SLOW_CA_CMD + Slow cache command + 0x108 + 32 + read-write + 0x0 + 0x1 + + + INV + Cache and prefetch buffer invalidation. +SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. +Note, +A write access will invalidate the prefetch buffer automatically in hardware. +A write access should invalidate both fast and slow caches, by firmware. +Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. + [0:0] + read-write + + + + + FAST_CA_CTL + Fast cache control + 0x180 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + See SLOW_CA_CTL.WAY. + [17:16] + read-write + + + SET_ADDR + See SLOW_CA_CTL.SET_ADDR. + [25:24] + read-write + + + PREF_EN + See SLOW_CA_CTL.PREF_EN. + [30:30] + read-write + + + ENABLED + See SLOW_CA_CTL.ENABLED. + [31:31] + read-write + + + + + FAST_CA_CMD + Fast cache command + 0x188 + 32 + read-write + 0x0 + 0x1 + + + INV + See SLOW_CA_CMD.INV. + [0:0] + read-write + + + + + CRYPTO_CMD + Cryptography Command + 0x200 + 32 + read-write + 0x0 + 0x1 + + + START + SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. + +The operation takes roughly 13 clk_hf clock cycles. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + + + CRYPTO_INPUT0 + Cryptography input 0 + 0x220 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT1 + Cryptography input 1 + 0x224 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT2 + Cryptography input 2 + 0x228 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT3 + Cryptography input 3 + 0x22C + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_KEY0 + Cryptography key 0 + 0x240 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY1 + Cryptography key 1 + 0x244 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY2 + Cryptography key 2 + 0x248 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY3 + Cryptography key 3 + 0x24C + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_OUTPUT0 + Cryptography output 0 + 0x260 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT1 + Cryptography output 1 + 0x264 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT2 + Cryptography output 2 + 0x268 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT3 + Cryptography output 3 + 0x26C + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. + [31:0] + read-write + + + + + INTR + Interrupt register + 0x7C0 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. + [0:0] + read-write + + + TR_RX_REQ + Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Activated in XIP mode, if: +- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. +- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. + +Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. + [5:5] + read-write + + + + + INTR_SET + Interrupt set register + 0x7C4 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x7C8 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x7CC + 32 + read-only + 0x0 + 0x3F + + + TR_TX_REQ + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TR_RX_REQ + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + XIP_ALIGNMENT_ERROR + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TX_CMD_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + TX_DATA_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + RX_DATA_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + 3 + 128 + DEVICE[%s] + Device (only used in XIP mode) + 0x00000800 + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80030101 + + + WR_EN + Write enable: +'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. +'1': write transfers are allowed to this device. + [0:0] + read-write + + + CRYPTO_EN + Cryptography on read/write accesses: +'0': disabled. +'1': enabled. + [8:8] + read-write + + + DATA_SEL + Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): +'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. +'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. +'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. +'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. + [17:16] + read-write + + + ENABLED + Device enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + ADDR + Device region base address + 0x8 + 32 + read-write + 0x0 + 0x0 + + + ADDR + Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. + +In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. + +The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. + [31:8] + read-write + + + + + MASK + Device region mask + 0xC + 32 + read-write + 0x0 + 0x0 + + + MASK + Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. + +The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. + +Note: a transfer request that is not in any device region results in an AHB-Lite bus error. + [31:8] + read-write + + + + + ADDR_CTL + Address control + 0x20 + 32 + read-write + 0x0 + 0x103 + + + SIZE2 + Specifies the size of the XIP device address in Bytes: +'0': 1 Byte address. +'1': 2 Byte address. +'2': 3 Byte address. +'3': 4 Byte address. +The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [1:0] + read-write + + + DIV2 + Specifies if the AHB-Lite bus transfer address is divided by 2 or not: +'0': No divide by 2. +'1': Divide by 2. + +This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [8:8] + read-write + + + + + RD_CMD_CTL + Read command control + 0x40 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of data transfer: +'0': 1 bit/cycle (single data transfer). +'1': 2 bits/cycle (dual data transfer). +'2': 4 bits/cycle (quad data transfer). +'3': 8 bits/cycle (octal data transfer). + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_ADDR_CTL + Read address control + 0x44 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + RD_MODE_CTL + Read mode control + 0x48 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DUMMY_CTL + Read dummy control + 0x4C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + +Note: this field specifies dummy cycles, not dummy Bytes! + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DATA_CTL + Read data control + 0x50 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_CMD_CTL + Write command control + 0x60 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_ADDR_CTL + Write address control + 0x64 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_MODE_CTL + Write mode control + 0x68 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DUMMY_CTL + Write dummy control + 0x6C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DATA_CTL + Write data control + 0x70 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + + + + SDHC0 + SD/eMMC Host Controller + SDHC + 0x40460000 + + 0 + 65536 + registers + + + + WRAP + MMIO at SDHC wrapper level + 0x00000000 + + CTL + Top level wrapper control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + IP Enable: +0: IP disabled, RAM in DeepSleep, SDHC_CORE regs are inaccessible (any attempts to access will result in AHB Error responses), IP is NOT held in reset but the clocks are gated +1: IP enabled, normal operation + [31:31] + read-write + + + + + + CORE + MMIO for Synopsys Mobile Storage Host Controller IP + 0x00001000 + + SDMASA_R + SDMA System Address register + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This +register contains the system memory address for an +SDMA transfer in the 32-bit addressing mode. When the +Host Controller stops an SDMA transfer, this register +points to the system address of the next contiguous data +position. It can be accessed only if no transaction is +executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the +Host Controller Version 4.10 specification, this register is +redefined as 32-bit Block Count. The Host Controller +decrements the block count of this register for every block +transfer and the data transfer stops when the count +reaches zero. This register must be accessed when no +transaction is executing. Reading this register during data +transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF - 4G - 1 Block +- ...... +- 0x0000_0002 - 2 Blocks +- 0x0000_0001 - 1 Block +- 0x0000_0000 - Stop Count +Note: +- When Host Version 4 Enable = 0, SDMA uses this register as system address and hence Auto CMD23 cannot be used with SDMA since this register is assigned for Auto CMD23 as 32-bit Block Count register. +-When Host Version 4 Enable = 1, SDMA uses ADMA system address register and this register is reassigned to 32-bit Block Count. This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. SDMA may use Auto CMD23 if 32-bit Block Count register is used. + [31:0] + read-write + + + + + BLOCKSIZE_R + Block Size register + 0x4 + 16 + read-write + 0x0 + 0x7FFF + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of +memory, it is set to 512 bytes. It can be accessed only if no +transaction is executing. Read operations during transfers +may return an invalid value, and write operations are +ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- ...... +- 0x1FF: 511 byte +- 0x200: 512 bytes +- ...... +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero +value for data transfer. + [11:0] + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system +memory. The SDMA transfer waits at every boundary +specified by these fields and the Host Controller generates +the DMA interrupt to request the Host Driver to update the +SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + [14:12] + read-write + + + + + BLOCKCOUNT_R + 16-bit Block Count register + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block +Count register is set to non-zero, the 16-bit Block Count +register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit +Block Count register is set to zero, the 32-bit Block Count +register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- ... - ... +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be +set to 0000h before programming the 32-bit block count +register when Auto CMD23 is enabled for non-DMA and +ADMA modes. + [15:0] + read-write + + + + + ARGUMENT_R + Argument register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ARGUMENT + Command Argument +These bits specify the SD/eMMC command argument that is +specified in bits 39-8 of the Command format. + [31:0] + read-write + + + + + XFER_MODE_R + Transfer Mode register + 0xC + 16 + read-write + 0x0 + 0x1FF + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a +DMA operation begins when the Host Driver writes to the +Command register. You can select one of the DMA modes by +using DMA Select in the Host Control 1 register. +Values: +- 0x1 (ENABLED): DMA Data transfer +- 0x0 (DISABLED): No data transfer or Non-DMA data +transfer + [0:0] + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is +relevant for multiple block transfers. If this bit is set to 0, the +Block Count register is disabled, which is useful in executing +an infinite transfer. The Host Driver must set this bit to 0 +when ADMA is used. When 16-bit Block Count register is used, the Host Driver can set this bit to 0 in ADMA2 mode to enable larger data transfer than the maximum of 65535 block counts supported by the 16-bit Block Count register. + [1:1] + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command +Disabled). +Values: +- 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +- 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +- 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +- 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Select + [3:2] + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. This +bit is set to 1 by the Host Driver to transfer data from the +SD/eMMC card to the Host Controller and it is set to 0 for all +other commands. +Values: +- 0x1 (READ): Read (Card to Host) +- 0x0 (WRITE): Write (Host to Card) + [4:4] + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer +commands using the DAT line. If this bit is set to 0, it is not +necessary to set the Block Count register. + [5:5] + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the +Response Error Check is selected. +Error statuses checked in R1: +- OUT_OF_RANGE +- ADDRESS_ERROR +- BLOCK_LEN_ERROR +- WP_VIOLATION +- CARD_IS_LOCKED +- COM_CRC_ERROR +- CARD_ECC_FAILED +- CC_ERROR +- ERROR +Response Flags checked in R5: +- COM_CRC_ERROR +- ERROR +- FUNCTION_NUMBER +- OUT_OF_RANGE +Values: +- 0x0 (RESP_R1): R1 (Memory) +- 0x1 (RESP_R5): R5 (SDIO) + [6:6] + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to +avoid overhead of response error check by Host driver. +Response types of only R1 and R5 can be checked by the +Controller. If the Host Controller checks the response error, +set this bit to 1 and set Response Interrupt Disable to 1. If an +error is detected, the Response Error interrupt is generated +in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any +response type other than R1 and R5. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + [7:7] + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to +avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the +Controller. +If Host Driver checks the response error, set this bit to 0 and +wait for Command Complete Interrupt and then check the +response register. +If the Host Controller checks the response error, set this bit +to 1 and set the Response Error Check Enable bit to 1. The +Command Complete Interrupt is disabled by this bit +regardless of the Command Complete Signal Enable. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + [8:8] + read-write + + + + + CMD_R + Command register + 0xE + 16 + read-write + 0x0 + 0x3FFF + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the +card. +Values: +- 0x0 (NO_RESP): No Response +- 0x1 (RESP_LEN_136): Response Length 136 +- 0x2 (RESP_LEN_48): Response Length 48 +- 0x3 (RESP_LEN_48B): Response Length 48; Check +Busy after response + [1:0] + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub +command. +Values: +- 0x0 (MAIN): Main Command +- 0x1 (SUB): Sub Command + [2:2] + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in +the response. If an error is detected, it is reported as a +Command CRC error. +Note: +- CRC Check enable must be set to 0 for the command +with no response, R3 response, and R4 response. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [3:3] + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in +the response to verify if it has the same value as the +command index. If the value is not the same, it is reported as +a Command Index error. +Note: +- Index Check enable must be set to 0 for the command +with no response, R2 response, R3 response and R4 +response. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [4:4] + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the +data is transferred using the DAT line. This bit is set to 0 in +the following instances: +- Command using the CMD line +- Command with no data transfer but using busy signal on +the DAT[0] line +- Resume Command +Values: +- 0x0 (NO_DATA): No Data Present +- 0x1 (DATA): Data Present + [5:5] + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or +reset CMD using CMD0/CMD52, CMD_TYPE field shall be +set to 0x3. +Values: +- 0x3 (ABORT_CMD): Abort +- 0x2 (RESUME_CMD): Resume +- 0x1 (SUSPEND_CMD): Suspend +- 0x0 (NORMAL_CMD): Normal + [7:6] + read-write + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified +in bits 45-40 of the Command Format. + [13:8] + read-write + + + + + RESP01_R + Response Register 0/1 + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the +Response Field) is updated in the RESP67_R register. + [31:0] + read-only + + + + + RESP23_R + Response Register 2/3 + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP23 + Command Response +These bits reflect 71-40 bits of the SD/eMMC Response + [31:0] + read-only + + + + + RESP45_R + Response Register 4/5 + 0x18 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP45 + Command Response +These bits reflect 103-72 bits of the Response Field. + [31:0] + read-only + + + + + RESP67_R + Response Register 6/7 + 0x1C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP67 + Command Response +These bits reflect bits 135-104 of SD/EMMC Response +Field. +Note: For Auto CMD, this register also reflects the 32-bit +response (bits 39-8 of the Response Field). + [31:0] + read-only + + + + + BUF_DATA_R + Buffer Data Port Register + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet +buffer. + [31:0] + read-write + + + + + PSTATE_REG + Present State Register + 0x24 + 32 + read-only + 0x0 + 0x1BFF0FF7 + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +- SD/eMMC mode: If this bit is set to 0, it indicates that the +CMD line is not in use and the Host controller can issue +an SD/eMMC command using the CMD line. This bit is +set when the command register is written. This bit is +cleared when the command response is received. This bit +is not cleared by the response of auto CMD12/23 but +cleared by the response of read/write command. +Values: +- 0x0 (READY): Host Controller is ready to issue a +command +- 0x1 (NOT_READY): Host Controller is not ready to issue +a command + [0:0] + read-only + + + CMD_INHIBIT_DAT + Command Inhibit (DAT) +This bit is applicable for SD/eMMC mode and is generated if +either DAT line active or Read transfer active is set to 1. If +this bit is set to 0, it indicates that the Host Controller can +issue subsequent SD/eMMC commands. +Values: +- 0x0 (READY): Can issue command which used DAT line +- 0x1 (NOT_READY): Cannot issue command which used +DAT line + [1:1] + read-only + + + DAT_LINE_ACTIVE + DAT Line Active (SD/eMMC Mode only) +This bit indicates whether one of the DAT lines on the +SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a +read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a +write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the +command executing busy is executing on an SD or eMMC +bus. +Values: +- 0x0 (INACTIVE): DAT Line Inactive +- 0x1 (ACTIVE): DAT Line Active + [2:2] + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from +errors and for debugging. These bits reflect the value of the +sd_dat_in (upper nibble) signal. + [7:4] + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for +SD/eMMC mode. +Values: +- 0x0 (INACTIVE): No valid data +- 0x1 (ACTIVE): Transferring data + [8:8] + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for +SD/eMMC mode. +Values: +- 0x0 (INACTIVE): No valid data +- 0x1 (ACTIVE): Transferring data + [9:9] + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space +is available for writing data. +Values: +- 0x0 (DISABLED): Write disable +- 0x1 (ENABLED): Write enable + [10:10] + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid +data exists in the Host buffer. +Values: +- 0x0 (DISABLED): Read disable +- 0x1 (ENABLED): Read enable + [11:11] + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The +Host Controller debounces this signal so that Host Driver +need not wait for it to stabilize. +Values: +- 0x0 (FALSE): Reset, Debouncing, or No card +- 0x1 (TRUE): Card Inserted + [16:16] + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A +card is not detected if this bit is set to 1 and the value of the +CARD_INSERTED bit is 0. +Values: +- 0x0 (FALSE): Reset or Debouncing +- 0x1 (TRUE): No Card or Inserted + [17:17] + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the +card_detect_n signal. +Values: +- 0x0 (FALSE): No card present +- 0x1 (TRUE): Card Present + [18:18] + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This +bit reflects the synchronized value of the card_write_prot +signal. +Values: +- 0x0 (FALSE): Write protected +- 0x1 (TRUE): Write enabled + [19:19] + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from +errors and for debugging. These bits reflect the value of the +sd_dat_in (lower nibble) signal. + [23:20] + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from +errors and for debugging. These bits reflect the value of the +sd_cmd_in signal. + [24:24] + read-only + + + HOST_REG_VOL + Host Regulator Voltage Stable +This bit is used to check whether the host regulator voltage is +stable for switching the voltage of UHS-I mode. This bit +reflects the synchronized value of the host_reg_vol_stable +signal. +Values: +- 0x0 (FALSE): Host Regulator Voltage is not stable +- 0x1 (TRUE): Host Regulator Voltage is stable + [25:25] + read-only + + + CMD_ISSU_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting +the command register due to an error except the Auto +CMD12 error. +Values: +- 0x0 (FALSE): No error for issuing a command +- 0x1 (TRUE): Command cannot be issued + [27:27] + read-only + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and +a sub command status. +Values: +- 0x0 (FALSE): Main Command Status +- 0x1 (TRUE): Sub Command Status + [28:28] + read-only + + + + + HOST_CTRL1_R + Host Control 1 Register + 0x28 + 8 + read-write + 0x0 + 0xFF + + + LED_CTRL + LED Control +This bit is used to caution the user not to remove the card +while the SD card is being accessed. The value is reflected +on the led_ctrl ouput. +Values: +- 0x0 (OFF): LED off +- 0x1 (ON): LED on + [0:0] + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of +the Host Controller. The Host Driver sets it to match the data +width of the SD/eMMC card. +Values: +- 0x1 (FOUR_BIT): 4-bit mode +- 0x0 (ONE_BIT): 1-bit mode + [1:1] + read-write + + + HIGH_SPEED_EN + High Speed Enable (SD/eMMC Mode only) +Before setting this bit, the Host Driver checks the High Speed +Support in the Capabilities register. +Note: SDHC always outputs the sd_cmd_out and +sd_dat_out lines at the rising edge of card clock +irrespective of this bit. +Values: +- 0x1 (HIGH_SPEED): High Speed mode +- 0x0 (NORMAL_SPEED): Normal Speed mode + [2:2] + read-write + + + DMA_SEL + N/A + [4:3] + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +- 0x1 (EIGHT_BIT): 8-bit Bus Width +- 0x0 (DEFAULT): Bus Width is selected by the Data +Transfer Width + [5:5] + read-write + + + CARD_DETECT_TEST_LVL + Card Detect Test Level +This bit is enabled while the Card Detect Signal Selection is +set to 1 and it indicates whether a card inserted or not. +Values: +- 0x1 (CARD_INSERTED): Card Inserted +- 0x0 (No_CARD): No Card + [6:6] + read-write + + + CARD_DETECT_SIG_SEL + Card Detect Signal Selection +This bit selects a source for card detection. When the source +for the card detection is switched, the interrupt must be +disabled during the switching period. +Values: +- 0x1 (CARD_DT_TEST_LEVEL): Card Detect Test Level +is selected (for test purpose) +- 0x0 (card_detect_n): card_detect_n signal is +selected (for normal use) + [7:7] + read-write + + + + + PWR_CTRL_R + Power Control Register + 0x29 + 8 + read-write + 0x0 + 0xF + + + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. This setting is +available on the card_if_pwr_en output so that it +can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus +Voltage Select bit. If the Host Controller detects a No Card +state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops +the SD Clock by clearing the SD_CLK_IN bit in the +CLK_CTRL_R register. +Values: +- 0x0 (OFF): Power off +- 0x1 (ON): Power on + [0:0] + read-write + + + SD_BUS_VOL_VDD1 + These bits are NON-operational (they can be written and read but they have no effect). In a generic HCI host these would select the card supply voltage. But, for the applications targeted for this block it is assumed that the card supply voltage is always fixed at the board level. If for some reason there is a variable power supply then that can be managed through normal GPIO programming separately. + [3:1] + read-write + + + + + BGAP_CTRL_R + Block Gap Control Register + 0x2A + 8 + read-write + 0x0 + 0xF + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions +at the next block gap for non-DMA, SDMA, and ADMA +transfers. +Values: +- 0x0 (XFER): Transfer +- 0x1 (STOP): Stop + [0:0] + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped +using the Stop At Block Gap Request. The Host Controller +automatically clears this bit when the transaction restarts. If +stop at block gap request is set to 1, any write to this bit is +ignored. +Values: +- 0x0 (NO_AFFECT): No Affect +- 0x1 (RESTART): Restart + [1:1] + read-write + + + RD_WAIT_CTRL + N/A + [2:2] + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is +used to select a sample point in the interrupt cycle. Setting to +1 enables interrupt detection at the block gap for a multiple +block transfer. +Values: +- 0x0 (DISABLE): Disabled +- 0x1 (ENABLE): Enabled + [3:3] + read-write + + + + + WUP_CTRL_R + Wakeup Control Register + 0x2B + 8 + read-write + 0x0 + 0x7 + + + WUP_CARD_INT + Wakeup Event Enable on SDIO Card Interrupt (through DAT[1]). +This bit enables wakeup event through an SDIO Card Interrupt +assertion in the Normal Interrupt Status register. This bit can +be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [0:0] + read-write + + + WUP_CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion +assertion in the Normal Interrupt Status register. FN_WUS +(Wake Up Support) in CIS does not affect this bit. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [1:1] + read-write + + + WUP_CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal +assertion in the Normal Interrupt Status register. For the +SDIO card, Wake Up Support (FN_WUS) in the Card +Information Structure (CIS) register does not affect this bit. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [2:2] + read-write + + + + + CLK_CTRL_R + Clock Control Register + 0x2C + 16 + read-write + 0x0 + 0xFFEF + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host +Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a +very low power state. Certain registers are not accessible when this bit is off. So, to be safe turn it on for any register access. +Values: +- 0x0 (FALSE): Stop +- 0x1 (TRUE): Oscillate + [0:0] + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability +twice after the Internal Clock Enable bit is set and after the +PLL Enable bit is set. This bit reflects the synchronized +value of the Internal Clock Stable signal after the Internal Clock +Enable bit is set to 1 and also reflects the synchronized +value of the Card Clock Stable signal after the PLL Enable bit is +set to 1. +Values: +- 0x0 (FALSE): Not Ready +- 0x1 (TRUE): Ready + [1:1] + read-only + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the clk_card output when set to 0. The +SDCLK Frequency Select bit can be changed when +this bit is set to 0. +Values: +- 0x0 (FALSE): Disable providing clk_card +- 0x1 (TRUE): Enable providing clk_card + [2:2] + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host +Version 4 Enable = 1). +Values: +- 0x0 (FALSE): PLL is in low power mode +- 0x1 (TRUE): PLL is enabled + [3:3] + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in +SDCLK Frequency Select. +Values: +- 0x0 (FALSE): Divided Clock Mode +- 0x1 (TRUE): Programmable Clock Mode + [5:5] + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK +Frequency Select control. + [7:6] + read-write + + + FREQ_SEL + SDCLK Frequency Select +These bits are used to select the frequency of the SDCLK +signal. +10-bit Divided Clock Mode: +- 0x3FF - 1/2046 Divided clock +- .......... +- N - 1/2N Divided Clock +- .......... +- 0x002 - 1/4 Divided Clock +- 0x001 - 1/2 Divided Clock +- 0x000 - Base clock (10MHz - 255 MHz) + [15:8] + read-write + + + + + TOUT_CTRL_R + Timeout Control Register + 0x2E + 8 + read-write + 0x0 + 0xF + + + TOUT_CNT + N/A + [3:0] + read-write + + + + + SW_RST_R + Software Reset Register + 0x2F + 8 + read-write + 0x0 + 0x7 + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the +card detection circuit. During its initialization, the Host Driver +sets this bit to 1 to reset the Host Controller. All registers are +reset except the capabilities register. If this bit is set to 1, the +Host Driver must issue reset command and reinitialize the +card. +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [0:0] + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able +to issue a command. This reset is effective only for a command +issuing circuit (including response error statuses related to +Command Inhibit (CMD) control) and does not affect the +data transfer circuit. Host Controller can continue data +transfer even after this reset is executed while handling +subcommand-response errors. +The following registers and bits are cleared by this bit: +- Present State register - Command Inhibit (CMD) bit +- Normal Interrupt Status register - Command Complete bit +- Error Interrupt Status - Response error statuses related +to Command Inhibit (CMD) bit +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [1:1] + read-write + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part +of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +- Buffer Data Port register +- Buffer is cleared and initialized. +- Present state register +- Buffer Read Enable +- Buffer Write Enable +- Read Transfer Active +- Write Transfer Active +- DAT Line Active +- Command Inhibit (DAT) +- Block Gap Control register +- Continue Request +- Stop At Block Gap Request +- Normal Interrupt status register +- Buffer Read Ready +- Buffer Write Ready +- DMA Interrupt +- Block Gap Event +- Transfer Complete +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [2:2] + read-write + + + + + NORMAL_INT_STAT_R + Normal Interrupt Status Register + 0x30 + 16 + read-write + 0x0 + 0xE1FF + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a +response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt +Disable in Transfer Mode Register is set to 1. +Values: +- 0x0 (FALSE): No command complete +- 0x1 (TRUE): Command Complete + [0:0] + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command +with status busy is completed. +Values: +- 0x0 (FALSE): Not complete +- 0x1 (TRUE): Command execution is completed + [1:1] + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at +block gap due to a Stop at Block Gap Request. +Values: +- 0x0 (FALSE): No Block Gap Event +- 0x1 (TRUE): Transaction stopped at block gap + [2:2] + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer +Boundary during transfer. In case of ADMA, by setting the Int +field in the descriptor table, the Host controller generates this +interrupt. This interrupt is not generated after a Transfer +Complete. +Values: +- 0x0 (FALSE): No DMA Interrupt +- 0x1 (TRUE): DMA Interrupt is generated + [3:3] + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +- 0x0 (FALSE): Not ready to write buffer +- 0x1 (TRUE): Ready to write buffer + [4:4] + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +- 0x0 (FALSE): Not ready to read buffer +- 0x1 (TRUE): Ready to read buffer + [5:5] + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State +register changes from 0 to 1. +Values: +- 0x0 (FALSE): Card state stable or Debouncing +- 0x1 (TRUE): Card Inserted + [6:6] + read-write + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State +register changes from 1 to 0. +Values: +- 0x0 (FALSE): Card state stable or Debouncing +- 0x1 (TRUE): Card Removed + [7:7] + read-write + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +- DAT[1] Interrupt Input for SD Mode +Values: +- 0x0 (FALSE): No Card Interrupt +- 0x1 (TRUE): Generate Card Interrupt + [8:8] + read-only + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 +and Response Type R1/R5 is set to 0 in Transfer Mode +register. This interrupt is used with response check function. +Values: +- 0x0 (FALSE): No Event +- 0x1 (TRUE): FX Event is detected + [13:13] + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event +has occurred in eMMC/SD mode. Read CQHCI's +CQIS/CRNQIS register for more details. In UHS-II Mode, +this bit is irrelevant. +Values: +- 0x0 (FALSE): No Event +- 0x1 (TRUE): Command Queuing Event is detected + [14:14] + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, +then this bit is set. +Values: +- 0x0 (FALSE): No Error +- 0x1 (TRUE): Error + [15:15] + read-only + + + + + ERROR_INT_STAT_R + Error Interrupt Status Register + 0x32 + 16 + read-write + 0x0 + 0x1FFF + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is +returned within 64 SD clock cycles from the end bit of the +command. If the Host Controller detects a CMD line conflict, +along with Command CRC Error bit, this bit is set to 1, +without waiting for 64 SD/eMMC card clock cycles. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Time out + [0:0] + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for +following two cases. +- If a response is returned and the Command Timeout +Error is set to 0 (indicating no timeout), this bit is set to 1 +when detecting a CRC error in the command response. +- The Host Controller detects a CMD line conflict by +monitoring the CMD line when a command is issued. If +the Host Controller drives the CMD line to 1 level, but +detects 0 level on the CMD line at the next SD clock +edge, then the Host Controller aborts the command (stop +driving CMD line) and set this bit to 1. The Command +Timeout Error is also set to 1 to distinguish a CMD line +conflict. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): CRC error generated + [1:1] + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command +response is 0 in SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): End Bit error generated + [2:2] + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the +command respons in SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [3:3] + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the +following timeout conditions: +- Busy timeout for R1b, R5b type +- Busy timeout after Write CRC status +- Write CRC Status timeout +- Read Data timeout +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Time out + [4:4] + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC +error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other +than 010 or when write CRC status timeout. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [5:5] + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 +at the end bit position of read data that uses the DAT line or +at the end bit position of the CRC status. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [6:6] + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control +register, the Host Controller is requested to supply power for +the SD Bus. If the Host Controller supports the Current Limit +function, it can be protected from an illegal card by stopping +power supply to the card in which case this bit indicates a +failure status. A reading of 1 for this bit means that the Host +Controller is not supplying power to the SD card due to some +failure. A reading of 0 for this bit means that the Host +Controller is supplying power and no error has occurred. The +Host Controller may require some sampling time to detect +the current limit. DWC_mshc Host Controller does not +support this function, this bit is always set to 0. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Power Fail + [7:7] + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in +SD/eMMC mode. This bit is set when detecting that any of +the bits D00 to D05 in Auto CMD Error Status register has +changed from 0 to 1. D07 is effective in case of Auto CMD12. +Auto CMD Error Status register is valid while this bit is set to +1 and may be cleared by clearing of this bit. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [8:8] + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during +ADMA-based data transfer. The error could be due to +following reasons: +- Error response received from System bus (Master I/F) +- ADMA3,ADMA2 Descriptors invalid +- CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the +ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects +an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that +an error has occurred in ST_FDS state. The Host Driver may +find that Valid bit is not set at the error descriptor. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [9:9] + read-write + + + TUNING_ERR + N/A + [10:10] + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check +function to avoid overhead of response error check by Host +Driver during DMA execution. If Response Error Check +Enable is set to 1 in the Transfer Mode register, Host +Controller Checks R1 or R5 response. If an error is detected +in a response, this bit is set to 1.This is applicable in +SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [11:11] + read-write + + + BOOT_ACK_ERR + Boot Acknowledgement Error +This bit is set when there is a timeout for boot +acknowledgement or when detecting boot ack status having +a value other than 010. This is applicable only when boot +acknowledgement is expected in eMMC mode. +In SD mode, this bit is irrelevant. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [12:12] + read-write + + + + + NORMAL_INT_STAT_EN_R + Normal Interrupt Status Enable Register + 0x34 + 16 + read-write + 0x0 + 0x7FFF + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt +request to the System. The Card Interrupt detection is +stopped when this bit is cleared and restarted when this bit is +set to 1. The Host Driver may clear the Card Interrupt Status +Enable before servicing the Card Interrupt and may set this +bit again after all interrupt requests from the card are cleared +to prevent inadvertent interrupts. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + INT_A_STAT_EN + N/A + [9:9] + read-write + + + INT_B_STAT_EN + N/A + [10:10] + read-write + + + INT_C_STAT_EN + N/A + [11:11] + read-write + + + RE_TUNE_EVENT_STAT_EN + N/A + [12:12] + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [13:13] + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + + + ERROR_INT_STAT_EN_R + Error Interrupt Status Enable Register + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode +only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + CMD_CRC_ERR_STAT_EN + ommand CRC Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [9:9] + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [10:10] + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [11:11] + read-write + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment +Error in Error Interrupt Status register +(ERROR_INT_STAT_R). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [12:12] + read-write + + + VENDOR_ERR_STAT_EN1 + N/A + [13:13] + read-write + + + VENDOR_ERR_STAT_EN2 + N/A + [14:14] + read-write + + + VENDOR_ERR_STAT_EN3 + N/A + [15:15] + read-write + + + + + NORMAL_INT_SIGNAL_EN_R + Normal Interrupt Signal Enable Register + 0x38 + 16 + read-write + 0x0 + 0x7FFF + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + INT_A_SIGNAL_EN + N/A + [9:9] + read-write + + + INT_B_SIGNAL_EN + N/A + [10:10] + read-write + + + INT_C_SIGNAL_EN + N/A + [11:11] + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + N/A + [12:12] + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [13:13] + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + + + ERROR_INT_SIGNAL_EN_R + Error Interrupt Signal Enable Register + 0x3A + 16 + read-write + 0x0 + 0xFFFF + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [3:3] + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [9:9] + read-write + + + TUNING_ERR_SIGNAL_EN + N/A + [10:10] + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [11:11] + read-write + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when +Boot Acknowledgement Error in Error Interrupt Status +register is set. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [12:12] + read-write + + + VENDOR_ERR_SIGNAL_EN1 + N/A + [13:13] + read-write + + + VENDOR_ERR_SIGNAL_EN2 + N/A + [14:14] + read-write + + + VENDOR_ERR_SIGNAL_EN3 + N/A + [15:15] + read-write + + + + + AUTO_CMD_STAT_R + Auto CMD Status Register + 0x3C + 16 + read-only + 0x0 + 0xBF + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a +command error, this bit is not set because it is not necessary +to issue an Auto CMD12. Setting this bit to 1 means that the +Host Controller cannot issue Auto CMD12 to stop multiple +memory block data transfer, due to some error. If this bit is +set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by +Auto CMD23. +Values: +- 0x1 (TRUE): Not Executed +- 0x0 (FALSE): Executed + [0:0] + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK +cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are +meaningless. +Values: +- 0x1 (TRUE): Time out +- 0x0 (FALSE): No Error + [1:1] + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command +response. +Values: +- 0x1 (TRUE): CRC Error Generated +- 0x0 (FALSE): No Error + [2:2] + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command +response is 0. +Values: +- 0x1 (TRUE): End Bit Error Generated +- 0x0 (FALSE): No Error + [3:3] + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response +to a command. +Values: +- 0x1 (TRUE): Error +- 0x0 (FALSE): No Error + [4:4] + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the +Transfer Mode register is set to 1 and an error is detected in +R1 response of either Auto CMD12 or CMD13. This status is +ignored if any bit between D00 to D04 is set to 1. +Values: +- 0x1 (TRUE): Error +- 0x0 (FALSE): No Error + [5:5] + read-only + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an +Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by +Auto CMD23. +Values: +- 0x1 (TRUE): Not Issued +- 0x0 (FALSE): No Error + [7:7] + read-only + + + + + HOST_CTRL2_R + Host Control 2 Register + 0x3E + 16 + read-write + 0x0 + 0xFDFF + + + UHS_MODE_SEL + N/A + [2:0] + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in SD UHS-I mode. Setting this bit from 0 to 1 starts changing the +signal voltage from 3.3V to 1.8V. Host Controller clears this +bit if switching to 1.8V signaling fails per protocol. The value is reflected on the io_volt_sel output which can then be used to change an external regulator to supply 1.8V instead of 3.3V on the VDDIO pin associated with the CLK/CMD/DAT signals. +Note: This bit must be set for all UHS-I speed modes +(SDR12/SDR25/SDR50/DDR50). +Values: +- 0x0 (V_3_3): 3.3V Signalling +- 0x1 (V_1_8): 1.8V Signalling + [3:3] + read-write + + + DRV_STRENGTH_SEL + Driver Strength Select +These bits are used to select the Host Controller output driver in +1.8V signaling UHS-I/eMMC speed modes. The value is reflected on the io_drive_strength[1:0] output. +- 0x0 (TYPEB): Driver TYPEB is selected +- 0x1 (TYPEA): Driver TYPEA is selected +- 0x2 (TYPEC): Driver TYPEC is selected +- 0x3 (TYPED): Driver TYPED is selected + [5:4] + read-write + + + EXEC_TUNING + N/A + [6:6] + read-write + + + SAMPLE_CLK_SEL + N/A + [7:7] + read-write + + + UHS2_IF_ENABLE + N/A + [8:8] + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or +26-bit. +Values: +- 0x0 (FALSE): 16-bit Data Length Mode +- 0x1 (TRUE): 26-bit Data Length Mode + [10:10] + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is +used to select Auto CMD23 or Auto CMD12 for ADMA3 data +transfer. +Values: +- 0x0 (FALSE): Auto CMD23 is disabled +- 0x1 (TRUE): Auto CMD23 is enabled + [11:11] + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or +Version 4 mode. +Functions of following fields are modified for Host Version 4 +mode: +- SDMA Address: SDMA uses ADMA System Address +(05Fh-058h) instead of SDMA System Address register +(003h-000h) +- ADMA2/ADMA3 selection: ADMA3 is selected by DMA +select in Host Control 1 register +- 32-bit Block Count: SDMA System Address register +(003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated +Descriptor Address registers and +Command Queuing registers (if applicable) while operating +in Host version less than 4 mode (Host Version 4 Enable = +0). +Values: +- 0x0 (FALSE): Version 3.00 compatible mode +- 0x1 (TRUE): Version 4 mode + [12:12] + read-write + + + ADDRESSING + N/A + [13:13] + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous +interrupts and Asynchronous Interrupt Support is set to 1 in +the Capabilities register. +Values: +- 0x0 (FALSE): Disabled +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + PRESET_VAL_ENABLE + N/A + [15:15] + read-write + + + + + CAPABILITIES1_R + Capabilities 1 Register - 0 to 31 + 0x40 + 32 + read-only + 0x276C6481 + 0xFFEFFFBF + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data +Timeout Error. The Timeout Clock unit defines the unit of +timeout clock frequency. It can be KHz or MHz. +- 0x00 - Get information through another method +- 0x01 - 1KHz / 1MHz +- 0x02 - 2KHz / 2MHz +- 0x03 - 3KHz / 3MHz +- ........... +- 0x3F - 63KHz / 63MHz + [5:0] + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to +detect Data TImeout Error. +Values: +- 0x0 (KHZ): KHz +- 0x1 (MHZ): MHz + [7:7] + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for +the SD Clock. The definition of these bits depend on the Host +Controller Version. +- 6-Bit Base Clock Frequency: This mode is supported by +the Host Controller version 1.00 and 2.00. The upper 2 +bits are not effective and are always 0. The unit values +are 1 MHz. The supported clock range is 10 MHz to 63 +MHz. +- 0x00 - Get information through another method +- 0x01 - 1 MHz +- 0x02 - 2 MHz +- ............. +- 0x3F - 63 MHz +- 0x40-0xFF - Not Supported +- 8-Bit Base Clock Frequency: This mode is supported by +the Host Controller version 3.00. The unit values are 1 +MHz. The supported clock range is 10 MHz to 255 MHz. +- 0x00 - Get information through another method +- 0x01 - 1 MHz +- 0x02 - 2 MHz +- ............ +- 0xFF - 255 MHz +If the frequency is 16.5 MHz, the larger value is set to +0001001b (17 MHz) because the Host Driver uses this value +to calculate the clock divider value and it does not exceed +the upper limit of the SD Clock frequency. If these bits are all +0, the Host system has to get information using a different +method. + [15:8] + read-only + + + MAX_BLK_LEN + N/A + [17:16] + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of +using an 8-bit bus width mode. This bit is not effective when +the Slot Type is set to 10b. +Values: +- 0x0 (FALSE): 8-bit Bus Width not Supported +- 0x1 (TRUE): 8-bit Bus Width Supported + [18:18] + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of +using ADMA2. +Values: +- 0x0 (FALSE): ADMA2 not Supported +- 0x1 (TRUE): ADMA2 Supported + [19:19] + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host +System supports High Speed mode and they can supply the +SD Clock frequency from 25 MHz to 50 MHz. +Values: +- 0x0 (FALSE): High Speed not Supported +- 0x1 (TRUE): High Speed Supported + [21:21] + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of +using SDMA to transfer data between the system memory +and the Host Controller directly. +Values: +- 0x0 (FALSE): SDMA not Supported +- 0x1 (TRUE): SDMA Supported + [22:22] + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports +Suspend/Resume functionality. If this bit is 0, the Host Driver +does not issue either Suspend or Resume commands +because the Suspend and Resume mechanism is not +supported. +Values: +- 0x0 (FALSE): Not Supported +- 0x1 (TRUE): Supported + [23:23] + read-only + + + VOLT_33 + Voltage Support 3.3V +Values: +- 0x0 (FALSE): 3.3V Not Supported +- 0x1 (TRUE): 3.3V Supported + [24:24] + read-only + + + VOLT_30 + Voltage Support 3.0V +Values: +- 0x0 (FALSE): 3.0V Not Supported +- 0x1 (TRUE): 3.0V Supported + [25:25] + read-only + + + VOLT_18 + Voltage Support 1.8V +Values: +- 0x0 (FALSE): 1.8V Not Supported +- 0x1 (TRUE): 1.8V Supported + [26:26] + read-only + + + SYS_ADDR_64_V4 + 64-bit System Address Support for V4 +This bit sets the Host Controller to support 64-bit System +Addressing of V4 mode. When this bit is set to 1, full or part +of 64-bit address must be used to decode the Host Controller +Registers so that Host Controller Registers can be placed +above system memory area. 64-bit address decode of Host +Controller registers is effective regardless of setting to 64-bit +Addressing in Host Control 2. +If this bit is set to 1, 64-bit DMA Addressing for version 4 is +enabled by setting Host Version 4 Enable +(HOST_VER4_ENABLE = 1) and by setting 64-bit +Addressing (ADDRESSING =1) in the Host Control 2 +register. SDMA can be used and ADMA2 uses 128-bit +Descriptor. +Values: +- 0x0 (FALSE): 64-bit System Address for V4 is Not +Supported +- 0x1 (TRUE): 64-bit System Address for V4 is Supported + [27:27] + read-only + + + SYS_ADDR_64_V3 + 64-bit System Address Support for V3 +This bit sets the Host controller to support 64-bit System +Addressing of V3 mode. +SDMA cannot be used in 64-bit Addressing in Version 3 +Mode. +If this bit is set to 1, 64-bit ADMA2 with using 96-bit +Descriptor can be enabled by setting Host Version 4 Enable +(HOST_VER4_ENABLE = 0) and DMA select (DMA_SEL = +11b). +Values: +- 0x0 (FALSE): 64-bit System Address for V3 is Not +Supported +- 0x1 (TRUE): 64-bit System Address for V3 is Supported + [28:28] + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +- 0x0 (FALSE): Asynchronous Interrupt Not Supported +- 0x1 (TRUE): Asynchronous Interrupt Supported + [29:29] + read-only + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host +System. +Values: +- 0x0 (REMOVABLE_SLOT): Removable Card Slot +- 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +- 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +- 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple +Embedded Devices + [31:30] + read-only + + + + + CAPABILITIES2_R + Capabilities Register - 32 to 63 + 0x44 + 32 + read-only + 0x8000077 + 0x18FFEF7F + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +Thsi bit indicates that SDR50 is supported. The bit 13 +(USE_TUNING_SDR50) indicates whether SDR50 requires +tuning or not. +Values: +- 0x0 (FALSE): SDR50 is not supported +- 0x1 (TRUE): SDR50 is supported + [0:0] + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +- 0x0 (FALSE): SDR104 is not supported +- 0x1 (TRUE): SDR104 is supported (NOT ACTUALLY SUPPORTED) + [1:1] + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +- 0x0 (FALSE): DDR50 is not supported +- 0x1 (TRUE): DDR50 is supported + [2:2] + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +- 0x0 (FALSE): UHS-II is not supported +- 0x1 (TRUE): UHS-II is supported + [3:3] + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type A is not supported +- 0x1 (TRUE): Driver Type A is supported + [4:4] + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type C is not supported +- 0x1 (TRUE): Driver Type C is supported + [5:5] + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type D is not supported +- 0x1 (TRUE): Driver Type D is supported + [6:6] + read-only + + + RETUNE_CNT + N/A + [11:8] + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +- 0x0 (ZERO): SDR50 does not require tuning +- 0x1 (ONE): SDR50 requires tuning + [13:13] + read-only + + + RE_TUNING_MODES + N/A + [15:14] + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable +clock generator. Setting these bits to 0 means that the Host +Controller does not support a programmable clock generator. +- 0x0: Clock Multiplier is not Supported +- 0x1: Clock Multiplier M = 2 +- 0x2: Clock Multiplier M = 3 +- ......... +- 0xFF: Clock Multiplier M = 256 + [23:16] + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of +using ADMA3. +Values: +- 0x0 (FALSE): ADMA3 not Supported +- 0x1 (TRUE): ADMA3 Supported + [27:27] + read-only + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +Values: +- 0x0 (FALSE): 1.8V VDD2 is not Supported +- 0x1 (TRUE): 1.8V VDD2 is Supported + [28:28] + read-only + + + + + CURR_CAPABILITIES1_R + Current Capabilities Register - 0 to 31 + 0x48 + 32 + read-only + 0x0 + 0xFFFFFF + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [7:0] + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [15:8] + read-only + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [23:16] + read-only + + + + + CURR_CAPABILITIES2_R + Maximum Current Capabilities Register - 32 to 63 + 0x4C + 32 + read-only + 0x0 + 0xFF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power +supply for the UHS-II card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [7:0] + read-only + + + + + FORCE_AUTO_CMD_STAT_R + Force Event Register for Auto CMD Error Status register + 0x50 + 16 + write-only + 0x0 + 0xBF + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +- 0x1 (TRUE): Auto CMD12 Not Executed Status is set +- 0x0 (FALSE): Not Affected + [0:0] + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +- 0x1 (TRUE): Auto CMD Timeout Error Status is set +- 0x0 (FALSE): Not Affected + [1:1] + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +- 0x1 (TRUE): Auto CMD CRC Error Status is set +- 0x0 (FALSE): Not Affected + [2:2] + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +- 0x1 (TRUE): Auto CMD End Bit Error Status is set +- 0x0 (FALSE): Not Affected + [3:3] + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +- 0x1 (TRUE): Auto CMD Index Error Status is set +- 0x0 (FALSE): Not Affected + [4:4] + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +- 0x1 (TRUE): Auto CMD Response Error Status is set +- 0x0 (FALSE): Not Affected + [5:5] + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +- 0x1 (TRUE): Command Not Issued By Auto CMD12 Error +Status is set +- 0x0 (FALSE): Not Affected + [7:7] + write-only + + + + + FORCE_ERROR_INT_STAT_R + Force Event Register for Error Interrupt Status + 0x52 + 16 + read-write + 0x0 + 0xFFFF + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command Timeout Error Status is set + [0:0] + read-write + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command CRC Error Status is set + [1:1] + read-write + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command End Bit Error Status is set + [2:2] + read-write + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command Index Error Status is set + [3:3] + read-write + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data Timeout Error Status is set + [4:4] + read-write + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data CRC Error Status is set + [5:5] + read-write + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data End Bit Error Status is set + [6:6] + read-write + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Current Limit Error Status is set + [7:7] + read-write + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Auto CMD Error Status is set + [8:8] + read-write + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): ADMA Error Status is set + [9:9] + read-write + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Tuning Error Status is set + [10:10] + read-write + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Response Error Status is set + [11:11] + read-write + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Boot ack Error Status is set + [12:12] + read-write + + + FORCE_VENDOR_ERR1 + N/A + [13:13] + read-write + + + FORCE_VENDOR_ERR2 + N/A + [14:14] + read-write + + + FORCE_VENDOR_ERR3 + N/A + [15:15] + read-write + + + + + ADMA_ERR_STAT_R + ADMA Error Status Register + 0x54 + 8 + read-only + 0x0 + 0x7 + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs +during ADMA data transfer. +Values: +- 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to +a location next to the error descriptor +- 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register +points to the error descriptor +- 0x2 (UNUSED): Never set this state +- 0x3 (ST_TFR): Transfer Data - SYS_ADR register points +to a location next to the error descriptor + [1:0] + read-only + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +- While the Block Count Enable is being set, the total data +length specified by the Descriptor table is different from +that specified by the Block Count and Block Length +- When the total data length cannot be divided by the block +length +Values: +- 0x0 (NO_ERR): No Error +- 0x1 (ERROR): Error + [2:2] + read-only + + + + + ADMA_SA_LOW_R + ADMA System Address Register - Low + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADMA_SA_LOW + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system +address. +- SDMA: If Host Version 4 Enable is set to 1, this register +stores the system address of the data location +- ADMA2: This register stores the byte address of the +executing command of the descriptor table +- ADMA3: This register is set by ADMA3. ADMA2 +increments the address of this register that points to the +next line, every time a Descriptor line is fetched. + [31:0] + read-write + + + + + ADMA_ID_LOW_R + ADMA3 Integrated Descriptor Address Register - Low + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADMA_ID_LOW + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated +Descriptor address. The start address of Integrated +Descriptor is set to these register bits. The ADMA3 fetches +one Descriptor Address and increments these bits to indicate +the next Descriptor address. + [31:0] + read-write + + + + + HOST_CNTRL_VERS_R + Host Controller Version + 0xFE + 16 + read-only + 0x5 + 0xFFFF + + + SPEC_VERSION_NUM + N/A + [7:0] + read-only + + + VENDOR_VERSION_NUM + N/A + [15:8] + read-only + + + + + CQVER + Command Queuing Version register + 0x180 + 32 + read-only + 0x510 + 0xFFF + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of +decimal point) in BCD format. + [3:0] + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of +decimal point) in BCD format. + [7:4] + read-only + + + EMMC_VER_MAJOR + This bit indicates the eMMC major version (1st digit left of +decimal point) in BCD format. + [11:8] + read-only + + + + + CQCAP + Command Queuing Capabilities register + 0x184 + 32 + read-only + 0x30C8 + 0x1000F3FF + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by +ITCFMUL. The Final clock frequency of actual timer clock is +calculated as ITCFVAL* ITCFMUL. + [9:0] + read-only + + + ITCFMUL + N/A + [15:12] + read-only + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports +cryptographic operations. +Values: +- 0x0 (FALSE): Crypto not Supported +- 0x1 (TRUE): Crypto Supported + [28:28] + read-only + + + + + CQCFG + Command Queuing Configuration register + 0x188 + 32 + read-write + 0x0 + 0x1103 + + + CQ_EN + Enable command queuing engine (CQE). +When CQE is disable, the software controls the eMMC bus +using the registers between the addresses 0x000 to 0x1FF. +Before the software writes to this bit, the software verifies +that the eMMC host controller is in idle state and there are no +ongoing commands or data transfers. When software wants +to exit command queuing mode, it clears all previous tasks (if +any) before setting this bit to 0. +Values: +- 0x1 (CQE_ENABLE): Enable command queuing +- 0x0 (CQE_DISABLE): Disable command queuing + [0:0] + read-write + + + CR_GENERAL_EN + N/A + [1:1] + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host +memory. This bit can only be configured when Command +Queuing Enable bit is 0 (command queuing is disabled). +Values: +- 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +- 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits + [8:8] + read-write + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor +or a direct-command descriptor. CQE uses this bit when a +task is issued in slot #31, to determine how to decode the +Task Descriptor. +Values: +- 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot +#31 is a DCMD Task Descriptor +- 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot +#31 is a data Transfer Task Descriptor + [12:12] + read-write + + + + + CQCTL + Command Queuing Control register + 0x18C + 32 + read-write + 0x0 + 0x101 + + + HALT + Halt request and resume +Values: +- 0x1 (HALT_CQE): Software writes 1 to this bit when it +wants to acquire software control over the eMMC bus and +to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command +(CMDQ_TASK_MGMT). When the software writes 1, CQE +completes the ongoing task (if any in progress). After the +task is completed and the CQE is in idle state, CQE does not +issue new commands and indicates to the software by +setting this bit to 1. The software can poll on this bit until it is +set to 1 and only then send commands on the eMMC bus. +- 0x0 (RESUME_CQE): Software writes 0 to this bit to exit +from the halt state and resume CQE activity. + [0:0] + read-write + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This +bit does not clear tasks in the device. The software has to +use the CMDQ_TASK_MGMT command to clear device's +queue. +Values: +- 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the +controller +- 0x0 (NO_EFFECT): Programming 0 has no effect + [8:8] + read-write + + + + + CQIS + Command Queuing Interrupt Status register + 0x190 + 32 + read-write + 0x0 + 0x3F + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when +halt bit in the CQCTL register transitions from 0 to 1 +indicating that the host controller has completed its current +ongoing task and has entered halt state. A value of 1 clears +this status bit. +Values: +- 0x1 (SET): HAC Interrupt is set +- 0x0 (NOTSET): HAC Interrupt is not set + [0:0] + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at +least one of the following conditions are met: +- A task is completed and the INT bit is set in its Task +Descriptor +- Interrupt caused by Interrupt Coalescing logic due to +timeout +- Interrupt Coalescing logic reached the configured +threshold +A value of 1 clears this status bit +Values: +- 0x1 (SET): TCC Interrupt is set +- 0x0 (NOTSET): TCC Interrupt is not set + [1:1] + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a +response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device +status bit fields that may trigger an interrupt and that are +masked. A value of 1 clears this status bit. +Values: +- 0x1 (SET): RED Interrupt is set +- 0x0 (NOTSET): RED Interrupt is not set + [2:2] + read-write + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a +task clear operation is completed by CQE. The completed +task clear operation is either an individual task clear (by +writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +- 0x1 (SET): TCL Interrupt is set +- 0x0 (NOTSET): TCL Interrupt is not set + [3:3] + read-write + + + GCE + N/A + [4:4] + read-write + + + ICCE + N/A + [5:5] + read-write + + + + + CQISE + Command Queuing Interrupt Status Enable register + 0x194 + 32 + read-write + 0x0 + 0x3F + + + HAC_STE + Halt complete interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + [0:0] + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + [1:1] + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.RED is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.RED is disabled + [2:2] + read-write + + + TCL_STE + Task cleared interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + [3:3] + read-write + + + GCE_STE + General Crypto Error interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.GCE is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.GCE is disabled + [4:4] + read-write + + + ICCE_STE + Invalid Crypto Configuration Error interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.ICCE is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.ICCE is disabled + [5:5] + read-write + + + + + CQISGE + Command Queuing Interrupt signal enable register + 0x198 + 32 + read-write + 0x0 + 0x3F + + + HAC_SGE + Halt complete interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal +generation is disabled + [0:0] + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal +generation is disabled + [1:1] + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal +generation is disabled + [2:2] + read-write + + + TCL_SGE + Task cleared interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal +generation is disabled + [3:3] + read-write + + + GCE_SGE + General Crypto Error interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.GCE interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.GCE interrupt signal +generation is disabled + [4:4] + read-write + + + ICCE_SGE + Invalid Crypto Configuration Error interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.ICCE interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.ICCE interrupt signal +generation is disabled + [5:5] + read-write + + + + + CQIC + Command Queuing Interrupt Coalescing register + 0x19C + 32 + read-write + 0x0 + 0x80119FFF + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time +allowed between the completion of a task on the bus and the +generation of an interrupt. +Timer Operation: The timer is reset by software during the +interrupt service routine. It starts running when the first data +transfer task with INT=0 is completed, after the timer was +reset. When the timer reaches the value configured in +ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock +whose frequency is specified in the Internal Timer Clock +Frequency field CQCAP register. +- 0x0: Timer is disabled. Timeout-based interrupt is not +generated +- 0x1: Timeout on 01x1024 cycles of timer clock frequency +- 0x2: Timeout on 02x1024 cycles of timer clock frequency +- ........ +- 0x7f: Timeout on 127x1024 cycles of timer clock +frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + [6:0] + read-write + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is +updated with the contents written on the same cycle. +Values: +- 0x1 (WEN_SET): Sets TOUT_VAL_WEN +- 0x0 (WEN_CLR): clears TOUT_VAL_WEN + [7:7] + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task +completions (only tasks with INT=0 in the Task Descriptor), +which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 +complete, they are counted by CQE. The counter is reset by +software during the interrupt service routine. The counter +stops counting when it reaches the value configured in +INTC_TH, and generates interrupt. +- 0x0: Interrupt coalescing feature disabled +- 0x1: Interrupt coalescing interrupt generated after 1 task +when INT=0 completes +- 0x2: Interrupt coalescing interrupt generated after 2 tasks +when INT=0 completes +- ........ +- 0x1f: Interrupt coalescing interrupt generated after 31 +tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set +during the same write operation. + [12:8] + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is +updated with the contents written on the same cycle. +Values: +- 0x1 (WEN_SET): Sets INTC_TH_WEN +- 0x0 (WEN_CLR): Clears INTC_TH_WEN + [15:15] + write-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and +counter are reset. +Values: +- 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer +and counter are reset +- 0x0 (NO_EFFECT): No Effect + [16:16] + write-only + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with +INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +- 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task +completion has been counted (INTC counter > 0) +- 0x0 (INTC_NO_TASK_COMP): INT0 Task completions +have not occurred since last counter reset (INTC counter +== 0) + [20:20] + read-only + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +- 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing +mechanism is active. Interrupts are counted and timed, +and coalesced interrupts are generated +- 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing +mechanism is disabled (Default). + [31:31] + read-write + + + + + CQTDLBA + Command Queuing Task Descriptor List Base Address register + 0x1A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of +the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor +size + Transfer Descriptor size) as configured by the host +driver. This address is set on 1 KB boundary. The lower 10 +bits of this register are set to 0 by the software and are +ignored by CQE. + [31:0] + read-write + + + + + CQTDBR + Command Queuing DoorBell register + 0x1A8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start +processing the task encoded in slot n of the TDL. Writing 0 +by the software does not have any impact on the hardware, +and does not change the value of the register bit. +CQE always processes tasks according to the order +submitted to the list by CQTDBR write transactions. CQE +processes Data Transfer tasks by reading the Task +Descriptor and sending QUEUED_TASK_PARAMS (CMD44) +and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when +enabled) by reading the Task Descriptor, and generating the +command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the +following events: +- A task execution is completed (with success or error). +- The task is cleared using CQTCLR register. +- All tasks are cleared using CQCTL register. +- CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch +submission) by writing 1 to multiple bits of this register in the +same transaction. In the case of batch submission, CQE +processes the tasks in order of the task index, starting with +the lowest index. If one or more tasks in the batch are +marked with QBR, the ordering of execution is based on said +processing order. + [31:0] + read-write + + + + + CQTCN + Command Queuing TaskClear Notification register + 0x1AC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Task-N has completed execution (with success +or errors) +- Bit-N(0): Task-N has not completed, could be pending or +not submitted. +On task completion, software may read this register to know +tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the +corresponding bits. + [31:0] + read-write + + + + + CQDQS + Device queue status register + 0x1B0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Device has marked task N as ready for +execution +- Bit-N(0): Task-N is not ready for execution. This task +could be pending in device or not submitted. +Host controller updates this register with response of the +Device Queue Status command. + [31:0] + read-only + + + + + CQDPT + Device pending tasks register + 0x1B4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Task-N has been successfully queued into the +device and is awaiting execution +- Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if +QUEUED_TASK_PARAMS (CMD44) and +QUEUED_TASK_ADDRESS (CMD45) were sent for this +specific task and if this task has not been executed. +The controller sets this bit after receiving a successful +response for CMD45. CQE clears this bit after the task has +completed execution. +Software reads this register in the task-discard procedure to +determine if the task is queued in the device. + [31:0] + read-only + + + + + CQTCLR + Command Queuing DoorBell register + 0x1B8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task +that the software has previously issued. +This bit can only be written when CQE is in Halt state as +indicated in CQCFG register Halt bit. When software writes 1 +to a bit in this register, CQE updates the value to 1, and +starts clearing the data structures related to the task. CQE +clears the bit fields (sets a value of 0) in CQTCLR and in +CQTDBR once the clear operation is complete. Software +must poll on the CQTCLR until it is cleared to verify that a +clear operation was done. + [31:0] + read-write + + + + + CQSSC1 + CQ Send Status Configuration 1 register + 0x1C0 + 32 + read-write + 0x11000 + 0xFFFFF + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when +using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the +device, but no data transfer is in progress. When a +SEND_QUEUE_STATUS response indicates that no task is +ready for execution, CQE counts the configured time until it +issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is +specified in the Internal Timer Clock Frequency field CQCAP +register. The minimum value is 0001h (1 clock period) and +the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz +clock frequency (period = 52.08 ns). If the setting in +CQSSC1.CIT is 1000h, the calculated polling period is +4096*52.08 ns= 213.33 ns. +Should be programmed only when CQCFG.CQ_EN is '0'. + [15:0] + read-write + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data +transfer is in progress. +A value of 'n' indicates that CQE sends status command on +the CMD line, during the transfer of data block BLOCK_CNTn, +on the data lines, where BLOCK_CNT is the number of +blocks in the current transaction. +- 0x0: SEND_QUEUE_STATUS (CMD13) command is not +sent during the transaction. Instead, it is sent only when +the data lines are idle. +- 0x1: SEND_QUEUE_STATUS command is to be sent +during the last block of the transaction. +- 0x2: SEND_QUEUE_STATUS command when last 2 +blocks are pending. +- 0x3: SEND_QUEUE_STATUS command when last 3 +blocks are pending. +- ........ +- 0xf: SEND_QUEUE_STATUS command when last 15 +blocks are pending. +Should be programmed only when CQCFG.CQ_EN is '0' + [19:16] + read-write + + + + + CQSSC2 + CQ Send Status Configuration 2 register + 0x1C4 + 32 + read-write + 0x0 + 0xFFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA +field in SEND_QUEUE_STATUS (CMD13) command +argument. +CQE copies this field to bits 31:16 of the argument when +transmitting SEND_ QUEUE_STATUS (CMD13) command. + [15:0] + read-write + + + + + CQCRDCT + Command response for direct command register + 0x1C8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command +generated by the last direct command (DCMD) task that was +sent. +Contents of this register are valid only after bit 31 of +CQTDBR register is cleared by the controller. + [31:0] + read-only + + + + + CQRMEM + Command response mode error mask register + 0x1D0 + 32 + read-write + 0xFDF9A080 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status +filed that is received in R1/R1b responses. +- 1: When a R1/R1b response is received, with a bit i in the +device status set, a RED interrupt is generated. +- 0: When a R1/R1b response is received, bit i in the device +status is ignored. +The reset value of this register is set to trigger an interrupt on +all 'Error' type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that +they are ignored by this logic. + [31:0] + read-write + + + + + CQTERRI + CQ Task Error Information register + 0x1D4 + 32 + read-only + 0x0 + 0x9F3F9F3F + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was +executed on the command line when the error occurred. + [5:0] + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on +the command line when the error occurred. + [12:8] + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a +command transaction was in progress. +Values: +- 0x1 (SET): Response-related error is detected. Check +contents of RESP_ERR_TASKID and +RESP_ERR_CMD_INDX fields +- 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID +and RESP_ERR_CMD_INDX + [15:15] + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was +executed and whose data transfer has errors. + [21:16] + read-only + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and +whose data transfer has errors. + [28:24] + read-only + + + TRANS_ERR_FIELDS_VALID + This bit is updated when an error is detected while a data +transfer transaction was in progress. +Values: +- 0x1 (SET): data transfer related error detected. Check +contents of TRANS_ERR_TASKID and +TRANS_ERR_CMD_INDX fields +- 0x0 (NOT_SET): Ignore contents of +TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX + [31:31] + read-only + + + + + CQCRI + CQ Command response index + 0x1D8 + 32 + read-only + 0x0 + 0x3F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command +response. Controller updates the value every time a +command response is received. + [5:0] + read-only + + + + + CQCRA + CQ Command response argument register + 0x1DC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command +response. Controller updates the value every time a +command response is received. + [31:0] + read-only + + + + + MSHC_VER_ID_R + MSHC version + 0x500 + 32 + read-only + 0x3137302A + 0xFFFFFFFF + + + MSHC_VER_ID + Current release number +This field indicates the Synopsys DesignWare Cores +DWC_mshc/DWC_mshc_lite current release number that is +read by an application. +For example, release number '1.60a' is represented in +ASCII as 0x313630. Lower 8 bits read from this register can +be ignored by the application. +An application reading this register in conjunction with the +MSHC_VER_TYPE_R register, gathers details of the current +release. + [31:0] + read-only + + + + + MSHC_VER_TYPE_R + MSHC version type + 0x504 + 32 + read-only + 0x67612A2A + 0xFFFFFFFF + + + MSHC_VER_TYPE + Current release type +This field indicates the Synopsys DesignWare Cores +DWC_mshc/DWC_mshc_lite current release type that is +read by an application. +For example, release type is 'ga' is represented in ASCII as +0x6761. Lower 16 bits read from this register can be ignored +by the application. +An application reading this register in conjunction with the +MSHC_VER_ID_R register, gathers details of the current +release. + [31:0] + read-only + + + + + MSHC_CTRL_R + MSHC Control register + 0x508 + 8 + read-write + 0x1 + 0x11 + + + CMD_CONFLICT_CHECK + Command conflict check +This bit enables command conflict check. +Note: DWC_mshc controller monitors the CMD line +whenever a command is issued and checks whether the +value driven on sd_cmd_out matches the value on +sd_cmd_in at next subsequent edge of cclk_tx to determine +command conflict error. This bit is cleared only if the feed +back delay (including IO Pad delay) is more than +(t_card_clk_period - t_setup), where t_setup is the setup +time of a flop in DWC_mshc. The I/O pad delay is consistent +across CMD and DATA lines, and it is within the value: +(2*t_card_clk_period - t_setup) +Values: +- 0x0 (DISABLE_CMD_CONFLICT_CHK): Disable +command conflict check +- 0x1 (CMD_CONFLICT_CHK_LAT1): Check for command +conflict after 1 card clock cycle + [0:0] + read-write + + + SW_CG_DIS + Internal clock gating disable control +This bit must be used to disable IP's internal clock gating +when required. when disabled clocks are not gated. Clocks +to the core (except hclk) must be stopped when +programming this bit. +Values: +- 0x0 (ENABLE): Internal clock gates are active and clock +gating is controlled internally +- 0x1 (DISABLE): Internal clock gating is disabled, clocks +are not gated internally + [4:4] + read-write + + + + + MBIU_CTRL_R + MBIU Control register + 0x510 + 8 + read-write + 0x1 + 0xF + + + UNDEFL_INCR_EN + Undefined INCR Burst +Controls generation of undefined length INCR transfer on +Master interface. +Values: +- 0x0 (FALSE): Undefined INCR type burst is the least +preferred burst on AHB Master I/F +- 0x1 (TRUE): Undefined INCR type burst is the most +preferred burst on AHB Master I/F + [0:0] + read-write + + + BURST_INCR4_EN + INCR4 Burst +Controls generation of INCR4 transfers on Master interface. +Values: +- 0x0 (FALSE): AHB INCR4 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR4 burst type can be generated on +Master I/F + [1:1] + read-write + + + BURST_INCR8_EN + INCR8 Burst +Controls generation of INCR8 transfers on Master interface. +Values: +- 0x0 (FALSE): AHB INCR8 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR8 burst type can be generated on +Master I/F + [2:2] + read-write + + + BURST_INCR16_EN + INCR16 Burst +Controls generation of INCR16 transfers on Master +interface. +Values: +- 0x0 (FALSE): AHB INCR16 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR16 burst type can be generated +on Master I/F + [3:3] + read-write + + + + + EMMC_CTRL_R + eMMC Control register + 0x52C + 16 + read-write + 0xC + 0x60F + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application +program this bit based on the card connected to SDHC. +Values: +- 0x1 (EMMC_CARD): Card connected to SDHC is an +eMMC card +- 0x0 (NON_EMMC_CARD): Card connected to SDHC is +a non-eMMC card + [0:0] + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in +eMMC mode. This is useful in bus testing (CMD19) for an +eMMC device. In bus testing, an eMMC card does not send +CRC status for a block, which may generate CRC error. This +CRC error can be masked using this bit during bus testing. +Values: +- 0x1 (DISABLE): DATA CRC check is disabled +- 0x0 (ENABLE): DATA CRC check is enabled + [1:1] + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the card_emmc_reset_n output of SDHC +Values: +- 0x1 (RST_DEASSERT): Reset to eMMC device is +deasserted +- 0x0 (RST_ASSERT): Reset to eMMC device asserted +(active low) + [2:2] + read-write + + + EMMC_RST_N_OE + Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n). +Values: +- 0x1 (ENABLE): OE for card_emmc_reset_n is 1 +- 0x0 (DISABLE): OE for card_emmc_reset_n is 0 + [3:3] + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the +many ready tasks for execution. +Values: +- 0x0 (PRI_REORDER_PLUS_FCFS): Priority based +reordering with FCFS to resolve equal priority tasks +- 0x1 (FCFS_ONLY): First come First serve, in the order of +DBR rings + [9:9] + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch +feature when set to 1. +Values: +- 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for +sucessive WRITE transfers and pipeline sucessive READ +transfers +- 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and +Pipeline for READ are disabled + [10:10] + read-write + + + + + BOOT_CTRL_R + eMMC Boot Control register + 0x52E + 16 + read-write + 0x0 + 0xF181 + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The +application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDHC clears this bit after the +boot transfer is completed or terminated. +Values: +- 0x1 (MAN_BOOT_EN): Mandatory boot enable +- 0x0 (MAN_BOOT_DIS): Mandatory boot disable + [0:0] + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +- 0x1 (TRUE): Validate Mandatory boot enable bit +- 0x0 (FALSE): Ignore Mandatory boot Enable bit + [7:7] + write-only + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDHC checks for boot acknowledge +start pattern of 0-1-0 during boot operation. This bit is +applicable for both mandatory and alternate boot mode. +Values: +- 0x1 (TRUE): Boot Ack enable +- 0x0 (FALSE): Boot Ack disable + [8:8] + read-write + + + BOOT_TOUT_CNT + N/A + [15:12] + read-write + + + + + GP_IN_R + General Purpose Input register + 0x530 + 32 + read-only + 0x0 + 0x1 + + + GP_IN + It reflects the value of gp_in ports. +NOT USED - ALWAYS READS 0 + [0:0] + read-only + + + + + GP_OUT_R + General Purpose Output register + 0x534 + 32 + read-write + 0x0 + 0x3FF + + + CARD_DETECT_EN + 0: Force card_detect_n input to 0 +1: Normal card_detect_n operation allowing card detection from a device pin + [0:0] + read-write + + + CARD_MECH_WRITE_PROT_EN + card_mech_write_prot, despite its name, is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#). Consider that in the following: +0: Force card_mech_write_prot input to 0 internally; this forces write protection to be active +1: Allow card_mech_write_prot to work normally per the device's pin state + [1:1] + read-write + + + LED_CTRL_OE + Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL: +0: disable OE associated with the led_ctrl output +1: enable OE associated with the led_ctrl output + [2:2] + read-write + + + CARD_CLOCK_OE + Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN: +0: disable OE to the clk_card output +1: enable OE to the clk_card output + [3:3] + read-write + + + CARD_IF_PWR_EN_OE + Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1: +0: disable OE to the card_if_pwr_en output +1: enable OE to the card_if_pwr_en output + [4:4] + read-write + + + IO_VOLT_SEL_OE + Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN: +0: disable OE to the io_volt_sel output +1: enable OE to the io_volt_sel output + [5:5] + read-write + + + CARD_CLOCK_OUT_DLY + N/A + [7:6] + read-write + + + CARD_CLOCK_IN_DLY + Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode: +00: SD Default Speed, SD SDR12, eMMC Legacy +01: SD SDR25, SD SDR50 +10: SD High Speed, eMMC High Speed SDR +11: SD DDR50, eMMC DDR + [9:8] + read-write + + + + + + + + CANFD0 + CAN Controller + CANFD + 0x40520000 + + 0 + 131072 + registers + + + + CH + FIFO wrapper around M_TTCAN 3PIP, to enable DMA + 0x00000000 + + M_TTCAN + TTCAN 3PIP, includes FD + 0x00000000 + + CREL + Core Release Register + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAY + Time Stamp Day +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [7:0] + read-only + + + MON + Time Stamp Month +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [15:8] + read-only + + + YEAR + Time Stamp Year +One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [19:16] + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded. + [23:20] + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + [27:24] + read-only + + + REL + Core Release +One digit, BCD-coded. + [31:28] + read-only + + + + + ENDN + Endian Register + 0x4 + 32 + read-only + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness Test Value +The endianness test value is 0x87654321. + [31:0] + read-only + + + + + DBTP + Data Bit Timing & Prescaler Register + 0xC + 32 + read-write + 0xA33 + 0x9F1FFF + + + DSJW + Data (Re)Synchronization Jump Width +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [3:0] + read-write + + + DTSEG2 + Data time segment after sample point +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [7:4] + read-write + + + DTSEG1 + Data time segment before sample point +0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [12:8] + read-write + + + DBRP + Data Bit Rate Prescaler +0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [20:16] + read-write + + + TDC + Transmitter Delay Compensation +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + [23:23] + read-write + + + + + TEST + Test Register + 0x10 + 32 + read-write + 0x0 + 0x7F + + + TAM + ASC is not supported by M_TTCAN +Test ASC Multiplexer Control +Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_ascm controlled by FSE +1= Level at pin m_ttcan_ascm = '1' + [0:0] + read-write + + + TAT + ASC is not supported by M_TTCAN +Test ASC Transmit Control +Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_asct controlled by FSE +1= Level at pin m_ttcan_asct = '1' + [1:1] + read-write + + + CAM + ASC is not supported by M_TTCAN +Check ASC Multiplexer Control +Monitors level at output pin m_ttcan_ascm. +0= Output pin m_ttcan_ascm = '0' +1= Output pin m_ttcan_ascm = '1' + [2:2] + read-write + + + CAT + ASC is not supported by M_TTCAN +Check ASC Transmit Control +Monitors level at output pin m_ttcan_asct. +0= Output pin m_ttcan_asct = '0' + [3:3] + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) + [4:4] + read-write + + + TX + Control of Transmit Pin +00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_ttcan_tx +10 Dominant ('0') level at pin m_ttcan_tx +11 Recessive ('1') at pin m_ttcan_tx + [6:5] + read-write + + + RX + Receive Pin +Monitors the actual value of pin m_ttcan_rx +0= The CAN bus is dominant (m_ttcan_rx = '0') +1= The CAN bus is recessive (m_ttcan_rx = '1') + [7:7] + read-only + + + + + RWD + RAM Watchdog + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is +disabled. + [7:0] + read-write + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + [15:8] + read-only + + + + + CCCR + CC Control Register + 0x18 + 32 + read-write + 0x1 + 0xF3FF + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + [0:0] + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + [1:1] + read-write + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + [2:2] + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk + [3:3] + read-write + + + CSR + Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after +all pending transfer requests have been completed and the CAN bus reached idle. + [4:4] + read-write + + + MON_ + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + [5:5] + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + [6:6] + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + [7:7] + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + [8:8] + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled + [9:9] + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled + [12:12] + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + [13:13] + read-write + + + TXP + Transmit Pause +If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission +after itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + [14:14] + read-write + + + NISO + Non ISO Operation +If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD + [15:15] + read-write + + + + + NBTP + Nominal Bit Timing & Prescaler Register + 0x1C + 32 + read-write + 0x6000A03 + 0xFFFFFF7F + + + NTSEG2 + Nominal Time segment after sample point +0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [6:0] + read-write + + + NTSEG1 + Nominal Time segment before sample point +0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [15:8] + read-write + + + NBRP + Nominal Bit Rate Prescaler +0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [24:16] + read-write + + + NSJW + Nominal (Re)Synchronization Jump Width +0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [31:25] + read-write + + + + + TSCC + Timestamp Counter Configuration + 0x20 + 32 + read-write + 0x0 + 0xF0003 + + + TSS + Timestamp Select, should always be set to external timestamp counter +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as '00' + [1:0] + read-write + + + TCP + Timestamp Counter Prescaler (still used for TOCC) +0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times +[1...16]. The actual interpretation by the hardware of this value is such that one more +than the value programmed here is used. + [19:16] + read-write + + + + + TSCV + Timestamp Counter Value + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + TSC + Timestamp Counter, not used for M_TTCAN +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). +When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times +[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. +Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external +Timestamp Counter value. A write access has no impact. + [15:0] + read-write + + + + + TOCC + Timeout Counter Configuration + 0x28 + 32 + read-write + 0xFFFF0000 + 0xFFFF0007 + + + ETOC + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + [0:0] + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured +by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the +FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting +is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + [2:1] + read-write + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + [31:16] + read-write + + + + + TOCV + Timeout Counter Value + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the +configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the +Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + [15:0] + read-write + + + + + ECR + Error Counter Register + 0x40 + 32 + read-only + 0x0 + 0xFFFFFF + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 + [7:0] + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + [14:8] + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + [15:15] + read-only + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter +or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops +at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. + [23:16] + read-only + + + + + PSR + Protocol Status Register + 0x44 + 32 + read-only + 0x707 + 0x7F7FFF + + + LEC + Last Error Code, +Set on Read0 +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' +when a message has been transferred (reception or transmission) without error. + +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus + value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or +overload flag), the device wanted to send a dominant level (data or identifier bit logical value +0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set +each time a sequence of 11 recessive bits has been monitored. This enables the CPU to +monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming +message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. +When the LEC shows the value '7', no CAN bus event was detected since the last CPU read +access to the Protocol Status Register. + [2:0] + read-only + + + ACT + Activity +Monitors the module's CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter + [4:3] + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + [5:5] + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + [6:6] + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + [7:7] + read-only + + + DLEC + Data Phase Last Error Code +, Set on Read +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + [10:8] + read-only + + + RESI + ESI flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set + [11:11] + read-only + + + RBRS + BRS flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set + [12:12] + read-only + + + RFDF + Received a CAN FD Message +, Reset on Read +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received + [13:13] + read-only + + + PXE + Protocol Exception Event +, Reset on Read +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred + [14:14] + read-only + + + TDCV + Transmitter Delay Compensation Value +0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + [22:16] + read-only + + + + + TDCR + Transmitter Delay Compensation Register + 0x48 + 32 + read-write + 0x0 + 0x7F7F + + + TDCF + Transmitter Delay Compensation Filter Window Length +0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx +that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than +TDCO. Valid values are 0 to 127 mtq + [6:0] + read-write + + + TDCO + Transmitter Delay Compensation Offset +0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to +m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. + [14:8] + read-write + + + + + IR + Interrupt Register + 0x50 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + [0:0] + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + [1:1] + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [2:2] + read-write + + + RF0L_ + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [3:3] + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + [4:4] + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + [5:5] + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [6:6] + read-write + + + RF1L_ + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [7:7] + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + [8:8] + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + [9:9] + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + [10:10] + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + [11:11] + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + [12:12] + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + [13:13] + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [14:14] + read-write + + + TEFL_ + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + [15:15] + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + [16:16] + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. +- was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM +in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted +Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + [17:17] + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + [18:18] + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into a Rx Buffer + [19:19] + read-write + + + BEC + M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. +Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] +generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + [20:20] + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] +generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected +Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + [21:21] + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + [22:22] + read-write + + + EP_ + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + [23:23] + read-write + + + EW_ + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + [24:24] + read-write + + + BO_ + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + [25:25] + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + [26:26] + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) + [27:27] + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC != 0,7) + [28:28] + read-write + + + ARA + N/A + [29:29] + read-write + + + + + IE + Interrupt Enable + 0x54 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + [0:0] + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + [1:1] + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + [2:2] + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + [3:3] + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + [4:4] + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + [5:5] + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + [6:6] + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + [7:7] + read-write + + + HPME + High Priority Message Interrupt Enable + [8:8] + read-write + + + TCE + Transmission Completed Interrupt Enable + [9:9] + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + [10:10] + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + [11:11] + read-write + + + TEFNE + Tx Event FIDO New Entry Interrupt Enable + [12:12] + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + [13:13] + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + [14:14] + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + [15:15] + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + [16:16] + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + [17:17] + read-write + + + TOOE + Timeout Occurred Interrupt Enable + [18:18] + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + [19:19] + read-write + + + BECE + Bit Error Corrected Interrupt Enable (not used in M_TTCAN) + [20:20] + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + [21:21] + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + [22:22] + read-write + + + EPE + Error Passive Interrupt Enable + [23:23] + read-write + + + EWE + Warning Status Interrupt Enable + [24:24] + read-write + + + BOE + Bus_Off Status Interrupt Enable + [25:25] + read-write + + + WDIE + Watchdog Interrupt Enable + [26:26] + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + [27:27] + read-write + + + PEDE + Protocol Error in Data Phase Enable + [28:28] + read-write + + + ARAE + N/A + [29:29] + read-write + + + + + ILS + Interrupt Line Select + 0x58 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + [0:0] + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + [1:1] + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + [2:2] + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + [3:3] + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + [4:4] + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + [5:5] + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + [6:6] + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + [7:7] + read-write + + + HPML + High Priority Message Interrupt Line + [8:8] + read-write + + + TCL + Transmission Completed Interrupt Line + [9:9] + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + [10:10] + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + [11:11] + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + [12:12] + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + [13:13] + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + [14:14] + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + [15:15] + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + [16:16] + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + [17:17] + read-write + + + TOOL + Timeout Occurred Interrupt Line + [18:18] + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + [19:19] + read-write + + + BECL + Bit Error Corrected Interrupt Line (not used in M_TTCAN) + [20:20] + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + [21:21] + read-write + + + ELOL + Error Logging Overflow Interrupt Line + [22:22] + read-write + + + EPL + Error Passive Interrupt Line + [23:23] + read-write + + + EWL + Warning Status Interrupt Line + [24:24] + read-write + + + BOL + Bus_Off Status Interrupt Line + [25:25] + read-write + + + WDIL + Watchdog Interrupt Line + [26:26] + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + [27:27] + read-write + + + PEDL + Protocol Error in Data Phase Line + [28:28] + read-write + + + ARAL + N/A + [29:29] + read-write + + + + + ILE + Interrupt Line Enable + 0x5C + 32 + read-write + 0x0 + 0x3 + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_ttcan_int0 disabled +1= Interrupt line m_ttcan_int0 enabled + [0:0] + read-write + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_ttcan_int1 disabled +1= Interrupt line m_ttcan_int1 enabled + [1:1] + read-write + + + + + GFC + Global Filter Configuration + 0x80 + 32 + read-write + 0x0 + 0x3F + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + [0:0] + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + [1:1] + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [3:2] + read-write + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [5:4] + read-write + + + + + SIDFC + Standard ID Filter Configuration + 0x84 + 32 + read-write + 0x0 + 0xFFFFFC + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +128= Values greater than 128 are interpreted as 128 + [23:16] + read-write + + + + + XIDFC + Extended ID Filter Configuration + 0x88 + 32 + read-write + 0x0 + 0x7FFFFC + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + XIDAM + Extended ID AND Mask + 0x90 + 32 + read-write + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message +ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all +bits set to one the mask is not active. + [28:0] + read-write + + + + + HPMS + High Priority Message Status + 0x94 + 32 + read-only + 0x0 + 0xFFFF + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. + [5:0] + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + [7:6] + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + [14:8] + read-only + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + [15:15] + read-only + + + + + NDAT1 + New Data 1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + NDAT2 + New Data 2 + 0x9C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + RXF0C + Rx FIFO 0 Configuration + 0xA0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + [22:16] + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + [31:31] + read-write + + + + + RXF0S + Rx FIFO 0 Status + 0xA4 + 32 + read-only + 0x0 + 0x33F3F7F + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + [6:0] + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. +This field is updated by the software writing to RxF0A.F0AI + [13:8] + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + [21:16] + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [24:24] + read-only + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [25:25] + read-only + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0xA8 + 32 + read-write + 0x0 + 0x3F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the + buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index + RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + [5:0] + read-write + + + + + RXBC + Rx Buffer Configuration + 0xAC + 32 + read-write + 0x0 + 0xFFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +Also used to reference debug messages A,B,C. + [15:2] + read-write + + + + + RXF1C + Rx FIFO 1 Configuration + 0xB0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + [22:16] + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + [31:31] + read-write + + + + + RXF1S + Rx FIFO 1 Status + 0xB4 + 32 + read-only + 0x0 + 0xC33F3F7F + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + [6:0] + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. +This field is updated by the software writing to RxF1A.FAI + [13:8] + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + [21:16] + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [24:24] + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [25:25] + read-only + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + [31:30] + read-only + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0xB8 + 32 + read-write + 0x0 + 0x3F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the + buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index + RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + [5:0] + read-write + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0xBC + 32 + read-write + 0x0 + 0x777 + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [6:4] + read-write + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [10:8] + read-write + + + + + TXBC + Tx Buffer Configuration + 0xC0 + 32 + read-write + 0x0 + 0x7F3FFFFC + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +32= Values greater than 32 are interpreted as 32 + [21:16] + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +32= Values greater than 32 are interpreted as 32 + [29:24] + read-write + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + [30:30] + read-write + + + + + TXFQS + Tx FIFO/Queue Status + 0xC4 + 32 + read-only + 0x0 + 0x3F1F3F + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when +Tx Queue operation is configured (TXBC.TFQM = '1') + [5:0] + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +TXBC.TFQM = '1'). + [12:8] + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + [20:16] + read-only + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + [21:21] + read-only + + + + + TXESC + Tx Buffer Element Size Configuration + 0xC8 + 32 + read-write + 0x0 + 0x7 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + + + TXBRP + Tx Buffer Request Pending + 0xCC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. +The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, +a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register +TXBRP. In case a transmission has already been started when a cancellation is requested, this is +done at the end of the transmission, regardless whether the transmission was successful or not. The +cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signaled via TXBCF +after successful transmission together with the corresponding TXBTO bit +when the transmission has not yet been started at the point of cancellation +when the transmission has been aborted due to lost arbitration +when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The +corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending + [31:0] + read-only + + + + + TXBAR + Tx Buffer Add Request + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request +bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan +process has completed. +0= No transmission request added +1= Transmission requested added + [31:0] + read-write + + + + + TXBCR + Tx Buffer Cancellation Request + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding +Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation +requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx +Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + [31:0] + read-write + + + + + TXBTO + Tx Buffer Transmission Occurred + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding +TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission +is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + [31:0] + read-only + + + + + TXBCF + Tx Buffer Cancellation Finished + 0xDC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding +TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding +TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a +new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + [31:0] + read-only + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + [31:0] + read-write + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0xE4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + [31:0] + read-write + + + + + TXEFC + Tx Event FIFO Configuration + 0xF0 + 32 + read-write + 0x0 + 0x3F3FFFFC + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS-1 + [21:16] + read-write + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +32= Watermark interrupt disabled + [29:24] + read-write + + + + + TXEFS + Tx Event FIFO Status + 0xF4 + 32 + read-only + 0x0 + 0x31F1F3F + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + [5:0] + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + [12:8] + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + [20:16] + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [24:24] + read-only + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + [25:25] + read-only + + + + + TXEFA + Tx Event FIFO Acknowledge + 0xF8 + 32 + read-write + 0x0 + 0x1F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write +the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + [4:0] + read-write + + + + + TTTMC + TT Trigger Memory Configuration + 0x100 + 32 + read-write + 0x0 + 0x7FFFFC + + + TMSA + Trigger Memory Start Address +Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + TME + Trigger Memory Elements +0= No Trigger Memory +1-64= Number of Trigger Memory elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + TTRMC + TT Reference Message Configuration + 0x104 + 32 + read-write + 0x0 + 0xDFFFFFFF + + + RID + Reference Identifier +Identifier transmitted with reference message and used for reference message filtering. Standard or +extended reference identifier depending on bit XTD. A standard identifier has to be written to +ID[28:18]. + [28:0] + read-write + + + XTD + Extended Identifier +0= 11-bit standard identifier +1= 29-bit extended identifier + [30:30] + read-write + + + RMPS + Reference Message Payload Select +Ignored in case of time slaves. +0= Reference message has no additional payload +1= The following elements are taken from Tx Buffer 0: +Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB +Level 1: bytes 2-8, Level 0,2: bytes 5-8) + [31:31] + read-write + + + + + TTOCF + TT Operation Configuration + 0x108 + 32 + read-write + 0x10000 + 0x7FFFFFB + + + OM + Operation Mode +00= Event-driven CAN communication, default +01= TTCAN level 1 +10= TTCAN level 2 +11= TTCAN level 0 + [1:0] + read-write + + + GEN + Gap Enable +0= Strictly time-triggered operation +1= External event-synchronized time-triggered operation + [3:3] + read-write + + + TM + Time Master +0= Time Master function disabled +1= Potential Time Master + [4:4] + read-write + + + LDSDL + LD of Synchronization Deviation Limit +The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = +2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. +0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) + [7:5] + read-write + + + IRTO + Initial Reference Trigger Offset +0x00-7F Positive offset, range from 0 to 127 + [14:8] + read-write + + + EECS + Enable External Clock Synchronization +If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. +0= External clock synchronization in TTCAN Level 0,2 disabled +1= External clock synchronization in TTCAN Level 0,2 enabled + [15:15] + read-write + + + AWL + Application Watchdog Limit +The application watchdog can be disabled by programming AWL to 0x00. +0x00-FF Maximum time after which the application has to serve the application watchdog. +The application watchdog is incremented once each 256 NTUs. + [23:16] + read-write + + + EGTF + Enable Global Time Filtering +0= Global time filtering in TTCAN Level 0,2 is disabled +1= Global time filtering in TTCAN Level 0,2 is enabled + [24:24] + read-write + + + ECC + Enable Clock Calibration +0= Automatic clock calibration in TTCAN Level 0,2 is disabled +1= Automatic clock calibration in TTCAN Level 0,2 is enabled + [25:25] + read-write + + + EVTP + Event Trigger Polarity +0= Rising edge trigger +1= Falling edge trigger + [26:26] + read-write + + + + + TTMLM + TT Matrix Limits + 0x10C + 32 + read-write + 0x0 + 0xFFF0FFF + + + CCM + N/A + [5:0] + read-write + + + CSS + N/A + [7:6] + read-write + + + TXEW + Tx Enable Window +0x0-F Length of Tx enable window, 1-16 NTU cycles + [11:8] + read-write + + + ENTT + Expected Number of Tx Triggers +0x000-FFF Expected number of Tx Triggers in one Matrix Cycle + [27:16] + read-write + + + + + TURCF + TUR Configuration + 0x110 + 32 + read-write + 0x10000000 + 0xBFFFFFFF + + + NCL + Numerator Configuration Low +Write access to the TUR Numerator Configuration Low is only possible during configuration with +TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new +value for NCL is written outside TT Configuration Mode, the new value takes effect when +TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. +0x0000-FFFF Numerator Configuration Low + [15:0] + read-write + + + DC + Denominator Configuration +0x0000 Illegal value +0x0001-3FFF Denominator Configuration + [29:16] + read-write + + + ELT + Enable Local Time +0= Local time is stopped, default +1= Local time is enabled + [31:31] + read-write + + + + + TTOCN + TT Operation Control + 0x114 + 32 + read-write + 0x0 + 0xBFFF + + + SGT + Set Global time +Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one +Host clock period. The global time preset takes effect when the node transmits the next reference +message with the Master_Ref_Mark modified by the preset value written to TTGTP. + [0:0] + read-write + + + ECS + External Clock Synchronization +Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one +Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. + [1:1] + read-write + + + SWP + Stop Watch Polarity +0= Rising edge trigger +1= Falling edge trigger + [2:2] + read-write + + + SWS + Stop Watch Source +00= Stop Watch disabled +01= Actual value of cycle time is copied to TTCPT.SWV +10= Actual value of local time is copied to TTCPT.SWV +11= Actual value of global time is copied to TTCPT.SWV + [4:3] + read-write + + + RTIE + Register Time Mark Interrupt Pulse Enable +Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse +with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or +global) equals TTTMK.TM, independent of the synchronization state. +0= Register Time Mark Interrupt output m_ttcan_rtp disabled +1= Register Time Mark Interrupt output m_ttcan_rtp enabled + [5:5] + read-write + + + TMC + Register Time Mark Compare +00= No Register Time Mark Interrupt generated +01= Register Time Mark Interrupt if Time Mark = cycle time +10= Register Time Mark Interrupt if Time Mark = local time +11= Register Time Mark Interrupt if Time Mark = global time + [7:6] + read-write + + + TTIE + Trigger Time Mark Interrupt Pulse Enable +External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A +trigger time mark interrupt pulse is generated when the trigger memory element becomes active, +and the M_TTCAN is in synchronization state In_Schedule or In_Gap. +0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled +1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled + [8:8] + read-write + + + GCS + Gap Control Select +0= Gap control independent from m_ttcan_evt +1= Gap control by input pin m_ttcan_evt + [9:9] + read-write + + + FGP + Finish Gap +Set by the CPU, reset by each reference message +0= No reference message requested +1= Application requested start of reference message + [10:10] + read-write + + + TMG + Time Mark Gap +0= Reset by each reference message +1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated + [11:11] + read-write + + + NIG + Next is Gap +This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for +external event-synchronized time-triggered operation (TTOCF.GEN = '1') +0= No action, reset by reception of any reference message +1= Transmit next reference message with Next_is_Gap = '1' + [12:12] + read-write + + + ESCN + External Synchronization Control +If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising +edge at pin m_ttcan_evt (see Section 4.11). +0= External synchronization disabled +1= External synchronization enabled + [13:13] + read-write + + + LCKC + TT Operation Control Register Locked +Set by a write access to register TTOCN. Reset when the updated configuration has been +synchronized into the CAN clock domain. +0= Write access to TTOCN enabled +1= Write access to TTOCN locked + [15:15] + read-only + + + + + TTGTP + TT Global Time Preset + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TP + N/A + [15:0] + read-write + + + CTP + Cycle Time Target Phase +CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). +0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected + [31:16] + read-write + + + + + TTTMK + TT Time Mark + 0x11C + 32 + read-write + 0x0 + 0x807FFFFF + + + TM_ + Time Mark +0x0000-FFFF Time Mark + [15:0] + read-write + + + TICC + Time Mark Cycle Code +Cycle count for which the time mark is valid. +0b000000x valid for all cycles +0b000001c valid every second cycle at cycle count mod2 = c +0b00001cc valid every fourth cycle at cycle count mod4 = cc +0b0001ccc valid every eighth cycle at cycle count mod8 = ccc +0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc +0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc +0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc + [22:16] + read-write + + + LCKM + TT Time Mark Register Locked +Always set by a write access to registers TTOCN. Set by write access to register TTTMK when +TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. +0= Write access to TTTMK enabled +1= Write access to TTTMK locked + [31:31] + read-only + + + + + TTIR + TT Interrupt Register + 0x120 + 32 + read-write + 0x0 + 0x7FFFF + + + SBC + Start of Basic Cycle +0= No Basic Cycle started since bit has been reset +1= Basic Cycle started + [0:0] + read-write + + + SMC + Start of Matrix Cycle +0= No Matrix Cycle started since bit has been reset +1= Matrix Cycle started + [1:1] + read-write + + + CSM_ + Change of Synchronization Mode +0= No change in master to slave relation or schedule synchronization +1= Master to slave relation or schedule synchronization changed, +also set when TTOST.SPL is reset + [2:2] + read-write + + + SOG + Start of Gap +0= No reference message seen with Next_is_Gap bit set +1= Reference message with Next_is_Gap bit set becomes valid + [3:3] + read-write + + + RTMI + Register Time Mark Interrupt +Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent +of the synchronization state. +0= Time mark not reached +1= Time mark reached + [4:4] + read-write + + + TTMI + Trigger Time Mark Event Internal +Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set +when the trigger memory element becomes active, and the M_TTCAN is in synchronization state +In_Gap or In_Schedule. +0= Time mark not reached +1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) + [5:5] + read-write + + + SWE + Stop Watch Event +0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected +1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected + [6:6] + read-write + + + GTW + Global Time Wrap +0= No global time wrap occurred +1= Global time wrap from 0xFFFF to 0x0000 occurred + [7:7] + read-write + + + GTD + Global Time Discontinuity +0= No discontinuity of global time +1= Discontinuity of global time + [8:8] + read-write + + + GTE + Global Time Error +Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. +0= Synchronization deviation within limit +1= Synchronization deviation exceeded limit + [9:9] + read-write + + + TXU + Tx Count Underflow +0= Number of Tx Trigger as expected +1= Less Tx trigger than expected in one matrix cycle + [10:10] + read-write + + + TXO + Tx Count Overflow +0= Number of Tx Trigger as expected +1= More Tx trigger than expected in one matrix cycle + [11:11] + read-write + + + SE1 + Scheduling Error 1 +0= No scheduling error 1 +1= Scheduling error 1 occurred + [12:12] + read-write + + + SE2 + Scheduling Error 2 +0= No scheduling error 2 +1= Scheduling error 2 occurred + [13:13] + read-write + + + ELC + Error Level Changed +Not set when error level changed during initialization. +0= No change in error level +1= Error level changed + [14:14] + read-write + + + IWT + Initialization Watch Trigger +The initialization is restarted by resetting IWT. +0= No missing reference message during system startup +1= No system startup due to missing reference message + [15:15] + read-write + + + WT + Watch Trigger +0= No missing reference message +1= Missing reference message (Level 0: cycle time 0xFF00) + [16:16] + read-write + + + AW + Application Watchdog +0= Application watchdog served in time +1= Application watchdog not served in time + [17:17] + read-write + + + CER + Configuration Error +Trigger out of order. +0= No error found in trigger list +1= Error found in trigger list + [18:18] + read-write + + + + + TTIE + TT Interrupt Enable + 0x124 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCE + Start of Basic Cycle Interrupt Enable + [0:0] + read-write + + + SMCE + Start of Matrix Cycle Interrupt Enable + [1:1] + read-write + + + CSME + Change of Synchronization Mode Interrupt Enable + [2:2] + read-write + + + SOGE + Start of Gap Interrupt Enable + [3:3] + read-write + + + RTMIE + Register Time Mark Interrupt Enable + [4:4] + read-write + + + TTMIE + Trigger Time Mark Event Internal Enable + [5:5] + read-write + + + SWEE + Stop Watch Event Interrupt Enable + [6:6] + read-write + + + GTWE + Global Time Wrap Interrupt Enable + [7:7] + read-write + + + GTDE + Global Time Discontinuity Interrupt Enable + [8:8] + read-write + + + GTEE + Global Time Error Interrupt Enable + [9:9] + read-write + + + TXUE + Tx Count Underflow Interrupt Enable + [10:10] + read-write + + + TXOE + Tx Count Overflow Interrupt Enable + [11:11] + read-write + + + SE1E + Scheduling Error 1 Interrupt Enable + [12:12] + read-write + + + SE2E + Scheduling Error 2 Interrupt Enable + [13:13] + read-write + + + ELCE + Change Error Level Interrupt Enable + [14:14] + read-write + + + IWTE + Initialization Watch Trigger Interrupt Enable + [15:15] + read-write + + + WTE + Watch Trigger Interrupt Enable + [16:16] + read-write + + + AWE_ + Application Watchdog Interrupt Enable + [17:17] + read-write + + + CERE + Configuration Error Interrupt Enable + [18:18] + read-write + + + + + TTILS + TT Interrupt Line Select + 0x128 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCL + Start of Basic Cycle Interrupt Line + [0:0] + read-write + + + SMCL + Start of Matrix Cycle Interrupt Line + [1:1] + read-write + + + CSML + Change of Synchronization Mode Interrupt Line + [2:2] + read-write + + + SOGL + Start of Gap Interrupt Line + [3:3] + read-write + + + RTMIL + Register Time Mark Interrupt Line + [4:4] + read-write + + + TTMIL + Trigger Time Mark Event Internal Line + [5:5] + read-write + + + SWEL + Stop Watch Event Interrupt Line + [6:6] + read-write + + + GTWL + Global Time Wrap Interrupt Line + [7:7] + read-write + + + GTDL + Global Time Discontinuity Interrupt Line + [8:8] + read-write + + + GTEL + Global Time Error Interrupt Line + [9:9] + read-write + + + TXUL + Tx Count Underflow Interrupt Line + [10:10] + read-write + + + TXOL + Tx Count Overflow Interrupt Line + [11:11] + read-write + + + SE1L + Scheduling Error 1 Interrupt Line + [12:12] + read-write + + + SE2L + Scheduling Error 2 Interrupt Line + [13:13] + read-write + + + ELCL + Change Error Level Interrupt Line + [14:14] + read-write + + + IWTL + Initialization Watch Trigger Interrupt Line + [15:15] + read-write + + + WTL + Watch Trigger Interrupt Line + [16:16] + read-write + + + AWL_ + Application Watchdog Interrupt Line + [17:17] + read-write + + + CERL + Configuration Error Interrupt Line + [18:18] + read-write + + + + + TTOST + TT Operation Status + 0x12C + 32 + read-only + 0x0 + 0xFFC0FFFF + + + EL + Error Level +00= Severity 0 - No Error +01= Severity 1 - Warning +10= Severity 2 - Error +11= Severity 3 - Severe Error + [1:0] + read-only + + + MS + Master State +00= Master_Off, no master properties relevant +01= Operating as Time Slave +10= Operating as Backup Time Master +11= Operating as current Time Master + [3:2] + read-only + + + SYS + Synchronization State +00= Out of Synchronization +01= Synchronizing to TTCAN communication +10= Schedule suspended by Gap (In_Gap) +11= Synchronized to schedule (In_Schedule) + [5:4] + read-only + + + QGTP + Quality of Global Time Phase +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. +0= Global time not valid +1= Global time in phase with Time Master + [6:6] + read-only + + + QCS + Quality of Clock Speed +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. +0= Local clock speed not synchronized to Time Master clock speed +1= Synchronization Deviation <= SDL + [7:7] + read-only + + + RTO + Reference Trigger Offset +The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). +There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes +Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and +CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. +0x00-FF Actual Reference Trigger offset value + [15:8] + read-only + + + WGTD + Wait for Global Time Discontinuity +0= No global time preset pending +1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted +a reference message with Disc_Bit = '1' or after it received a reference message. + [22:22] + read-only + + + GFI + Gap Finished Indicator +Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin +m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another +node sending a reference message. +0= Reset at the end of each reference message +1= Gap finished by M_TTCAN + [23:23] + read-only + + + TMP + Time Master Priority +0x0-7 Priority of actual Time Master + [26:24] + read-only + + + GSI + Gap Started Indicator +0= No Gap in schedule, reset by each reference message and for all time slaves +1= Gap time after Basic Cycle has started + [27:27] + read-only + + + WFE + Wait for Event +0= No Gap announced, reset by a reference message with Next_is_Gap = '0' +1= Reference message with Next_is_Gap = '1' received + [28:28] + read-only + + + AWE + Application Watchdog Event +The application watchdog is served by reading TTOST. When the watchdog is not served in time, +bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring +Mode. +0= Application Watchdog served in time +1= Failed to serve Application Watchdog in time + [29:29] + read-only + + + WECS + Wait for External Clock Synchronization +0= No external clock synchronization pending +1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the +next basic cycle. + [30:30] + read-only + + + SPL + Schedule Phase Lock +The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it +signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the +rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). +0= Phase outside range +1= Phase inside range + [31:31] + read-only + + + + + TURNA + TUR Numerator Actual + 0x130 + 32 + read-only + 0x10000 + 0x3FFFF + + + NAV + N/A + [17:0] + read-only + + + + + TTLGT + TT Local & Global Time + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + LT + Local Time +Non-fractional part of local time, incremented once each local NTU (see Section 4.5). +0x0000-FFFF Local time value of TTCAN node + [15:0] + read-only + + + GT + Global Time +Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). +0x0000-FFFF Global time value of TTCAN network + [31:16] + read-only + + + + + TTCTC + TT Cycle Time & Count + 0x138 + 32 + read-only + 0x3F0000 + 0x3FFFFF + + + CT + Cycle Time +Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). +0x0000-FFFF Cycle time value of TTCAN Basic Cycle + [15:0] + read-only + + + CC + Cycle Count +0x00-3F Number of actual Basic Cycle in the System Matrix + [21:16] + read-only + + + + + TTCPT + TT Capture Time + 0x13C + 32 + read-only + 0x0 + 0xFFFF003F + + + CCV + Cycle Count Value +Cycle count value captured together with SWV. +0x00-3F Captured cycle count value + [5:0] + read-only + + + SWV + Stop Watch Value +On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected +by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. +0x0000-FFFF Captured Stop Watch value + [31:16] + read-only + + + + + TTCSM + TT Cycle Sync Mark + 0x140 + 32 + read-only + 0x0 + 0xFFFF + + + CSM + Cycle Sync Mark +The Cycle Sync Mark is measured + [15:0] + read-only + + + + + + RXFTOP_CTL + Receive FIFO Top control + 0x180 + 32 + read-write + 0x0 + 0x3 + + + F0TPE + FIFO 0 Top Pointer Enable. +This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. +This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). +When this logic is disabled a Read from RXFTOP0_DATA is undefined. + [0:0] + read-write + + + F1TPE + FIFO 1 Top Pointer Enable. + [1:1] + read-write + + + + + RXFTOP0_STAT + Receive FIFO 0 Top Status + 0x1A0 + 32 + read-only + 0x0 + 0xFFFF + + + F0TA + Current FIFO 0 Top Address. +This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) +FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC + [15:0] + read-only + + + + + RXFTOP0_DATA + Receive FIFO 0 Top Data + 0x1A8 + 32 + read-only + 0x0 + 0x0 + + + F0TD + When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: +- M_TTCAN not being reconfigured (CCCR.CCE=0) +- FIFO Top Pointer logic is enabled (FnTPE=1) +- FIFO is not empty (FnFL!=0) +The read side effect is as follows: +- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI +- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) +- the FIFO top address FnTA is incremented (with FIFO wrap around) +When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. + [31:0] + read-only + + + + + RXFTOP1_STAT + Receive FIFO 1 Top Status + 0x1B0 + 32 + read-only + 0x0 + 0xFFFF + + + F1TA + See F0TA description + [15:0] + read-only + + + + + RXFTOP1_DATA + Receive FIFO 1 Top Data + 0x1B8 + 32 + read-only + 0x0 + 0x0 + + + F1TD + See F0TD description + [31:0] + read-only + + + + + + CTL + Global CAN control register + 0x1000 + 32 + read-write + 0x0 + 0x800000FF + + + STOP_REQ + Clock Stop Request for each TTCAN IP . +The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. + [7:0] + read-write + + + MRAM_OFF + MRAM off +0= Default MRAM on (with MRAM retained in DeepSleep). +1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. +When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). +After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. + +To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. + [31:31] + read-write + + + + + STATUS + Global CAN status register + 0x1004 + 32 + read-only + 0x0 + 0xFF + + + STOP_ACK + Clock Stop Acknowledge for each TTCAN IP. +These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. +When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write + [7:0] + read-only + + + + + INTR0_CAUSE + Consolidated interrupt0 cause register + 0x1010 + 32 + read-only + 0x0 + 0xFF + + + INT0 + Show pending m_ttcan_int0 of each channel + [7:0] + read-only + + + + + INTR1_CAUSE + Consolidated interrupt1 cause register + 0x1014 + 32 + read-only + 0x0 + 0xFF + + + INT1 + Show pending m_ttcan_int1 of each channel + [7:0] + read-only + + + + + TS_CTL + Time Stamp control register + 0x1020 + 32 + read-write + 0x0 + 0x8000FFFF + + + PRESCALE + Time Stamp counter prescale value. +When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. + [15:0] + read-write + + + ENABLED + Counter enable bit +0 = Count disabled. Stop counting up and keep the counter value +1 = Count enabled. Start counting up from the current value + [31:31] + read-write + + + + + TS_CNT + Time Stamp counter value + 0x1024 + 32 + read-write + 0x0 + 0xFFFF + + + VALUE + The counter value of the Time Stamp Counter. +When enabled this counter will count Time Stamp clock ticks from the pre-scaler. +When written this counter and the pre-scaler will reset to 0 (write data is ignored). + [15:0] + read-write + + + + + ECC_CTL + ECC control + 0x1080 + 32 + read-write + 0x0 + 0x10000 + + + ECC_EN + Enable ECC for CANFD SRAM +When disabled also all error injection functionality is disabled. + [16:16] + read-write + + + + + ECC_ERR_INJ + ECC error injection + 0x1084 + 32 + read-write + 0xFFFC + 0x7F10FFFC + + + ERR_ADDR + Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. +When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. +When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. +Note that error reporting to the fault structure cannot be suppressed. + [15:2] + read-write + + + ERR_EN + Enable error injection (ECC_EN must be 1). +When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. +When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). +When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. + [20:20] + read-write + + + ERR_PAR + ECC Parity bits to use for ECC error injection at address ERR_ADDR. + [30:24] + read-write + + + + + + + SCB0 + Serial Communications Block (SPI/UART/I2C) + SCB + 0x40600000 + + 0 + 65536 + registers + + + + CTRL + Generic control + 0x0 + 32 + read-write + 0x300000F + 0x83031F0F + + + OVS + N/A + [3:0] + read-write + + + EC_AM_MODE + Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field should be '0'. + [8:8] + read-write + + + EC_OP_MODE + Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). + +In UART mode this field should be '0'. + [9:9] + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field should be '0'. + [10:10] + read-write + + + BYTE_MODE + Determines the number of bits per FIFO data element: +'0': 16-bit FIFO data elements. +'1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. + [11:11] + read-write + + + CMD_RESP_MODE + Determines CMD_RESP mode of operation: +'0': CMD_RESP mode disabled. +'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). + [12:12] + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). + +In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. + +In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. + [16:16] + read-write + + + BLOCK + Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. + [17:17] + read-write + + + MODE + N/A + [25:24] + read-write + + + I2C + Inter-Integrated Circuits (I2C) mode. + 0 + + + SPI + Serial Peripheral Interface (SPI) mode. + 1 + + + UART + Universal Asynchronous Receiver/Transmitter (UART) mode. + 2 + + + + + ENABLED + IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: +- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL to enable IP, select the specific operation mode and oversampling factor. +When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + [31:31] + read-write + + + + + STATUS + Generic status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. + [0:0] + read-only + + + + + CMD_RESP_CTRL + Command/response control + 0x8 + 32 + read-write + 0x0 + 0x1FF01FF + + + BASE_RD_ADDR + I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. + [8:0] + read-write + + + BASE_WR_ADDR + I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. + [24:16] + read-write + + + + + CMD_RESP_STATUS + Command/response status + 0xC + 32 + read-only + 0x0 + 0x0 + + + CURR_RD_ADDR + I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [8:0] + read-only + + + CURR_WR_ADDR + I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [24:16] + read-only + + + CMD_RESP_EC_BUS_BUSY + Indicates whether there is an ongoing bus transfer to the IP. +'0': no ongoing bus transfer. +'1': ongoing bus transfer. + +For SPI, the field is '1' when the slave is selected. + +For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. + [30:30] + read-only + + + CMD_RESP_EC_BUSY + Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: +- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. + Note that this update lasts one I2C clock cycle, or two SPI clock cycles. + [31:31] + read-only + + + + + SPI_CTRL + SPI control + 0x20 + 32 + read-write + 0x3000000 + 0x8F010F3F + + + SSEL_CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. + +When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. + +When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames. + [0:0] + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. + +When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. + +When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. + [1:1] + read-write + + + CPHA + Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: +- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. +- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. + +In SPI Motorola submode, all four CPOL/CPHA modes are valid. +in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. +in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. + [2:2] + read-write + + + CPOL + Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: +- CPOL is '0': SCLK is '0' when not transmitting data. +- CPOL is '1': SCLK is '1' when not transmitting data. + [3:3] + read-write + + + LATE_MISO_SAMPLE + Changes the SCLK edge on which MISO is captured. Only used in master mode. + +When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). + +When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. + [4:4] + read-write + + + SCLK_CONTINUOUS + Only applicable in master mode. +'0': SCLK is generated, when the SPI master is enabled and data is transmitted. +'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. + [5:5] + read-write + + + SSEL_POLARITY0 + Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: +'0': slave select is low/'0' active. +'1': slave select is high/'1' active. +For Texas Instruments submode: +'0': high/'1' active precede/coincide pulse. +'1': low/'0' active precede/coincide pulse. + [8:8] + read-write + + + SSEL_POLARITY1 + Slave select polarity. + [9:9] + read-write + + + SSEL_POLARITY2 + Slave select polarity. + [10:10] + read-write + + + SSEL_POLARITY3 + Slave select polarity. + [11:11] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. +'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. +'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + SPI_MOTOROLA + SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 0 + + + SPI_TI + SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. + 1 + + + SPI_NS + SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 2 + + + + + SSEL + Selects one of the four incoming/outgoing SPI slave select signals: +- 0: Slave 0, SSEL[0]. +- 1: Slave 1, SSEL[1]. +- 2: Slave 2, SSEL[2]. +- 3: Slave 3, SSEL[3]. +The IP should be disabled when changes are made to this field. + [27:26] + read-write + + + MASTER_MODE + Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. + [31:31] + read-write + + + + + SPI_STATUS + SPI status + 0x24 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. + [0:0] + read-only + + + SPI_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. + [1:1] + read-only + + + CURR_EZ_ADDR + SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + UART_CTRL + UART control + 0x40 + 32 + read-write + 0x3000000 + 0x3010000 + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. + +This allows a SCB UART transmitter to communicate with its receiver counterpart. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + UART_STD + Standard UART submode. + 0 + + + UART_SMARTCARD + SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. + 1 + + + UART_IRDA + Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. + 2 + + + + + + + UART_TX_CTRL + UART transmitter control + 0x44 + 32 + read-write + 0x2 + 0x137 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware + [5:5] + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + [8:8] + read-write + + + + + UART_RX_CTRL + UART receiver control + 0x48 + 32 + read-write + 0xA0002 + 0xF3777 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + +Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. + [5:5] + read-write + + + POLARITY + Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + [6:6] + read-write + + + DROP_ON_PARITY_ERROR + Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). + [8:8] + read-write + + + DROP_ON_FRAME_ERROR + Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + [9:9] + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. + [10:10] + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [12:12] + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. + [13:13] + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. + [19:16] + read-write + + + + + UART_RX_STATUS + UART receiver status + 0x4C + 32 + read-only + 0x0 + 0x0 + + + BR_COUNTER + Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. + [11:0] + read-only + + + + + UART_FLOW_CTRL + UART flow control + 0x50 + 32 + read-write + 0x0 + 0x30100FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). + [7:0] + read-write + + + RTS_POLARITY + Polarity of the RTS output signal 'uart_rts_out': +'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. +'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. + +During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. + [16:16] + read-write + + + CTS_POLARITY + Polarity of the CTS input signal 'uart_cts_in': +'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. +'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. + [24:24] + read-write + + + CTS_ENABLED + Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: +'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. +'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. + +If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). + [25:25] + read-write + + + + + I2C_CTRL + I2C control + 0x60 + 32 + read-write + 0xFB88 + 0xC001FBFF + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. + [3:0] + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. + [7:4] + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. + [8:8] + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). + [9:9] + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. + [11:11] + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [12:12] + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [13:13] + read-write + + + S_NOT_READY_ADDR_NACK + For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: +- EC_AM is '0', EC_OP is '0' and non EZ mode. +Functionality is as follows: +- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + +For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): +- EC_AM is '1' and EC_OP is '0'. +- EC_AM is '1' and general call address match. +- EC_AM is '1' and non EZ mode. +Functionality is as follows: +- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). +- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. + [14:14] + read-write + + + S_NOT_READY_DATA_NACK + For internally clocked logic only. Only used when: +- non EZ mode. +Functionality is as follows: +- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + [15:15] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. + [16:16] + read-write + + + SLAVE_MODE + Slave mode enabled ('1') or not ('0'). + [30:30] + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. + [31:31] + read-write + + + + + I2C_STATUS + I2C status + 0x64 + 32 + read-only + 0x0 + 0x31 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). + +For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). + +For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). + [0:0] + read-only + + + I2C_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. + [1:1] + read-only + + + S_READ + I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. + [4:4] + read-only + + + M_READ + I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. + [5:5] + read-only + + + CURR_EZ_ADDR + I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + I2C_M_CMD + I2C master command + 0x68 + 32 + read-write + 0x0 + 0x1F + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. + [0:0] + read-write + + + M_START_ON_IDLE + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. + [1:1] + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + [2:2] + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + [3:3] + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. + I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. + [4:4] + read-write + + + + + I2C_S_CMD + I2C slave command + 0x6C + 32 + read-write + 0x0 + 0x3 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). + [0:0] + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. + [1:1] + read-write + + + + + I2C_CFG + I2C configuration + 0x70 + 32 + read-write + 0x2A1013 + 0x303F1313 + + + SDA_IN_FILT_TRIM + Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + +SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. +1: enable clock_scb_en, has no effect on ec_busy_pp +0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) + [1:0] + read-write + + + SDA_IN_FILT_SEL + Selection of 'i2c_sda_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [4:4] + read-write + + + SCL_IN_FILT_TRIM + Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [9:8] + read-write + + + SCL_IN_FILT_SEL + Selection of 'i2c_scl_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [12:12] + read-write + + + SDA_OUT_FILT0_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [17:16] + read-write + + + SDA_OUT_FILT1_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [19:18] + read-write + + + SDA_OUT_FILT2_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [21:20] + read-write + + + SDA_OUT_FILT_SEL + Selection of cumulative 'i2c_sda_out' filter delay: +'0': 0 ns. +'1': 50 ns (filter 0 enabled). +'2': 100 ns (filters 0 and 1 enabled). +'3': 150 ns (filters 0, 1 and 2 enabled). + [29:28] + read-write + + + + + TX_CTRL + Transmitter control + 0x200 + 32 + read-write + 0x107 + 0x1010F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + OPEN_DRAIN + Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. +'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. +'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). + +The open drain mode is supported for: +- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. +- UART mode, 'uart_tx' IO cell (SPI slave). +- SPI mode, 'spi_miso' IO cell. + [16:16] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control + 0x204 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + [17:17] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status + 0x208 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + [31:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write + 0x240 + 32 + write-only + 0x0 + 0xFFFF + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. + [15:0] + write-only + + + + + RX_CTRL + Receiver control + 0x300 + 32 + read-write + 0x107 + 0x30F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. + [9:9] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control + 0x304 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + [17:17] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status + 0x308 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + [31:24] + read-only + + + + + RX_MATCH + Slave address and mask + 0x310 + 32 + read-write + 0x0 + 0xFF00FF + + + ADDR + Slave device address. + +In UART multi-processor mode, all 8 bits are used. + +In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). + [7:0] + read-write + + + MASK + Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). + [23:16] + read-write + + + + + RX_FIFO_RD + Receiver FIFO read + 0x340 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read silent + 0x344 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + INTR_CAUSE + Active clocked interrupt signal + 0xE00 + 32 + read-only + 0x0 + 0x3F + + + M + Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. + [0:0] + read-only + + + S + Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. + [1:1] + read-only + + + TX + Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. + [2:2] + read-only + + + RX + Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. + [3:3] + read-only + + + I2C_EC + Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. + [4:4] + read-only + + + SPI_EC + Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. + [5:5] + read-only + + + + + INTR_I2C_EC + Externally clocked I2C interrupt request + 0xE80 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (I2C STOP). + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask + 0xE88 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_I2C_EC_MASKED + Externally clocked I2C interrupt masked + 0xE8C + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_SPI_EC + Externally clocked SPI interrupt request + 0xEC0 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (SPI deselection). + +Only available in EZ and CMD_RESP mode and when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask + 0xEC8 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked + 0xECC + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_M + Master interrupt request + 0xF00 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + [0:0] + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + [1:1] + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + [2:2] + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + [4:4] + read-write + + + I2C_BUS_ERROR + I2C master bus error (unexpected detection of START or STOP condition). + [8:8] + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. + [9:9] + read-write + + + + + INTR_M_SET + Master interrupt set request + 0xF04 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASK + Master interrupt mask + 0xF08 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASKED + Master interrupt masked request + 0xF0C + 32 + read-only + 0x0 + 0x317 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + + + INTR_S + Slave interrupt request + 0xF40 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [0:0] + read-write + + + I2C_NACK + I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). + [1:1] + read-write + + + I2C_ACK + I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). + [2:2] + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. + +In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). + [3:3] + read-write + + + I2C_STOP + I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. + [4:4] + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. + [5:5] + read-write + + + I2C_ADDR_MATCH + I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [6:6] + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [7:7] + read-write + + + I2C_BUS_ERROR + I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + SPI slave deselected after a write EZ SPI transfer occurred. + [9:9] + read-write + + + SPI_EZ_STOP + SPI slave deselected after any EZ SPI transfer occurred. + [10:10] + read-write + + + SPI_BUS_ERROR + SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [11:11] + read-write + + + + + INTR_S_SET + Slave interrupt set request + 0xF44 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASK + Slave interrupt mask + 0xF48 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASKED + Slave interrupt masked request + 0xF4C + 32 + read-only + 0x0 + 0xFFF + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_START + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + SPI_EZ_STOP + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + SPI_BUS_ERROR + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + INTR_TX + Transmitter interrupt request + 0xF80 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_FULL + TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries != FF_DATA_NR/2. +BYTE_MODE is '1': # entries != FF_DATA_NR. + +Only used in FIFO mode. + [1:1] + read-write + + + EMPTY + TX FIFO is empty; i.e. it has 0 entries. + +Only used in FIFO mode. + [4:4] + read-write + + + OVERFLOW + Attempt to write to a full TX FIFO. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + UART_NACK + UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. + [8:8] + read-write + + + UART_DONE + UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. + [9:9] + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + + + INTR_TX_SET + Transmitter interrupt set request + 0xF84 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASK + Transmitter interrupt mask + 0xF88 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASKED + Transmitter interrupt masked request + 0xF8C + 32 + read-only + 0x0 + 0x7F3 + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + UART_NACK + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + UART_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + INTR_RX + Receiver interrupt request + 0xFC0 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_EMPTY + RX FIFO is not empty. + +Only used in FIFO mode. + [2:2] + read-write + + + FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries == FF_DATA_NR/2. +BYTE_MODE is '1': # entries == FF_DATA_NR. + +Only used in FIFO mode. + [3:3] + read-write + + + OVERFLOW + Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty RX FIFO. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + FRAME_ERROR + Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: +Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. +Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. + +A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. + [8:8] + read-write + + + PARITY_ERROR + Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. + [9:9] + read-write + + + BAUD_DETECT + LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. + [11:11] + read-write + + + + + INTR_RX_SET + Receiver interrupt set request + 0xFC4 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt status register. + [2:2] + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt status register. + [3:3] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt status register. + [7:7] + read-write + + + FRAME_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [8:8] + read-write + + + PARITY_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [9:9] + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [10:10] + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [11:11] + read-write + + + + + INTR_RX_MASK + Receiver interrupt mask + 0xFC8 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + FRAME_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + PARITY_ERROR + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_RX_MASKED + Receiver interrupt masked request + 0xFCC + 32 + read-only + 0x0 + 0xFED + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + FULL + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + FRAME_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + PARITY_ERROR + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + BAUD_DETECT + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + BREAK_DETECT + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + + + SCB1 + 0x40610000 + + + SCB2 + 0x40620000 + + + SCB3 + 0x40630000 + + + SCB4 + 0x40640000 + + + SCB5 + 0x40650000 + + + SCB6 + 0x40660000 + + + SAR + SAR ADC with Sequencer + 0x409D0000 + + 0 + 65536 + registers + + + + CTRL + Analog control register. + 0x0 + 32 + read-write + 0x10000000 + 0xFF3FEEF7 + + + PWR_CTRL_VREF + VREF buffer low power mode. + [2:0] + read-write + + + PWR_100 + full power (100 percent) (default), bypass cap, max clk_sar is 18MHz. + 0 + + + PWR_80 + 80 percent power + 1 + + + PWR_60 + 60 percent power + 2 + + + PWR_50 + 50 percent power + 3 + + + PWR_40 + 40 percent power + 4 + + + PWR_30 + 30 percent power + 5 + + + PWR_20 + 20 percent power + 6 + + + PWR_10 + 10 percent power + 7 + + + + + VREF_SEL + SARADC internal VREF selection. + [6:4] + read-write + + + VREF0 + VREF0 from PRB (VREF buffer on) + 0 + + + VREF1 + VREF1 from PRB (VREF buffer on) + 1 + + + VREF2 + VREF2 from PRB (VREF buffer on) + 2 + + + VREF_AROUTE + VREF from AROUTE (VREF buffer on) + 3 + + + VBGR + 1.024V from BandGap (VREF buffer on) + 4 + + + VREF_EXT + External precision Vref direct from a pin (low impedance path). + 5 + + + VDDA_DIV_2 + Vdda/2 (VREF buffer on) + 6 + + + VDDA + Vdda. + 7 + + + + + VREF_BYP_CAP_EN + VREF bypass cap enable for when VREF buffer is on + [7:7] + read-write + + + NEG_SEL + SARADC internal NEG selection for Single ended conversion + [11:9] + read-write + + + VSSA_KELVIN + NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high. + 0 + + + ART_VSSA + NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC + 1 + + + P1 + NEG input of SARADC is connected to P1 pin of SARMUX + 2 + + + P3 + NEG input of SARADC is connected to P3 pin of SARMUX + 3 + + + P5 + NEG input of SARADC is connected to P5 pin of SARMUX + 4 + + + P7 + NEG input of SARADC is connected to P7 pin of SARMUX + 5 + + + ACORE + NEG input of SARADC is connected to an ACORE in AROUTE + 6 + + + VREF + NEG input of SARADC is shorted with VREF input of SARADC. + 7 + + + + + SAR_HW_CTRL_NEGVREF + Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. + [13:13] + read-write + + + COMP_DLY + Set the comparator latch delay in accordance with SAR conversion rate + [15:14] + read-write + + + D2P5 + 2.5ns delay, use this for 2.5Msps + 0 + + + D4 + 4.0ns delay, use this for 2.0Msps + 1 + + + D10 + 10ns delay, use this for 1.5Msps + 2 + + + D12 + 12ns delay, use this for 1.0Msps or less + 3 + + + + + SPARE + Spare controls, not yet designated, for late changes done with an ECO + [19:16] + read-write + + + BOOSTPUMP_EN + deprecated + [20:20] + read-write + + + REFBUF_EN + For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. +Setting this bit is critical to proper function of switches inside SARREF block. + [21:21] + read-write + + + COMP_PWR + Comparator power mode. + [26:24] + read-write + + + P100 + Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz + 0 + + + P80 + N/A + 1 + + + P60 + Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz. + 2 + + + P50 + N/A + 3 + + + P40 + N/A + 4 + + + P30 + N/A + 5 + + + P20 + Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz + 6 + + + P10 + N/A + 7 + + + + + DEEPSLEEP_ON + - 0: SARMUX IP disabled off during DeepSleep power mode +- 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) + [27:27] + read-write + + + DSI_SYNC_CONFIG + - 0: bypass clock domain synchronization of the DSI config signals. +- 1: synchronize the DSI config signals to peripheral clock domain. + [28:28] + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) +- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations +- 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored + [29:29] + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) +- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations +- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX + [30:30] + read-write + + + ENABLED + - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgating) on write. +- 1: SAR IP enabled. + [31:31] + read-write + + + + + SAMPLE_CTRL + Sample control register. + 0x4 + 32 + read-write + 0x80008 + 0xDFCF01FE + + + LEFT_ALIGN + Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. + [1:1] + read-write + + + SINGLE_ENDED_SIGNED + Output data from a single ended conversion as a signed value + +If AVG_MODE = 1 (Interleaved averaging), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED. + [2:2] + read-write + + + UNSIGNED + Default: result data is unsigned (zero extended if needed) + 0 + + + SIGNED + result data is signed (sign extended if needed) + 1 + + + + + DIFFERENTIAL_SIGNED + Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 + +If AVG_MODE = 1 (Interleaved averaging), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED. + [3:3] + read-write + + + UNSIGNED + result data is unsigned (zero extended if needed) + 0 + + + SIGNED + Default: result data is signed (sign extended if needed) + 1 + + + + + AVG_CNT + Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. +- In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). +- In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). + [6:4] + read-write + + + AVG_SHIFT + Averaging shifting: after averaging the result is shifted right to fit in 12 bits. + [7:7] + read-write + + + AVG_MODE + Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. + [8:8] + read-write + + + ACCUNDUMP + Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged + 0 + + + INTERLEAVED + Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans. + 1 + + + + + CONTINUOUS + - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. +- 1: Continuously scan enabled channels, ignore triggers. + [16:16] + read-write + + + DSI_TRIGGER_EN + - 0: firmware trigger only: disable hardware trigger tr_sar_in. +- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). + [17:17] + read-write + + + DSI_TRIGGER_LEVEL + - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. +- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. + [18:18] + read-write + + + DSI_SYNC_TRIGGER + - 0: bypass clock domain synchronization of the trigger signal. +- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. + [19:19] + read-write + + + UAB_SCAN_MODE + Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored. + [22:22] + read-write + + + UNSCHEDULED + Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable. + 0 + + + SCHEDULED + Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. +This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator. + 1 + + + + + REPEAT_INVALID + For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: +- 0: use the last known valid sample for that channel and clear the NEWVALUE flag +- 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling) + [23:23] + read-write + + + VALID_SEL + Static UAB Valid select +0=UAB0 half 0 Valid output +1=UAB0 half 1 Valid output +2=UAB1 half 0 Valid output +3=UAB1 half 1 Valid output +4=UAB2 half 0 Valid output +5=UAB2 half 1 Valid output +6=UAB3 half 0 Valid output +7=UAB3 half 1 Valid output + [26:24] + read-write + + + VALID_SEL_EN + Enable static UAB Valid selection (override Hardware) + [27:27] + read-write + + + VALID_IGNORE + Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above + [28:28] + read-write + + + TRIGGER_OUT_EN + SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1). + [30:30] + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. + [31:31] + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x10 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. + [9:0] + read-write + + + SAMPLE_TIME1 + Sample time1 + [25:16] + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x14 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME2 + Sample time2 + [9:0] + read-write + + + SAMPLE_TIME3 + Sample time3 + [25:16] + read-write + + + + + RANGE_THRES + Global range detect threshold register. + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RANGE_LOW + Low threshold for range detect. + [15:0] + read-write + + + RANGE_HIGH + High threshold for range detect. + [31:16] + read-write + + + + + RANGE_COND + Global range detect mode register. + 0x1C + 32 + read-write + 0x0 + 0xC0000000 + + + RANGE_COND + Range condition select. + [31:30] + read-write + + + BELOW + result < RANGE_LOW + 0 + + + INSIDE + RANGE_LOW <= result < RANGE_HIGH + 1 + + + ABOVE + RANGE_HIGH <= result + 2 + + + OUTSIDE + result < RANGE_LOW || RANGE_HIGH <= result + 3 + + + + + + + CHAN_EN + Enable bits for the channels + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CHAN_EN + Channel enable. +- 0: the corresponding channel is disabled. +- 1: the corresponding channel is enabled, it will be included in the next scan. + [15:0] + read-write + + + + + START_CTRL + Start control register (firmware trigger). + 0x24 + 32 + read-write + 0x0 + 0x1 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. + [0:0] + read-write + + + + + 16 + 4 + CHAN_CONFIG[%s] + Channel configuration register. + 0x80 + 32 + read-write + 0x0 + 0x81773577 + + + POS_PIN_ADDR + Address of the pin to be sampled by this channel (connected to Vplus) + [2:0] + read-write + + + POS_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel (connected to Vplus) + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + DIFFERENTIAL_EN + Differential enable for this channel. +If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + NEG_PIN_ADDR + Address of the neg pin to be sampled by this channel. + [18:16] + read-write + + + NEG_PORT_ADDR + Address of the neg port that contains the pin to be sampled by this channel. + [22:20] + read-write + + + SARMUX + SARMUX pins. + 0 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + NEG_ADDR_EN + 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. + [24:24] + read-write + + + DSI_OUT_EN + DSI data output enable for this channel. +- 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. +- 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. + [31:31] + read-write + + + + + 16 + 4 + CHAN_WORK[%s] + Channel working data register + 0x100 + 32 + read-only + 0x0 + 0x88000000 + + + WORK + SAR conversion working data of the channel. The data is written here right after sampling this channel. + [15:0] + read-only + + + CHAN_WORK_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register + [27:27] + read-only + + + CHAN_WORK_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register + [31:31] + read-only + + + + + 16 + 4 + CHAN_RESULT[%s] + Channel result data register + 0x180 + 32 + read-only + 0x0 + 0xE8000000 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + [15:0] + read-only + + + CHAN_RESULT_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register + [27:27] + read-only + + + SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_SATURATE_INTR register + [29:29] + read-only + + + RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_RANGE_INTR register + [30:30] + read-only + + + CHAN_RESULT_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register + [31:31] + read-only + + + + + CHAN_WORK_UPDATED + Channel working data register 'updated' bits + 0x200 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_UPDATED + If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_RESULT_UPDATED + Channel result data register 'updated' bits + 0x204 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_UPDATED + If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_WORK_NEWVALUE + Channel working data register 'new value' bits + 0x208 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_NEWVALUE + If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + CHAN_RESULT_NEWVALUE + Channel result data register 'new value' bits + 0x20C + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_NEWVALUE + If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + INTR + Interrupt request register. + 0x210 + 32 + read-write + 0x0 + 0xFF + + + EOS_INTR + End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. + [0:0] + read-write + + + OVERFLOW_INTR + Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. + [1:1] + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [2:2] + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [3:3] + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. + [4:4] + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [5:5] + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [6:6] + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit. + [7:7] + read-write + + + + + INTR_SET + Interrupt set request register + 0x214 + 32 + read-write + 0x0 + 0xFF + + + EOS_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask register. + 0x218 + 32 + read-write + 0x0 + 0xFF + + + EOS_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_MASK + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x21C + 32 + read-only + 0x0 + 0xFF + + + EOS_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + OVERFLOW_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + FW_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + DSI_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + INJ_EOC_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + INJ_SATURATE_MASKED + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + INJ_RANGE_MASKED + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + INJ_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + + + SATURATE_INTR + Saturate interrupt request register. + 0x220 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_INTR + Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [15:0] + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x224 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register. + 0x228 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x22C + 32 + read-only + 0x0 + 0xFFFF + + + SATURATE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + RANGE_INTR + Range detect interrupt request register. + 0x230 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_INTR + Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [15:0] + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x234 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register. + 0x238 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x23C + 32 + read-only + 0x0 + 0xFFFF + + + RANGE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + INTR_CAUSE + Interrupt cause register + 0x240 + 32 + read-only + 0x0 + 0xC00000FF + + + EOS_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [0:0] + read-only + + + OVERFLOW_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [1:1] + read-only + + + FW_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [2:2] + read-only + + + DSI_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [3:3] + read-only + + + INJ_EOC_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [4:4] + read-only + + + INJ_SATURATE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [5:5] + read-only + + + INJ_RANGE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [6:6] + read-only + + + INJ_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [7:7] + read-only + + + SATURATE_MASKED_RED + Reduction OR of all SAR_SATURATION_INTR_MASKED bits + [30:30] + read-only + + + RANGE_MASKED_RED + Reduction OR of all SAR_RANGE_INTR_MASKED bits + [31:31] + read-only + + + + + INJ_CHAN_CONFIG + Injection channel configuration register. + 0x280 + 32 + read-write + 0x0 + 0xC0003577 + + + INJ_PIN_ADDR + Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. + [2:0] + read-write + + + INJ_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel. + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT + AROUTE virtual port + 6 + + + SARMUX_VIRT + SARMUX virtual port + 7 + + + + + INJ_DIFFERENTIAL_EN + Differential enable for this channel. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + INJ_AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + INJ_SAMPLE_TIME_SEL + Injection sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + INJ_TAILGATING + Injection channel tailgating. +- 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set if the SAR is not busy. If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan. +- 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. + [30:30] + read-write + + + INJ_START_EN + Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. + [31:31] + read-write + + + + + INJ_RESULT + Injection channel result register + 0x290 + 32 + read-only + 0x0 + 0xF8000000 + + + INJ_RESULT + SAR conversion result of the channel. + [15:0] + read-only + + + INJ_NEWVALUE + The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit) + [27:27] + read-only + + + INJ_COLLISION_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [28:28] + read-only + + + INJ_SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [29:29] + read-only + + + INJ_RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [30:30] + read-only + + + INJ_EOC_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register + [31:31] + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x2A0 + 32 + read-only + 0x0 + 0xC000001F + + + CUR_CHAN + current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. + [4:0] + read-only + + + SW_VREF_NEG + the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). + [30:30] + read-only + + + BUSY + If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. + [31:31] + read-only + + + + + AVG_STAT + Current averaging status (for debug) + 0x2A4 + 32 + read-only + 0x0 + 0xFF8FFFFF + + + CUR_AVG_ACCU + the current value of the averaging accumulator + [19:0] + read-only + + + INTRLV_BUSY + If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. +This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. + [23:23] + read-only + + + CUR_AVG_CNT + the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. + [31:24] + read-only + + + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x300 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit. + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit. + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit. + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit. + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit. + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit. + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit. + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit. + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit. + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit. + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit. + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit. + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit. + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit. + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit. + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit. + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit. + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit. + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit. + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit. + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit. + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit. + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit. + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit. + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit. + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit. + [29:29] + read-write + + + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x304 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [29:29] + read-write + + + + + MUX_SWITCH_DS_CTRL + SARMUX switch DSI control + 0x340 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_DS_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_DS_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_DS_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_DS_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_DS_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_DS_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_DS_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_DS_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_DS_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_DS_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_DS_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_DS_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_DS_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_DS_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_SQ_CTRL + SARMUX switch Sar Sequencer control + 0x344 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_SQ_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_SQ_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_SQ_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_SQ_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_SQ_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_SQ_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_SQ_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_SQ_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_SQ_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_SQ_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_SQ_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_SQ_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_SQ_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_SQ_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x348 + 32 + read-only + 0x0 + 0x3FFFFFF + + + MUX_FW_P0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [0:0] + read-only + + + MUX_FW_P1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [1:1] + read-only + + + MUX_FW_P2_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [2:2] + read-only + + + MUX_FW_P3_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [3:3] + read-only + + + MUX_FW_P4_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [4:4] + read-only + + + MUX_FW_P5_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [5:5] + read-only + + + MUX_FW_P6_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [6:6] + read-only + + + MUX_FW_P7_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [7:7] + read-only + + + MUX_FW_P0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [8:8] + read-only + + + MUX_FW_P1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [9:9] + read-only + + + MUX_FW_P2_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [10:10] + read-only + + + MUX_FW_P3_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [11:11] + read-only + + + MUX_FW_P4_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [12:12] + read-only + + + MUX_FW_P5_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [13:13] + read-only + + + MUX_FW_P6_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [14:14] + read-only + + + MUX_FW_P7_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [15:15] + read-only + + + MUX_FW_VSSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [16:16] + read-only + + + MUX_FW_TEMP_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [17:17] + read-only + + + MUX_FW_AMUXBUSA_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [18:18] + read-only + + + MUX_FW_AMUXBUSB_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [19:19] + read-only + + + MUX_FW_AMUXBUSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [20:20] + read-only + + + MUX_FW_AMUXBUSB_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [21:21] + read-only + + + MUX_FW_SARBUS0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [22:22] + read-only + + + MUX_FW_SARBUS1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [23:23] + read-only + + + MUX_FW_SARBUS0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [24:24] + read-only + + + MUX_FW_SARBUS1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [25:25] + read-only + + + + + ANA_TRIM0 + Analog trim register. + 0xF00 + 32 + read-write + 0x0 + 0x3F + + + CAP_TRIM + Attenuation cap trimming + [4:0] + read-write + + + TRIMUNIT + Attenuation cap trimming + [5:5] + read-write + + + + + ANA_TRIM1 + Analog trim register. + 0xF04 + 32 + read-write + 0x0 + 0x3F + + + SAR_REF_BUF_TRIM + SAR Reference buffer trim + [5:0] + read-write + + + + + + + PASS + PASS top-level MMIO (DSABv2, INTR) + 0x409F0000 + + 0 + 65536 + registers + + + + INTR_CAUSE + Interrupt cause register + 0x0 + 32 + read-only + 0x0 + 0xFF + + + CTB0_INT + CTB0 interrupt pending + [0:0] + read-only + + + CTB1_INT + CTB1 interrupt pending + [1:1] + read-only + + + CTB2_INT + CTB2 interrupt pending + [2:2] + read-only + + + CTB3_INT + CTB3 interrupt pending + [3:3] + read-only + + + CTDAC0_INT + CTDAC0 interrupt pending + [4:4] + read-only + + + CTDAC1_INT + CTDAC1 interrupt pending + [5:5] + read-only + + + CTDAC2_INT + CTDAC2 interrupt pending + [6:6] + read-only + + + CTDAC3_INT + CTDAC3 interrupt pending + [7:7] + read-only + + + + + AREF + AREF configuration + 0x00000E00 + + AREF_CTRL + global AREF control + 0x0 + 32 + read-write + 0x0 + 0xF039FFFD + + + AREF_MODE + Control bit to trade off AREF settling and noise performance + [0:0] + read-write + + + NORMAL + Nominal noise normal startup mode (meets normal mode settling and noise specifications) + 0 + + + FAST_START + High noise fast startup mode (meets fast mode settling and noise specifications) + 1 + + + + + AREF_BIAS_SCALE + BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) +0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) +1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) +2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) +3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) + [3:2] + read-write + + + AREF_RMB + AREF control signals (RMB). + +Bit 0: Manual VBG startup circuit enable + 0: normal VBG startup circuit operation + 1: VBG startup circuit is forced 'always on' + +Bit 1: Manual disable of IPTAT2 DAC + 0: normal IPTAT2 DAC operation + 1: PTAT2 DAC is disabled while VBG startup is active + +Bit 2: Manual enable of VBG offset correction DAC + 0: normal VBG offset correction DAC operation + 1: VBG offset correction DAC is enabled while VBG startup is active + [6:4] + read-write + + + CTB_IPTAT_SCALE + CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). +0: 1uA +1: 100nA + [7:7] + read-write + + + CTB_IPTAT_REDIRECT + Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). +0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT +1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT + +*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. + [15:8] + read-write + + + IZTAT_SEL + iztat current select control + [16:16] + read-write + + + SRSS + Use 250nA IZTAT from SRSS + 0 + + + LOCAL + Use locally generated 250nA + 1 + + + + + CLOCK_PUMP_PERI_SEL + CTBm charge pump clock source select. This field has nothing to do with the AREF. +0: Use the dedicated pump clock from SRSS (default) +1: Use one of the CLK_PERI dividers + [19:19] + read-write + + + VREF_SEL + bandgap voltage select control + [21:20] + read-write + + + SRSS + Use 0.8V Vref from SRSS + 0 + + + LOCAL + Use locally generated Vref + 1 + + + EXTERNAL + Use externally supplied Vref (aref_ext_vref) + 2 + + + + + DEEPSLEEP_MODE + AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) + [29:28] + read-write + + + OFF + All blocks 'OFF' in DeepSleep + 0 + + + IPTAT + IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) + 1 + + + IPTAT_IZTAT + IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) + +*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep + 2 + + + IPTAT_IZTAT_VREF + IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. + 3 + + + + + DEEPSLEEP_ON + - 0: AREF IP disabled/off during DeepSleep power mode +- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + Disable AREF + [31:31] + read-write + + + + + + VREF_TRIM0 + VREF Trim bits + 0xF00 + 32 + read-write + 0x0 + 0xFF + + + VREF_ABS_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM1 + VREF Trim bits + 0xF04 + 32 + read-write + 0x0 + 0xFF + + + VREF_TEMPCO_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM2 + VREF Trim bits + 0xF08 + 32 + read-write + 0x0 + 0xFF + + + VREF_CURV_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM3 + VREF Trim bits + 0xF0C + 32 + read-write + 0x0 + 0xF + + + VREF_ATTEN_TRIM + Obsolete + [3:0] + read-write + + + + + IZTAT_TRIM0 + IZTAT Trim bits + 0xF10 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_ABS_TRIM + N/A + [7:0] + read-write + + + + + IZTAT_TRIM1 + IZTAT Trim bits + 0xF14 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_TC_TRIM + IZTAT temperature correction trim (RMB) +0x00 : No IZTAT temperature correction +0xFF : Maximum IZTAT temperature correction + +As this is a Risk Mitigation Register, it should be loaded with 0x08. + [7:0] + read-write + + + + + IPTAT_TRIM0 + IPTAT Trim bits + 0xF18 + 32 + read-write + 0x0 + 0xFF + + + IPTAT_CORE_TRIM + IPTAT trim +0x0 : Minimum IPTAT current (~150nA at room) +0xF : Maximum IPTAT current (~350nA at room) + [3:0] + read-write + + + IPTAT_CTBM_TRIM + CTMB PTAT Current Trim +0x0 : Minimum CTMB IPTAT Current (~875nA) +0xF : Maximum CTMB IPTAT Current (~1.1uA) + [7:4] + read-write + + + + + ICTAT_TRIM0 + ICTAT Trim bits + 0xF1C + 32 + read-write + 0x0 + 0xF + + + ICTAT_TRIM + ICTAT trim +0x00 : Minimum ICTAT current (~150nA at room) +0x0F : Maximum ICTAT current (~350nA at room) + [3:0] + read-write + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_04.svd b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_04.svd new file mode 100644 index 0000000000..e2e82c8be7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/psoc6_04.svd @@ -0,0 +1,43124 @@ + + + + Cypress Semiconductor + Cypress + psoc6_04 + PSoC6_04 + 1.0 + PSoC6_04 + Copyright 2016-2021 Cypress Semiconductor Corporation\n + SPDX-License-Identifier: Apache-2.0\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + CM4 + r0p1 + little + true + true + 1 + 3 + 0 + + 8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERI + Peripheral interconnect + 0x40000000 + + 0 + 65536 + registers + + + + TIMEOUT_CTL + Timeout control + 0x200 + 32 + read-write + 0xFFFF + 0xFFFF + + + TIMEOUT + This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). +'0x0000'-'0xfffe': Number of clock cycles. +'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. + [15:0] + read-write + + + + + TR_CMD + Trigger command + 0x220 + 32 + read-write + 0x0 + 0xE0001FFF + + + TR_SEL + Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. + [7:0] + read-write + + + GROUP_SEL + Specifies the trigger group: +'0'-'15': trigger multiplexer groups. +'16'-'31': trigger 1-to-1 groups. + [12:8] + read-write + + + TR_EDGE + Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. +'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. + [29:29] + read-write + + + OUT_SEL + Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. +'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. +'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. + +Note: this field is not used for trigger 1-to-1 groups. + [30:30] + read-write + + + ACTIVATE + SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. + +Note: when ACTIVATE is '1', SW should not modify the other register fields. + [31:31] + read-write + + + + + DIV_CMD + Divider command + 0x400 + 32 + read-write + 0x3FF03FF + 0xC3FF03FF + + + DIV_SEL + (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. + [7:0] + read-write + + + TYPE_SEL + Specifies the divider type of the divider on which the command is performed: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + PA_DIV_SEL + (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. + +If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. + [23:16] + read-write + + + PA_TYPE_SEL + Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [25:24] + read-write + + + DISABLE + Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. + +The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. + [30:30] + read-write + + + ENABLE + Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the DIV_CMD.DISABLE field. +1: Configure the divider's DIV_XXX_CTL register. +2: Enable the divider using the DIV_CMD_ENABLE field. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. + +The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. + +The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. + [31:31] + read-write + + + + + 256 + 4 + CLOCK_CTL[%s] + Clock control + 0xC00 + 32 + read-write + 0x3FF + 0x3FF + + + DIV_SEL + Specifies one of the dividers of the divider type specified by TYPE_SEL. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. + +When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. + [7:0] + read-write + + + TYPE_SEL + Specifies divider type: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + + + 256 + 4 + DIV_8_CTL[%s] + Divider control (for 8.0 divider) + 0x1000 + 32 + read-write + 0x0 + 0xFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT8_DIV + Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 256]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + 256 + 4 + DIV_16_CTL[%s] + Divider control (for 16.0 divider) + 0x1400 + 32 + read-write + 0x0 + 0xFFFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 256 + 4 + DIV_16_5_CTL[%s] + Divider control (for 16.5 divider) + 0x1800 + 32 + read-write + 0x0 + 0xFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. + +For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 255 + 4 + DIV_24_5_CTL[%s] + Divider control (for 24.5 divider) + 0x1C00 + 32 + read-write + 0x0 + 0xFFFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT24_DIV + Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. + +For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [31:8] + read-write + + + + + ECC_CTL + ECC control + 0x2000 + 32 + read-write + 0x10000 + 0xFF0507FF + + + WORD_ADDR + Specifies the word address where the parity is injected. +- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [10:0] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_INJ_EN + Enable error injection for PERI protection structure SRAM. +When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. + [18:18] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:24] + read-write + + + + + 10 + 32 + GR[%s] + Peripheral group structure + 0x00004000 + + CLOCK_CTL + Clock control + 0x0 + 32 + read-write + 0x0 + 0xFF00 + + + INT8_DIV + Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + SL_CTL + Slave control + 0x10 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ENABLED_0 + Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [0:0] + read-write + + + ENABLED_1 + Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [1:1] + read-write + + + ENABLED_2 + N/A + [2:2] + read-write + + + ENABLED_3 + N/A + [3:3] + read-write + + + ENABLED_4 + N/A + [4:4] + read-write + + + ENABLED_5 + N/A + [5:5] + read-write + + + ENABLED_6 + N/A + [6:6] + read-write + + + ENABLED_7 + N/A + [7:7] + read-write + + + ENABLED_8 + N/A + [8:8] + read-write + + + ENABLED_9 + N/A + [9:9] + read-write + + + ENABLED_10 + N/A + [10:10] + read-write + + + ENABLED_11 + N/A + [11:11] + read-write + + + ENABLED_12 + N/A + [12:12] + read-write + + + ENABLED_13 + N/A + [13:13] + read-write + + + ENABLED_14 + N/A + [14:14] + read-write + + + ENABLED_15 + N/A + [15:15] + read-write + + + DISABLED_0 + Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. + [16:16] + read-write + + + DISABLED_1 + N/A + [17:17] + read-write + + + DISABLED_2 + N/A + [18:18] + read-write + + + DISABLED_3 + N/A + [19:19] + read-write + + + DISABLED_4 + N/A + [20:20] + read-write + + + DISABLED_5 + N/A + [21:21] + read-write + + + DISABLED_6 + N/A + [22:22] + read-write + + + DISABLED_7 + N/A + [23:23] + read-write + + + DISABLED_8 + N/A + [24:24] + read-write + + + DISABLED_9 + N/A + [25:25] + read-write + + + DISABLED_10 + N/A + [26:26] + read-write + + + DISABLED_11 + N/A + [27:27] + read-write + + + DISABLED_12 + N/A + [28:28] + read-write + + + DISABLED_13 + N/A + [29:29] + read-write + + + DISABLED_14 + N/A + [30:30] + read-write + + + DISABLED_15 + N/A + [31:31] + read-write + + + + + + 12 + 1024 + TR_GR[%s] + Trigger group + 0x00008000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x13FF + + + TR_SEL + Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. + [7:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + 9 + 1024 + TR_1TO1_GR[%s] + Trigger 1-to-1 group + 0x0000C000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x1301 + + + TR_SEL + Specifies input trigger: +'0'': constant signal level '0'. +'1': input trigger. + [0:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + + + PERI_MS + Peripheral interconnect, master interface + 0x40010000 + + 0 + 65536 + registers + + + + 8 + 64 + PPU_PR[%s] + Programmable protection structure pair + 0x00000000 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-write + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-write + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + 227 + 64 + PPU_FX[%s] + Fixed protection structure pair + 0x00000800 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFC + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-only + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-only + 0x80000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-only + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-only + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + + + CPUSS + CPU subsystem (CPUSS) + 0x40200000 + + 0 + 65536 + registers + + + ioss_interrupts_gpio_0 + GPIO Port Interrupt #0 + 0 + + + ioss_interrupts_gpio_2 + GPIO Port Interrupt #2 + 2 + + + ioss_interrupts_gpio_3 + GPIO Port Interrupt #3 + 3 + + + ioss_interrupts_gpio_5 + GPIO Port Interrupt #5 + 5 + + + ioss_interrupts_gpio_6 + GPIO Port Interrupt #6 + 6 + + + ioss_interrupts_gpio_7 + GPIO Port Interrupt #7 + 7 + + + ioss_interrupts_gpio_8 + GPIO Port Interrupt #8 + 8 + + + ioss_interrupts_gpio_9 + GPIO Port Interrupt #9 + 9 + + + ioss_interrupts_gpio_10 + GPIO Port Interrupt #10 + 10 + + + ioss_interrupts_gpio_11 + GPIO Port Interrupt #11 + 11 + + + ioss_interrupts_gpio_12 + GPIO Port Interrupt #12 + 12 + + + ioss_interrupts_gpio_14 + GPIO Port Interrupt #14 + 14 + + + ioss_interrupt_gpio + GPIO All Ports + 15 + + + ioss_interrupt_vdd + GPIO Supply Detect Interrupt + 16 + + + lpcomp_interrupt + Low Power Comparator Interrupt + 17 + + + scb_6_interrupt + Serial Communication Block #6 (DeepSleep capable) + 18 + + + srss_interrupt_mcwdt_0 + Multi Counter Watchdog Timer interrupt + 19 + + + srss_interrupt_mcwdt_1 + Multi Counter Watchdog Timer interrupt + 20 + + + srss_interrupt_backup + Backup domain interrupt + 21 + + + srss_interrupt + Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + 22 + + + cpuss_interrupts_ipc_0 + CPUSS Inter Process Communication Interrupt #0 + 23 + + + cpuss_interrupts_ipc_1 + CPUSS Inter Process Communication Interrupt #1 + 24 + + + cpuss_interrupts_ipc_2 + CPUSS Inter Process Communication Interrupt #2 + 25 + + + cpuss_interrupts_ipc_3 + CPUSS Inter Process Communication Interrupt #3 + 26 + + + cpuss_interrupts_ipc_4 + CPUSS Inter Process Communication Interrupt #4 + 27 + + + cpuss_interrupts_ipc_5 + CPUSS Inter Process Communication Interrupt #5 + 28 + + + cpuss_interrupts_ipc_6 + CPUSS Inter Process Communication Interrupt #6 + 29 + + + cpuss_interrupts_ipc_7 + CPUSS Inter Process Communication Interrupt #7 + 30 + + + cpuss_interrupts_ipc_8 + CPUSS Inter Process Communication Interrupt #8 + 31 + + + cpuss_interrupts_ipc_9 + CPUSS Inter Process Communication Interrupt #9 + 32 + + + cpuss_interrupts_ipc_10 + CPUSS Inter Process Communication Interrupt #10 + 33 + + + cpuss_interrupts_ipc_11 + CPUSS Inter Process Communication Interrupt #11 + 34 + + + cpuss_interrupts_ipc_12 + CPUSS Inter Process Communication Interrupt #12 + 35 + + + cpuss_interrupts_ipc_13 + CPUSS Inter Process Communication Interrupt #13 + 36 + + + cpuss_interrupts_ipc_14 + CPUSS Inter Process Communication Interrupt #14 + 37 + + + cpuss_interrupts_ipc_15 + CPUSS Inter Process Communication Interrupt #15 + 38 + + + pass_interrupt_sar_0 + SAR ADC0 interrupt + 39 + + + pass_interrupt_sar_1 + SAR ADC1 interrupt + 40 + + + pass_interrupt_ctbs + individual interrupt per CTB + 41 + + + pass_interrupt_fifo_0 + PASS FIFO0 + 43 + + + pass_interrupt_fifo_1 + PASS FIFO1 + 44 + + + scb_0_interrupt + Serial Communication Block #0 + 45 + + + scb_1_interrupt + Serial Communication Block #1 + 46 + + + scb_2_interrupt + Serial Communication Block #2 + 47 + + + scb_4_interrupt + Serial Communication Block #4 + 49 + + + scb_5_interrupt + Serial Communication Block #5 + 50 + + + csd_interrupt + CSD (Capsense) interrupt + 51 + + + cpuss_interrupts_dmac_0 + CPUSS DMAC, Channel #0 + 52 + + + cpuss_interrupts_dmac_1 + CPUSS DMAC, Channel #1 + 53 + + + cpuss_interrupts_dw0_0 + CPUSS DataWire #0, Channel #0 + 56 + + + cpuss_interrupts_dw0_1 + CPUSS DataWire #0, Channel #1 + 57 + + + cpuss_interrupts_dw0_2 + CPUSS DataWire #0, Channel #2 + 58 + + + cpuss_interrupts_dw0_3 + CPUSS DataWire #0, Channel #3 + 59 + + + cpuss_interrupts_dw0_4 + CPUSS DataWire #0, Channel #4 + 60 + + + cpuss_interrupts_dw0_5 + CPUSS DataWire #0, Channel #5 + 61 + + + cpuss_interrupts_dw0_6 + CPUSS DataWire #0, Channel #6 + 62 + + + cpuss_interrupts_dw0_7 + CPUSS DataWire #0, Channel #7 + 63 + + + cpuss_interrupts_dw0_8 + CPUSS DataWire #0, Channel #8 + 64 + + + cpuss_interrupts_dw0_9 + CPUSS DataWire #0, Channel #9 + 65 + + + cpuss_interrupts_dw0_10 + CPUSS DataWire #0, Channel #10 + 66 + + + cpuss_interrupts_dw0_11 + CPUSS DataWire #0, Channel #11 + 67 + + + cpuss_interrupts_dw0_12 + CPUSS DataWire #0, Channel #12 + 68 + + + cpuss_interrupts_dw0_13 + CPUSS DataWire #0, Channel #13 + 69 + + + cpuss_interrupts_dw0_14 + CPUSS DataWire #0, Channel #14 + 70 + + + cpuss_interrupts_dw0_15 + CPUSS DataWire #0, Channel #15 + 71 + + + cpuss_interrupts_dw0_16 + CPUSS DataWire #0, Channel #16 + 72 + + + cpuss_interrupts_dw0_17 + CPUSS DataWire #0, Channel #17 + 73 + + + cpuss_interrupts_dw0_18 + CPUSS DataWire #0, Channel #18 + 74 + + + cpuss_interrupts_dw0_19 + CPUSS DataWire #0, Channel #19 + 75 + + + cpuss_interrupts_dw0_20 + CPUSS DataWire #0, Channel #20 + 76 + + + cpuss_interrupts_dw0_21 + CPUSS DataWire #0, Channel #21 + 77 + + + cpuss_interrupts_dw0_22 + CPUSS DataWire #0, Channel #22 + 78 + + + cpuss_interrupts_dw0_23 + CPUSS DataWire #0, Channel #23 + 79 + + + cpuss_interrupts_dw0_24 + CPUSS DataWire #0, Channel #24 + 80 + + + cpuss_interrupts_dw0_25 + CPUSS DataWire #0, Channel #25 + 81 + + + cpuss_interrupts_dw0_26 + CPUSS DataWire #0, Channel #26 + 82 + + + cpuss_interrupts_dw0_27 + CPUSS DataWire #0, Channel #27 + 83 + + + cpuss_interrupts_dw0_28 + CPUSS DataWire #0, Channel #28 + 84 + + + cpuss_interrupts_dw1_0 + CPUSS DataWire #1, Channel #0 + 85 + + + cpuss_interrupts_dw1_1 + CPUSS DataWire #1, Channel #1 + 86 + + + cpuss_interrupts_dw1_2 + CPUSS DataWire #1, Channel #2 + 87 + + + cpuss_interrupts_dw1_3 + CPUSS DataWire #1, Channel #3 + 88 + + + cpuss_interrupts_dw1_4 + CPUSS DataWire #1, Channel #4 + 89 + + + cpuss_interrupts_dw1_5 + CPUSS DataWire #1, Channel #5 + 90 + + + cpuss_interrupts_dw1_6 + CPUSS DataWire #1, Channel #6 + 91 + + + cpuss_interrupts_dw1_7 + CPUSS DataWire #1, Channel #7 + 92 + + + cpuss_interrupts_dw1_8 + CPUSS DataWire #1, Channel #8 + 93 + + + cpuss_interrupts_dw1_9 + CPUSS DataWire #1, Channel #9 + 94 + + + cpuss_interrupts_dw1_10 + CPUSS DataWire #1, Channel #10 + 95 + + + cpuss_interrupts_dw1_11 + CPUSS DataWire #1, Channel #11 + 96 + + + cpuss_interrupts_dw1_12 + CPUSS DataWire #1, Channel #12 + 97 + + + cpuss_interrupts_dw1_13 + CPUSS DataWire #1, Channel #13 + 98 + + + cpuss_interrupts_dw1_14 + CPUSS DataWire #1, Channel #14 + 99 + + + cpuss_interrupts_dw1_15 + CPUSS DataWire #1, Channel #15 + 100 + + + cpuss_interrupts_dw1_16 + CPUSS DataWire #1, Channel #16 + 101 + + + cpuss_interrupts_dw1_17 + CPUSS DataWire #1, Channel #17 + 102 + + + cpuss_interrupts_dw1_18 + CPUSS DataWire #1, Channel #18 + 103 + + + cpuss_interrupts_dw1_19 + CPUSS DataWire #1, Channel #19 + 104 + + + cpuss_interrupts_dw1_20 + CPUSS DataWire #1, Channel #20 + 105 + + + cpuss_interrupts_dw1_21 + CPUSS DataWire #1, Channel #21 + 106 + + + cpuss_interrupts_dw1_22 + CPUSS DataWire #1, Channel #22 + 107 + + + cpuss_interrupts_dw1_23 + CPUSS DataWire #1, Channel #23 + 108 + + + cpuss_interrupts_dw1_24 + CPUSS DataWire #1, Channel #24 + 109 + + + cpuss_interrupts_dw1_25 + CPUSS DataWire #1, Channel #25 + 110 + + + cpuss_interrupts_dw1_26 + CPUSS DataWire #1, Channel #26 + 111 + + + cpuss_interrupts_dw1_27 + CPUSS DataWire #1, Channel #27 + 112 + + + cpuss_interrupts_dw1_28 + CPUSS DataWire #1, Channel #28 + 113 + + + cpuss_interrupts_fault_0 + CPUSS Fault Structure Interrupt #0 + 114 + + + cpuss_interrupts_fault_1 + CPUSS Fault Structure Interrupt #1 + 115 + + + cpuss_interrupt_crypto + CRYPTO Accelerator Interrupt + 116 + + + cpuss_interrupt_fm + FLASH Macro Interrupt + 117 + + + cpuss_interrupts_cm4_fp + Floating Point operation fault + 118 + + + cpuss_interrupts_cm0_cti_0 + CM0+ CTI #0 + 119 + + + cpuss_interrupts_cm0_cti_1 + CM0+ CTI #1 + 120 + + + cpuss_interrupts_cm4_cti_0 + CM4 CTI #0 + 121 + + + cpuss_interrupts_cm4_cti_1 + CM4 CTI #1 + 122 + + + tcpwm_0_interrupts_0 + TCPWM #0, Counter #0 + 123 + + + tcpwm_0_interrupts_1 + TCPWM #0, Counter #1 + 124 + + + tcpwm_0_interrupts_2 + TCPWM #0, Counter #2 + 125 + + + tcpwm_0_interrupts_3 + TCPWM #0, Counter #3 + 126 + + + tcpwm_0_interrupts_256 + TCPWM #0, Counter #256 + 131 + + + tcpwm_0_interrupts_257 + TCPWM #0, Counter #257 + 132 + + + tcpwm_0_interrupts_258 + TCPWM #0, Counter #258 + 133 + + + tcpwm_0_interrupts_259 + TCPWM #0, Counter #259 + 134 + + + tcpwm_0_interrupts_260 + TCPWM #0, Counter #260 + 135 + + + tcpwm_0_interrupts_261 + TCPWM #0, Counter #261 + 136 + + + tcpwm_0_interrupts_262 + TCPWM #0, Counter #262 + 137 + + + tcpwm_0_interrupts_263 + TCPWM #0, Counter #263 + 138 + + + pass_interrupt_dacs + Consolidated interrrupt for all DACs + 146 + + + smif_interrupt + Serial Memory Interface interrupt + 160 + + + usb_interrupt_hi + USB Interrupt + 161 + + + usb_interrupt_med + USB Interrupt + 162 + + + usb_interrupt_lo + USB Interrupt + 163 + + + canfd_0_interrupt0 + Can #0, Consolidated interrupt #0 + 168 + + + canfd_0_interrupts0_0 + CAN #0, Interrupt #0, Channel #0 + 169 + + + canfd_0_interrupts1_0 + CAN #0, Interrupt #1, Channel #0 + 170 + + + cpuss_interrupts_dw1_29 + CPUSS DataWire #1, Channel #29 + 171 + + + cpuss_interrupts_dw1_30 + CPUSS DataWire #1, Channel #30 + 172 + + + cpuss_interrupts_dw1_31 + CPUSS DataWire #1, Channel #31 + 173 + + + cpuss_interrupts_dw0_29 + CPUSS DataWire #0, Channel #29 + 174 + + + + IDENTITY + Identity + 0x0 + 32 + read-only + 0x0 + 0x0 + + + P + This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. + [0:0] + read-only + + + NS + This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. + [1:1] + read-only + + + PC + This field specifies the protection context of the transfer that reads the register. + [7:4] + read-only + + + MS + This field specifies the bus master identifier of the transfer that reads the register. + [11:8] + read-only + + + + + CM4_STATUS + CM4 status + 0x4 + 32 + read-only + 0x13 + 0x13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + + + CM4_CLOCK_CTL + CM4 clock control + 0x8 + 32 + read-write + 0x0 + 0xFF00 + + + FAST_INT_DIV + Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM4_CTL + CM4 control + 0xC + 32 + read-write + 0x0 + 0x9F000000 + + + IOC_MASK + CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. + +Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. + +Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. + [24:24] + read-write + + + DZC_MASK + CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [25:25] + read-write + + + OFC_MASK + CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [26:26] + read-write + + + UFC_MASK + CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [27:27] + read-write + + + IXC_MASK + CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. + [28:28] + read-write + + + IDC_MASK + CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. + [31:31] + read-write + + + + + CM4_INT0_STATUS + CM4 interrupt 0 status + 0x100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 0. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT1_STATUS + CM4 interrupt 1 status + 0x104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT2_STATUS + CM4 interrupt 2 status + 0x108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT3_STATUS + CM4 interrupt 3 status + 0x10C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT4_STATUS + CM4 interrupt 4 status + 0x110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT5_STATUS + CM4 interrupt 5 status + 0x114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT6_STATUS + CM4 interrupt 6 status + 0x118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT7_STATUS + CM4 interrupt 7 status + 0x11C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_VECTOR_TABLE_BASE + CM4 vector table base + 0x200 + 32 + read-write + 0x0 + 0xFFFFFC00 + + + ADDR22 + Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. + +Note: the CM4 vector table is at an address that is a 1024 B multiple. + [31:10] + read-write + + + + + 4 + 4 + CM4_NMI_CTL[%s] + CM4 NMI control + 0x240 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + UDB_PWR_CTL + UDB power control + 0x300 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for UDBs + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RESET + See CM4_PWR_CTL + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + UDB_PWR_DELAY_CTL + UDB power control + 0x304 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CTL + CM0+ control + 0x1000 + 32 + read-write + 0xFA050002 + 0xFFFF0003 + + + SLV_STALL + Processor debug access control: +'0': Access. +'1': Stall access. + +This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. + [0:0] + read-write + + + ENABLED + Processor enable: +'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. +'1': Enabled. +Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). + +Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). + [1:1] + read-write + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM0_STATUS + CM0+ status + 0x1004 + 32 + read-only + 0x0 + 0x3 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + + + CM0_CLOCK_CTL + CM0+ clock control + 0x1008 + 32 + read-write + 0x0 + 0xFF00FF00 + + + SLOW_INT_DIV + Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + PERI_INT_DIV + Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + +Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. + [31:24] + read-write + + + + + CM0_INT0_STATUS + CM0+ interrupt 0 status + 0x1100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 0. + +Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). + +The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. + [9:0] + read-only + + + SYSTEM_INT_VALID + Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. + [31:31] + read-only + + + + + CM0_INT1_STATUS + CM0+ interrupt 1 status + 0x1104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT2_STATUS + CM0+ interrupt 2 status + 0x1108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT3_STATUS + CM0+ interrupt 3 status + 0x110C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT4_STATUS + CM0+ interrupt 4 status + 0x1110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT5_STATUS + CM0+ interrupt 5 status + 0x1114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT6_STATUS + CM0+ interrupt 6 status + 0x1118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT7_STATUS + CM0+ interrupt 7 status + 0x111C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_VECTOR_TABLE_BASE + CM0+ vector table base + 0x1120 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. + +Note: the CM0+ vector table is at an address that is a 256 B multiple. + [31:8] + read-write + + + + + 4 + 4 + CM0_NMI_CTL[%s] + CM0+ NMI control + 0x1140 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + CM4_PWR_CTL + CM4 power control + 0x1200 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Switch CM4 off +Power off, clock off, isolate, reset and no retain. + 0 + + + RESET + Reset CM4 +Clock off, no isolated, no retain and reset. + +Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. + 1 + + + RETAINED + Put CM4 in Retained mode +This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. +Power off, clock off, isolate, no reset and retain. + 2 + + + ENABLED + Switch CM4 on. +Power on, clock on, no isolate, no reset and no retain. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM4_PWR_DELAY_CTL + CM4 power control + 0x1204 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + RAM0_CTL0 + RAM 0 control + 0x1300 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_AUTO_CORRECT + HW ECC autocorrect functionality: +'0': Disabled. +'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. + [17:17] + read-write + + + ECC_INJ_EN + Enable error injection for system SRAM 0. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. + [18:18] + read-write + + + + + RAM0_STATUS + RAM 0 status + 0x1304 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. +'0': Write buffer NOT empty. +'1': Write buffer empty. + +Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). + [0:0] + read-only + + + + + 16 + 4 + RAM0_PWR_MACRO_CTL[%s] + RAM 0 power control + 0x1340 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + SRAM Power mode. + [1:0] + read-write + + + OFF + Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. + 0 + + + RSVD + undefined + 1 + + + RETAINED + Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. +The SRAM contents will be retained in DeepSleep system power mode. + 2 + + + ENABLED + Enable SRAM for regular operation. +The SRAM contents will be retained in DeepSleep system power mode. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + RAM1_CTL0 + RAM 1 control + 0x1380 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM1_STATUS + RAM 1 status + 0x1384 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM1_PWR_CTL + RAM 1 power control + 0x1388 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM2_CTL0 + RAM 2 control + 0x13A0 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM2_STATUS + RAM 2 status + 0x13A4 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM2_PWR_CTL + RAM 2 power control + 0x13A8 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM_PWR_DELAY_CTL + Power up delay used for all SRAM power domains + 0x13C0 + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + ROM_CTL + ROM control + 0x13C4 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + +Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + + + ECC_CTL + ECC control + 0x13C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. +This field needs to be written with the offset address within the memory, divided by 4. +For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. + [24:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + PRODUCT_ID + Product identifier and version (same as CoreSight RomTables) + 0x1400 + 32 + read-only + 0x0 + 0xFFF + + + FAMILY_ID + Family ID a.k.a. Partnumber a.k.a. Silicon ID + [11:0] + read-only + + + MAJOR_REV + Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) + [19:16] + read-only + + + MINOR_REV + Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) + [23:20] + read-only + + + + + DP_STATUS + Debug port status + 0x1410 + 32 + read-only + 0x4 + 0x7 + + + SWJ_CONNECTED + Specifies if the SWJ debug port is connected; i.e. debug host interface is active: +'0': Not connected/not active. +'1': Connected/active. + [0:0] + read-only + + + SWJ_DEBUG_EN + Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: +'0': Disabled. +'1': Enabled. + [1:1] + read-only + + + SWJ_JTAG_SEL + Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). +'0': SWD selected. +'1': JTAG selected. + [2:2] + read-only + + + + + AP_CTL + Access port control + 0x1414 + 32 + read-write + 0x0 + 0x70007 + + + CM0_ENABLE + Enables the CM0 AP interface: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + CM4_ENABLE + Enables the CM4 AP interface: +'0': Disabled. +'1': Enabled. + [1:1] + read-write + + + SYS_ENABLE + Enables the system AP interface: +'0': Disabled. +'1': Enabled. + [2:2] + read-write + + + CM0_DISABLE + Disables the CM0 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. + [16:16] + read-write + + + CM4_DISABLE + Disables the CM4 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. + [17:17] + read-write + + + SYS_DISABLE + Disables the system AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. + [18:18] + read-write + + + + + BUFF_CTL + Buffer control + 0x1500 + 32 + read-write + 0x1 + 0x1 + + + WRITE_BUFF + Specifies if write transfer can be buffered in the bus infrastructure bridges: +'0': Write transfers are not buffered, independent of the transfer's bufferable attribute. +'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. + [0:0] + read-write + + + + + SYSTICK_CTL + SysTick timer control + 0x1600 + 32 + read-write + 0x40000147 + 0xC3FFFFFF + + + TENMS + Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. + [23:0] + read-write + + + CLOCK_SOURCE + Specifies an external clock source: +'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). +'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. +o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. +'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). + +Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. +Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. + [25:24] + read-write + + + SKEW + Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: +'0': Precise. +'1': Imprecise. + [30:30] + read-write + + + NOREF + Specifies if an external clock source is provided: +'0': An external clock source is provided. +'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. + [31:31] + read-write + + + + + MBIST_STAT + Memory BIST status + 0x1704 + 32 + read-only + 0x0 + 0x3 + + + SFP_READY + Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. + [0:0] + read-only + + + SFP_FAIL + Report status of the BIST run, only valid if SFP_READY=1 + [1:1] + read-only + + + + + CAL_SUP_SET + Calibration support set and read + 0x1800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read without side effect, write 1 to set + [31:0] + read-write + + + + + CAL_SUP_CLR + Calibration support clear and reset + 0x1804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read side effect: when read all bits are cleared, write 1 to clear a specific bit +Note: no exception for the debug host, it also causes the read side effect + [31:0] + read-write + + + + + CM0_PC_CTL + CM0+ protection context control + 0x2000 + 32 + read-write + 0x0 + 0xF + + + VALID + Valid fields for the protection context handler CM0_PCi_HANDLER registers: +Bit 0: Valid field for CM0_PC0_HANDLER. +Bit 1: Valid field for CM0_PC1_HANDLER. +Bit 2: Valid field for CM0_PC2_HANDLER. +Bit 3: Valid field for CM0_PC3_HANDLER. + [3:0] + read-write + + + + + CM0_PC0_HANDLER + CM0+ protection context 0 handler + 0x2040 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. + [31:0] + read-write + + + + + CM0_PC1_HANDLER + CM0+ protection context 1 handler + 0x2044 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 1 handler. + [31:0] + read-write + + + + + CM0_PC2_HANDLER + CM0+ protection context 2 handler + 0x2048 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 2 handler. + [31:0] + read-write + + + + + CM0_PC3_HANDLER + CM0+ protection context 3 handler + 0x204C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 3 handler. + [31:0] + read-write + + + + + PROTECTION + Protection status + 0x20C4 + 32 + read-write + 0x0 + 0x7 + + + STATE + Protection state: +'0': UNKNOWN. +'1': VIRGIN. +'2': NORMAL. +'3': SECURE. +'4': DEAD. + +The following state transitions are allowed (and enforced by HW): +- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD +- NORMAL => DEAD +- SECURE => DEAD +An attempt to make a NOT allowed state transition will NOT affect this register field. + [2:0] + read-write + + + + + TRIM_ROM_CTL + ROM trim control + 0x2100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + TRIM_RAM_CTL + RAM trim control + 0x2104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + 1023 + 4 + CM0_SYSTEM_INT_CTL[%s] + CM0+ system interrupt control + 0x8000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. + +Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. + [2:0] + read-write + + + CPU_INT_VALID + Interrupt enable: +'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. +'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. + +Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. + [31:31] + read-write + + + + + 1023 + 4 + CM4_SYSTEM_INT_CTL[%s] + CM4 system interrupt control + 0xA000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + N/A + [2:0] + read-write + + + CPU_INT_VALID + N/A + [31:31] + read-write + + + + + + + FAULT + Fault structures + 0x40210000 + + 0 + 65536 + registers + + + + 2 + 256 + STRUCT[%s] + Fault structure + 0x00000000 + + CTL + Fault control + 0x0 + 32 + read-write + 0x0 + 0x7 + + + TR_EN + Trigger output enable: +'0': Disabled. The trigger output 'tr_fault' is '0'. +'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). + [0:0] + read-write + + + OUT_EN + IO output signal enable: +'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. +'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. + [1:1] + read-write + + + RESET_REQ_EN + Reset request enable: +'0': Disabled. +'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). + +The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. + [2:2] + read-write + + + + + STATUS + Fault status + 0xC + 32 + read-write + 0x0 + 0x80000000 + + + IDX + The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. + +Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. + [6:0] + read-write + + + VALID + Valid indication: +'0': Invalid. +'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. + +Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. + +An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: +- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. + +Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) + [31:31] + read-write + + + + + 4 + 4 + DATA[%s] + Fault data + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + Captured fault source data. + +Note: the DATA registers can only be written when STATUS.VALID is '0'. + +Note: the fault source index STATUS.IDX specifies the format of the DATA registers. + [31:0] + read-write + + + + + PENDING0 + Fault pending 0 + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: CM0 MPU. +Bit 1: CRYPTO MPU. +Bit 2: DW 0 MPU. +Bit 3: DW 1 MPU. +Bit 4: DMA controller MPU. +... +Bit 15: DAP MPU. +Bit 16: CM4 system bus MPU. +Bit 17: CM4 code bus MPU (for non FLASH controller accesses). +Bit 18: CM4 code bus MPU (for FLASH controller accesses). + [31:0] + read-only + + + + + PENDING1 + Fault pending 1 + 0x44 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: Peripheral group 0 PPU. +Bit 1: Peripheral group 1 PPU. +Bit 2: Peripheral group 2 PPU. +Bit 3: Peripheral group 3 PPU. +Bit 4: Peripheral group 4 PPU. +Bit 5: Peripheral group 5 PPU. +Bit 6: Peripheral group 6 PPU. +Bit 7: Peripheral group 7 PPU. +... +Bit 15: Peripheral group 15 PPU. + +Bit 16 - 31: See STATUS register. + [31:0] + read-only + + + + + PENDING2 + Fault pending 2 + 0x48 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0 - 31: See STATUS register. + [31:0] + read-only + + + + + MASK0 + Fault mask 0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 31 to 0. + [31:0] + read-write + + + + + MASK1 + Fault mask 1 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 63 to 32. + [31:0] + read-write + + + + + MASK2 + Fault mask 2 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 95 to 64. + [31:0] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1 + + + FAULT + This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: +- STATUS.VALID is set to '1'. +- STATUS.IDX specifies the fault source index. +- DATA0 through DATA3 captures the fault source data. + +SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1 + + + FAULT + SW writes a '1' to this field to set the corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1 + + + FAULT + Mask bit for corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1 + + + FAULT + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + IPC + IPC + 0x40220000 + + 0 + 65536 + registers + + + + 16 + 32 + STRUCT[%s] + IPC structure + 0x00000000 + + ACQUIRE + IPC acquire + 0x0 + 32 + read-only + 0x0 + 0x80000000 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the access that successfully acquired the lock. + [0:0] + read-only + + + NS + Secure/non-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the access that successfully acquired the lock. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + SUCCESS + Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): +'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. +'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. + +Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). + [31:31] + read-only + + + + + RELEASE + IPC release + 0x4 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_RELEASE + Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. + +SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + NOTIFY + IPC notification + 0x8 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_NOTIFY + This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. + +SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + DATA0 + IPC data 0 + 0xC + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + DATA1 + IPC data 1 + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + LOCK_STATUS + IPC lock status + 0x1C + 32 + read-only + 0x0 + 0x80000000 + + + P + This field specifies the user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + This field specifies the secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + ACQUIRED + Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. + [31:31] + read-only + + + + + + 16 + 32 + INTR_STRUCT[%s] + IPC interrupt structure + 0x00001000 + + INTR + Interrupt + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [15:0] + read-write + + + NOTIFY + These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [31:16] + read-write + + + + + INTR_SET + Interrupt set + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + SW writes a '1' to this field to set the corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASK + Interrupt mask + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + Mask bit for corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RELEASE + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + NOTIFY + Logical and of corresponding INTR and INTR_MASK fields. + [31:16] + read-only + + + + + + + + PROT + Protection + 0x40230000 + + 0 + 65536 + registers + + + + SMPU + SMPU + 0x00000000 + + MS0_CTL + Master 0 protection context control + 0x0 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + Privileged setting ('0': user mode; '1': privileged mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. +The default/reset field value provides privileged mode access capabilities. + [0:0] + read-write + + + NS + Security setting ('0': secure mode; '1': non-secure mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. +Note that the default/reset field value provides non-secure mode access capabilities to all masters. + [1:1] + read-write + + + PRIO + Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). + +Notes: +The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). +The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). +Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. + [9:8] + read-write + + + PC_MASK_0 + Protection context mask for protection context '0'. This field is a constant '0': +- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. + [16:16] + read-only + + + PC_MASK_15_TO_1 + Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': +- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. +- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. + +Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). + [31:17] + read-write + + + + + MS1_CTL + Master 1 protection context control + 0x4 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS2_CTL + Master 2 protection context control + 0x8 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS3_CTL + Master 3 protection context control + 0xC + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS4_CTL + Master 4 protection context control + 0x10 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS5_CTL + Master 5 protection context control + 0x14 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS6_CTL + Master 6 protection context control + 0x18 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS7_CTL + Master 7 protection context control + 0x1C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS8_CTL + Master 8 protection context control + 0x20 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS9_CTL + Master 9 protection context control + 0x24 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS10_CTL + Master 10 protection context control + 0x28 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS11_CTL + Master 11 protection context control + 0x2C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS12_CTL + Master 12 protection context control + 0x30 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS13_CTL + Master 13 protection context control + 0x34 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS14_CTL + Master 14 protection context control + 0x38 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS15_CTL + Master 15 protection context control + 0x3C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + 16 + 64 + SMPU_STRUCT[%s] + SMPU structure + 0x00002000 + + ADDR0 + SMPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + SMPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x100 + 0x80000100 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + SMPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + SMPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'7': 256 B region (8 32 B subregions) + +Note: this field is read-only. + [28:24] + read-only + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + [31:31] + read-write + + + + + + + 16 + 1024 + MPU[%s] + MPU + 0x00004000 + + MS_CTL + Master control + 0x0 + 32 + read-write + 0x0 + 0xF000F + + + PC + Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). + +The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: +* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: + IF (the new PC is the same as MS_CTL.PC) + PC is not affected; PC_SAVED is not affected. + ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) + An AHB-Lite bus error is generated for the exception handler fetch; + PC is not affected; PC_SAVED is not affected. + ELSE + PC = 'new PC'; PC_SAVED = PC (push operation). +* On entry of any other exception/interrupt handler: + PC = PC_SAVED; PC_SAVED is not affected (pop operation). + +Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. + +Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. + [3:0] + read-write + + + PC_SAVED + Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. + +Note: this field is ONLY used by the CM0+. + [19:16] + read-write + + + + + 127 + 4 + MS_CTL_READ_MIR[%s] + Master control read mirror + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + PC + Read-only mirror of MS_CTL.PC + [3:0] + read-only + + + PC_SAVED + Read-only mirror of MS_CTL.PC_SAVED + [19:16] + read-only + + + + + 8 + 32 + MPU_STRUCT[%s] + MPU structure + 0x00000200 + + ADDR + MPU region address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT + MPU region attrributes + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + + + + + FLASHC + Flash controller + 0x40240000 + + 0 + 65536 + registers + + + + FLASH_CTL + Control + 0x0 + 32 + read-write + 0x110000 + 0x77330F + + + MAIN_WS + FLASH macro main interface wait states: +'0': 0 wait states. +... +'15': 15 wait states + [3:0] + read-write + + + MAIN_MAP + Specifies mapping of FLASH macro main array. +0: Mapping A. +1: Mapping B. + +This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). + [8:8] + read-write + + + WORK_MAP + Specifies mapping of FLASH macro work array. +0: Mapping A. +1: Mapping B. + +This field is only used when WORK_BANK_MODE is '1' (dual bank mode). + [9:9] + read-write + + + MAIN_BANK_MODE + Specifies bank mode of FLASH macro main array. +0: Single bank mode. +1: Dual bank mode. + [12:12] + read-write + + + WORK_BANK_MODE + Specifies bank mode of FLASH macro work array. +0: Single bank mode. +1: Dual bank mode. + [13:13] + read-write + + + MAIN_ECC_EN + Enable ECC checking for FLASH main interface: +0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [16:16] + read-write + + + MAIN_ECC_INJ_EN + Enable error injection for FLASH main interface. +When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [17:17] + read-write + + + MAIN_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro main interface internal error. +- FLASH macro main interface non-recoverable ECC error. +- FLASH macro main interface recoverable ECC error. +- FLASH macro main interface memory hole error. + [18:18] + read-write + + + WORK_ECC_EN + Enable ECC checking for FLASH work interface: +0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [20:20] + read-write + + + WORK_ECC_INJ_EN + Enable error injection for FLASH work interface. +When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [21:21] + read-write + + + WORK_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro work interface internal error. +- FLASH macro work interface non-recoverable ECC error. +- FLASH macro work interface recoverable ECC error. +- FLASH macro work interface memory hole error. + [22:22] + read-write + + + + + FLASH_PWR_CTL + Flash power control + 0x4 + 32 + read-write + 0x3 + 0x3 + + + ENABLE + Controls 'enable' pin of the Flash memory. + [0:0] + read-write + + + ENABLE_HV + Controls 'enable_hv' pin of the Flash memory. + [1:1] + read-write + + + + + FLASH_CMD + Command + 0x8 + 32 + read-write + 0x0 + 0x3 + + + INV + Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. + [0:0] + read-write + + + BUFF_INV + Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. + +Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. + [1:1] + read-write + + + + + ECC_CTL + ECC control + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. +- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). +- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). + [23:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. +- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. +- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. +- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. + [31:24] + read-write + + + + + FM_SRAM_ECC_CTL0 + eCT Flash SRAM ECC control 0 + 0x2B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ECC_INJ_DATA + 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. + [31:0] + read-write + + + + + FM_SRAM_ECC_CTL1 + eCT Flash SRAM ECC control 1 + 0x2B4 + 32 + read-write + 0x0 + 0x7F + + + ECC_INJ_PARITY + 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. + [6:0] + read-write + + + + + FM_SRAM_ECC_CTL2 + eCT Flash SRAM ECC control 2 + 0x2B8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CORRECTED_DATA + 32-bit corrected data output of the ECC syndrome logic. + [31:0] + read-only + + + + + FM_SRAM_ECC_CTL3 + eCT Flash SRAM ECC control 3 + 0x2BC + 32 + read-write + 0x1 + 0x111 + + + ECC_ENABLE + ECC generation/check enable for eCT Flash SRAM memory. + [0:0] + read-write + + + ECC_INJ_EN + eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: +1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. +2. Set the ECC_INJ_EN bit to '1'. +3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. +4. Check the corrected data in FM_SRAM_ECC_CTL2. +5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if +corrupted data was written in step 1). +6. If not finished, start over at 1 with different data. + [4:4] + read-write + + + ECC_TEST_FAIL + Status of ECC test. +1 : ECC test failed because eCT Flash macro is busy and using the SRAM. +0: ECC was performed. + [8:8] + read-only + + + + + CM0_CA_CTL0 + CM0+ cache control + 0x400 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + Enable ECC checking for cache accesses: +0: Disabled. +1: Enabled. + [0:0] + read-write + + + RAM_ECC_INJ_EN + Enable error injection for cache. +When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. + [1:1] + read-write + + + WAY + Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. + [26:24] + read-write + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + CA_EN + Cache enable: +0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). +1: Enabled. + [31:31] + read-write + + + + + CM0_CA_CTL1 + CM0+ cache control + 0x404 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM0 cache. +The following sequnece should be followed for turning OFF/ON the cache SRAM. +Turn OFF sequence: +a) Write CM0_CA_CTL0 to disable cache. +b) Write CM0_CA_CTL1 to turn OFF cache SRAM. +Turn ON sequence: +a) Write CM0_CA_CTL1 to turn ON cache SRAM. +b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. +c) Write CM0_CA_CTL0 to enable cache. + [1:0] + read-write + + + OFF + Power OFF the CM0 cache SRAM. + 0 + + + RSVD + Undefined + 1 + + + RETAINED + Put CM0 cache SRAM in retained mode. + 2 + + + ENABLED + Enable/Turn ON the CM0 cache SRAM. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_CA_CTL2 + CM0+ cache control + 0x408 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CA_STATUS0 + CM0+ cache status 0 + 0x440 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS1 + CM0+ cache status 1 + 0x444 + 32 + read-only + 0x0 + 0x0 + + + TAG + Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS2 + CM0+ cache status 2 + 0x448 + 32 + read-only + 0x0 + 0x0 + + + LRU + Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): +Bit 5: 0_LRU_1: way 0 less recently used than way 1. +Bit 4: 0_LRU_2. +Bit 3: 0_LRU_3. +Bit 2: 1_LRU_2. +Bit 1: 1_LRU_3. +Bit 0: 2_LRU_3. + [5:0] + read-only + + + + + CM0_STATUS + CM0+ interface status + 0x460 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CM4_CA_CTL0 + CM4 cache control + 0x480 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + See CM0_CA_CTL. + [0:0] + read-write + + + RAM_ECC_INJ_EN + See CM0_CA_CTL. + [1:1] + read-write + + + WAY + See CM0_CA_CTL. + [17:16] + read-write + + + SET_ADDR + See CM0_CA_CTL. + [26:24] + read-write + + + PREF_EN + See CM0_CA_CTL. + [30:30] + read-write + + + CA_EN + See CM0_CA_CTL. + [31:31] + read-write + + + + + CM4_CA_CTL1 + CM4 cache control + 0x484 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. + [1:0] + read-write + + + OFF + See CM0_CA_CTL1 + 0 + + + RSVD + Undefined + 1 + + + RETAINED + See CM0_CA_CTL1 + 2 + + + ENABLED + See CM0_CA_CTL1 + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM4_CA_CTL2 + CM4 cache control + 0x488 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM4_CA_STATUS0 + CM4 cache status 0 + 0x4C0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + See CM0_CA_STATUS0. + [31:0] + read-only + + + + + CM4_CA_STATUS1 + CM4 cache status 1 + 0x4C4 + 32 + read-only + 0x0 + 0x0 + + + TAG + See CM0_CA_STATUS1. + [31:0] + read-only + + + + + CM4_CA_STATUS2 + CM4 cache status 2 + 0x4C8 + 32 + read-only + 0x0 + 0x0 + + + LRU + See CM0_CA_STATUS2. + [5:0] + read-only + + + + + CM4_STATUS + CM4 interface status + 0x4E0 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM4_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CRYPTO_BUFF_CTL + Cryptography buffer control + 0x500 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. +A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. +For eCT work Flash, prefetch will not be done. + [30:30] + read-write + + + + + DW0_BUFF_CTL + Datawire 0 buffer control + 0x580 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DW1_BUFF_CTL + Datawire 1 buffer control + 0x600 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DMAC_BUFF_CTL + DMA controller buffer control + 0x680 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS0_BUFF_CTL + External master 0 buffer control + 0x700 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS1_BUFF_CTL + External master 1 buffer control + 0x780 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + FM_CTL + Flash Macro Registers + 0x0000F000 + + FM_CTL + Flash macro control + 0x0 + 32 + read-write + 0x0 + 0x37F030F + + + FM_MODE + Requires (IF_SEL|WR_EN)=1 +Flash macro mode selection + [3:0] + read-write + + + FM_SEQ + Requires (IF_SEL|WR_EN)=1 +Flash macro sequence selection + [9:8] + read-write + + + DAA_MUX_SEL + Direct memory cell access address. + [22:16] + read-write + + + IF_SEL + Interface selection. Specifies the interface that is used for flash memory read operations: +0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. +1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. +Note: IF_SEL and WR_EN cannot be changed at the same time + [24:24] + read-write + + + WR_EN + 0: normal mode +1: Fm Write Enable +Note: IF_SEL and WR_EN cannot be changed at the same time + [25:25] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x1800 + 0xFFFFFFFF + + + TIMER_ENABLED + This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires +0: timer not running +1: Timer is enabled and not expired yet + [0:0] + read-only + + + HV_REGS_ISOLATED + Indicates the isolation status at HV trim and redundancy registers inputs +0: Not isolated, writing permitted +1: isolated writing disabled + [1:1] + read-only + + + ILLEGAL_HVOP + Indicates a bulk, sector erase, program has been requested when axa=1 +0: no error +1: illegal HV operation error + [2:2] + read-only + + + TURBO_N + After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. +Used in the testchip boot only as an 'FM READY' flag. +0: turbo mode +1: normal mode + [3:3] + read-only + + + WR_EN_MON + FM_CTL.WR_EN bit after being synchronized in clk_r domain + [4:4] + read-only + + + IF_SEL_MON + FM_CTL.IF_SEL bit after being synchronized in clk_r domain + [5:5] + read-only + + + TIMER_STATUS + The actual timer state sync-ed in clk_c domain: +0: timer is not running: +1: timer is running; + [6:6] + read-only + + + R_GRANT_DELAY_STATUS + 0: R_GRANT_DELAY timer is not running +1: R_GRANT_DELAY timer is running + [7:7] + read-only + + + FM_BUSY + 0': FM not busy +1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. + [8:8] + read-only + + + FM_READY + 0: FM not ready +1: FM ready + [9:9] + read-only + + + POS_PUMP_VLO + POS pump VLO + [10:10] + read-only + + + NEG_PUMP_VHI + NEG pump VHI + [11:11] + read-only + + + RWW + FM Type (Read While Write or Not Read While Write): +0: Non RWW FM Type +1: RWW FM Type + [12:12] + read-only + + + MAX_DOUT_WIDTH + Internal memory core max data out size +(number of data out bits per column): +0: x128 bits +1: x256 bits + [13:13] + read-only + + + SECTOR0_SR + 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. +1: Sector 0 contains special rows + [14:14] + read-only + + + RESET_MM + Test_only, internal node: mpcon reset_mm + [15:15] + read-only + + + ROW_ODD + Test_only, internal node: mpcon row_odd + [16:16] + read-only + + + ROW_EVEN + Test_only, internal node: mpcon row_even + [17:17] + read-only + + + HVOP_SUB_SECTOR_N + Test_only, internal node: mpcon bk_subb + [18:18] + read-only + + + HVOP_SECTOR + Test_only, internal node: mpcon bk_sec + [19:19] + read-only + + + HVOP_BULK_ALL + Test_only, internal node: mpcon bk_all + [20:20] + read-only + + + CBUS_RA_MATCH + Test_only, internal node: mpcon ra match + [21:21] + read-only + + + CBUS_RED_ROW_EN + Test_only, internal node: mpcon red_row_en + [22:22] + read-only + + + RQ_ERROR + Test_only, internal node: rq_error sync-de in clk_c domain + [23:23] + read-only + + + PUMP_PDAC + Test_only, internal node: regif pdac outputs to pos pump + [27:24] + read-only + + + PUMP_NDAC + Test_only, internal node: regif ndac outputs to pos pump + [31:28] + read-only + + + + + FM_ADDR + Flash macro address + 0x8 + 32 + read-write + 0x0 + 0x1FFFFFF + + + RA + Row address. + [15:0] + read-write + + + BA + Bank address. + [23:16] + read-write + + + AXA + Auxiliary address field: +0: regular flash memory. +1: supervisory flash memory. + [24:24] + read-write + + + + + BOOKMARK + Bookmark register - keeps the current FW HV seq + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BOOKMARK + Used by FW. Keeps the Current HV cycle sequence + [31:0] + read-write + + + + + GEOMETRY + Regular flash geometry + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1): +0: 1 row +1: 2 rows +2: 3 rows +... +'65535': 65536 rows + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1): +0: 1 bank +1: 2 banks +... +'255': 256 banks + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +3: 128 Bytes + +The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2): +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +15: 32768 Bytes + +The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. + [31:28] + read-only + + + + + GEOMETRY_SUPERVISORY + Supervisory flash geometry + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. + [31:28] + read-only + + + + + ANA_CTL0 + Analog control 0 + 0x18 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + MDAC + Trimming of the output margin Voltage as a function of Vpos and Vneg. + [7:0] + read-write + + + CSLDAC + Trimming of common source line DAC. + [10:8] + read-write + + + FLIP_AMUXBUS_AB + Flips amuxbusa and amuxbusb +0: amuxbusa, amuxbusb +1: amuxbusb, amuxbusb + [11:11] + read-write + + + NDAC_MIN + NDAC staircase min value + [15:12] + read-write + + + PDAC_MIN + PDAC staircase min value + [19:16] + read-write + + + SCALE_PRG_SEQ01 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [21:20] + read-write + + + SCALE_PRG_SEQ12 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [23:22] + read-write + + + SCALE_PRG_SEQ23 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [25:24] + read-write + + + SCALE_SEQ30 + PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [27:26] + read-write + + + SCALE_PRG_PEON + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [29:28] + read-write + + + SCALE_PRG_PEOFF + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [31:30] + read-write + + + + + ANA_CTL1 + Analog control 1 + 0x1C + 32 + read-write + 0xD32FAFA + 0xFFFFFFFF + + + NDAC_MAX + Ndac Max Value.Trimming of negative pump output Voltage. + [3:0] + read-write + + + NDAC_STEP + Ndac step increment + [7:4] + read-write + + + PDAC_MAX + Pdac Max Value.Trimming of positive pump output Voltage: + [11:8] + read-write + + + PDAC_STEP + Pdac step increment + [15:12] + read-write + + + NPDAC_STEP_TIME + Ndac/Pdac step duration: (1uS .. 255uS) * 8 +When = 0 N/PDAC_MAX control the pumps + [23:16] + read-write + + + NPDAC_ZERO_TIME + Ndac/Pdac LO duration: (1uS .. 255uS) * 8 +When 0, N/PDAC don't return to 0 + [31:24] + read-write + + + + + WAIT_CTL + Wait State control + 0x28 + 32 + read-write + 0x30B09 + 0x3F070F0F + + + WAIT_FM_MEM_RD + Number of C interface wait cycles (on 'clk_c') for a read from the memory + [3:0] + read-write + + + WAIT_FM_HV_RD + Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. +Common for reading HV Page Latches and the DATA_COMP_RESULT bit + [11:8] + read-write + + + WAIT_FM_HV_WR + Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. + [18:16] + read-write + + + FM_RWW_MODE + 00: Full CBUS MODE +01: RWW +10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration + [25:24] + read-write + + + LV_SPARE_1 + Spare register + [26:26] + read-write + + + DRMM + 0: Normal +1: Test mode to enable Margin mode for 2 rows at a time + [27:27] + read-write + + + MBA + 0: Normal +1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). + [28:28] + read-write + + + PL_SOFT_SET_EN + Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API + [29:29] + read-write + + + + + TIMER_CLK_CTL + Timer prescaler (clk_t to timer clock frequency divider) + 0x34 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TIMER_CLOCK_FREQ + Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. +Equal to the frequency in MHz of the timer clock 'clk_t'. +Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' +Max clk_t frequency = 100MHz. +This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table + [7:0] + read-write + + + RGRANT_DELAY_PRG_PEON + PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_PRG_PEOFF + PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_PRG_SEQ01 + PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + TIMER_CTL + Timer control + 0x38 + 32 + read-write + 0x4000001 + 0xE700FFFF + + + PERIOD + Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. + [14:0] + read-write + + + SCALE + Timer tick scale: +0: 1 microsecond. +1: 100 microseconds. + [15:15] + read-write + + + AUTO_SEQUENCE + 1': Starts1 the HV automatic sequencing +Cleared by HW + [24:24] + read-write + + + PRE_PROG + 1 during pre-program operation + [25:25] + read-write + + + PRE_PROG_CSL + 0: CSL lines driven by CSL_DAC +1: CSL lines driven by VNEG_G + [26:26] + read-write + + + PUMP_EN + Pump enable: +0: disabled +1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). +SW sets this field to '1' to generate a single PE pulse. +HW clears this field when timer is expired. + [29:29] + read-write + + + ACLK_EN + ACLK enable (generates a single cycle pulse for the FM): +0: disabled +1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. + [30:30] + read-write + + + TIMER_EN + Timer enable: +0: disabled +1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. + [31:31] + read-write + + + + + ACLK_CTL + MPCON clock + 0x3C + 32 + write-only + 0x0 + 0x1 + + + ACLK_GEN + A write to this register generates the clock pulse for HV control registers (mpcon outputs) + [0:0] + write-only + + + + + INTR + Interrupt + 0x40 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x44 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x48 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x4C + 32 + read-only + 0x0 + 0x1 + + + TIMER_EXPIRED + Logical and of corresponding request and mask fields. + [0:0] + read-only + + + + + CAL_CTL0 + Cal control BG LO trim bits + 0x50 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_LO_HV + LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_LO_HV + LO Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control + [15:13] + read-write + + + ICREF_TC_TRIM_LO_HV + LO Bandgap Current Temperature Compensation trim control + [18:16] + read-write + + + IPREF_TRIMA_LO_HV + Adds 100-150nA boost on IPREF_LO + [19:19] + read-write + + + + + CAL_CTL1 + Cal control BG HI trim bits + 0x54 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_HI_HV + HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_HI_HV + HI Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [15:13] + read-write + + + ICREF_TC_TRIM_HI_HV + HI Bandgap Current Temperature Compensation trim control. + [18:16] + read-write + + + IPREF_TRIMA_HI_HV + Adds 100-150nA boost on IPREF_HI + [19:19] + read-write + + + + + CAL_CTL2 + Cal control BG LO&HI trim bits + 0x58 + 32 + read-write + 0x7BE10 + 0xFFFFF + + + ICREF_TRIM_LO_HV + LO Bandgap Current trim control. + [4:0] + read-write + + + ICREF_TRIM_HI_HV + HI Bandgap Current trim control. + [9:5] + read-write + + + IPREF_TRIM_LO_HV + LO Bandgap IPTAT trim control. + [14:10] + read-write + + + IPREF_TRIM_HI_HV + HI Bandgap IPTAT trim control. + [19:15] + read-write + + + + + CAL_CTL3 + Cal control osc trim bits, idac, sdac, itim + 0x5C + 32 + read-write + 0x2004 + 0xFFFFF + + + OSC_TRIM_HV + Flash macro pump clock trim control. + [3:0] + read-write + + + OSC_RANGE_TRIM_HV + 0: Oscillator High Frequency Range +1: Oscillator Low Frequency range + [4:4] + read-write + + + VPROT_ACT_HV + Forces VPROT in active mode all the time + [5:5] + read-write + + + IPREF_TC_HV + 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA +1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA + [6:6] + read-write + + + VREF_SEL_HV + Voltage reference: +0: internal bandgap reference +1: external voltage reference + [7:7] + read-write + + + IREF_SEL_HV + Current reference: +0: internal current reference +1: external current reference + [8:8] + read-write + + + REG_ACT_HV + 0: VBST regulator will operate in active/standby mode based on control signal. +1: Forces the VBST regulator in active mode all the time + [9:9] + read-write + + + FDIV_TRIM_HV + FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. +Following are the clock frequencies seen by doubler +00: F = 1MHz +01: F = 0.5MHz +10: F = 2MHz +11: F = 4MHz + [11:10] + read-write + + + VDDHI_HV + 0: vdd < 2.3V +1: vdd >= 2.3V +'0' setting can used for vdd > 2.3V also, but with a current penalty. + [12:12] + read-write + + + TURBO_PULSEW_HV + Turbo pulse width trim (Typical) +00: 40 us +01: 20 us +10: 15 us +11: 8 us + [14:13] + read-write + + + BGLO_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable LO Bandgap + [15:15] + read-write + + + BGHI_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable HI Bandgap +When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active + [16:16] + read-write + + + CL_ISO_DIS_HV + 0: The internal logic controls the CL isolation +1: Forces CL bypass + [17:17] + read-write + + + R_GRANT_EN_HV + 0: r_grant handshake disabled, r_grant always 1. +1: r_grand handshake enabled + [18:18] + read-write + + + LP_ULP_SW_HV + LP<-->ULP switch for trim signals: +0: LP +1: ULP + [19:19] + read-write + + + + + CAL_CTL4 + Cal Control Vlim, SA, fdiv, reg_act + 0x60 + 32 + read-write + 0x12AE0 + 0xFFFFF + + + VLIM_TRIM_ULP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_ULP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_ULP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_ULP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_ULP_HV + 00: Default : delay 1ns +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_ULP_HV + N/A + [15:15] + read-write + + + READY_RESTART_N_HV + Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. + [16:16] + read-write + + + VBST_S_DIS_HV + 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. +1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. + [17:17] + read-write + + + AUTO_HVPULSE_HV + 0: HV Pulse controlled by FW +1: HV Pulse controlled by Hardware + [18:18] + read-write + + + UGB_EN_HV + UGB enable in TM control + [19:19] + read-write + + + + + CAL_CTL5 + Cal control + 0x64 + 32 + read-write + 0x2AE0 + 0xFFFFF + + + VLIM_TRIM_LP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_LP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_LP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_LP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_LP_HV + 00: Delayed by 1us +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_LP_HV + N/A + [15:15] + read-write + + + SPARE52_HV + N/A + [17:16] + read-write + + + AMUX_SEL_HV + Amux Select in AMUX_UGB +00: Bypass UGB for both amuxbusa and amuxbusb +01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. +10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. +11: UGB Calibrate mode + [19:18] + read-write + + + + + CAL_CTL6 + SA trim LP/ULP + 0x68 + 32 + read-write + 0x36F7F + 0xFFFFF + + + SA_CTL_TRIM_T1_ULP_HV + clk_trk delay + [0:0] + read-write + + + SA_CTL_TRIM_T4_ULP_HV + SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) + [3:1] + read-write + + + SA_CTL_TRIM_T5_ULP_HV + SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) + [6:4] + read-write + + + SA_CTL_TRIM_T6_ULP_HV + SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) + [8:7] + read-write + + + SA_CTL_TRIM_T8_ULP_HV + saen3 pulse width trim (Current trim) + [9:9] + read-write + + + SA_CTL_TRIM_T1_LP_HV + clk_trk delay + [10:10] + read-write + + + SA_CTL_TRIM_T4_LP_HV + SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) + [13:11] + read-write + + + SA_CTL_TRIM_T5_LP_HV + SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) + [16:14] + read-write + + + SA_CTL_TRIM_T6_LP_HV + SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) + [18:17] + read-write + + + SA_CTL_TRIM_T8_LP_HV + saen3 pulse width trim (Current trim) + [19:19] + read-write + + + + + CAL_CTL7 + Cal control + 0x6C + 32 + read-write + 0x0 + 0xFFFFF + + + ERSX8_CLK_SEL_HV + Clock frequency into the ersx8 shift register block +00: Oscillator clock +01: Oscillator clock / 2 +10: Oscillator clock / 4 +11: Oscillator clock + [1:0] + read-write + + + FM_ACTIVE_HV + 0: Normal operation +1: Forces FM SYS in active mode + [2:2] + read-write + + + TURBO_EXT_HV + 0: Normal operation +1: Uses external turbo pulse + [3:3] + read-write + + + NPDAC_HWCTL_DIS_HV + 0': ndac, pdac staircase hardware controlled +1: ndac, pdac staircase disabled. Enables FW control. + [4:4] + read-write + + + FM_READY_DIS_HV + 0': fm ready is enabled +1: fm ready is disabled (fm_ready is always '1') + [5:5] + read-write + + + ERSX8_EN_ALL_HV + 0': Staggered turn on/off of GWL +1: GWL are turned on/off at the same time (old FM legacy) + [6:6] + read-write + + + DISABLE_LOAD_ONCE_HV + 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. +1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. + [7:7] + read-write + + + SPARE7_HV + N/A + [9:8] + read-write + + + SPARE7_ULP_HV + N/A + [14:10] + read-write + + + SPARE7_LP_HV + N/A + [19:15] + read-write + + + + + RED_CTL01 + Redundancy Control normal sectors 0,1 + 0x80 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_0 + Bad Row Pair Address for Sector 0 + [7:0] + read-write + + + RED_EN_0 + 1: Redundancy Enable for Sector 0 + [8:8] + read-write + + + RED_ADDR_1 + Bad Row Pair Address for Sector 1 + [23:16] + read-write + + + RED_EN_1 + 1: Redundancy Enable for Sector 1 + [24:24] + read-write + + + + + RED_CTL23 + Redundancy Control normal sectors 2,3 + 0x84 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_2 + Bad Row Pair Address for Sector 2 + [7:0] + read-write + + + RED_EN_2 + 1: Redundancy Enable for Sector 2 + [8:8] + read-write + + + RED_ADDR_3 + Bad Row Pair Address for Sector 3 + [23:16] + read-write + + + RED_EN_3 + 1: Redundancy Enable for Sector 3 + [24:24] + read-write + + + + + RED_CTL45 + Redundancy Control normal sectors 4,5 + 0x88 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_4 + Bad Row Pair Address for Sector 4 + [7:0] + read-write + + + RED_EN_4 + 1: Redundancy Enable for Sector 4 + [8:8] + read-write + + + RED_ADDR_5 + Bad Row Pair Address for Sector 5 + [23:16] + read-write + + + RED_EN_5 + 1: Redundancy Enable for Sector 5 + [24:24] + read-write + + + + + RED_CTL67 + Redundancy Control normal sectors 6,7 + 0x8C + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_6 + Bad Row Pair Address for Sector 6 + [7:0] + read-write + + + RED_EN_6 + 1: Redundancy Enable for Sector 6 + [8:8] + read-write + + + RED_ADDR_7 + Bad Row Pair Address for Sector 7 + [23:16] + read-write + + + RED_EN_7 + 1: Redundancy Enable for Sector 7 + [24:24] + read-write + + + + + RED_CTL_SM01 + Redundancy Control special sectors 0,1 + 0x90 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_SM0 + Bad Row Pair Address for Special Sector 0 + [7:0] + read-write + + + RED_EN_SM0 + Redundancy Enable for Special Sector 0 + [8:8] + read-write + + + RED_ADDR_SM1 + Bad Row Pair Address for Special Sector 1 + [23:16] + read-write + + + RED_EN_SM1 + Redundancy Enable for Special Sector 1 + [24:24] + read-write + + + + + RGRANT_DELAY_PRG + R-grant delay for program + 0x98 + 32 + read-write + 0x1000000 + 0x8FFFFFFF + + + RGRANT_DELAY_PRG_SEQ12 + PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_PRG_SEQ23 + PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_SEQ30 + PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_CLK + Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay +The value of this field is the integer result of 'clk_t frequency / 8'. +Example: for clk_t=100 this field is INT(100/8) =12. +This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table + [27:24] + read-write + + + HV_PARAMS_LOADED + 0: HV Pulse common params not loaded +1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 + [31:31] + read-write + + + + + PW_SEQ12 + HV Pulse Delay for seq 1&2 pre + 0xA0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ1 + Seq1 delay + [15:0] + read-write + + + PW_SEQ2_PRE + Seq2 pre delay + [31:16] + read-write + + + + + PW_SEQ23 + HV Pulse Delay for seq2 post & seq3 + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ2_POST + Seq2 post delay + [15:0] + read-write + + + PW_SEQ3 + Seq3 delay + [31:16] + read-write + + + + + RGRANT_SCALE_ERS + R-grant delay scale for erase + 0xA8 + 32 + read-write + 0x0 + 0xFFFF03FF + + + SCALE_ERS_SEQ01 + ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [1:0] + read-write + + + SCALE_ERS_SEQ12 + ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [3:2] + read-write + + + SCALE_ERS_SEQ23 + ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [5:4] + read-write + + + SCALE_ERS_PEON + ERASE: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [7:6] + read-write + + + SCALE_ERS_PEOFF + ERASE: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [9:8] + read-write + + + RGRANT_DELAY_ERS_PEON + ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_ERS_PEOFF + ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + RGRANT_DELAY_ERS + R-grant delay for erase + 0xAC + 32 + read-write + 0x0 + 0xFFFFFF + + + RGRANT_DELAY_ERS_SEQ01 + ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_ERS_SEQ12 + ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_ERS_SEQ23 + ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + + + FM_PL_WRDATA_ALL + Flash macro write page latches all + 0x7FC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Write all high Voltage page latches with the same 32-bit data in a single write cycle +Read always returns 0. + [31:0] + read-write + + + + + 256 + 4 + FM_PL_DATA[%s] + Flash macro Page Latches data + 0x800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Four page latch Bytes +When reading the page latches it requires FM_CTL.IF_SEL to be '1' +Note: the high Voltage page latches are readable for test mode functionality. + [31:0] + read-write + + + + + 256 + 4 + FM_MEM_DATA[%s] + Flash macro memory sense amplifier and column decoder data + 0xC00 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: +- IF_SEL is 0: data as specified by the R interface address +- IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. + [31:0] + read-only + + + + + + + + SRSS + SRSS Core Registers + 0x40260000 + + 0 + 65536 + registers + + + + PWR_CTL + Power Mode Control + 0x0 + 32 + read-write + 0x0 + 0xFFFC0033 + + + POWER_MODE + Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. + [1:0] + read-only + + + RESET + System is resetting. + 0 + + + ACTIVE + At least one CPU is running. + 1 + + + SLEEP + No CPUs are running. Peripherals may be running. + 2 + + + DEEPSLEEP + Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. + 3 + + + + + DEBUG_SESSION + Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) + [4:4] + read-only + + + NO_SESSION + No debug session active + 0 + + + SESSION_ACTIVE + Debug session is active. Power modes behave differently to keep the debug session active, and current consumption may be higher than datasheet specification. + 1 + + + + + LPM_READY + Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. +1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. + [5:5] + read-only + + + IREF_LPMODE + Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Current reference generator operates in normal mode. +1: Current reference generator operates in low power mode. Response time is reduced to save current. + [18:18] + read-write + + + VREFBUF_OK + Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. + [19:19] + read-only + + + DPSLP_REG_DIS + Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: DeepSleep Regulator is on. +1: DeepSleep Regulator is off. + [20:20] + read-write + + + RET_REG_DIS + Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Retention Regulator is on. +1: Retention Regulator is off. + [21:21] + read-write + + + NWELL_REG_DIS + Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Nwell Regulator is on. +1: Nwell Regulator is off. + [22:22] + read-write + + + LINREG_DIS + Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear regulator is on. +1: Linear regulator is off. + [23:23] + read-write + + + LINREG_LPMODE + Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear Regulator operates in normal mode. +1: Linear Regulator operates in low power mode. Load current capability is reduced, and firmware must ensure the current is kept within the limit for this operating mode. + [24:24] + read-write + + + PORBOD_LPMODE + Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: POR/BOD circuits operate in normal mode. +1: POR/BOD circuits operate in low power mode. Response time is reduced to save current. + [25:25] + read-write + + + BGREF_LPMODE + Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Bandgap Voltage and Current Reference operates in normal mode. +1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current. The Active Reference may be disabled using ACT_REF_DIS=0. + [26:26] + read-write + + + PLL_LS_BYPASS + Bypass level shifter inside the PLL. +0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. +1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. + [27:27] + read-write + + + VREFBUF_LPMODE + Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. +0: Voltage Reference Buffer operates in normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current. + [28:28] + read-write + + + VREFBUF_DIS + Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. + [29:29] + read-write + + + ACT_REF_DIS + Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Reference is enabled +1: Active Reference is disabled + [30:30] + read-write + + + ACT_REF_OK + Indicates that the normal mode of the Active Reference is ready. + [31:31] + read-only + + + + + PWR_HIBERNATE + HIBERNATE Mode Register + 0x4 + 32 + read-write + 0x0 + 0xCFFEFFFF + + + TOKEN + Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. + [7:0] + read-write + + + UNLOCK + This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. + [15:8] + read-write + + + FREEZE + Controls whether mode and state of GPIOs and SIOs in the system are frozen. This is intended to be used as part of the HIBERNATE entry and exit sequences. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. + [17:17] + read-write + + + MASK_HIBALARM + When set, HIBERNATE will wakeup for a RTC interrupt + [18:18] + read-write + + + MASK_HIBWDT + When set, HIBERNATE will wakeup if WDT matches + [19:19] + read-write + + + POLARITY_HIBPIN + Each bit sets the active polarity of the corresponding wakeup pin. +0: Pin input of 0 will wakeup the part from HIBERNATE +1: Pin input of 1 will wakeup the part from HIBERNATE + [23:20] + read-write + + + MASK_HIBPIN + When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the HIBERNATE wakeup pins. + [27:24] + read-write + + + HIBERNATE_DISABLE + Hibernate disable bit. +0: Normal operation, HIBERNATE works as described +1: Further writes to this register are ignored +Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. + [30:30] + read-write + + + HIBERNATE + Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. + [31:31] + read-write + + + + + PWR_LVD_CTL + Low Voltage Detector (LVD) Configuration Register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + HVLVD1_TRIPSEL + Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. +0: rise=1.225V (nom), fall=1.2V (nom) +1: rise=1.425V (nom), fall=1.4V (nom) +2: rise=1.625V (nom), fall=1.6V (nom) +3: rise=1.825V (nom), fall=1.8V (nom) +4: rise=2.025V (nom), fall=2V (nom) +5: rise=2.125V (nom), fall=2.1V (nom) +6: rise=2.225V (nom), fall=2.2V (nom) +7: rise=2.325V (nom), fall=2.3V (nom) +8: rise=2.425V (nom), fall=2.4V (nom) +9: rise=2.525V (nom), fall=2.5V (nom) +10: rise=2.625V (nom), fall=2.6V (nom) +11: rise=2.725V (nom), fall=2.7V (nom) +12: rise=2.825V (nom), fall=2.8V (nom) +13: rise=2.925V (nom), fall=2.9V (nom) +14: rise=3.025V (nom), fall=3.0V (nom) +15: rise=3.125V (nom), fall=3.1V (nom) + [3:0] + read-write + + + HVLVD1_SRCSEL + Source selection for HVLVD1 + [6:4] + read-write + + + VDDD + Select VDDD + 0 + + + AMUXBUSA + Select AMUXBUSA (VDDD branch) + 1 + + + RSVD + N/A + 2 + + + VDDIO + N/A + 3 + + + AMUXBUSB + Select AMUXBUSB (VDDD branch) + 4 + + + + + HVLVD1_EN + Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. + [7:7] + read-write + + + + + PWR_BUCK_CTL + Buck Control Register + 0x14 + 32 + read-write + 0x5 + 0xC0000007 + + + BUCK_OUT1_SEL + Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 0.85V +1: 0.875V +2: 0.90V +3: 0.95V +4: 1.05V +5: 1.10V +6: 1.15V +7: 1.20V + [2:0] + read-write + + + BUCK_EN + Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. + [30:30] + read-write + + + BUCK_OUT1_EN + Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. + [31:31] + read-write + + + + + PWR_BUCK_CTL2 + Buck Control Register 2 + 0x18 + 32 + read-write + 0x0 + 0xC0000007 + + + BUCK_OUT2_SEL + Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 1.15V +1: 1.20V +2: 1.25V +3: 1.30V +4: 1.35V +5: 1.40V +6: 1.45V +7: 1.50V + [2:0] + read-write + + + BUCK_OUT2_HW_SEL + Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. + [30:30] + read-write + + + BUCK_OUT2_EN + Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. + [31:31] + read-write + + + + + PWR_LVD_STATUS + Low Voltage Detector (LVD) Status Register + 0x1C + 32 + read-only + 0x0 + 0x1 + + + HVLVD1_OK + HVLVD1 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + 16 + 4 + PWR_HIB_DATA[%s] + HIBERNATE Data Register + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HIB_DATA + Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. + [31:0] + read-write + + + + + WDT_CTL + Watchdog Counter Control Register + 0x180 + 32 + read-write + 0xC0000001 + 0xC0000001 + + + WDT_EN + Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. + [0:0] + read-write + + + WDT_LOCK + Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. +Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + WDT_CNT + Watchdog Counter Count Register + 0x184 + 32 + read-write + 0x0 + 0xFFFF + + + COUNTER + Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. + [15:0] + read-write + + + + + WDT_MATCH + Watchdog Counter Match Register + 0x188 + 32 + read-write + 0x1000 + 0xFFFFF + + + MATCH + Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). + [15:0] + read-write + + + IGNORE_BITS + The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. + [19:16] + read-write + + + + + 2 + 64 + MCWDT_STRUCT[%s] + Multi-Counter Watchdog Timer + MCWDT_STRUCT + 0x00000200 + + MCWDT_CNTLOW + Multi-Counter Watchdog Sub-counters 0/1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR0 + Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. + [15:0] + read-write + + + WDT_CTR1 + Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:16] + read-write + + + + + MCWDT_CNTHIGH + Multi-Counter Watchdog Sub-counter 2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR2 + Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:0] + read-write + + + + + MCWDT_MATCH + Multi-Counter Watchdog Counter Match Register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_MATCH0 + Match value for sub-counter 0 of this MCWDT + [15:0] + read-write + + + WDT_MATCH1 + Match value for sub-counter 1 of this MCWDT + [31:16] + read-write + + + + + MCWDT_CONFIG + Multi-Counter Watchdog Counter Configuration + 0x10 + 32 + read-write + 0x0 + 0x1F010F0F + + + WDT_MODE0 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). + [1:0] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR0 + Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. + [2:2] + read-write + + + WDT_CASCADE0_1 + Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. +0: Independent counters +1: Cascaded counters + [3:3] + read-write + + + WDT_MODE1 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). + [9:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR1 + Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. + [10:10] + read-write + + + WDT_CASCADE1_2 + Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. +0: Independent counters +1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. + [11:11] + read-write + + + WDT_MODE2 + Watchdog Counter 2 Mode. + [16:16] + read-write + + + NOTHING + Free running counter with no interrupt requests + 0 + + + INT + Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). + 1 + + + + + WDT_BITS2 + Bit to observe for WDT_INT2: +0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) +... +31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) + [28:24] + read-write + + + + + MCWDT_CTL + Multi-Counter Watchdog Counter Control + 0x14 + 32 + read-write + 0x0 + 0xB0B0B + + + WDT_ENABLE0 + Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [0:0] + read-write + + + WDT_ENABLED0 + Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. + [1:1] + read-only + + + WDT_RESET0 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [3:3] + read-write + + + WDT_ENABLE1 + Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [8:8] + read-write + + + WDT_ENABLED1 + Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. + [9:9] + read-only + + + WDT_RESET1 + Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [11:11] + read-write + + + WDT_ENABLE2 + Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [16:16] + read-write + + + WDT_ENABLED2 + Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. + [17:17] + read-only + + + WDT_RESET2 + Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [19:19] + read-write + + + + + MCWDT_INTR + Multi-Counter Watchdog Counter Interrupt Register + 0x18 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. + [0:0] + read-write + + + MCWDT_INT1 + MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. + [1:1] + read-write + + + MCWDT_INT2 + MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. + [2:2] + read-write + + + + + MCWDT_INTR_SET + Multi-Counter Watchdog Counter Interrupt Set Register + 0x1C + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Set interrupt for MCWDT_INT0 + [0:0] + read-write + + + MCWDT_INT1 + Set interrupt for MCWDT_INT1 + [1:1] + read-write + + + MCWDT_INT2 + Set interrupt for MCWDT_INT2 + [2:2] + read-write + + + + + MCWDT_INTR_MASK + Multi-Counter Watchdog Counter Interrupt Mask Register + 0x20 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Mask for sub-counter 0 + [0:0] + read-write + + + MCWDT_INT1 + Mask for sub-counter 1 + [1:1] + read-write + + + MCWDT_INT2 + Mask for sub-counter 2 + [2:2] + read-write + + + + + MCWDT_INTR_MASKED + Multi-Counter Watchdog Counter Interrupt Masked Register + 0x24 + 32 + read-only + 0x0 + 0x7 + + + MCWDT_INT0 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + MCWDT_INT1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + MCWDT_INT2 + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + MCWDT_LOCK + Multi-Counter Watchdog Counter Lock Register + 0x28 + 32 + read-write + 0x0 + 0xC0000000 + + + MCWDT_LOCK + Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + + 16 + 4 + CLK_DSI_SELECT[%s] + Clock DSI Select Register + 0x300 + 32 + read-write + 0x0 + 0x1F + + + DSI_MUX + Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. + [4:0] + read-write + + + DSI_OUT0 + DSI0 - dsi_out[0] + 0 + + + DSI_OUT1 + DSI1 - dsi_out[1] + 1 + + + DSI_OUT2 + DSI2 - dsi_out[2] + 2 + + + DSI_OUT3 + DSI3 - dsi_out[3] + 3 + + + DSI_OUT4 + DSI4 - dsi_out[4] + 4 + + + DSI_OUT5 + DSI5 - dsi_out[5] + 5 + + + DSI_OUT6 + DSI6 - dsi_out[6] + 6 + + + DSI_OUT7 + DSI7 - dsi_out[7] + 7 + + + DSI_OUT8 + DSI8 - dsi_out[8] + 8 + + + DSI_OUT9 + DSI9 - dsi_out[9] + 9 + + + DSI_OUT10 + DSI10 - dsi_out[10] + 10 + + + DSI_OUT11 + DSI11 - dsi_out[11] + 11 + + + DSI_OUT12 + DSI12 - dsi_out[12] + 12 + + + DSI_OUT13 + DSI13 - dsi_out[13] + 13 + + + DSI_OUT14 + DSI14 - dsi_out[14] + 14 + + + DSI_OUT15 + DSI15 - dsi_out[15] + 15 + + + ILO + ILO - Internal Low-speed Oscillator + 16 + + + WCO + WCO - Watch-Crystal Oscillator + 17 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock + 18 + + + PILO + PILO - Precision Internal Low-speed Oscillator + 19 + + + + + + + 16 + 4 + CLK_PATH_SELECT[%s] + Clock Path Select Register + 0x340 + 32 + read-write + 0x0 + 0x7 + + + PATH_MUX + Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + DSI_MUX + DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. + 4 + + + + + + + 16 + 4 + CLK_ROOT_SELECT[%s] + Clock Root Select Register + 0x380 + 32 + read-write + 0x0 + 0x8000003F + + + ROOT_MUX + Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [3:0] + read-write + + + PATH0 + Select PATH0 (can be configured for FLL) + 0 + + + PATH1 + Select PATH1 (can be configured for PLL0, if available in the product) + 1 + + + PATH2 + Select PATH2 (can be configured for PLL1, if available in the product) + 2 + + + PATH3 + Select PATH3 (can be configured for PLL2, if available in the product) + 3 + + + PATH4 + Select PATH4 (can be configured for PLL3, if available in the product) + 4 + + + PATH5 + Select PATH5 (can be configured for PLL4, if available in the product) + 5 + + + PATH6 + Select PATH6 (can be configured for PLL5, if available in the product) + 6 + + + PATH7 + Select PATH7 (can be configured for PLL6, if available in the product) + 7 + + + PATH8 + Select PATH8 (can be configured for PLL7, if available in the product) + 8 + + + PATH9 + Select PATH9 (can be configured for PLL8, if available in the product) + 9 + + + PATH10 + Select PATH10 (can be configured for PLL9, if available in the product) + 10 + + + PATH11 + Select PATH11 (can be configured for PLL10, if available in the product) + 11 + + + PATH12 + Select PATH12 (can be configured for PLL11, if available in the product) + 12 + + + PATH13 + Select PATH13 (can be configured for PLL12, if available in the product) + 13 + + + PATH14 + Select PATH14 (can be configured for PLL13, if available in the product) + 14 + + + PATH15 + Select PATH15 (can be configured for PLL14, if available in the product) + 15 + + + + + ROOT_DIV + Selects predivider value for this clock root and DSI input. + [5:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + + + ENABLE + Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. + [31:31] + read-write + + + + + CLK_SELECT + Clock selection register + 0x500 + 32 + read-write + 0x0 + 0xFF03 + + + LFCLK_SEL + Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. + [1:0] + read-write + + + ILO + ILO - Internal Low-speed Oscillator + 0 + + + WCO + WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). + 1 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock. Capability is product-specific + 2 + + + PILO + PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. + 3 + + + + + PUMP_SEL + Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. + [11:8] + read-write + + + PUMP_DIV + Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. + [14:12] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + + + PUMP_ENABLE + Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: +1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. +2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. +3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. + [15:15] + read-write + + + + + CLK_TIMER_CTL + Timer Clock Control Register + 0x504 + 32 + read-write + 0x70000 + 0x80FF0301 + + + TIMER_SEL + Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. + [0:0] + read-write + + + IMO + IMO - Internal Main Oscillator + 0 + + + HF0_DIV + Select the output of the predivider configured by TIMER_HF0_DIV. + 1 + + + + + TIMER_HF0_DIV + Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. + [9:8] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. + 0 + + + DIV_BY_2 + Divide HFCLK0 by 2. + 1 + + + DIV_BY_4 + Divide HFCLK0 by 4. + 2 + + + DIV_BY_8 + Divide HFCLK0 by 8. + 3 + + + + + TIMER_DIV + Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. + [23:16] + read-write + + + ENABLE + Enable for TIMERCLK. +0: TIMERCLK is off +1: TIMERCLK is enabled + [31:31] + read-write + + + + + CLK_ILO_CONFIG + ILO Configuration + 0x50C + 32 + read-write + 0x80000000 + 0x80000001 + + + ILO_BACKUP + If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. +0: ILO turns off at XRES/BOD event or HIBERNATE entry. +1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. + [0:0] + read-write + + + ENABLE + Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. + [31:31] + read-write + + + + + CLK_IMO_CONFIG + IMO Configuration + 0x510 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLE + Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if CLK_MFO_CONFIG.DPSLP_ENABLE==0. + [31:31] + read-write + + + + + CLK_OUTPUT_FAST + Fast Clock Output Select Register + 0x514 + 32 + read-write + 0x0 + 0xFFF0FFF + + + FAST_SEL0 + Select signal for fast clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL0 + Selects the clock path chosen by PATH_SEL0 field + 5 + + + HFCLK_SEL0 + Selects the output of the HFCLK_SEL0 mux + 6 + + + SLOW_SEL0 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 + 7 + + + + + PATH_SEL0 + Selects a clock path to use in fast clock output #0 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [7:4] + read-write + + + HFCLK_SEL0 + Selects a HFCLK tree for use in fast clock output #0 + [11:8] + read-write + + + FAST_SEL1 + Select signal for fast clock output #1 + [19:16] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL1 + Selects the clock path chosen by PATH_SEL1 field + 5 + + + HFCLK_SEL1 + Selects the output of the HFCLK_SEL1 mux + 6 + + + SLOW_SEL1 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 + 7 + + + + + PATH_SEL1 + Selects a clock path to use in fast clock output #1 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [23:20] + read-write + + + HFCLK_SEL1 + Selects a HFCLK tree for use in fast clock output #1 logic + [27:24] + read-write + + + + + CLK_OUTPUT_SLOW + Slow Clock Output Select Register + 0x518 + 32 + read-write + 0x0 + 0xFF + + + SLOW_SEL0 + Select signal for slow clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + SLOW_SEL1 + Select signal for slow clock output #1 + [7:4] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + + + CLK_CAL_CNT1 + Clock Calibration Counter 1 + 0x51C + 32 + read-write + 0x80000000 + 0x80FFFFFF + + + CAL_COUNTER1 + Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. + [23:0] + read-write + + + CAL_COUNTER_DONE + Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up + [31:31] + read-only + + + + + CLK_CAL_CNT2 + Clock Calibration Counter 2 + 0x520 + 32 + read-only + 0x0 + 0xFFFFFF + + + CAL_COUNTER2 + Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) + [23:0] + read-only + + + + + CLK_ECO_CONFIG + ECO Configuration Register + 0x52C + 32 + read-write + 0x2 + 0x80000002 + + + AGC_EN + Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. + [1:1] + read-write + + + ECO_EN + Master enable for ECO oscillator. + [31:31] + read-write + + + + + CLK_ECO_STATUS + ECO Status Register + 0x530 + 32 + read-only + 0x0 + 0x3 + + + ECO_OK + Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. + [0:0] + read-only + + + ECO_READY + Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. + [1:1] + read-only + + + + + CLK_PILO_CONFIG + Precision ILO Configuration Register + 0x53C + 32 + read-write + 0x80 + 0xE00003FF + + + PILO_FFREQ + Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. + [9:0] + read-write + + + PILO_CLK_EN + Enable the PILO clock output. See PILO_EN field for required sequencing. + [29:29] + read-write + + + PILO_RESET_N + Reset the PILO. See PILO_EN field for required sequencing. + [30:30] + read-write + + + PILO_EN + Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. + [31:31] + read-write + + + + + CLK_MF_SELECT + Medium Frequency Clock Select Register + 0x544 + 32 + read-write + 0x0 + 0x8000FF07 + + + MFCLK_SEL + Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior. + [2:0] + read-write + + + MFO + MFO - medium frequency oscillator + 0 + + + + + MFCLK_DIV + Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1, 256]. Do not change this setting while ENABLE==1. + [15:8] + read-write + + + ENABLE + Enable for MFCLK (clk_mf). + [31:31] + read-write + + + + + CLK_MFO_CONFIG + MFO Configuration Register + 0x548 + 32 + read-write + 0x80000000 + 0xC0000000 + + + DPSLP_ENABLE + Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1: +0: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup; +1: MFO is kept enabled throughout DEEPSLEEP + [30:30] + read-write + + + ENABLE + Enable for MFO. + [31:31] + read-write + + + + + CLK_FLL_CONFIG + FLL Configuration Register + 0x580 + 32 + read-write + 0x1000000 + 0x8103FFFF + + + FLL_MULT + Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). + +Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) + [17:0] + read-write + + + FLL_OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: no division +1: divide by 2 + [24:24] + read-write + + + FLL_ENABLE + Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. + +To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. + +To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. + +Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. + +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_CONFIG2 + FLL Configuration Register 2 + 0x584 + 32 + read-write + 0x20001 + 0x1FF1FFF + + + FLL_REF_DIV + Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +8191: divide by 8191 + [12:0] + read-write + + + LOCK_TOL + Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. +0: tolerate error of 1 count value +1: tolerate error of 2 count values +... +511: tolerate error of 512 count values + [24:16] + read-write + + + + + CLK_FLL_CONFIG3 + FLL Configuration Register 3 + 0x588 + 32 + read-write + 0x2800 + 0x301FFFFF + + + FLL_LF_IGAIN + FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [3:0] + read-write + + + FLL_LF_PGAIN + FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [7:4] + read-write + + + SETTLING_COUNT + Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. +0: no settling time +1: wait one reference clock cycle +... +8191: wait 8191 reference clock cycles + [20:8] + read-write + + + BYPASS_SEL + Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. + [29:28] + read-write + + + AUTO + N/A + 0 + + + AUTO1 + N/A + 1 + + + FLL_REF + Select FLL reference input (bypass mode). Ignores lock indicator + 2 + + + FLL_OUT + Select FLL output. Ignores lock indicator. + 3 + + + + + + + CLK_FLL_CONFIG4 + FLL Configuration Register 4 + 0x58C + 32 + read-write + 0xFF + 0xC1FF07FF + + + CCO_LIMIT + Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) + [7:0] + read-write + + + CCO_RANGE + Frequency range of CCO + [10:8] + read-write + + + RANGE0 + Target frequency is in range [48, 64) MHz + 0 + + + RANGE1 + Target frequency is in range [64, 85) MHz + 1 + + + RANGE2 + Target frequency is in range [85, 113) MHz + 2 + + + RANGE3 + Target frequency is in range [113, 150) MHz + 3 + + + RANGE4 + Target frequency is in range [150, 200] MHz + 4 + + + + + CCO_FREQ + CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. + [24:16] + read-write + + + CCO_HW_UPDATE_DIS + Disable CCO frequency update by FLL hardware +0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. +1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. + [30:30] + read-write + + + CCO_ENABLE + Enable the CCO. It is required to enable the CCO before using the FLL. +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_STATUS + FLL Status Register + 0x590 + 32 + read-write + 0x0 + 0x7 + + + LOCKED + FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. + [0:0] + read-only + + + UNLOCK_OCCURRED + N/A + [1:1] + read-write + + + CCO_READY + This indicates that the CCO is internally settled and ready to use. + [2:2] + read-only + + + + + 15 + 4 + CLK_PLL_CONFIG[%s] + PLL Configuration Register + 0x600 + 32 + read-write + 0x20116 + 0xB81F1F7F + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-21: illegal (undefined behavior) +22: divide by 22 +... +112: divide by 112 +>112: illegal (undefined behavior) + [6:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +20: divide by 20 +others: illegal (undefined behavior) + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + PLL_LF_MODE + VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. +0: VCO frequency is [200MHz, 400MHz] +1: VCO frequency is [170MHz, 200MHz) + [27:27] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. + 0 + + + AUTO1 + Same as AUTO + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. + +Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled +1: Block is enabled + [31:31] + read-write + + + + + 15 + 4 + CLK_PLL_STATUS[%s] + PLL Status Register + 0x640 + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + SRSS_INTR + SRSS Interrupt Register + 0x700 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. + [0:0] + read-write + + + HVLVD1 + Interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Clock calibration counter is done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_SET + SRSS Interrupt Set Register + 0x704 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Set interrupt for low voltage detector WDT_MATCH + [0:0] + read-write + + + HVLVD1 + Set interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_MASK + SRSS Interrupt Mask Register + 0x708 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. + [0:0] + read-write + + + HVLVD1 + Mask for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Mask for clock calibration done + [5:5] + read-write + + + + + SRSS_INTR_MASKED + SRSS Interrupt Masked Register + 0x70C + 32 + read-only + 0x0 + 0x23 + + + WDT_MATCH + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + HVLVD1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CLK_CAL + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + SRSS_INTR_CFG + SRSS Interrupt Configuration Register + 0x710 + 32 + read-write + 0x0 + 0x3 + + + HVLVD1_EDGE_SEL + Sets which edge(s) will trigger an IRQ for HVLVD1 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + + + RES_CAUSE + Reset Cause Observation Register + 0x800 + 32 + read-write + 0x0 + 0x1FF + + + RESET_WDT + A basic WatchDog Timer (WDT) reset has occurred since last power cycle. + [0:0] + read-write + + + RESET_ACT_FAULT + Fault logging system requested a reset from its Active logic. + [1:1] + read-write + + + RESET_DPSLP_FAULT + Fault logging system requested a reset from its DeepSleep logic. + [2:2] + read-write + + + RESET_CSV_WCO_LOSS + Clock supervision logic requested a reset due to loss of a watch-crystal clock. + [3:3] + read-write + + + RESET_SOFT + A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. + [4:4] + read-write + + + RESET_MCWDT0 + Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. + [5:5] + read-write + + + RESET_MCWDT1 + Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. + [6:6] + read-write + + + RESET_MCWDT2 + Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. + [7:7] + read-write + + + RESET_MCWDT3 + Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. + [8:8] + read-write + + + + + RES_CAUSE2 + Reset Cause Observation Register 2 + 0x804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESET_CSV_HF_LOSS + Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [15:0] + read-write + + + RESET_CSV_HF_FREQ + Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [31:16] + read-write + + + + + PWR_TRIM_REF_CTL + Reference Trim Register + 0x7F00 + 32 + read-write + 0x70F00000 + 0xF1FF5FFF + + + ACT_REF_TCTRIM + Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [3:0] + read-write + + + ACT_REF_ITRIM + Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [7:4] + read-write + + + ACT_REF_ABSTRIM + Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [12:8] + read-write + + + ACT_REF_IBOOST + Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: normal operation +others: risk mitigation + [14:14] + read-write + + + DPSLP_REF_TCTRIM + DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [19:16] + read-write + + + DPSLP_REF_ABSTRIM + DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [24:20] + read-write + + + DPSLP_REF_ITRIM + DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:28] + read-write + + + + + PWR_TRIM_BODOVP_CTL + BOD/OVP Trim Register + 0x7F04 + 32 + read-write + 0x40D04 + 0xFDFF7 + + + HVPORBOD_TRIPSEL + HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [2:0] + read-write + + + HVPORBOD_OFSTRIM + HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [6:4] + read-write + + + HVPORBOD_ITRIM + HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [9:7] + read-write + + + LVPORBOD_TRIPSEL + LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [12:10] + read-write + + + LVPORBOD_OFSTRIM + LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [16:14] + read-write + + + LVPORBOD_ITRIM + LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [19:17] + read-write + + + + + CLK_TRIM_CCO_CTL + CCO Trim Register + 0x7F08 + 32 + read-write + 0xA7000020 + 0xBF00003F + + + CCO_RCSTRIM + CCO reference current source trim. + [5:0] + read-write + + + CCO_STABLE_CNT + Terminal count for the stabilization counter from CCO_ENABLE until stable. + [29:24] + read-write + + + ENABLE_CNT + Enables the automatic stabilization counter. + [31:31] + read-write + + + + + CLK_TRIM_CCO_CTL2 + CCO Trim Register 2 + 0x7F0C + 32 + read-write + 0x884110 + 0x1FFFFFF + + + CCO_FCTRIM1 + CCO frequency 1st range calibration + [4:0] + read-write + + + CCO_FCTRIM2 + CCO frequency 2nd range calibration + [9:5] + read-write + + + CCO_FCTRIM3 + CCO frequency 3rd range calibration + [14:10] + read-write + + + CCO_FCTRIM4 + CCO frequency 4th range calibration + [19:15] + read-write + + + CCO_FCTRIM5 + CCO frequency 5th range calibration + [24:20] + read-write + + + + + PWR_TRIM_WAKE_CTL + Wakeup Trim Register + 0x7F30 + 32 + read-write + 0x0 + 0xFF + + + WAKE_DELAY + Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. + [7:0] + read-write + + + + + PWR_TRIM_LVD_CTL + LVD Trim Register + 0xFF10 + 32 + read-write + 0x20 + 0x77 + + + HVLVD1_OFSTRIM + HVLVD1 offset trim + [2:0] + read-write + + + HVLVD1_ITRIM + HVLVD1 current trim + [6:4] + read-write + + + + + CLK_TRIM_ILO_CTL + ILO Trim Register + 0xFF18 + 32 + read-write + 0x2C + 0x3F + + + ILO_FTRIM + ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + + + PWR_TRIM_PWRSYS_CTL + Power System Trim Register + 0xFF1C + 32 + read-write + 0x17 + 0x1F + + + ACT_REG_TRIM + Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: +5'h07: 900mV (nominal) +5'h17: 1100mV (nominal) + [4:0] + read-write + + + ACT_REG_BOOST + Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: +2'b00: 50uA +2'b01: 100uA +2'b10: 150uA +2'b11: 200uA + +The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. +50mA chip: 2'b00 (default); +100mA chip: 2'b00 (default); +150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); +200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); +250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); +300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); + +This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:30] + read-write + + + + + CLK_TRIM_ECO_CTL + ECO Trim Register + 0xFF20 + 32 + read-write + 0x1F0003 + 0x3F3FF7 + + + WDTRIM + Watch Dog Trim - Delta voltage below steady state level +0x0 - 50mV +0x1 - 75mV +0x2 - 100mV +0x3 - 125mV +0x4 - 150mV +0x5 - 175mV +0x6 - 200mV +0x7 - 225mV + [2:0] + read-write + + + ATRIM + Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. +0x0 - 150mV +0x1 - 175mV +0x2 - 200mV +0x3 - 225mV +0x4 - 250mV +0x5 - 275mV +0x6 - 300mV +0x7 - 325mV +0x8 - 350mV +0x9 - 375mV +0xA - 400mV +0xB - 425mV +0xC - 450mV +0xD - 475mV +0xE - 500mV +0xF - 525mV + [7:4] + read-write + + + FTRIM + Filter Trim - 3rd harmonic oscillation + [9:8] + read-write + + + RTRIM + Feedback resistor Trim + [11:10] + read-write + + + GTRIM + Gain Trim - Startup time + [13:12] + read-write + + + ITRIM + Current Trim + [21:16] + read-write + + + + + CLK_TRIM_PILO_CTL + PILO Trim Register + 0xFF24 + 32 + read-write + 0x108500F + 0x7DFF703F + + + PILO_CFREQ + Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. + [5:0] + read-write + + + PILO_OSC_TRIM + Trim for current in oscillator block. + [14:12] + read-write + + + PILO_COMP_TRIM + Trim for comparator bias current. + [17:16] + read-write + + + PILO_NBIAS_TRIM + Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier + [19:18] + read-write + + + PILO_RES_TRIM + Trim for beta-multiplier branch current + [24:20] + read-write + + + PILO_ISLOPE_TRIM + Trim for beta-multiplier current slope + [27:26] + read-write + + + PILO_VTDIFF_TRIM + Trim for VT-DIFF output (internal power supply) + [30:28] + read-write + + + + + CLK_TRIM_PILO_CTL2 + PILO Trim Register 2 + 0xFF28 + 32 + read-write + 0xDA10E0 + 0xFF1FFF + + + PILO_VREF_TRIM + Trim for voltage reference + [7:0] + read-write + + + PILO_IREFBM_TRIM + Trim for beta-multiplier current reference + [12:8] + read-write + + + PILO_IREF_TRIM + Trim for current reference + [23:16] + read-write + + + + + CLK_TRIM_PILO_CTL3 + PILO Trim Register 3 + 0xFF2C + 32 + read-write + 0x4800 + 0xFFFF + + + PILO_ENGOPT + Engineering options for PILO circuits +0: Short vdda to vpwr +1: Beta:mult current change +2: Iref generation Ptat current addition +3: Disable current path in secondary Beta:mult startup circuit +4: Double oscillator current +5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block +6: Spare +7: Ptat component increase in Iref +8: vpwr_rc and vpwr_dig_rc shorting testmode +9: Switch b/w psub connection for cascode nfet for vref generation +10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. +15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. + [15:0] + read-write + + + + + + + BACKUP + SRSS Backup Domain + 0x40270000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFF0F3308 + + + WCO_EN + Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. +After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. + [3:3] + read-write + + + CLK_SEL + Clock select for BAK clock + [9:8] + read-write + + + WCO + Watch-crystal oscillator input. + 0 + + + ALTBAK + This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. + 1 + + + + + PRESCALER + N/A + [13:12] + read-write + + + WCO_BYPASS + Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. +0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. +1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. + [16:16] + read-write + + + VDDBAK_CTL + Controls the behavior of the switch that generates vddbak from vbackup or vddd. +0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. +1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. + [18:17] + read-write + + + VBACKUP_MEAS + Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. + [19:19] + read-write + + + EN_CHARGE_KEY + When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. + [31:24] + read-write + + + + + RTC_RW + RTC Read Write register + 0x8 + 32 + read-write + 0x0 + 0x3 + + + READ + Read bit +When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. +Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. + [0:0] + read-write + + + WRITE + Write bit +Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. +The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. +Only user RTC registers that were written to will get copied, others will not be affected. +When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). +When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. +Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. + [1:1] + read-write + + + + + CAL_CTL + Oscillator calibration for absolute frequency + 0xC + 32 + read-write + 0x0 + 0x8000007F + + + CALIB_VAL + Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). +Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) + +Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. + [5:0] + read-write + + + CALIB_SIGN + Calibration sign: +0= Negative sign: remove pulses (it takes more clock ticks to count one second) +1= Positive sign: add pulses (it takes less clock ticks to count one second) + [6:6] + read-write + + + CAL_OUT + Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. + [31:31] + read-write + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x0 + 0x5 + + + RTC_BUSY + pending RTC write + [0:0] + read-only + + + WCO_OK + Indicates that output has transitioned. + [2:2] + read-only + + + + + RTC_TIME + Calendar Seconds, Minutes, Hours, Day of Week + 0x14 + 32 + read-write + 0x0 + 0x77F7F7F + + + RTC_SEC + Calendar seconds in BCD, 0-59 + [6:0] + read-write + + + RTC_MIN + Calendar minutes in BCD, 0-59 + [14:8] + read-write + + + RTC_HOUR + Calendar hours in BCD, value depending on 12/24HR mode +0=24HR: [21:16]=0-23 +1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 + [21:16] + read-write + + + CTRL_12HR + Select 12/24HR mode: 1=12HR, 0=24HR + [22:22] + read-write + + + RTC_DAY + Calendar Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + + + RTC_DATE + Calendar Day of Month, Month, Year + 0x18 + 32 + read-write + 0x0 + 0xFF1F3F + + + RTC_DATE + Calendar Day of the Month in BCD, 1-31 +Automatic Leap Year Correction + [5:0] + read-write + + + RTC_MON + Calendar Month in BCD, 1-12 + [12:8] + read-write + + + RTC_YEAR + Calendar year in BCD, 0-99 + [23:16] + read-write + + + + + ALM1_TIME + Alarm 1 Seconds, Minute, Hours, Day of Week + 0x1C + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM1_DATE + Alarm 1 Day of Month, Month + 0x20 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 1. +0: Alarm 1 is disabled. Fields for date and time are ignored. +1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + ALM2_TIME + Alarm 2 Seconds, Minute, Hours, Day of Week + 0x24 + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM2_DATE + Alarm 2 Day of Month, Month + 0x28 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 2. +0: Alarm 2 is disabled. Fields for date and time are ignored. +1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x2C + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Alarm 1 Interrupt + [0:0] + read-write + + + ALARM2 + Alarm 2 Interrupt + [1:1] + read-write + + + CENTURY + Century overflow interrupt + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x30 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x34 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x38 + 32 + read-only + 0x0 + 0x7 + + + ALARM1 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + ALARM2 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CENTURY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + OSCCNT + 32kHz oscillator counter + 0x3C + 32 + read-only + 0x0 + 0xFF + + + CNT32KHZ + 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. + [7:0] + read-only + + + + + TICKS + 128Hz tick counter + 0x40 + 32 + read-only + 0x0 + 0x3F + + + CNT128HZ + 128Hz counter (msb=2Hz) +When SECONDS is written this field will be reset. + [5:0] + read-only + + + + + PMIC_CTL + PMIC control register + 0x44 + 32 + read-write + 0xA0000000 + 0xE001FF00 + + + UNLOCK + This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. + [15:8] + read-write + + + POLARITY + N/A + [16:16] + read-write + + + PMIC_EN_OUTEN + Output enable for the output driver in the PMIC_EN pad. +0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present +1: Output pad is enabled for PMIC_EN pin. + [29:29] + read-write + + + PMIC_ALWAYSEN + Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. +0: Normal operation, PMIC_EN and PMIC_OUTEN work as described +1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. +Note: This bit is a write-once bit until the next backup reset. + [30:30] + read-write + + + PMIC_EN + Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. + [31:31] + read-write + + + + + RESET + Backup reset register + 0x48 + 32 + read-write + 0x0 + 0x80000000 + + + RESET + Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. + [31:31] + read-write + + + + + 64 + 4 + BREG[%s] + Backup register region + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BREG + Backup memory that contains application-specific data. Memory is retained on vbackup supply. + [31:0] + read-write + + + + + TRIM + Trim Register + 0xFF00 + 32 + read-write + 0x0 + 0x3F + + + TRIM + WCO trim + [5:0] + read-write + + + + + + + DW0 + Datawire Controller + DW + 0x40280000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x1 + 0x80000003 + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + ECC_INJ_EN + Enable parity injection for SRAM. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. + [1:1] + read-write + + + ENABLED + IP enable: +'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0xF0000000 + + + P + Active channel, user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + Active channel, secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + B + Active channel, non-bufferable/bufferable access control: +'0': non-bufferable +'1': bufferable. + [2:2] + read-only + + + PC + Active channel protection context. + [7:4] + read-only + + + PRIO + Active channel priority. + [9:8] + read-only + + + PREEMPTABLE + Active channel preemptable. + [11:11] + read-only + + + CH_IDX + Active channel index. + [24:16] + read-only + + + STATE + State of the DW controller. +'0': Default/inactive state. +'1': Loading descriptor. +'2': Loading data element from source location. +'3': Storing data element to destination location. +'4': CRC functionality (only used for CRC transfer descriptor type). +'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. +'6': Error. + [30:28] + read-only + + + ACTIVE + Active channel present: +'0': No. +'1': Yes. + [31:31] + read-only + + + + + ACT_DESCR_CTL + Active descriptor control + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-only + + + + + ACT_DESCR_SRC + Active descriptor source + 0x24 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_SRC of the currently active descriptor. + +Base address of source location. + [31:0] + read-only + + + + + ACT_DESCR_DST + Active descriptor destination + 0x28 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_DST of the currently active descriptor. + +Base address of destination location. + +Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. + [31:0] + read-only + + + + + ACT_DESCR_X_CTL + Active descriptor X loop control + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_X_CTL of the currently active descriptor. + +[11:0] SRC_X_INCR +Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + +[23:12] DST_X_INCR +Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + +Note: this field is not used for CRC transfer descriptors and must be set to '0'. + +[31:24] X_COUNT +Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For a single transfer descriptor type, descriptor will not have X_CTL. + [31:0] + read-only + + + + + ACT_DESCR_Y_CTL + Active descriptor Y loop control + 0x34 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_Y_CTL of the currently active descriptor. + +[11:0] SRC_Y_INCR +Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[23:12] DST_Y_INCR +Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[31:24] Y_COUNT +Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. + [31:0] + read-only + + + + + ACT_DESCR_NEXT_PTR + Active descriptor next pointer + 0x38 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Copy of DESCR_NEXT_PTR of the currently active descriptor. + +[31:2] ADDR +Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + ACT_SRC + Active source + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SRC_ADDR + Current address of source location. + [31:0] + read-only + + + + + ACT_DST + Active destination + 0x44 + 32 + read-only + 0x0 + 0x0 + + + DST_ADDR + Current address of destination location. + [31:0] + read-only + + + + + ECC_CTL + ECC control + 0x80 + 32 + read-write + 0x0 + 0xFE0003FF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [9:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + CRC_CTL + CRC control + 0x100 + 32 + read-write + 0x0 + 0x101 + + + DATA_REVERSE + Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): +'0': Most significant bit (bit 1) first. +'1': Least significant bit (bit 0) first. + [0:0] + read-write + + + REM_REVERSE + Specifies whether the remainder is bit reversed (reversal is performed after XORing): +'0': No. +'1': Yes. + [8:8] + read-write + + + + + CRC_DATA_CTL + CRC data control + 0x110 + 32 + read-write + 0x0 + 0xFF + + + DATA_XOR + Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. + [7:0] + read-write + + + + + CRC_POL_CTL + CRC polynomial control + 0x120 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POLYNOMIAL + CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: +- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). +- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). +- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). + [31:0] + read-write + + + + + CRC_LFSR_CTL + CRC LFSR control + 0x130 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LFSR32 + State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. + +The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. + +Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). + [31:0] + read-write + + + + + CRC_REM_CTL + CRC remainder control + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REM_XOR + Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. + [31:0] + read-write + + + + + CRC_REM_RESULT + CRC remainder result + 0x148 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REM + Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: +'0': the more significant bits (bit 31 and down) contain the remainder. +'1': the less significant bits (bit 0 and up) contain the remainder. + +Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. + [31:0] + read-only + + + + + 32 + 64 + CH_STRUCT[%s] + DW channel structure + 0x00008000 + + CH_CTL + Channel control + 0x0 + 32 + read-write + 0x0 + 0x80000300 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). + [9:8] + read-write + + + PREEMPTABLE + Specifies if the channel is preemptable. +'0': Not preemptable. +'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. + [11:11] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). + [31:31] + read-write + + + + + CH_STATUS + Channel status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + INTR_CAUSE + Specifies the source of the interrupt cause: +'0': No interrupt generated +'1': Interrupt based on transfer complettion configuration based on INTR_TYPE +'2': Source transfer bus error +'3': Destination transfer bus error +'4': Source address misalignment +'5': Destination address misalignment +'6': Current descriptor pointer is null +'7': Active channel is disabled +'8': Descriptor bus error +'9'-'15': Not used. + +For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). + [3:0] + read-only + + + PENDING + Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). + [31:31] + read-only + + + + + CH_IDX + Channel current indices + 0x8 + 32 + read-write + 0x0 + 0x0 + + + X_IDX + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [7:0] + read-write + + + Y_IDX + Specifies the Y loop index, with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [15:8] + read-write + + + + + CH_CURR_PTR + Channel current descriptor pointer + 0xC + 32 + read-write + 0x0 + 0x0 + + + ADDR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. + [31:2] + read-write + + + + + INTR + Interrupt + 0x10 + 32 + read-write + 0x0 + 0x1 + + + CH + Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x14 + 32 + read-write + 0x0 + 0x1 + + + CH + Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x18 + 32 + read-write + 0x0 + 0x1 + + + CH + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x1C + 32 + read-only + 0x0 + 0x1 + + + CH + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + SRAM_DATA0 + SRAM data 0 + 0x20 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + SRAM_DATA1 + SRAM data 1 + 0x24 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + TR_CMD + Channel software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + + + + DW1 + 0x40290000 + + + DMAC + DMAC + 0x402A0000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + ACTIVE + Active channels + 0x8 + 32 + read-only + 0x0 + 0xFF + + + ACTIVE + Specifies active channels; i.e. enabled channels whose trigger got activated. + [7:0] + read-only + + + + + 2 + 256 + CH[%s] + DMA controller channel + 0x00001000 + + CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x800003F7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. +A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. + [9:8] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' when an error interrupt cause is activated. + [31:31] + read-write + + + + + IDX + Channel current indices + 0x10 + 32 + read-only + 0x0 + 0x0 + + + X + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor. + [15:0] + read-only + + + Y + Specifies the Y loop index, with Y_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor.. + [31:16] + read-only + + + + + SRC + Channel current source address + 0x14 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of source location. + [31:0] + read-only + + + + + DST + Channel current destination address + 0x18 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of destination location. + [31:0] + read-only + + + + + CURR + Channel current descriptor pointer + 0x20 + 32 + read-write + 0x0 + 0x0 + + + PTR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + [31:2] + read-write + + + + + TR_CMD + Channle software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + DESCR_STATUS + Channel descriptor status + 0x40 + 32 + read-only + 0x0 + 0x80000000 + + + VALID + Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. + [31:31] + read-only + + + + + DESCR_CTL + Channel descriptor control + 0x60 + 32 + read-only + 0x0 + 0x0 + + + WAIT_FOR_DEACT + Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. +'0': Do not wait for trigger de-activation (for pulse sensitive triggers). +'1': Wait for up to 4 cycles. +'2': Wait for up to 16 cycles. +'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. + [1:0] + read-only + + + INTR_TYPE + Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): +'0': An interrupt is generated after a single transfer. +'1': An interrupt is generated after a single 1D transfer or a memory copy transfer +- If the descriptor type is 'single', the interrupt is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. +'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). +'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [3:2] + read-only + + + TR_OUT_TYPE + Specifies when an output trigger is generated: +'0': An output trigger is generated after a single transfer. +'1': An output trigger is generated after a single 1D transfer or a memory copy transfer. +- If the descriptor type is 'single', the output trigger is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. +'2': An output trigger is generated after the execution of the current descriptor. +'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [5:4] + read-only + + + TR_IN_TYPE + Specifies the input trigger type (not to be confused with the descriptor type): +'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. +'1': A trigger results in the execution of a single 1D transfer. +- If the descriptor type is 'single', the trigger results in the execution of a single transfer. +- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. +'2': A trigger results in the execution of the current descriptor. +'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. + [7:6] + read-only + + + DATA_PREFETCH + Source data prefetch: +'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. +'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. + +Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. + [8:8] + read-only + + + DATA_SIZE + Specifies the data element size: +'0': Byte (8 bits). +'1': Halfword (16 bits). +'2': Word (32 bits). +DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: +- DATA is 8 bit, SRC is 8 bit, DST is 8 bit. +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. +- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). +- DATA is 16 bit, SRC is 16 bit, DST is 16 bit. +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. +- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). +- DATA is 32 bit, SRC is 32 bit, DST is 32 bit. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. + [17:16] + read-only + + + CH_DISABLE + Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): +'0': Channel is not disabled. +'1': Channel is disabled. + [24:24] + read-only + + + SRC_TRANSFER_SIZE + Specifies the bus transfer size to the source location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [26:26] + read-only + + + DST_TRANSFER_SIZE + Specifies the bus transfer size to the destination location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [27:27] + read-only + + + DESCR_TYPE + Specifies the descriptor type (not to be confused with the trigger type): +'0': Single transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. +'1': 1D transfer. +The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. +'2': 2D transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. +'3': Memory copy. +The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. +'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. +'5'-'7': Undefined. + +After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. + [30:28] + read-only + + + + + DESCR_SRC + Channel descriptor source + 0x64 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of source location. + [31:0] + read-only + + + + + DESCR_DST + Channel descriptor destination + 0x68 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of destination location. + [31:0] + read-only + + + + + DESCR_X_SIZE + Channel descriptor X size + 0x6C + 32 + read-only + 0x0 + 0x0 + + + X_COUNT + Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + +For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. + [15:0] + read-only + + + + + DESCR_X_INCR + Channel descriptor X increment + 0x70 + 32 + read-only + 0x0 + 0x0 + + + SRC_X + Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + [15:0] + read-only + + + DST_X + Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + [31:16] + read-only + + + + + DESCR_Y_SIZE + Channel descriptor Y size + 0x74 + 32 + read-only + 0x0 + 0x0 + + + Y_COUNT + Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + [15:0] + read-only + + + + + DESCR_Y_INCR + Channel descriptor Y increment + 0x78 + 32 + read-only + 0x0 + 0x0 + + + SRC_Y + Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [15:0] + read-only + + + DST_Y + Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [31:16] + read-only + + + + + DESCR_NEXT + Channel descriptor next pointer + 0x7C + 32 + read-only + 0x0 + 0x0 + + + PTR + Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + INTR + Interrupt + 0x80 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. + [0:0] + read-write + + + SRC_BUS_ERROR + Activated (set to '1') on a bus error for a load from the source. + [1:1] + read-write + + + DST_BUS_ERROR + Activated (set to '1') on a bus error for a store to the destination. + [2:2] + read-write + + + SRC_MISAL + Activated (set to '1') on a misalignment of the source address. + [3:3] + read-write + + + DST_MISAL + Activated (set to '1') on a misalignment of the destination address. + [4:4] + read-write + + + CURR_PTR_NULL + Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. + [6:6] + read-write + + + DESCR_BUS_ERROR + Activated (set to '1') on a bus error for a load of the descriptor. + [7:7] + read-write + + + + + INTR_SET + Interrupt set + 0x84 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). + [0:0] + read-write + + + SRC_BUS_ERROR + Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). + [1:1] + read-write + + + DST_BUS_ERROR + Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). + [2:2] + read-write + + + SRC_MISAL + Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). + [3:3] + read-write + + + DST_MISAL + Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). + [4:4] + read-write + + + CURR_PTR_NULL + Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). + [6:6] + read-write + + + DESCR_BUS_ERROR + Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask + 0x88 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Mask for INTR.COMPLETION interrupt. + [0:0] + read-write + + + SRC_BUS_ERROR + Mask for INTR.SRC_BUS_ERROR interrupt. + [1:1] + read-write + + + DST_BUS_ERROR + Mask for INTR.DST_BUS_ERROR interrupt. + [2:2] + read-write + + + SRC_MISAL + Mask for INTR.SRC_MISAL interrupt. + [3:3] + read-write + + + DST_MISAL + Mask for INTR.DST_MISAL interrupt. + [4:4] + read-write + + + CURR_PTR_NULL + Mask for INTR.CURR_PTR_NULL interrupt. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Mask for INTR.ACTIVE_CH_DISABLED interrupt. + [6:6] + read-write + + + DESCR_BUS_ERROR + Mask for INTR.DESCR_BUS_ERROR interrupt. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x8C + 32 + read-only + 0x0 + 0xFF + + + COMPLETION + Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. + [0:0] + read-only + + + SRC_BUS_ERROR + Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. + [1:1] + read-only + + + DST_BUS_ERROR + Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. + [2:2] + read-only + + + SRC_MISAL + Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. + [3:3] + read-only + + + DST_MISAL + Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. + [4:4] + read-only + + + CURR_PTR_NULL + Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. + [5:5] + read-only + + + ACTIVE_CH_DISABLED + Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. + [6:6] + read-only + + + DESCR_BUS_ERROR + Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. + [7:7] + read-only + + + + + + + + EFUSE + EFUSE MXS40 registers + 0x402C0000 + + 0 + 128 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + + + CMD + Command + 0x10 + 32 + read-write + 0x1 + 0x800F1F71 + + + BIT_DATA + Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. + [0:0] + read-write + + + BIT_ADDR + Bit address. This field specifies a bit within a Byte. + [6:4] + read-write + + + BYTE_ADDR + Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). + [12:8] + read-write + + + MACRO_ADDR + Macro address. This field specifies an eFUSE macro. + [19:16] + read-write + + + START + FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. + +Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. + +Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. + +Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. + [31:31] + read-write + + + + + SEQ_DEFAULT + Sequencer Default value + 0x20 + 32 + read-write + 0x1D0000 + 0x7F0000 + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + + + SEQ_READ_CTL_0 + Sequencer read control 0 + 0x40 + 32 + read-write + 0x80560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_1 + Sequencer read control 1 + 0x44 + 32 + read-write + 0x540004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_2 + Sequencer read control 2 + 0x48 + 32 + read-write + 0x560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_3 + Sequencer read control 3 + 0x4C + 32 + read-write + 0x540003 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_4 + Sequencer read control 4 + 0x50 + 32 + read-write + 0x80150001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_5 + Sequencer read control 5 + 0x54 + 32 + read-write + 0x310004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_0 + Sequencer program control 0 + 0x60 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_1 + Sequencer program control 1 + 0x64 + 32 + read-write + 0x220020 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_2 + Sequencer program control 2 + 0x68 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_3 + Sequencer program control 3 + 0x6C + 32 + read-write + 0x310005 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_4 + Sequencer program control 4 + 0x70 + 32 + read-write + 0x80350006 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_5 + Sequencer program control 5 + 0x74 + 32 + read-write + 0x803D0019 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + + + HSIOM + High Speed IO Matrix (HSIOM) + 0x40300000 + + 0 + 16384 + registers + + + + 15 + 16 + PRT[%s] + HSIOM port registers + 0x00000000 + + PORT_SEL0 + Port selection 0 + 0x0 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO0_SEL + Selects connection for IO pin 0 route. + [4:0] + read-write + + + GPIO + GPIO controls 'out' + 0 + + + GPIO_DSI + GPIO controls 'out', DSI controls 'output enable' + 1 + + + DSI_DSI + DSI controls 'out' and 'output enable' + 2 + + + DSI_GPIO + DSI controls 'out', GPIO controls 'output enable' + 3 + + + AMUXA + Analog mux bus A + 4 + + + AMUXB + Analog mux bus B + 5 + + + AMUXA_DSI + Analog mux bus A, DSI control + 6 + + + AMUXB_DSI + Analog mux bus B, DSI control + 7 + + + ACT_0 + Active functionality 0 + 8 + + + ACT_1 + Active functionality 1 + 9 + + + ACT_2 + Active functionality 2 + 10 + + + ACT_3 + Active functionality 3 + 11 + + + DS_0 + DeepSleep functionality 0 + 12 + + + DS_1 + DeepSleep functionality 1 + 13 + + + DS_2 + DeepSleep functionality 2 + 14 + + + DS_3 + DeepSleep functionality 3 + 15 + + + ACT_4 + Active functionality 4 + 16 + + + ACT_5 + Active functionality 5 + 17 + + + ACT_6 + Active functionality 6 + 18 + + + ACT_7 + Active functionality 7 + 19 + + + ACT_8 + Active functionality 8 + 20 + + + ACT_9 + Active functionality 9 + 21 + + + ACT_10 + Active functionality 10 + 22 + + + ACT_11 + Active functionality 11 + 23 + + + ACT_12 + Active functionality 12 + 24 + + + ACT_13 + Active functionality 13 + 25 + + + ACT_14 + Active functionality 14 + 26 + + + ACT_15 + Active functionality 15 + 27 + + + DS_4 + DeepSleep functionality 4 + 28 + + + DS_5 + DeepSleep functionality 5 + 29 + + + DS_6 + DeepSleep functionality 6 + 30 + + + DS_7 + DeepSleep functionality 7 + 31 + + + + + IO1_SEL + Selects connection for IO pin 1 route. + [12:8] + read-write + + + IO2_SEL + Selects connection for IO pin 2 route. + [20:16] + read-write + + + IO3_SEL + Selects connection for IO pin 3 route. + [28:24] + read-write + + + + + PORT_SEL1 + Port selection 1 + 0x4 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO4_SEL + Selects connection for IO pin 4 route. +See PORT_SEL0 for connection details. + [4:0] + read-write + + + IO5_SEL + Selects connection for IO pin 5 route. + [12:8] + read-write + + + IO6_SEL + Selects connection for IO pin 6 route. + [20:16] + read-write + + + IO7_SEL + Selects connection for IO pin 7 route. + [28:24] + read-write + + + + + + 64 + 4 + AMUX_SPLIT_CTL[%s] + AMUX splitter cell control + 0x2000 + 32 + read-write + 0x0 + 0x77 + + + SWITCH_AA_SL + T-switch control for Left AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [0:0] + read-write + + + SWITCH_AA_SR + T-switch control for Right AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [1:1] + read-write + + + SWITCH_AA_S0 + T-switch control for AMUXBUSA vssa/ground switch: +'0': switch open. +'1': switch closed. + [2:2] + read-write + + + SWITCH_BB_SL + T-switch control for Left AMUXBUSB switch. + [4:4] + read-write + + + SWITCH_BB_SR + T-switch control for Right AMUXBUSB switch. + [5:5] + read-write + + + SWITCH_BB_S0 + T-switch control for AMUXBUSB vssa/ground switch. + [6:6] + read-write + + + + + MONITOR_CTL_0 + Power/Ground Monitor cell control 0 + 0x2200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_1 + Power/Ground Monitor cell control 1 + 0x2204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_2 + Power/Ground Monitor cell control 2 + 0x2208 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_3 + Power/Ground Monitor cell control 3 + 0x220C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + ALT_JTAG_EN + Alternate JTAG IF selection register + 0x2240 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + Provides the selection for alternate JTAG IF connectivity. +0: Primary JTAG interface is selected +1: Secondary (alternate) JTAG interface is selected. + +This connectivity works ONLY in ACTIVE mode. + [31:31] + read-write + + + + + + + GPIO + GPIO port control/configuration + 0x40310000 + + 0 + 65536 + registers + + + + 15 + 128 + PRT[%s] + GPIO port registers + 0x00000000 + + OUT + Port output data register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO output data for pin 0 +'0': Output state set to '0' +'1': Output state set to '1' + [0:0] + read-write + + + OUT1 + IO output data for pin 1 + [1:1] + read-write + + + OUT2 + IO output data for pin 2 + [2:2] + read-write + + + OUT3 + IO output data for pin 3 + [3:3] + read-write + + + OUT4 + IO output data for pin 4 + [4:4] + read-write + + + OUT5 + IO output data for pin 5 + [5:5] + read-write + + + OUT6 + IO output data for pin 6 + [6:6] + read-write + + + OUT7 + IO output data for pin 7 + [7:7] + read-write + + + + + OUT_CLR + Port output data clear register + 0x4 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO clear output for pin 0: +'0': Output state not affected. +'1': Output state set to '0'. + [0:0] + read-write + + + OUT1 + IO clear output for pin 1 + [1:1] + read-write + + + OUT2 + IO clear output for pin 2 + [2:2] + read-write + + + OUT3 + IO clear output for pin 3 + [3:3] + read-write + + + OUT4 + IO clear output for pin 4 + [4:4] + read-write + + + OUT5 + IO clear output for pin 5 + [5:5] + read-write + + + OUT6 + IO clear output for pin 6 + [6:6] + read-write + + + OUT7 + IO clear output for pin 7 + [7:7] + read-write + + + + + OUT_SET + Port output data set register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO set output for pin 0: +'0': Output state not affected. +'1': Output state set to '1'. + [0:0] + read-write + + + OUT1 + IO set output for pin 1 + [1:1] + read-write + + + OUT2 + IO set output for pin 2 + [2:2] + read-write + + + OUT3 + IO set output for pin 3 + [3:3] + read-write + + + OUT4 + IO set output for pin 4 + [4:4] + read-write + + + OUT5 + IO set output for pin 5 + [5:5] + read-write + + + OUT6 + IO set output for pin 6 + [6:6] + read-write + + + OUT7 + IO set output for pin 7 + [7:7] + read-write + + + + + OUT_INV + Port output data invert register + 0xC + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO invert output for pin 0: +'0': Output state not affected. +'1': Output state inverted ('0' => '1', '1' => '0'). + [0:0] + read-write + + + OUT1 + IO invert output for pin 1 + [1:1] + read-write + + + OUT2 + IO invert output for pin 2 + [2:2] + read-write + + + OUT3 + IO invert output for pin 3 + [3:3] + read-write + + + OUT4 + IO invert output for pin 4 + [4:4] + read-write + + + OUT5 + IO invert output for pin 5 + [5:5] + read-write + + + OUT6 + IO invert output for pin 6 + [6:6] + read-write + + + OUT7 + IO invert output for pin 7 + [7:7] + read-write + + + + + IN + Port input state register + 0x10 + 32 + read-only + 0x0 + 0x1FF + + + IN0 + IO pin state for pin 0 +'0': Low logic level present on pin. +'1': High logic level present on pin. +On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. + [0:0] + read-only + + + IN1 + IO pin state for pin 1 + [1:1] + read-only + + + IN2 + IO pin state for pin 2 + [2:2] + read-only + + + IN3 + IO pin state for pin 3 + [3:3] + read-only + + + IN4 + IO pin state for pin 4 + [4:4] + read-only + + + IN5 + IO pin state for pin 5 + [5:5] + read-only + + + IN6 + IO pin state for pin 6 + [6:6] + read-only + + + IN7 + IO pin state for pin 7 + [7:7] + read-only + + + FLT_IN + Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. + [8:8] + read-only + + + + + INTR + Port interrupt status register + 0x14 + 32 + read-write + 0x0 + 0x1FF01FF + + + EDGE0 + Edge detect for IO pin 0 +'0': No edge was detected on pin. +'1': An edge was detected on pin. + [0:0] + read-write + + + EDGE1 + Edge detect for IO pin 1 + [1:1] + read-write + + + EDGE2 + Edge detect for IO pin 2 + [2:2] + read-write + + + EDGE3 + Edge detect for IO pin 3 + [3:3] + read-write + + + EDGE4 + Edge detect for IO pin 4 + [4:4] + read-write + + + EDGE5 + Edge detect for IO pin 5 + [5:5] + read-write + + + EDGE6 + Edge detect for IO pin 6 + [6:6] + read-write + + + EDGE7 + Edge detect for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Edge detected on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + IN_IN0 + IO pin state for pin 0 + [16:16] + read-only + + + IN_IN1 + IO pin state for pin 1 + [17:17] + read-only + + + IN_IN2 + IO pin state for pin 2 + [18:18] + read-only + + + IN_IN3 + IO pin state for pin 3 + [19:19] + read-only + + + IN_IN4 + IO pin state for pin 4 + [20:20] + read-only + + + IN_IN5 + IO pin state for pin 5 + [21:21] + read-only + + + IN_IN6 + IO pin state for pin 6 + [22:22] + read-only + + + IN_IN7 + IO pin state for pin 7 + [23:23] + read-only + + + FLT_IN_IN + Filtered pin state for pin selected by INTR_CFG.FLT_SEL + [24:24] + read-only + + + + + INTR_MASK + Port interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Masks edge interrupt on IO pin 0 +'0': Pin interrupt forwarding disabled +'1': Pin interrupt forwarding enabled + [0:0] + read-write + + + EDGE1 + Masks edge interrupt on IO pin 1 + [1:1] + read-write + + + EDGE2 + Masks edge interrupt on IO pin 2 + [2:2] + read-write + + + EDGE3 + Masks edge interrupt on IO pin 3 + [3:3] + read-write + + + EDGE4 + Masks edge interrupt on IO pin 4 + [4:4] + read-write + + + EDGE5 + Masks edge interrupt on IO pin 5 + [5:5] + read-write + + + EDGE6 + Masks edge interrupt on IO pin 6 + [6:6] + read-write + + + EDGE7 + Masks edge interrupt on IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_MASKED + Port interrupt masked status register + 0x1C + 32 + read-only + 0x0 + 0x1FF + + + EDGE0 + Edge detected AND masked on IO pin 0 +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [0:0] + read-only + + + EDGE1 + Edge detected and masked on IO pin 1 + [1:1] + read-only + + + EDGE2 + Edge detected and masked on IO pin 2 + [2:2] + read-only + + + EDGE3 + Edge detected and masked on IO pin 3 + [3:3] + read-only + + + EDGE4 + Edge detected and masked on IO pin 4 + [4:4] + read-only + + + EDGE5 + Edge detected and masked on IO pin 5 + [5:5] + read-only + + + EDGE6 + Edge detected and masked on IO pin 6 + [6:6] + read-only + + + EDGE7 + Edge detected and masked on IO pin 7 + [7:7] + read-only + + + FLT_EDGE + Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-only + + + + + INTR_SET + Port interrupt set register + 0x20 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Sets edge detect interrupt for IO pin 0 +'0': Interrupt state not affected +'1': Interrupt set + [0:0] + read-write + + + EDGE1 + Sets edge detect interrupt for IO pin 1 + [1:1] + read-write + + + EDGE2 + Sets edge detect interrupt for IO pin 2 + [2:2] + read-write + + + EDGE3 + Sets edge detect interrupt for IO pin 3 + [3:3] + read-write + + + EDGE4 + Sets edge detect interrupt for IO pin 4 + [4:4] + read-write + + + EDGE5 + Sets edge detect interrupt for IO pin 5 + [5:5] + read-write + + + EDGE6 + Sets edge detect interrupt for IO pin 6 + [6:6] + read-write + + + EDGE7 + Sets edge detect interrupt for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_CFG + Port interrupt configuration register + 0x40 + 32 + read-write + 0x0 + 0x1FFFFF + + + EDGE0_SEL + Sets which edge will trigger an IRQ for IO pin 0 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + EDGE1_SEL + Sets which edge will trigger an IRQ for IO pin 1 + [3:2] + read-write + + + EDGE2_SEL + Sets which edge will trigger an IRQ for IO pin 2 + [5:4] + read-write + + + EDGE3_SEL + Sets which edge will trigger an IRQ for IO pin 3 + [7:6] + read-write + + + EDGE4_SEL + Sets which edge will trigger an IRQ for IO pin 4 + [9:8] + read-write + + + EDGE5_SEL + Sets which edge will trigger an IRQ for IO pin 5 + [11:10] + read-write + + + EDGE6_SEL + Sets which edge will trigger an IRQ for IO pin 6 + [13:12] + read-write + + + EDGE7_SEL + Sets which edge will trigger an IRQ for IO pin 7 + [15:14] + read-write + + + FLT_EDGE_SEL + Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + FLT_SEL + Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. + [20:18] + read-write + + + + + CFG + Port configuration register + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DRIVE_MODE0 + The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [2:0] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Weak/resistive pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull up + D_OUT = '1': Weak/resistive pull up + 2 + + + PULLDOWN + Resistive pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': High Impedance +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 4 + + + OD_DRIVESHIGH + Open drain, drives high + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': High Impedance + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 5 + + + STRONG + Strong D_OUTput buffer + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 6 + + + PULLUP_DOWN + Pull up or pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = '0': + GPIO_DSI_OUT = '0': Weak/resistive pull down + GPIO_DSI_OUT = '1': Weak/resistive pull up +where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull up + 7 + + + + + IN_EN0 + Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. +'0': Input buffer disabled +'1': Input buffer enabled + [3:3] + read-write + + + DRIVE_MODE1 + The GPIO drive mode for IO pin 1 + [6:4] + read-write + + + IN_EN1 + Enables the input buffer for IO pin 1 + [7:7] + read-write + + + DRIVE_MODE2 + The GPIO drive mode for IO pin 2 + [10:8] + read-write + + + IN_EN2 + Enables the input buffer for IO pin 2 + [11:11] + read-write + + + DRIVE_MODE3 + The GPIO drive mode for IO pin 3 + [14:12] + read-write + + + IN_EN3 + Enables the input buffer for IO pin 3 + [15:15] + read-write + + + DRIVE_MODE4 + The GPIO drive mode for IO pin4 + [18:16] + read-write + + + IN_EN4 + Enables the input buffer for IO pin 4 + [19:19] + read-write + + + DRIVE_MODE5 + The GPIO drive mode for IO pin 5 + [22:20] + read-write + + + IN_EN5 + Enables the input buffer for IO pin 5 + [23:23] + read-write + + + DRIVE_MODE6 + The GPIO drive mode for IO pin 6 + [26:24] + read-write + + + IN_EN6 + Enables the input buffer for IO pin 6 + [27:27] + read-write + + + DRIVE_MODE7 + The GPIO drive mode for IO pin 7 + [30:28] + read-write + + + IN_EN7 + Enables the input buffer for IO pin 7 + [31:31] + read-write + + + + + CFG_IN + Port input buffer configuration register + 0x48 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_0 + Configures the pin 0 input buffer mode (trip points and hysteresis) + [0:0] + read-write + + + CMOS + PSoC 6:: Input buffer compatible with CMOS and I2C interfaces +Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 0 + + + TTL + PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces +Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 1 + + + + + VTRIP_SEL1_0 + Configures the pin 1 input buffer mode (trip points and hysteresis) + [1:1] + read-write + + + VTRIP_SEL2_0 + Configures the pin 2 input buffer mode (trip points and hysteresis) + [2:2] + read-write + + + VTRIP_SEL3_0 + Configures the pin 3 input buffer mode (trip points and hysteresis) + [3:3] + read-write + + + VTRIP_SEL4_0 + Configures the pin 4 input buffer mode (trip points and hysteresis) + [4:4] + read-write + + + VTRIP_SEL5_0 + Configures the pin 5 input buffer mode (trip points and hysteresis) + [5:5] + read-write + + + VTRIP_SEL6_0 + Configures the pin 6 input buffer mode (trip points and hysteresis) + [6:6] + read-write + + + VTRIP_SEL7_0 + Configures the pin 7 input buffer mode (trip points and hysteresis) + [7:7] + read-write + + + + + CFG_OUT + Port output buffer configuration register + 0x4C + 32 + read-write + 0x0 + 0xFFFF00FF + + + SLOW0 + Enables slow slew rate for IO pin 0 +'0': Fast slew rate +'1': Slow slew rate + [0:0] + read-write + + + SLOW1 + Enables slow slew rate for IO pin 1 + [1:1] + read-write + + + SLOW2 + Enables slow slew rate for IO pin 2 + [2:2] + read-write + + + SLOW3 + Enables slow slew rate for IO pin 3 + [3:3] + read-write + + + SLOW4 + Enables slow slew rate for IO pin 4 + [4:4] + read-write + + + SLOW5 + Enables slow slew rate for IO pin 5 + [5:5] + read-write + + + SLOW6 + Enables slow slew rate for IO pin 6 + [6:6] + read-write + + + SLOW7 + Enables slow slew rate for IO pin 7 + [7:7] + read-write + + + DRIVE_SEL0 + Sets the GPIO drive strength for IO pin 0 + [17:16] + read-write + + + DRIVE_SEL_ZERO + Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +Traveo II:_GPIO_SMC: GPIO_SMC default mode. +Traveo II:_HSIO_STD: HSIO default mode. +PSoC 6: GPIO cells and HSIO_STD cells: Full drive strength: GPIO drives current at its max rated spec. + 0 + + + DRIVE_SEL_ONE + Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +Traveo II:_GPIO_SMC: GPIO full drive strength. +Traveo II:_HSIO_STD: GPIO full drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec + 1 + + + DRIVE_SEL_TWO + Traveo II: GPIO_STD/GPIO_ENH: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec. +Traveo II:_GPIO_SMC: GPIO 1/2 drive strength. +Traveo II:_HSIO_STD: GPIO 1/2 drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/4 drive strength. GPIO drives current at 1/4 of its max rated spec. + 2 + + + DRIVE_SEL_THREE + Traveo II: GPIO_STD/GPIO_ENH: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec. +Traveo II:_GPIO_SMC: GPIO 1/4 drive strength. +Traveo II:_HSIO_STD: GPIO 1/4 drive strength. +PSoC 6: GPIO cells and HSIO_STD cells: 1/8 drive strength. GPIO drives current at 1/8 of its max rated spec. + 3 + + + + + DRIVE_SEL1 + Sets the GPIO drive strength for IO pin 1 + [19:18] + read-write + + + DRIVE_SEL2 + Sets the GPIO drive strength for IO pin 2 + [21:20] + read-write + + + DRIVE_SEL3 + Sets the GPIO drive strength for IO pin 3 + [23:22] + read-write + + + DRIVE_SEL4 + Sets the GPIO drive strength for IO pin 4 + [25:24] + read-write + + + DRIVE_SEL5 + Sets the GPIO drive strength for IO pin 5 + [27:26] + read-write + + + DRIVE_SEL6 + Sets the GPIO drive strength for IO pin 6 + [29:28] + read-write + + + DRIVE_SEL7 + Sets the GPIO drive strength for IO pin 7 + [31:30] + read-write + + + + + CFG_SIO + Port SIO configuration register + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VREG_EN01 + Selects the output buffer mode: +'0': Unregulated output buffer +'1': Regulated output buffer +The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. + [0:0] + read-write + + + IBUF_SEL01 + Selects the input buffer mode: +0: Singled ended input buffer +1: Differential input buffer + [1:1] + read-write + + + VTRIP_SEL01 + Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): +'0': Input buffer functions as a CMOS input buffer. +'1': Input buffer functions as a TTL input buffer. +In differential input buffer mode (IBUF_SEL = '1') +'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) +'1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) + [2:2] + read-write + + + VREF_SEL01 + Selects reference voltage (Vref) trip-point of the input buffer: +'0': Trip-point reference from pin_ref +'1': Trip-point reference of SRSS internal reference Vref (1.2 V) +'2': Trip-point reference of AMUXBUS_A +'3': Trip-point reference of AMUXBUS_B + [4:3] + read-write + + + VOH_SEL01 + Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). +'0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V +'1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V +'2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V +'3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V +'4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V +'5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V +'6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V +'7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V +Note: The upper value on Voh is limited to Vddio - 400mV + [7:5] + read-write + + + VREG_EN23 + See corresponding definition for IO pins 0 and 1 + [8:8] + read-write + + + IBUF_SEL23 + See corresponding definition for IO pins 0 and 1 + [9:9] + read-write + + + VTRIP_SEL23 + See corresponding definition for IO pins 0 and 1 + [10:10] + read-write + + + VREF_SEL23 + See corresponding definition for IO pins 0 and 1 + [12:11] + read-write + + + VOH_SEL23 + See corresponding definition for IO pins 0 and 1 + [15:13] + read-write + + + VREG_EN45 + See corresponding definition for IO pins 0 and 1 + [16:16] + read-write + + + IBUF_SEL45 + See corresponding definition for IO pins 0 and 1 + [17:17] + read-write + + + VTRIP_SEL45 + See corresponding definition for IO pins 0 and 1 + [18:18] + read-write + + + VREF_SEL45 + See corresponding definition for IO pins 0 and 1 + [20:19] + read-write + + + VOH_SEL45 + See corresponding definition for IO pins 0 and 1 + [23:21] + read-write + + + VREG_EN67 + See corresponding definition for IO pins 0 and 1 + [24:24] + read-write + + + IBUF_SEL67 + See corresponding definition for IO pins 0 and 1 + [25:25] + read-write + + + VTRIP_SEL67 + See corresponding definition for IO pins 0 and 1 + [26:26] + read-write + + + VREF_SEL67 + See corresponding definition for IO pins 0 and 1 + [28:27] + read-write + + + VOH_SEL67 + See corresponding definition for IO pins 0 and 1 + [31:29] + read-write + + + + + CFG_IN_AUTOLVL + Port input buffer AUTOLVL configuration register + 0x58 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_1 + Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: +{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: +0,0: CMOS +0,1: TTL +1,0: input buffer is compatible with automotive. +1,1: input buffer is compatible with automotvie + [0:0] + read-write + + + CMOS_OR_TTL + Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. + 0 + + + AUTO + Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. + 1 + + + + + VTRIP_SEL1_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [1:1] + read-write + + + VTRIP_SEL2_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [2:2] + read-write + + + VTRIP_SEL3_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [3:3] + read-write + + + VTRIP_SEL4_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [4:4] + read-write + + + VTRIP_SEL5_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [5:5] + read-write + + + VTRIP_SEL6_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [6:6] + read-write + + + VTRIP_SEL7_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [7:7] + read-write + + + + + + INTR_CAUSE0 + Interrupt port cause register 0 + 0x4000 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE1 + Interrupt port cause register 1 + 0x4004 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE2 + Interrupt port cause register 2 + 0x4008 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE3 + Interrupt port cause register 3 + 0x400C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + VDD_ACTIVE + Extern power supply detection register + 0x4010 + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. +'0': Supply is not present +'1': Supply is present + +When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. +For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: +0: vbackup, +1: vddio_0, +2: vddio_1, +3: vddio_a, +4: vddio_r, +5: vddusb' + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) + [31:31] + read-only + + + + + VDD_INTR + Supply detection interrupt register + 0x4014 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply state change detected. +'0': No change to supply detected +'1': Change to supply detected + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. + [31:31] + read-write + + + + + VDD_INTR_MASK + Supply detection interrupt mask register + 0x4018 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Masks supply interrupt on VDDIO. +'0': VDDIO interrupt forwarding disabled +'1': VDDIO interrupt forwarding enabled + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + VDD_INTR_MASKED + Supply detection interrupt masked register + 0x401C + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply transition detected AND masked +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-only + + + + + VDD_INTR_SET + Supply detection interrupt set register + 0x4020 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Sets supply interrupt. +'0': Interrupt state not affected +'1': Interrupt set + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + + + SMARTIO + Programmable IO configuration + 0x40320000 + + 0 + 65536 + registers + + + + 10 + 256 + PRT[%s] + Programmable IO port registers + 0x00000000 + + CTL + Control register + 0x0 + 32 + read-write + 0x2001400 + 0x82001F00 + + + BYPASS + Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. +'0': No bypass (programmable SMARTIO fabric is exposed). +'1': Bypass (programmable SMARTIOIO fabric is hidden). + [7:0] + read-write + + + CLOCK_SRC + Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: +'0': io_data_in[0]/'1'. +... +'7': io_data_in[7]/'1'. +'8': chip_data[0]/'1'. +... +'15': chip_data[7]/'1'. +'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. +'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. +'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. +'31': asynchronous mode/'1'. Select this when clockless operation is configured. + +NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. + [12:8] + read-write + + + HLD_OVR + IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: +'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). +'1': The SMARTIO controls the IO cel hold override functionality: +- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. +- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). + [24:24] + read-write + + + PIPELINE_EN + Enable for pipeline register: +'0': Disabled (register is bypassed). +'1': Enabled. + [25:25] + read-write + + + ENABLED + Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: +'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. + +If the IP is disabled: +- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. +- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. + +'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. + [31:31] + read-write + + + + + SYNC_CTL + Synchronization control register + 0x10 + 32 + read-write + 0x0 + 0x0 + + + IO_SYNC_EN + Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. +'0': No synchronization. +'1': Synchronization. + [7:0] + read-write + + + CHIP_SYNC_EN + Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. +'0': No synchronization. +'1': Synchronization. + [15:8] + read-write + + + + + 8 + 4 + LUT_SEL[%s] + LUT component input selection + 0x20 + 32 + read-write + 0x0 + 0x0 + + + LUT_TR0_SEL + LUT input signal 'tr0_in' source selection: +'0': Data unit output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [3:0] + read-write + + + LUT_TR1_SEL + LUT input signal 'tr1_in' source selection: +'0': LUT 0 output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [11:8] + read-write + + + LUT_TR2_SEL + LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. + [19:16] + read-write + + + + + 8 + 4 + LUT_CTL[%s] + LUT component control register + 0x40 + 32 + read-write + 0x0 + 0x0 + + + LUT + LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). + [7:0] + read-write + + + LUT_OPC + LUT opcode specifies the LUT operation: +'0': Combinatoral output, no feedback. + tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. +'1': Combinatorial output, feedback. + tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. +On clock: + lut_reg <= tr_in2. +'2': Sequential output, no feedback. + temp = LUT[{tr2_in, tr1_in, tr0_in}]. + tr_out = lut_reg. +On clock: + lut_reg <= temp. +'3': Register with asynchronous set and reset. + tr_out = lut_reg. + enable = (tr2_in ^ LUT[4]) | LUT[5]. + set = enable & (tr1_in ^ LUT[2]) & LUT[3]. + clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. +Asynchronously (no clock required): + lut_reg <= if (clr) '0' else if (set) '1' + [9:8] + read-write + + + + + DU_SEL + Data unit component input selection + 0xC0 + 32 + read-write + 0x0 + 0x0 + + + DU_TR0_SEL + Data unit input signal 'tr0_in' source selection: +'0': Constant '0'. +'1': Constant '1'. +'2': Data unit output. +'10-3': LUT 7 - 0 outputs. +Otherwise: Undefined. + [3:0] + read-write + + + DU_TR1_SEL + Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. + [11:8] + read-write + + + DU_TR2_SEL + Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. + [19:16] + read-write + + + DU_DATA0_SEL + Data unit input data 'data0_in' source selection: +'0': Constant '0'. +'1': chip_data[7:0]. +'2': io_data_in[7:0]. +'3': DATA.DATA MMIO register field. + [25:24] + read-write + + + DU_DATA1_SEL + Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. + [29:28] + read-write + + + + + DU_CTL + Data unit component control register + 0xC4 + 32 + read-write + 0x0 + 0x0 + + + DU_SIZE + Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. + [2:0] + read-write + + + DU_OPC + Data unit opcode specifies the data unit operation: +'1': INCR +'2': DECR +'3': INCR_WRAP +'4': DECR_WRAP +'5': INCR_DECR +'6': INCR_DECR_WRAP +'7': ROR +'8': SHR +'9': AND_OR +'10': SHR_MAJ3 +'11': SHR_EQL. +Otherwise: Undefined. + [11:8] + read-write + + + + + DATA + Data register + 0xF0 + 32 + read-write + 0x0 + 0x0 + + + DATA + Data unit input data source. + [7:0] + read-write + + + + + + + + LPCOMP + Low Power Comparators + 0x40350000 + + 0 + 65536 + registers + + + + CONFIG + LPCOMP Configuration Register + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + LPREF_EN + Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. + [30:30] + read-write + + + ENABLED + - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) +- 1: IP enabled + [31:31] + read-write + + + + + STATUS + LPCOMP Status Register + 0x4 + 32 + read-only + 0x0 + 0x10001 + + + OUT0 + Current output value of the comparator 0. + [0:0] + read-only + + + OUT1 + Current output value of the comparator 1. + [16:16] + read-only + + + + + INTR + LPCOMP Interrupt request register + 0x10 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + LPCOMP Interrupt set register + 0x14 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + LPCOMP Interrupt request mask + 0x18 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + LPCOMP Interrupt request masked + 0x1C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + CMP0_CTRL + Comparator 0 control Register + 0x40 + 32 + read-write + 0x0 + 0xCE3 + + + MODE0 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST0 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE0 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS0 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL0 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP0_SW + Comparator 0 switch control + 0x50 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + Comparator 0 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP0_AP0 + Comparator 0 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP0_BP0 + Comparator 0 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP0_IN0 + Comparator 0 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP0_AN0 + Comparator 0 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP0_BN0 + Comparator 0 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP0_VN0 + Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP0_SW_CLEAR + Comparator 0 switch control clear + 0x54 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + see corresponding bit in CMP0_SW + [0:0] + read-write + + + CMP0_AP0 + see corresponding bit in CMP0_SW + [1:1] + read-write + + + CMP0_BP0 + see corresponding bit in CMP0_SW + [2:2] + read-write + + + CMP0_IN0 + see corresponding bit in CMP0_SW + [4:4] + read-write + + + CMP0_AN0 + see corresponding bit in CMP0_SW + [5:5] + read-write + + + CMP0_BN0 + see corresponding bit in CMP0_SW + [6:6] + read-write + + + CMP0_VN0 + see corresponding bit in CMP0_SW + [7:7] + read-write + + + + + CMP1_CTRL + Comparator 1 control Register + 0x80 + 32 + read-write + 0x0 + 0xCE3 + + + MODE1 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST1 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE1 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS1 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL1 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP1_SW + Comparator 1 switch control + 0x90 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + Comparator 1 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP1_AP1 + Comparator 1 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP1_BP1 + Comparator 1 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP1_IN1 + Comparator 1 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP1_AN1 + Comparator 1 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP1_BN1 + Comparator 1 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP1_VN1 + Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP1_SW_CLEAR + Comparator 1 switch control clear + 0x94 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + see corresponding bit in CMP1_SW + [0:0] + read-write + + + CMP1_AP1 + see corresponding bit in CMP1_SW + [1:1] + read-write + + + CMP1_BP1 + see corresponding bit in CMP1_SW + [2:2] + read-write + + + CMP1_IN1 + see corresponding bit in CMP1_SW + [4:4] + read-write + + + CMP1_AN1 + see corresponding bit in CMP1_SW + [5:5] + read-write + + + CMP1_BN1 + see corresponding bit in CMP1_SW + [6:6] + read-write + + + CMP1_VN1 + see corresponding bit in CMP1_SW + [7:7] + read-write + + + + + + + CSD0 + Capsense Controller + CSD + 0x40360000 + + 0 + 4096 + registers + + + + CONFIG + Configuration and Control + 0x0 + 32 + read-write + 0x4000000 + 0xCF0E1DF1 + + + IREF_SEL + Select Iref supply. + [0:0] + read-write + + + IREF_SRSS + select SRSS Iref (default) + 0 + + + IREF_PASS + select PASS.AREF Iref, only available if PASS IP is on the chip. + 1 + + + + + FILTER_DELAY + This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on. +When set to 0 the digital filter is off. When set to any other value the ignoring will last for FILTER_DELAY clk_csd cycles after the start of each measurement and from the first comparator trip to the end of each measurement. + [8:4] + read-write + + + SHIELD_DELAY + Selects the delay by which csd_shield is delayed relative to csd_sense. + [11:10] + read-write + + + OFF + Delay line is off, csd_shield=csd_sense + 0 + + + D5NS + Introduces a 5ns delay (typ) + 1 + + + D10NS + Introduces a 10ns delay (typ) + 2 + + + D20NS + Introduces a 20ns delay (typ) + 3 + + + + + SENSE_EN + Enables the sense modulator output. +0: all switches, static or dynamic, are open and IDAC in CSD mode is off +1: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer. + [12:12] + read-write + + + FULL_WAVE + Enables full wave cap sensing mode + [17:17] + read-write + + + HALFWAVE + Half Wave mode (normal). +In this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change. + 0 + + + FULLWAVE + Full Wave mode. +In this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips. + 1 + + + + + MUTUAL_CAP + Enables mutual cap sensing mode + [18:18] + read-write + + + SELFCAP + Self-cap mode (configure sense line as CSD_SENSE) + 0 + + + MUTUALCAP + Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense. + 1 + + + + + CSX_DUAL_CNT + Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUTUAL_CAP=0 + [19:19] + read-write + + + ONE + Use one counter for both phases (source and sink). + 0 + + + TWO + Use two counters, separate count for when csd_sense is high and when csd_sense is low. + 1 + + + + + DSI_COUNT_SEL + Select what to output on the dsi_count bus. + [24:24] + read-write + + + CSD_RESULT + depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially. + 0 + + + ADC_RESULT + output ADC_RES.VIN_CNT on the dsi_count bus + 1 + + + + + DSI_SAMPLE_EN + Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER. + [25:25] + read-write + + + SAMPLE_SYNC + Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1). + [26:26] + read-write + + + DSI_SENSE_EN + Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals. + [27:27] + read-write + + + LP_MODE + Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP): +0: High Power mode +1: Low Power mode + [30:30] + read-write + + + ENABLE + Master enable of the CSDv2 IP. Must be set to 1 for any CSDv2, ADC or IDAC operation to function. +When 0 all analog components will be off and all switches will be open. + [31:31] + read-write + + + + + SPARE + Spare MMIO + 0x4 + 32 + read-write + 0x0 + 0xF + + + SPARE + Spare MMIO + [3:0] + read-write + + + + + STATUS + Status Register + 0x80 + 32 + read-only + 0x0 + 0xE + + + CSD_SENSE + Signal used to drive the Cs switches. + [1:1] + read-only + + + HSCMP_OUT + Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized) + [2:2] + read-only + + + C_LT_VREF + Vin < Vref + 0 + + + C_GT_VREF + Vin > Vref + 1 + + + + + CSDCMP_OUT + Output of main sensing comparator (synchronized) + [3:3] + read-only + + + + + STAT_SEQ + Current Sequencer status + 0x84 + 32 + read-only + 0x0 + 0x70007 + + + SEQ_STATE + CSD sequencer state + [2:0] + read-only + + + ADC_STATE + ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) + [18:16] + read-only + + + + + STAT_CNTS + Current status counts + 0x88 + 32 + read-only + 0x0 + 0xFFFF + + + NUM_CONV + Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) + [15:0] + read-only + + + + + STAT_HCNT + Current count of the HSCMP counter + 0x8C + 32 + read-only + 0x0 + 0xFFFF + + + CNT + Current value of HSCMP counter + [15:0] + read-only + + + + + RESULT_VAL1 + Result CSD/CSX accumulation counter value 1 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFF + + + VALUE + Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. + [15:0] + read-only + + + BAD_CONVS + Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. + [23:16] + read-only + + + + + RESULT_VAL2 + Result CSX accumulation counter value 2 + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + VALUE + Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. + [15:0] + read-only + + + + + ADC_RES + ADC measurement + 0xE0 + 32 + read-only + 0x0 + 0xC001FFFF + + + VIN_CNT + Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. + [15:0] + read-only + + + HSCMP_POL + Polarity used for IDACB for this last ADC result, 0= source, 1= sink + [16:16] + read-only + + + ADC_OVERFLOW + This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. + [30:30] + read-only + + + ADC_ABORT + This flag is set when the ADC sequencer was aborted before tripping HSCMP. + [31:31] + read-only + + + + + INTR + CSD Interrupt Request Register + 0xF0 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + A normal sample is complete + [1:1] + read-write + + + INIT + Coarse initialization complete or Sample initialization complete (the latter is typically ignored) + [2:2] + read-write + + + ADC_RES + ADC Result ready + [8:8] + read-write + + + + + INTR_SET + CSD Interrupt set register + 0xF4 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASK + CSD Interrupt mask register + 0xF8 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASKED + CSD Interrupt masked register + 0xFC + 32 + read-only + 0x0 + 0x106 + + + SAMPLE + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + INIT + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + ADC_RES + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + + + HSCMP + High Speed Comparator configuration + 0x180 + 32 + read-write + 0x0 + 0x80000011 + + + HSCMP_EN + High Speed Comparator enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + HSCMP_INVERT + Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT + [4:4] + read-write + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + AMBUF + Reference Generator configuration + 0x184 + 32 + read-write + 0x0 + 0x3 + + + PWR_MODE + Amux buffer power level + [1:0] + read-write + + + OFF + Disable buffer + 0 + + + NORM + On, normal or low power level depending on CONFIG.LP_MODE. + 1 + + + HI + On, high or low power level depending on CONFIG.LP_MODE. + 2 + + + + + + + REFGEN + Reference Generator configuration + 0x188 + 32 + read-write + 0x0 + 0x9F1F71 + + + REFGEN_EN + Reference Generator Enable + [0:0] + read-write + + + OFF + Disable Reference Generator + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + BYPASS + Bypass selected input reference unbuffered to Vrefhi + [4:4] + read-write + + + VDDA_EN + Close Vdda switch to top of resistor string (or Vrefhi?) + [5:5] + read-write + + + RES_EN + Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) + [6:6] + read-write + + + GAIN + Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) + [12:8] + read-write + + + VREFLO_SEL + Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) + [20:16] + read-write + + + VREFLO_INT + Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). + [23:23] + read-write + + + + + CSDCMP + CSD Comparator configuration + 0x18C + 32 + read-write + 0x0 + 0xB0000331 + + + CSDCMP_EN + CSD Comparator Enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + POLARITY_SEL + Select which IDAC polarity to use to detect CSDCMP triggering + [5:4] + read-write + + + IDACA_POL + Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX + 0 + + + IDACB_POL + Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) + 1 + + + DUAL_POL + Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case + 2 + + + + + CMP_PHASE + Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). + [9:8] + read-write + + + FULL + Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + Comparator is active during Phi1 only. Currently no known use-case. + 1 + + + PHI2 + Comparator is active during Phi2 only. Intended usage: CSD Low EMI. + 2 + + + PHI1_2 + Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. + 3 + + + + + CMP_MODE + Select which signal to output on dsi_sample_out. + [28:28] + read-write + + + CSD + CSD mode: output the filtered sample signal on dsi_sample_out + 0 + + + GP + General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. + 1 + + + + + FEEDBACK_MODE + This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. + [29:29] + read-write + + + FLOP + Use feedback from sampling flip-flop (used in most modes). + 0 + + + COMP + Use feedback from comparator directly (used in single Cmod mutual cap sensing only) + 1 + + + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + SW_RES + Switch Resistance configuration + 0x1F0 + 32 + read-write + 0x0 + 0xF00FF + + + RES_HCAV + Select resistance or low EMI (slow ramp) for the HCAV switch + [1:0] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + LOWEMI + Low EMI (slow ramp: 3 switches closed by fixed delay line) + 3 + + + + + RES_HCAG + Select resistance or low EMI for the corresponding switch + [3:2] + read-write + + + RES_HCBV + Select resistance or low EMI for the corresponding switch + [5:4] + read-write + + + RES_HCBG + Select resistance or low EMI for the corresponding switch + [7:6] + read-write + + + RES_F1PM + Select resistance for the corresponding switch + [17:16] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + RSVD + N/A + 3 + + + + + RES_F2PT + Select resistance for the corresponding switch + [19:18] + read-write + + + + + SENSE_PERIOD + Sense clock period + 0x200 + 32 + read-write + 0xC000000 + 0xFF70FFF + + + SENSE_DIV + The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . +Note this is the base divider, clock dithering may change the actual period length. +Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. +In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. + [11:0] + read-write + + + LFSR_SIZE + Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. + [18:16] + read-write + + + OFF + Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) + 0 + + + 6B + 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) + 1 + + + 7B + 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) + 2 + + + 9B + 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) + 3 + + + 10B + 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) + 4 + + + 8B + 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) + 5 + + + 12B + 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) + 6 + + + + + LFSR_SCALE + Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. +The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). +Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. + [23:20] + read-write + + + LFSR_CLEAR + When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. +Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. + [24:24] + read-write + + + SEL_LFSR_MSB + Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. + [25:25] + read-write + + + LFSR_BITS + Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. +Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. + [27:26] + read-write + + + 2B + use 2 bits: range = [-2,1] + 0 + + + 3B + use 3 bits: range = [-4,3] + 1 + + + 4B + use 4 bits: range = [-8,7] + 2 + + + 5B + use 5 bits: range = [-16,15] (default) + 3 + + + + + + + SENSE_DUTY + Sense clock duty cycle + 0x204 + 32 + read-write + 0x0 + 0xD0FFF + + + SENSE_WIDTH + Defines the length of the first phase of the sense clock in clk_csd cycles. +A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. +Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. + [11:0] + read-write + + + SENSE_POL + Polarity of the sense clock +0 = start with low phase (typical for regular negative transfer CSD) +1 = start with high phase + [16:16] + read-write + + + OVERLAP_PHI1 + NonOverlap or not for Phi1 (csd_sense=0). +0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. +1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. + [18:18] + read-write + + + OVERLAP_PHI2 + Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). + [19:19] + read-write + + + + + SW_HS_P_SEL + HSCMP Pos input switch Waveform selection + 0x280 + 32 + read-write + 0x0 + 0x11111111 + + + SW_HMPM + Set HMPM switch +0: static open +1: static closed + [0:0] + read-write + + + SW_HMPT + Set corresponding switch + [4:4] + read-write + + + SW_HMPS + Set corresponding switch + [8:8] + read-write + + + SW_HMMA + Set corresponding switch + [12:12] + read-write + + + SW_HMMB + Set corresponding switch + [16:16] + read-write + + + SW_HMCA + Set corresponding switch + [20:20] + read-write + + + SW_HMCB + Set corresponding switch + [24:24] + read-write + + + SW_HMRH + Set corresponding switch + [28:28] + read-write + + + + + SW_HS_N_SEL + HSCMP Neg input switch Waveform selection + 0x284 + 32 + read-write + 0x0 + 0x77110000 + + + SW_HCCC + Set corresponding switch + [16:16] + read-write + + + SW_HCCD + Set corresponding switch + [20:20] + read-write + + + SW_HCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_HCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_SHIELD_SEL + Shielding switches Waveform selection + 0x288 + 32 + read-write + 0x0 + 0x117777 + + + SW_HCAV + N/A + [2:0] + read-write + + + SW_HCAG + Select waveform for corresponding switch + [6:4] + read-write + + + SW_HCBV + N/A + [10:8] + read-write + + + SW_HCBG + Select waveform for corresponding switch, using csd_shield as base + [14:12] + read-write + + + SW_HCCV + Set corresponding switch + [16:16] + read-write + + + SW_HCCG + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_AMUXBUF_SEL + Amuxbuffer switches Waveform selection + 0x290 + 32 + read-write + 0x0 + 0x11171110 + + + SW_IRBY + Set corresponding switch + [4:4] + read-write + + + SW_IRLB + Set corresponding switch + [8:8] + read-write + + + SW_ICA + Set corresponding switch + [12:12] + read-write + + + SW_ICB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_IRLI + Set corresponding switch + [20:20] + read-write + + + SW_IRH + Set corresponding switch + [24:24] + read-write + + + SW_IRL + Set corresponding switch + [28:28] + read-write + + + + + SW_BYP_SEL + AMUXBUS bypass switches Waveform selection + 0x294 + 32 + read-write + 0x0 + 0x111000 + + + SW_BYA + Set corresponding switch + [12:12] + read-write + + + SW_BYB + Set corresponding switch + [16:16] + read-write + + + SW_CBCC + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_CMP_P_SEL + CSDCMP Pos Switch Waveform selection + 0x2A0 + 32 + read-write + 0x0 + 0x1111777 + + + SW_SFPM + Select waveform for corresponding switch + [2:0] + read-write + + + SW_SFPT + Select waveform for corresponding switch + [6:4] + read-write + + + SW_SFPS + Select waveform for corresponding switch + [10:8] + read-write + + + SW_SFMA + Set corresponding switch + [12:12] + read-write + + + SW_SFMB + Set corresponding switch + [16:16] + read-write + + + SW_SFCA + Set corresponding switch + [20:20] + read-write + + + SW_SFCB + Set corresponding switch + [24:24] + read-write + + + + + SW_CMP_N_SEL + CSDCMP Neg Switch Waveform selection + 0x2A4 + 32 + read-write + 0x0 + 0x77000000 + + + SW_SCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_SCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_REFGEN_SEL + Reference Generator Switch Waveform selection + 0x2A8 + 32 + read-write + 0x0 + 0x11110011 + + + SW_IAIB + Set corresponding switch + [0:0] + read-write + + + SW_IBCB + Set corresponding switch + [4:4] + read-write + + + SW_SGMB + Set corresponding switch + [16:16] + read-write + + + SW_SGRP + Set corresponding switch + [20:20] + read-write + + + SW_SGRE + Set corresponding switch + [24:24] + read-write + + + SW_SGR + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_MOD_SEL + Full Wave Cmod Switch Waveform selection + 0x2B0 + 32 + read-write + 0x0 + 0x11170701 + + + SW_F1PM + Set corresponding switch + [0:0] + read-write + + + SW_F1MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F1CA + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C1CC + Set corresponding switch + [20:20] + read-write + + + SW_C1CD + Set corresponding switch + [24:24] + read-write + + + SW_C1F1 + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_TANK_SEL + Full Wave Csh_tank Switch Waveform selection + 0x2B4 + 32 + read-write + 0x0 + 0x11177710 + + + SW_F2PT + Set corresponding switch + [4:4] + read-write + + + SW_F2MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F2CA + Select waveform for corresponding switch + [14:12] + read-write + + + SW_F2CB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C2CC + Set corresponding switch + [20:20] + read-write + + + SW_C2CD + Set corresponding switch + [24:24] + read-write + + + SW_C2F2 + Set corresponding switch + [28:28] + read-write + + + + + SW_DSI_SEL + DSI output switch control Waveform selection + 0x2C0 + 32 + read-write + 0x0 + 0xFF + + + DSI_CSH_TANK + Select waveform for dsi_csh_tank output signal +0: static open +1: static closed +2: phi1 +3: phi2 +4: phi1 & HSCMP +5: phi2 & HSCMP +6: HSCMP // ignores phi1/2 +7: !sense // = phi1 but ignores OVERLAP_PHI1 + +8: phi1_delay // phi1 delayed with shield delay +9: phi2_delay // phi2 delayed with shield delay + +10: !phi1 +11: !phi2 +12: !(phi1 & HSCMP) +13: !(phi2 & HSCMP) +14: !HSCMP // ignores phi1/2 +15: sense // = phi2 but ignores OVERLAP_PHI2 + [3:0] + read-write + + + DSI_CMOD + Select waveform for dsi_cmod output signal + [7:4] + read-write + + + + + IO_SEL + IO output control Waveform selection + 0x2D0 + 32 + read-write + 0x0 + 0xFFFF0FF + + + CSD_TX_OUT + Select waveform for csd_tx_out output signal + [3:0] + read-write + + + CSD_TX_OUT_EN + Select waveform for csd_tx_out_en output signal + [7:4] + read-write + + + CSD_TX_AMUXB_EN + Select waveform for csd_tx_amuxb_en output signal + [15:12] + read-write + + + CSD_TX_N_OUT + Select waveform for csd_tx_n_out output signal + [19:16] + read-write + + + CSD_TX_N_OUT_EN + Select waveform for csd_tx_n_out_en output signal + [23:20] + read-write + + + CSD_TX_N_AMUXA_EN + Select waveform for csd_tx_n_amuxa_en output signal + [27:24] + read-write + + + + + SEQ_TIME + Sequencer Timing + 0x300 + 32 + read-write + 0x0 + 0xFF + + + AZ_TIME + Define Auto-Zero time in csd_sense cycles -1. + [7:0] + read-write + + + + + SEQ_INIT_CNT + Sequencer Initial conversion and sample counts + 0x310 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. + [15:0] + read-write + + + + + SEQ_NORM_CNT + Sequencer Normal conversion and sample counts + 0x314 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. +Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). +Note for CSDv1 Sample window size = PERIOD + [15:0] + read-write + + + + + ADC_CTL + ADC Control + 0x320 + 32 + read-write + 0x0 + 0x300FF + + + ADC_TIME + ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 + [7:0] + read-write + + + ADC_MODE + Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state + [17:16] + read-write + + + OFF + No ADC measurement + 0 + + + VREF_CNT + Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB + 1 + + + VREF_BY2_CNT + Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) + 2 + + + VIN_CNT + Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. + 3 + + + + + + + SEQ_START + Sequencer start + 0x340 + 32 + read-write + 0x0 + 0x31B + + + START + Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). + [0:0] + read-write + + + SEQ_MODE + 0 = regular CSD scan + optional ADC +1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. + [1:1] + read-write + + + ABORT + When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. + [3:3] + read-write + + + DSI_START_EN + When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. + [4:4] + read-write + + + AZ0_SKIP + When set the AutoZero_0 state will be skipped + [8:8] + read-write + + + AZ1_SKIP + When set the AutoZero_1 state will be skipped + [9:9] + read-write + + + + + IDACA + IDACA Configuration + 0x400 + 32 + read-write + 0x0 + 0x3EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_MODE==CSD also mixed with the CSD configuration and operation. However in mutual cap mode with one IDAC (config.mutual_cap=1 & config.csx_dual_idac=0) the polarity of the IDAC is controlled by csd_sense. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + Balancing mode: only applies to legs configured as CSD. + [11:10] + read-write + + + FULL + enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking. + 1 + + + PHI2 + enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or dual IDAC CSX or Full-Wave. + 2 + + + PHI1_2 + enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave. + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 0 + + + GP + General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 1 + + + CSD_STATIC + CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. + 2 + + + CSD + CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled). +0: no DSI control + IDACA_POLARITY = IDACA.POLARITY + IDACA_LEG1_EN = IDACA.LEG1_EN + IDACA_LEG2_EN = IDACA.LEG2_EN +1: Mix MMIO with DSI control + IDACA_POLARITY = IDACA.POLARITY EXOR dsi_idaca_pol + IDACA_LEG1_EN = IDACA.LEG1_EN AND dsi_idaca_leg1_en + IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSA + [25:25] + read-write + + + + + IDACB + IDACB Configuration + 0x500 + 32 + read-write + 0x0 + 0x7EF0FFF + + + VAL + Current value setting for this IDAC (7 bits). + [6:0] + read-write + + + POL_DYN + Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. + [7:7] + read-write + + + STATIC + Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. + 0 + + + DYNAMIC + Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. + 1 + + + + + POLARITY + Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_EN==1 and LEG1_MODE==CSD also mixed with the CSD configuration and operation. In mutual cap mode however (see config.mutual_cap) the polarity of the IDAC is controlled by csd_sense. If LEG3_EN=1 (the other two legs must be off) then the ADC sequencer controls the IDACB polarity, optionally mixed with DSI. + [9:8] + read-write + + + VSSA_SRC + Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. + 0 + + + VDDA_SNK + Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. + 1 + + + SENSE + The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 2 + + + SENSE_INV + The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. + 3 + + + + + BAL_MODE + same as corresponding IDACA Balancing mode + [11:10] + read-write + + + FULL + same as corresponding IDACA Balancing mode + 0 + + + PHI1 + same as corresponding IDACA Balancing mode + 1 + + + PHI2 + same as corresponding IDACA Balancing mode + 2 + + + PHI1_2 + same as corresponding IDACA Balancing mode + 3 + + + + + LEG1_MODE + Controls the usage mode of LEG1 and the Polarity bit + [17:16] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG1_MODE + 0 + + + GP + same as corresponding IDACA.LEG1_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG1_MODE + 2 + + + CSD + same as corresponding IDACA.LEG1_MODE + 3 + + + + + LEG2_MODE + Controls the usage mode of LEG2 + [19:18] + read-write + + + GP_STATIC + same as corresponding IDACA.LEG2_MODE + 0 + + + GP + same as corresponding IDACA.LEG2_MODE + 1 + + + CSD_STATIC + same as corresponding IDACA.LEG2_MODE + 2 + + + CSD + same as corresponding IDACA.LEG2_MODE + 3 + + + + + DSI_CTRL_EN + Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled) +0: no DSI control + IDACB_POLARITY = IDACB.POLARITY + IDACB_LEG1_EN = IDACB.LEG1_EN + IDACB_LEG2_EN = IDACB.LEG2_EN + IDACB_LEG3_EN = IDACB.LEG3_EN +1: Mix MMIO with DSI control + IDACB_POLARITY = IDACB.POLARITY EXOR dsi_idacb_pol + IDACB_LEG1_EN = IDACB.LEG1_EN AND dsi_idacb_leg1_en + IDACB_LEG2_EN = IDACB.LEG2_EN AND dsi_idacb_leg2_en + IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en + [21:21] + read-write + + + RANGE + IDAC multiplier + [23:22] + read-write + + + IDAC_LO + 1 LSB = 37.5 nA + 0 + + + IDAC_MED + 1 LSB = 300 nA + 1 + + + IDAC_HI + 1 LSB = 2400 nA + 2 + + + + + LEG1_EN + output enable for leg 1 to CSDBUSB or CSDBUSA + [24:24] + read-write + + + LEG2_EN + output enable for leg 2 to CSDBUSB or CSDBUSA + [25:25] + read-write + + + LEG3_EN + output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit is set both other legs should be off. +Note that leg3 can only be used for ADC mode, not GP mode. Which means that leg3 can only be on when the ADC Sequencer is in the ADC_measure or Calib_measure state. In those states leg3 is controlled by the ADC configuration and the HSCMP output. In addition this leg3 enable bit can optionally be mixed with DSI (see DSI_CTRL_EN). +When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer. + [26:26] + read-write + + + + + + + TCPWM0 + Timer/Counter/PWM + TCPWM + 0x40380000 + + 0 + 131072 + registers + + + + 2 + 32768 + GRP[%s] + Group of counters + 0x00000000 + + 8 + 128 + CNT[%s] + Timer/Counter/PWM Counter Module + 0x00000000 + + CTRL + Counter control register + 0x0 + 32 + read-write + 0xF0 + 0xC73737FF + + + AUTO_RELOAD_CC0 + Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. +Timer, QUAD, SR modes: +'0': never switch. +'1': switch on a compare match 0 event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [0:0] + read-write + + + AUTO_RELOAD_CC1 + Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. +Timer, QUAD, SR modes: +'0': never switch. +'1': switch on a compare match 1 event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [1:1] + read-write + + + AUTO_RELOAD_PERIOD + Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + +In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function. +'0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event. +'1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff. + [2:2] + read-write + + + AUTO_RELOAD_LINE_SEL + Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + [3:3] + read-write + + + CC0_MATCH_UP_EN + Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. +'0': compare match 0 event generation disabled when counting up +'1': compare match 0 event generation enabled when counting up + +This field has a function in PWM and PWM_DT modes only. + [4:4] + read-write + + + CC0_MATCH_DOWN_EN + Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. +'0': compare match 0 event generation disabled when counting down +'1': compare match 0 event generation enabled when counting down + +This field has a function in PWM and PWM_DT modes only. + [5:5] + read-write + + + CC1_MATCH_UP_EN + Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. +'0': compare match 1 event generation disabled when counting up +'1': compare match 1 event generation enabled when counting up + +This field has a function in PWM and PWM_DT modes only. + [6:6] + read-write + + + CC1_MATCH_DOWN_EN + Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. +'0': compare match 1 event generation disabled when counting down +'1': compare match 1 event generation enabled when counting down + +This field has a function in PWM and PWM_DT modes only. + [7:7] + read-write + + + PWM_IMM_KILL + Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter'). +'0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter'). +'1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [8:8] + read-write + + + PWM_STOP_ON_KILL + Specifies whether the counter stops on a kill events: +'0': kill event does NOT stop counter. +'1': kill event stops counter. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [9:9] + read-write + + + PWM_SYNC_KILL + Specifies asynchronous/synchronous kill behavior: +'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. +'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. + +This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. + [10:10] + read-write + + + PWM_DISABLE_MODE + Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped. + +Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE). + [13:12] + read-write + + + Z + The behavior is the same is in previous mxtcpwm (version 1). + +When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). +Note: This is realized by driving the TCPWM output 'line_out_en' to 0. + +When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE). + 0 + + + RETAIN + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels). +While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1). + 1 + + + L + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'. + 2 + + + H + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'. + 3 + + + + + UP_DOWN_MODE + Determines counter direction. + +In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior. + [17:16] + read-write + + + COUNT_UP + Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. + 0 + + + COUNT_DOWN + Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 1 + + + COUNT_UPDN1 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 2 + + + COUNT_UPDN2 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). + 3 + + + + + ONE_SHOT + When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. + [18:18] + read-write + + + QUAD_ENCODING_MODE + In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode. +In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1]. + [21:20] + read-write + + + X1 + X1 encoding (QUAD mode) +This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input). + 0 + + + X2 + X2 encoding (QUAD mode) + 1 + + + X4 + X4 encoding (QUAD mode) + 2 + + + UP_DOWN + Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply. + 3 + + + + + MODE + Counter mode. + [26:24] + read-write + + + TIMER + Timer mode + 0 + + + RSVD1 + N/A + 1 + + + CAPTURE + Capture mode + 2 + + + QUAD + Quadrature mode + +Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality. +Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE). + 3 + + + PWM + Pulse width modulation (PWM) mode + 4 + + + PWM_DT + PWM with deadtime insertion mode + 5 + + + PWM_PR + Pseudo random pulse width modulation + 6 + + + SR + Shift register mode. + 7 + + + + + DBG_FREEZE_EN + Specifies the counter behavior in debug mode. +'0': The counter operation continues in debug mode. +'1': The counter operation freezes in debug mode. + [30:30] + read-write + + + ENABLED + Counter enable. +'0': counter disabled. +'1': counter enabled. +Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: +- the associated counter triggers in the CMD register are set to '0'. +- the counter's interrupt cause fields in counter's INTR register. +- the counter's status fields in counter's STATUS register.. +- the counter's trigger outputs ('tr_out0' and tr_out1'). +- the counter's line outputs ('line_out' and 'line_compl_out'). + [31:31] + read-write + + + + + STATUS + Counter status register + 0x4 + 32 + read-only + 0x20 + 0xFFFF8FF1 + + + DOWN + When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. + [0:0] + read-only + + + TR_CAPTURE0 + Indicates the actual level of the selected capture 0 trigger. + [4:4] + read-only + + + TR_COUNT + Indicates the actual level of the selected count trigger. + [5:5] + read-only + + + TR_RELOAD + Indicates the actual level of the selected reload trigger. + [6:6] + read-only + + + TR_STOP + Indicates the actual level of the selected stop trigger. + [7:7] + read-only + + + TR_START + Indicates the actual level of the selected start trigger. + [8:8] + read-only + + + TR_CAPTURE1 + Indicates the actual level of the selected capture 1 trigger. + [9:9] + read-only + + + LINE_OUT + Indicates the actual level of the PWM line output signal. + [10:10] + read-only + + + LINE_COMPL_OUT + Indicates the actual level of the complementary PWM line output signal. + [11:11] + read-only + + + RUNNING + When '0', the counter is NOT running. When '1', the counter is running. + +This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event. +When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'. + [15:15] + read-only + + + DT_CNT_L + Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter). +In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. + [23:16] + read-only + + + DT_CNT_H + High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter. + [31:24] + read-only + + + + + COUNTER + Counter count register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER + 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. + [31:0] + read-write + + + + + CC0 + Counter compare/capture 0 register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC0_BUFF + Counter buffered compare/capture 0 register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC register. + [31:0] + read-write + + + + + CC1 + Counter compare/capture 1 register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC1_BUFF + Counter buffered compare/capture 1 register + 0x1C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC1 register. + [31:0] + read-write + + + + + PERIOD + Counter period register + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. + [31:0] + read-write + + + + + PERIOD_BUFF + Counter buffered period register + 0x24 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Additional buffer for counter PERIOD register. + +In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree. +Examples for GRP_CNT_WIDTH = 16: +- Maximum length 16bit LFSR + - polynomial x^16 + x^14 + x^13 + x^11 + 1 + - taps 0,2,3,5 -> PERIOD = 0x002d + - period is 2^16-1 = 65535 cycles +- Maximum length 8bit LFSR: + - polynomial x^8 + x^6 + x^5 + x^4 + 1 + - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR) + - period is 2^8-1 = 255 cycles + +In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined. + [31:0] + read-write + + + + + LINE_SEL + Counter line selection register + 0x28 + 32 + read-write + 0x32 + 0x77 + + + OUT_SEL + Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control. +This field has a function in PWM and PWM_PR modes only. + +Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]). + [2:0] + read-write + + + L + fixed '0' + 0 + + + H + fixed '1' + 1 + + + PWM + PWM signal 'line' + 2 + + + PWM_INV + inverted PWM signal 'line' + 3 + + + Z + The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). + +Note: This is realized by driving the output 'line_out_en' to 0. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + COMPL_OUT_SEL + Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control. +This field has a function in PWM and PWM_PR modes only. + +Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]). + [6:4] + read-write + + + L + fixed '0' + 0 + + + H + fixed '1' + 1 + + + PWM + PWM signal 'line' + 2 + + + PWM_INV + inverted PWM signal 'line' + 3 + + + Z + The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). + +Note: This is realized by driving the output 'line_compl_out_en' to 0. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + + + LINE_SEL_BUFF + Counter buffered line selection register + 0x2C + 32 + read-write + 0x32 + 0x77 + + + OUT_SEL + Buffer for LINE_SEL.OUT_SEL. +Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event. + +This field has a function in PWM and PWM_PR modes only. + [2:0] + read-write + + + COMPL_OUT_SEL + Buffer for LINE_SEL.COMPL.OUT_SEL. +Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event. + +This field has a function in PWM and PWM_PR modes only. + [6:4] + read-write + + + + + DT + Counter PWM dead time register + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DT_LINE_OUT_L + In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. +In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. + +Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'. + [7:0] + read-write + + + DT_LINE_OUT_H + In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. + [15:8] + read-write + + + DT_LINE_COMPL_OUT + In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. + [31:16] + read-write + + + + + TR_CMD + Counter trigger command register + 0x40 + 32 + read-write + 0x0 + 0x3D + + + CAPTURE0 + SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'. + [0:0] + read-write + + + RELOAD + SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [2:2] + read-write + + + STOP + SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [3:3] + read-write + + + START + SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [4:4] + read-write + + + CAPTURE1 + SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [5:5] + read-write + + + + + TR_IN_SEL0 + Counter input trigger selection register 0 + 0x44 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CAPTURE0_SEL + Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected. +In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. + [7:0] + read-write + + + COUNT_SEL + Selects one of the 256 input triggers as a count trigger. +In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. + +Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL > 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields. + [15:8] + read-write + + + RELOAD_SEL + Selects one of the 256 input triggers as a reload trigger. +In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE. + [23:16] + read-write + + + STOP_SEL + Selects one of the 256 input triggers as a stop trigger. +In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. + [31:24] + read-write + + + + + TR_IN_SEL1 + Counter input trigger selection register 1 + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + START_SEL + Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). + [7:0] + read-write + + + CAPTURE1_SEL + Selects one of the 256 input triggers as a capture 1 trigger. + [15:8] + read-write + + + + + TR_IN_EDGE_SEL + Counter input trigger edge selection register + 0x4C + 32 + read-write + 0xFFF + 0xFFF + + + CAPTURE0_EDGE + A capture 0 event will copy the counter value into the CC0 register. + [1:0] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + COUNT_EDGE + A counter event will increase or decrease the counter by '1'. + [3:2] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + RELOAD_EDGE + A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. + [5:4] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + STOP_EDGE + A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. + [7:6] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + START_EDGE + A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. + [9:8] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + CAPTURE1_EDGE + A capture 1 event will copy the counter value into the CC1 register. + [11:10] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + + + TR_PWM_CTRL + Counter trigger PWM control register + 0x50 + 32 + read-write + 0xFF + 0xFF + + + CC0_MATCH_MODE + Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. +To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register. + [1:0] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + OVERFLOW_MODE + Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. + [3:2] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + UNDERFLOW_MODE + Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. + [5:4] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + CC1_MATCH_MODE + Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals. + [7:6] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + + + TR_OUT_SEL + Counter output trigger selection register + 0x54 + 32 + read-write + 0x32 + 0x77 + + + OUT0 + Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event. + [2:0] + read-write + + + OVERFLOW + Overflow event + 0 + + + UNDERFLOW + Underflow event + 1 + + + TC + Terminal count event (default selection) + 2 + + + CC0_MATCH + Compare match 0 event + 3 + + + CC1_MATCH + Compare match 1 event + 4 + + + LINE_OUT + PWM output signal 'line_out' + 5 + + + RSVD6 + N/A + 6 + + + Disabled + Output trigger disabled. + 7 + + + + + OUT1 + Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event. + [6:4] + read-write + + + OVERFLOW + Overflow event + 0 + + + UNDERFLOW + Underflow event + 1 + + + TC + Terminal count event + 2 + + + CC0_MATCH + Compare match 0 event (default selection) + 3 + + + CC1_MATCH + Compare match 1 event + 4 + + + LINE_OUT + PWM output signal 'line_out' + 5 + + + RSVD6 + N/A + 6 + + + Disabled + Output trigger disabled. + 7 + + + + + + + INTR + Interrupt request register + 0x70 + 32 + read-write + 0x0 + 0x7 + + + TC + Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. + [0:0] + read-write + + + CC0_MATCH + Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit. + [1:1] + read-write + + + CC1_MATCH + Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit. + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x74 + 32 + read-write + 0x0 + 0x7 + + + TC + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + CC0_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CC1_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x78 + 32 + read-write + 0x0 + 0x7 + + + TC + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + CC0_MATCH + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CC1_MATCH + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x7C + 32 + read-only + 0x0 + 0x7 + + + TC + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CC0_MATCH + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CC1_MATCH + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + + + + + LCD0 + LCD Controller Block + LCD + 0x403B0000 + + 0 + 65536 + registers + + + + ID + ID & Revision + 0x0 + 32 + read-only + 0x2F0F0 + 0xFFFFFFFF + + + ID + the ID of LCD controller peripheral is 0xF0F0 + [15:0] + read-only + + + REVISION + the version number is 0x0002 + [31:16] + read-only + + + + + DIVIDER + LCD Divider Register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SUBFR_DIV + Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. + [15:0] + read-write + + + DEAD_DIV + Length of the dead time period in cycles. When set to zero, no dead time period exists. + [31:16] + read-write + + + + + CONTROL + LCD Configuration Register + 0x8 + 32 + read-write + 0x0 + 0x80000FFF + + + LS_EN + Low speed (LS) generator enable +1: enable +0: disable + [0:0] + read-write + + + HS_EN + High speed (HS) generator enable +1: enable +0: disable + [1:1] + read-write + + + LCD_MODE + HS/LS Mode selection + [2:2] + read-write + + + LS + Select Low Speed Generator (Works in Active, Sleep and DeepSleep power modes). Low speed clock (clk_lf) or middle speed clock (clk_mf) can be selected for Low Speed Generator. + 0 + + + HS + Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). + 1 + + + + + TYPE + LCD driving waveform type configuration. + [3:3] + read-write + + + TYPE_A + Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. + 0 + + + TYPE_B + Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). + 1 + + + + + OP_MODE + Driving mode configuration + [4:4] + read-write + + + PWM + PWM Mode + 0 + + + CORRELATION + Digital Correlation Mode + 1 + + + + + BIAS + PWM bias selection + [6:5] + read-write + + + HALF + 1/2 Bias + 0 + + + THIRD + 1/3 Bias + 1 + + + FOURTH + 1/4 Bias + 2 + + + FIFTH + 1/5 Bias + 3 + + + + + CLOCK_LS_SEL + Low speed (LS) generator clock source selection +1: select clk_mf +0: select clk_lf + [7:7] + read-write + + + COM_NUM + The number of COM connections minus 2. So: +0: 2 COM's +1: 3 COM's +... +13: 15 COM's +14: 16 COM's +15: undefined + [11:8] + read-write + + + LS_EN_STAT + LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. +The following procedure should be followed to disable the LS generator: +1. If LS_EN=0 we are done. Exit the procedure. +2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. +3. Set LS_EN=0. +4. Wait until LS_EN_STAT=0. + [31:31] + read-only + + + + + 8 + 4 + DATA0[%s] + LCD Pin Data Registers + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA1[%s] + LCD Pin Data Registers + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA2[%s] + LCD Pin Data Registers + 0x300 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA3[%s] + LCD Pin Data Registers + 0x400 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). + [31:0] + read-write + + + + + + + USBFS0 + USB Host and Device Controller + USBFS + 0x403F0000 + + 0 + 65536 + registers + + + + USBDEV + USB Device + 0x00000000 + + 8 + 4 + EP0_DR[%s] + Control End point EP0 Data Register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + DATA_BYTE + This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. + [7:0] + read-write + + + + + CR0 + USB control 0 Register + 0x20 + 32 + read-write + 0x0 + 0xFF + + + DEVICE_ADDRESS + These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. +If USB bus reset is detected, these bits are initialized. + [6:0] + read-write + + + USB_ENABLE + This bit enables the device to respond to USB traffic. +If USB bus reset is detected, this bit is cleared. +Note: +When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. + [7:7] + read-write + + + + + CR1 + USB control 1 Register + 0x24 + 32 + read-write + 0x0 + 0xF + + + REG_ENABLE + This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. + [0:0] + read-write + + + ENABLE_LOCK + This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. + [1:1] + read-write + + + BUS_ACTIVITY + The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High +value until firmware clears it. + [2:2] + read-write + + + RSVD_3 + N/A + [3:3] + read-write + + + + + SIE_EP_INT_EN + USB SIE Data Endpoints Interrupt Enable Register + 0x28 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + SIE_EP_INT_SR + USB SIE Data Endpoint Interrupt Status + 0x2C + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-write + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-write + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-write + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-write + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-write + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-write + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-write + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-write + + + + + SIE_EP1_CNT0 + Non-control endpoint count register + 0x30 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP1_CNT1 + Non-control endpoint count register + 0x34 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP1_CR0 + Non-control endpoint's control Register + 0x38 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + USBIO_CR0 + USBIO Control 0 Register + 0x40 + 32 + read-write + 0x0 + 0xE0 + + + RD + Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. +If D+=D- (SE0), this value is undefined. + [0:0] + read-only + + + DIFF_LOW + D+ < D- (K state) + 0 + + + DIFF_HIGH + D+ > D- (J state) + 1 + + + + + TD + Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. + [5:5] + read-write + + + DIFF_K + Force USB K state (D+ is low D- is high). + 0 + + + DIFF_J + Force USB J state (D+ is high D- is low). + 1 + + + + + TSE0 + Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. + [6:6] + read-write + + + TEN + USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually +transmitting is to force a resume state on the bus. + [7:7] + read-write + + + + + USBIO_CR2 + USBIO control 2 Register + 0x44 + 32 + read-write + 0x0 + 0xFF + + + RSVD_5_0 + N/A + [5:0] + read-only + + + TEST_PKT + This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. + [6:6] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + + + USBIO_CR1 + USBIO control 1 Register + 0x48 + 32 + read-write + 0x20 + 0x20 + + + DMO + This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. +This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. +This bit is valid if USB Device. + [0:0] + read-only + + + DPO + This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. +This bit displays the output value of D+ pin when USB transmits SE0 or data. +This bit is valid if USB Device. + [1:1] + read-only + + + RSVD_2 + N/A + [2:2] + read-write + + + IOMODE + This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. + [5:5] + read-write + + + + + DYN_RECONFIG + USB Dynamic reconfiguration register + 0x50 + 32 + read-write + 0x0 + 0x1F + + + DYN_CONFIG_EN + This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. +Use 0 for EP1, 1 for EP2, etc. + [0:0] + read-write + + + DYN_RECONFIG_EPNO + These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. + [3:1] + read-write + + + DYN_RECONFIG_RDY_STS + This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. + [4:4] + read-only + + + + + SOF0 + Start Of Frame Register + 0x60 + 32 + read-only + 0x0 + 0xFF + + + FRAME_NUMBER + It has the lower 8 bits [7:0] of the SOF frame number. + [7:0] + read-only + + + + + SOF1 + Start Of Frame Register + 0x64 + 32 + read-only + 0x0 + 0x7 + + + FRAME_NUMBER_MSB + It has the upper 3 bits [10:8] of the SOF frame number. + [2:0] + read-only + + + + + SIE_EP2_CNT0 + Non-control endpoint count register + 0x70 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP2_CNT1 + Non-control endpoint count register + 0x74 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP2_CR0 + Non-control endpoint's control Register + 0x78 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + OSCLK_DR0 + Oscillator lock data register 0 + 0x80 + 32 + read-only + 0x0 + 0x0 + + + ADDER + These bits return the lower 8 bits of the oscillator locking circuits adder output. + [7:0] + read-only + + + + + OSCLK_DR1 + Oscillator lock data register 1 + 0x84 + 32 + read-only + 0x0 + 0x0 + + + ADDER_MSB + These bits return the upper 7 bits of the oscillator locking circuits adder output. + [6:0] + read-only + + + + + EP0_CR + Endpoint0 control Register + 0xA0 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + OUT_RCVD + When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. + [5:5] + read-write + + + IN_RCVD + When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. + [6:6] + read-write + + + SETUP_RCVD + When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. + [7:7] + read-write + + + + + EP0_CNT + Endpoint0 count Register + 0xA4 + 32 + read-write + 0x0 + 0xCF + + + BYTE_COUNT + These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. + [3:0] + read-write + + + DATA_VALID + This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT0 + Non-control endpoint count register + 0xB0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT1 + Non-control endpoint count register + 0xB4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP3_CR0 + Non-control endpoint's control Register + 0xB8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP4_CNT0 + Non-control endpoint count register + 0xF0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP4_CNT1 + Non-control endpoint count register + 0xF4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP4_CR0 + Non-control endpoint's control Register + 0xF8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP5_CNT0 + Non-control endpoint count register + 0x130 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP5_CNT1 + Non-control endpoint count register + 0x134 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP5_CR0 + Non-control endpoint's control Register + 0x138 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP6_CNT0 + Non-control endpoint count register + 0x170 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP6_CNT1 + Non-control endpoint count register + 0x174 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP6_CR0 + Non-control endpoint's control Register + 0x178 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP7_CNT0 + Non-control endpoint count register + 0x1B0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP7_CNT1 + Non-control endpoint count register + 0x1B4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP7_CR0 + Non-control endpoint's control Register + 0x1B8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP8_CNT0 + Non-control endpoint count register + 0x1F0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP8_CNT1 + Non-control endpoint count register + 0x1F4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP8_CR0 + Non-control endpoint's control Register + 0x1F8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + ARB_EP1_CFG + Endpoint Configuration Register *1 + 0x200 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP1_INT_EN + Endpoint Interrupt Enable Register *1 + 0x204 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP1_SR + Endpoint Interrupt Enable Register *1 + 0x208 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW1_WA + Endpoint Write Address value *1, *2 + 0x210 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW1_WA_MSB + Endpoint Write Address value *1, *2 + 0x214 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW1_RA + Endpoint Read Address value *1, *2 + 0x218 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW1_RA_MSB + Endpoint Read Address value *1, *2 + 0x21C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW1_DR + Endpoint Data Register + 0x220 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUF_SIZE + Dedicated Endpoint Buffer Size Register *1 + 0x230 + 32 + read-write + 0x0 + 0xFF + + + IN_BUF + Buffer size for IN Endpoints. + [3:0] + read-write + + + OUT_BUF + Buffer size for OUT Endpoints. + [7:4] + read-write + + + + + EP_ACTIVE + Endpoint Active Indication Register *1 + 0x238 + 32 + read-write + 0x0 + 0xFF + + + EP1_ACT + Indicates that Endpoint is currently active. + [0:0] + read-write + + + EP2_ACT + Indicates that Endpoint is currently active. + [1:1] + read-write + + + EP3_ACT + Indicates that Endpoint is currently active. + [2:2] + read-write + + + EP4_ACT + Indicates that Endpoint is currently active. + [3:3] + read-write + + + EP5_ACT + Indicates that Endpoint is currently active. + [4:4] + read-write + + + EP6_ACT + Indicates that Endpoint is currently active. + [5:5] + read-write + + + EP7_ACT + Indicates that Endpoint is currently active. + [6:6] + read-write + + + EP8_ACT + Indicates that Endpoint is currently active. + [7:7] + read-write + + + + + EP_TYPE + Endpoint Type (IN/OUT) Indication *1 + 0x23C + 32 + read-write + 0x0 + 0xFF + + + EP1_TYP + Endpoint Type Indication. + [0:0] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP2_TYP + Endpoint Type Indication. + [1:1] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP3_TYP + Endpoint Type Indication. + [2:2] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP4_TYP + Endpoint Type Indication. + [3:3] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP5_TYP + Endpoint Type Indication. + [4:4] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP6_TYP + Endpoint Type Indication. + [5:5] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP7_TYP + Endpoint Type Indication. + [6:6] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP8_TYP + Endpoint Type Indication. + [7:7] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + + + ARB_EP2_CFG + Endpoint Configuration Register *1 + 0x240 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP2_INT_EN + Endpoint Interrupt Enable Register *1 + 0x244 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP2_SR + Endpoint Interrupt Enable Register *1 + 0x248 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW2_WA + Endpoint Write Address value *1, *2 + 0x250 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW2_WA_MSB + Endpoint Write Address value *1, *2 + 0x254 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW2_RA + Endpoint Read Address value *1, *2 + 0x258 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW2_RA_MSB + Endpoint Read Address value *1, *2 + 0x25C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW2_DR + Endpoint Data Register + 0x260 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_CFG + Arbiter Configuration Register *1 + 0x270 + 32 + read-write + 0x0 + 0xF0 + + + AUTO_MEM + Enables Auto Memory Configuration. Manual memory configuration by default. + [4:4] + read-write + + + DMA_CFG + DMA Access Configuration. + [6:5] + read-write + + + DMA_NONE + No DMA + 0 + + + DMA_MANUAL + Manual DMA + 1 + + + DMA_AUTO + Auto DMA + 2 + + + + + CFG_CMP + Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. + [7:7] + read-write + + + + + USB_CLK_EN + USB Block Clock Enable Register + 0x274 + 32 + read-write + 0x0 + 0x1 + + + CSR_CLK_EN + Clock Enable for Core Logic clocked by AHB bus clock + [0:0] + read-write + + + + + ARB_INT_EN + Arbiter Interrupt Enable *1 + 0x278 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + ARB_INT_SR + Arbiter Interrupt Status *1 + 0x27C + 32 + read-only + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-only + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-only + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-only + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-only + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-only + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-only + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-only + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-only + + + + + ARB_EP3_CFG + Endpoint Configuration Register *1 + 0x280 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP3_INT_EN + Endpoint Interrupt Enable Register *1 + 0x284 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP3_SR + Endpoint Interrupt Enable Register *1 + 0x288 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW3_WA + Endpoint Write Address value *1, *2 + 0x290 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW3_WA_MSB + Endpoint Write Address value *1, *2 + 0x294 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW3_RA + Endpoint Read Address value *1, *2 + 0x298 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW3_RA_MSB + Endpoint Read Address value *1, *2 + 0x29C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW3_DR + Endpoint Data Register + 0x2A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + CWA + Common Area Write Address *1 + 0x2B0 + 32 + read-write + 0x0 + 0xFF + + + CWA + Write Address for Common Area + [7:0] + read-write + + + + + CWA_MSB + Endpoint Read Address value *1 + 0x2B4 + 32 + read-write + 0x0 + 0x1 + + + CWA_MSB + Write Address for Common Area + [0:0] + read-write + + + + + ARB_EP4_CFG + Endpoint Configuration Register *1 + 0x2C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP4_INT_EN + Endpoint Interrupt Enable Register *1 + 0x2C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP4_SR + Endpoint Interrupt Enable Register *1 + 0x2C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW4_WA + Endpoint Write Address value *1, *2 + 0x2D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW4_WA_MSB + Endpoint Write Address value *1, *2 + 0x2D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW4_RA + Endpoint Read Address value *1, *2 + 0x2D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW4_RA_MSB + Endpoint Read Address value *1, *2 + 0x2DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW4_DR + Endpoint Data Register + 0x2E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + DMA_THRES + DMA Burst / Threshold Configuration + 0x2F0 + 32 + read-write + 0x0 + 0xFF + + + DMA_THS + DMA Threshold count + [7:0] + read-write + + + + + DMA_THRES_MSB + DMA Burst / Threshold Configuration + 0x2F4 + 32 + read-write + 0x0 + 0x1 + + + DMA_THS_MSB + DMA Threshold count + [0:0] + read-write + + + + + ARB_EP5_CFG + Endpoint Configuration Register *1 + 0x300 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP5_INT_EN + Endpoint Interrupt Enable Register *1 + 0x304 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP5_SR + Endpoint Interrupt Enable Register *1 + 0x308 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW5_WA + Endpoint Write Address value *1, *2 + 0x310 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW5_WA_MSB + Endpoint Write Address value *1, *2 + 0x314 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW5_RA + Endpoint Read Address value *1, *2 + 0x318 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW5_RA_MSB + Endpoint Read Address value *1, *2 + 0x31C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW5_DR + Endpoint Data Register + 0x320 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUS_RST_CNT + Bus Reset Count Register + 0x330 + 32 + read-write + 0xA + 0xF + + + BUS_RST_CNT + Bus Reset Count Length + [3:0] + read-write + + + + + ARB_EP6_CFG + Endpoint Configuration Register *1 + 0x340 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP6_INT_EN + Endpoint Interrupt Enable Register *1 + 0x344 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP6_SR + Endpoint Interrupt Enable Register *1 + 0x348 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW6_WA + Endpoint Write Address value *1, *2 + 0x350 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW6_WA_MSB + Endpoint Write Address value *1, *2 + 0x354 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW6_RA + Endpoint Read Address value *1, *2 + 0x358 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW6_RA_MSB + Endpoint Read Address value *1, *2 + 0x35C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW6_DR + Endpoint Data Register + 0x360 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP7_CFG + Endpoint Configuration Register *1 + 0x380 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP7_INT_EN + Endpoint Interrupt Enable Register *1 + 0x384 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP7_SR + Endpoint Interrupt Enable Register *1 + 0x388 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW7_WA + Endpoint Write Address value *1, *2 + 0x390 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW7_WA_MSB + Endpoint Write Address value *1, *2 + 0x394 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW7_RA + Endpoint Read Address value *1, *2 + 0x398 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW7_RA_MSB + Endpoint Read Address value *1, *2 + 0x39C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW7_DR + Endpoint Data Register + 0x3A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP8_CFG + Endpoint Configuration Register *1 + 0x3C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP8_INT_EN + Endpoint Interrupt Enable Register *1 + 0x3C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP8_SR + Endpoint Interrupt Enable Register *1 + 0x3C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW8_WA + Endpoint Write Address value *1, *2 + 0x3D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW8_WA_MSB + Endpoint Write Address value *1, *2 + 0x3D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW8_RA + Endpoint Read Address value *1, *2 + 0x3D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW8_RA_MSB + Endpoint Read Address value *1, *2 + 0x3DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW8_DR + Endpoint Data Register + 0x3E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + 512 + 4 + MEM_DATA[%s] + DATA + 0x400 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + SOF16 + Start Of Frame Register + 0x1060 + 32 + read-only + 0x0 + 0x7FF + + + FRAME_NUMBER16 + The frame number (11b) + [10:0] + read-only + + + + + OSCLK_DR16 + Oscillator lock data register + 0x1080 + 32 + read-only + 0x0 + 0x0 + + + ADDER16 + These bits return the oscillator locking circuits adder output. + [14:0] + read-only + + + + + ARB_RW1_WA16 + Endpoint Write Address value *3 + 0x1210 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW1_RA16 + Endpoint Read Address value *3 + 0x1218 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW1_DR16 + Endpoint Data Register + 0x1220 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW2_WA16 + Endpoint Write Address value *3 + 0x1250 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW2_RA16 + Endpoint Read Address value *3 + 0x1258 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW2_DR16 + Endpoint Data Register + 0x1260 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW3_WA16 + Endpoint Write Address value *3 + 0x1290 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW3_RA16 + Endpoint Read Address value *3 + 0x1298 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW3_DR16 + Endpoint Data Register + 0x12A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + CWA16 + Common Area Write Address + 0x12B0 + 32 + read-write + 0x0 + 0x1FF + + + CWA16 + Write Address for Common Area + [8:0] + read-write + + + + + ARB_RW4_WA16 + Endpoint Write Address value *3 + 0x12D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW4_RA16 + Endpoint Read Address value *3 + 0x12D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW4_DR16 + Endpoint Data Register + 0x12E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + DMA_THRES16 + DMA Burst / Threshold Configuration + 0x12F0 + 32 + read-write + 0x0 + 0x1FF + + + DMA_THS16 + DMA Threshold count + [8:0] + read-write + + + + + ARB_RW5_WA16 + Endpoint Write Address value *3 + 0x1310 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW5_RA16 + Endpoint Read Address value *3 + 0x1318 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW5_DR16 + Endpoint Data Register + 0x1320 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW6_WA16 + Endpoint Write Address value *3 + 0x1350 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW6_RA16 + Endpoint Read Address value *3 + 0x1358 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW6_DR16 + Endpoint Data Register + 0x1360 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW7_WA16 + Endpoint Write Address value *3 + 0x1390 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW7_RA16 + Endpoint Read Address value *3 + 0x1398 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW7_DR16 + Endpoint Data Register + 0x13A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW8_WA16 + Endpoint Write Address value *3 + 0x13D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW8_RA16 + Endpoint Read Address value *3 + 0x13D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW8_DR16 + Endpoint Data Register + 0x13E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + + USBLPM + USB Device LPM and PHY Test + 0x00002000 + + POWER_CTL + Power Control Register + 0x0 + 32 + read-write + 0x0 + 0x303F0004 + + + SUSPEND + Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). +Note: +- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. + [2:2] + read-write + + + DP_UP_EN + Enables the pull up on the DP. +'0' : Disable. +'1' : Enable. + [16:16] + read-write + + + DP_BIG + Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DP. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DP + [17:17] + read-write + + + DP_DOWN_EN + Enables the ~15k pull down on the DP. + [18:18] + read-write + + + DM_UP_EN + Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. +'0' : Disable. +'1' : Enable. + [19:19] + read-write + + + DM_BIG + Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DM. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DM + [20:20] + read-write + + + DM_DOWN_EN + Enables the ~15k pull down on the DP. + [21:21] + read-write + + + ENABLE_DPO + Enables the single ended receiver on D+. + [28:28] + read-write + + + ENABLE_DMO + Enables the signle ended receiver on D-. + [29:29] + read-write + + + + + USBIO_CTL + USB IO Control Register + 0x8 + 32 + read-write + 0x0 + 0x3F + + + DM_P + The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. + [2:0] + read-write + + + OFF + Mode 0: Output buffer off (high Z). Input buffer off. + 0 + + + INPUT + Mode 1: Output buffer off (high Z). Input buffer on. + +Other values, not supported. + 1 + + + + + DM_M + The GPIO Drive Mode for DM IO pad. + [5:3] + read-write + + + + + FLOW_CTL + Flow Control Register + 0xC + 32 + read-write + 0x0 + 0xFF + + + EP1_ERR_RESP + End Point 1 error response +0: do nothing (backward compatibility mode) +1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK + [0:0] + read-write + + + EP2_ERR_RESP + End Point 2 error response + [1:1] + read-write + + + EP3_ERR_RESP + End Point 3 error response + [2:2] + read-write + + + EP4_ERR_RESP + End Point 4 error response + [3:3] + read-write + + + EP5_ERR_RESP + End Point 5 error response + [4:4] + read-write + + + EP6_ERR_RESP + End Point 6 error response + [5:5] + read-write + + + EP7_ERR_RESP + End Point 7 error response + [6:6] + read-write + + + EP8_ERR_RESP + End Point 8 error response + [7:7] + read-write + + + + + LPM_CTL + LPM Control Register + 0x10 + 32 + read-write + 0x0 + 0x17 + + + LPM_EN + LPM enable +0: Disabled, LPM token will not get a response (backward compatibility mode) +1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) + A STALL will be sent if the bLinkState is not 0001b + A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below + [0:0] + read-write + + + LPM_ACK_RESP + LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request +0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode +1: a LPM token will get an ACK response and the device will go to the requested low power mode + [1:1] + read-write + + + NYET_EN + Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). +0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. +1: a LPM token will get a NYET response + [2:2] + read-write + + + SUB_RESP + Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. + [4:4] + read-write + + + + + LPM_STAT + LPM Status register + 0x14 + 32 + read-only + 0x0 + 0x1F + + + LPM_BESL + Best Effort Service Latency +This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. + [3:0] + read-only + + + LPM_REMOTEWAKE + 0: Device is prohibited from initiating a remote wake +1: Device is allow to wake the host + [4:4] + read-only + + + + + INTR_SIE + USB SOF, BUS RESET and EP0 Interrupt Status + 0x20 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR + Interrupt status for USB SOF + [0:0] + read-write + + + BUS_RESET_INTR + Interrupt status for BUS RESET + [1:1] + read-write + + + EP0_INTR + Interrupt status for EP0 + [2:2] + read-write + + + LPM_INTR + Interrupt status for LPM (Link Power Management, L1 entry) + [3:3] + read-write + + + RESUME_INTR + Interrupt status for Resume + [4:4] + read-write + + + + + INTR_SIE_SET + USB SOF, BUS RESET and EP0 Interrupt Set + 0x24 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + BUS_RESET_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EP0_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + LPM_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + RESUME_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + + + INTR_SIE_MASK + USB SOF, BUS RESET and EP0 Interrupt Mask + 0x28 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [0:0] + read-write + + + BUS_RESET_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [1:1] + read-write + + + EP0_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [2:2] + read-write + + + LPM_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [3:3] + read-write + + + RESUME_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [4:4] + read-write + + + + + INTR_SIE_MASKED + USB SOF, BUS RESET and EP0 Interrupt Masked + 0x2C + 32 + read-only + 0x0 + 0x1F + + + SOF_INTR_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + BUS_RESET_INTR_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EP0_INTR_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + LPM_INTR_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + RESUME_INTR_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + + + INTR_LVL_SEL + Select interrupt level for each interrupt source + 0x30 + 32 + read-write + 0x0 + 0xFFFFC3FF + + + SOF_LVL_SEL + USB SOF Interrupt level select + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + BUS_RESET_LVL_SEL + BUS RESET Interrupt level select + [3:2] + read-write + + + EP0_LVL_SEL + EP0 Interrupt level select + [5:4] + read-write + + + LPM_LVL_SEL + LPM Interrupt level select + [7:6] + read-write + + + RESUME_LVL_SEL + Resume Interrupt level select + [9:8] + read-write + + + ARB_EP_LVL_SEL + Arbiter Endpoint Interrupt level select + [15:14] + read-write + + + EP1_LVL_SEL + EP1 Interrupt level select + [17:16] + read-write + + + EP2_LVL_SEL + EP2 Interrupt level select + [19:18] + read-write + + + EP3_LVL_SEL + EP3 Interrupt level select + [21:20] + read-write + + + EP4_LVL_SEL + EP4 Interrupt level select + [23:22] + read-write + + + EP5_LVL_SEL + EP5 Interrupt level select + [25:24] + read-write + + + EP6_LVL_SEL + EP6 Interrupt level select + [27:26] + read-write + + + EP7_LVL_SEL + EP7 Interrupt level select + [29:28] + read-write + + + EP8_LVL_SEL + EP8 Interrupt level select + [31:30] + read-write + + + + + INTR_CAUSE_HI + High priority interrupt Cause register + 0x34 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_MED + Medium priority interrupt Cause register + 0x38 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_LO + Low priority interrupt Cause register + 0x3C + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + DFT_CTL + DFT control + 0x70 + 32 + read-write + 0x0 + 0x1F + + + DDFT_OUT_SEL + DDFT output select signal + [2:0] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + DP_SE + Single Ended output of DP + 1 + + + DM_SE + Single Ended output of DM + 2 + + + TXOE + Output Enable + 3 + + + RCV_DF + Differential Receiver output + 4 + + + GPIO_DP_OUT + GPIO output of DP + 5 + + + GPIO_DM_OUT + GPIO output of DM + 6 + + + + + DDFT_IN_SEL + DDFT input select signal + [4:3] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + GPIO_DP_IN + GPIO input of DP + 1 + + + GPIO_DM_IN + GPIO input of DM + 2 + + + + + + + + USBHOST + USB Host Controller + 0x00004000 + + HOST_CTL0 + Host Control 0 Register. + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + HOST + This bit selects an operating mode of this IP. +'0' : USB Device +'1' : USB Host +Notes: +- The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. +- This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. +- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. + * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. + * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. + * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. + [0:0] + read-write + + + ENABLE + This bit enables the operation of this IP. +'0' : Disable USB Host +'1' : Enable USB Host +Note: +- This bit doesn't affect the USB Device. + [31:31] + read-write + + + + + HOST_CTL1 + Host Control 1 Register. + 0x10 + 32 + read-write + 0x83 + 0x83 + + + CLKSEL + This bit selects the operating clock of USB Host. +'0' : Low-speed clock +'1' : Full-speed clock +Notes: +- This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- This bit must always be set to '1' in the USB Device mode. + [0:0] + read-write + + + USTP + This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. +'0' : Normal operating mode. +'1' : Stops the clock for the USB Host operating unit. +Notes: +- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. + [1:1] + read-write + + + RST + This bit resets the USB Host. +'0' : Normal operating mode. +'1' : USB Host is reset. +Notes: +- This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. + [7:7] + read-write + + + + + HOST_CTL2 + Host Control 2 Register. + 0x100 + 32 + read-write + 0x1 + 0xFF + + + RETRY + If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). +* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' +'0' : Doesn't retry token sending. +'1' : Retries token sending +Note: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + CANCEL + When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). +'0' : Continues a token. +'1' : Cancels a token. + [1:1] + read-write + + + SOFSTEP + If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. +If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. +'0' : An interrupt occurred due to the HOST_HFCOMP setting. +'1' : An interrupt occurred. +Notes: +- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. + [2:2] + read-write + + + ALIVE + This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. +'0' : SOF output. +'1' : SE0 output (Keep alive) + [3:3] + read-write + + + RSVD_4 + N/A + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-write + + + TTEST + N/A + [7:6] + read-write + + + + + HOST_ERR + Host Error Status Register. + 0x104 + 32 + read-write + 0x3 + 0xFF + + + HS + These flags indicate the status of a handshake packet to be sent or received. +These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +These bits are updated when sending or receiving has been ended. +Write '11' to set the status back to 'NULL', all other write values are ignored. +Note: +This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:0] + read-write + + + ACK + Acknowledge Packet + 0 + + + NAK + Non-Acknowledge Packet + 1 + + + STALL + Stall Packet + 2 + + + NULL + Null Packet + 3 + + + + + STUFF + If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No stuffing error. +'1' : Stuffing error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + TGERR + If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No toggle error. +'1' : Toggle error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:3] + read-write + + + CRC + If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. +'0' : No CRC error. +'1' : CRC error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + TOUT + If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No timeout. +'1' : Timeout has detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RERR + When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. +'0' : No receive error. +'1' : Maximum packet receive error detected. +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:6] + read-write + + + LSTSOF + If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. +'0' : SOF sent without error. +'1' : SOF error detected. +Note: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + HOST_STATUS + Host Status Register. + 0x108 + 32 + read-write + 0xC2 + 0x1FF + + + CSTAT + When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. +'0' : Device is disconnected. +'1' : Device is connected. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [0:0] + read-only + + + TMODE + If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. +'0' : Low-speed. +'1' : Full-speed. +Notes: +- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. + [1:1] + read-only + + + SUSP + If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +Set to '1' : Suspend. +Set '0' when this bit is '1' : Resume. +Other conditions : Holds the status. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. +- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). +- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. + [2:2] + read-write + + + SOFBUSY + When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. +'0' : The SOF timer is stopped. +'1' : The SOF timer is active. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). +- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. + [3:3] + read-write + + + URST + When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-only + + + RSTBUSY + This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. +'0' : USB Host isn't being reset. +'1' : USB Host is being reset. +Notes: +- If this bit is '1', the a token must not be executed. +- This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. + [6:6] + read-only + + + CLKSEL_ST + This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +'0' : Low speed +'1' : Full speed +Note: +- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [7:7] + read-only + + + HOST_ST + This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. +'0' : USB Device +'1' : USB Host +Notes: +- If this bit is different from the HOST bit, The execution of a token must wait these bits match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. + [8:8] + read-only + + + + + HOST_FCOMP + Host SOF Interrupt Frame Compare Register + 0x10C + 32 + read-write + 0x0 + 0xFF + + + FRAMECOMP + These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. +If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:0] + read-write + + + + + HOST_RTIMER + Host Retry Timer Setup Register + 0x110 + 32 + read-write + 0x0 + 0x3FFFF + + + RTIMER + These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. +If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. + [17:0] + read-write + + + + + HOST_ADDR + Host Address Register + 0x114 + 32 + read-write + 0x0 + 0x7F + + + ADDRESS + These bits are used to specify a token address. +Note: +- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:0] + read-write + + + + + HOST_EOF + Host EOF Setup Register + 0x118 + 32 + read-write + 0x0 + 0x3FFF + + + EOF + These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. +Setting example: MAXPKT = 64 bytes, full-speed mode + (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time + =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit + Therefore, set 0x2C9. +Note: +- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [13:0] + read-write + + + + + HOST_FRAME + Host Frame Setup Register + 0x11C + 32 + read-write + 0x0 + 0x7FF + + + FRAME + These bits are used to specify a frame number of SOF. +Notes: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. + [10:0] + read-write + + + + + HOST_TOKEN + Host Token Endpoint Register + 0x120 + 32 + read-write + 0x0 + 0x17F + + + ENDPT + These bits are used to specify an endpoint to send or receive data to or from the device. +Note: +- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:0] + read-write + + + TKNEN + These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. +Notes: +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The PRE packet isn't supported. +- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' +- Mode should be USB Host before writing data to this bit. +- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. +- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. +- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [6:4] + read-write + + + NONE + Sends no data. + 0 + + + SETUP + Sends SETUP token. + 1 + + + IN + Sends IN token. + 2 + + + OUT + Sends OUT token. + 3 + + + SOF + Sends SOF token. + 4 + + + ISO_IN + Sends Isochronous IN. + 5 + + + ISO_OUT + Sends Isochronous OUT. + 6 + + + RSV + N/A + 7 + + + + + TGGL + This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. +'0' : DATA0 +'1' : DATA1 +Notes: +- This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. + [8:8] + read-write + + + + + HOST_EP1_CTL + Host Endpoint 1 Control Register + 0x400 + 32 + read-write + 0x8100 + 0x9DFF + + + PKS1 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. +- If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, + [8:0] + read-write + + + NULLE + When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the packet transfer mode. +'1' : Sets the packet transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. + [15:15] + read-write + + + + + HOST_EP1_STATUS + Host Endpoint 1 Status Register + 0x404 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE1 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. +The indication range is from 0x000 to 0x100. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [8:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP1 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. +'0' : Not initiatialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP1_RW1_DR + Host Endpoint 1 Data 1-Byte Register + 0x408 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP1 for 1-byte data + [7:0] + read-write + + + + + HOST_EP1_RW2_DR + Host Endpoint 1 Data 2-Byte Register + 0x40C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP1 for 2-byte data + [15:0] + read-write + + + + + HOST_EP2_CTL + Host Endpoint 2 Control Register + 0x500 + 32 + read-write + 0x8040 + 0x9C7F + + + PKS2 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. +- If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. + [6:0] + read-write + + + NULLE + When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the automatic buffer transfer mode. +'1' : Sets the automatic buffer transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. + [15:15] + read-write + + + + + HOST_EP2_STATUS + Host Endpoint 2 Status Register + 0x504 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE2 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. +The indication range is from 0x000 to 0x40. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [6:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP2 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. +'0' : Not Initialized +'1' : Initialized +Note: +- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP2_RW1_DR + Host Endpoint 2 Data 1-Byte Register + 0x508 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP2 for 1-byte data. + [7:0] + read-write + + + + + HOST_EP2_RW2_DR + Host Endpoint 2 Data 2-Byte Register + 0x50C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP2 for 2 byte data. + [15:0] + read-write + + + + + HOST_LVL1_SEL + Host Interrupt Level 1 Selection Register + 0x800 + 32 + read-write + 0x0 + 0xFFFF + + + SOFIRQ_SEL + These bits assign SOFIRQ interrupt flag to selected interrupt signals. + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + DIRQ_SEL + These bits assign DIRQ interrupt flag to selected interrupt signals. + [3:2] + read-write + + + CNNIRQ_SEL + These bits assign CNNIRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + CMPIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [7:6] + read-write + + + URIRQ_SEL + These bits assign URIRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + RWKIRQ_SEL + These bits assign RWKIRQ interrupt flag to selected interrupt signals. + [11:10] + read-write + + + RSVD_13_12 + N/A + [13:12] + read-write + + + TCAN_SEL + These bits assign TCAN interrupt flag to selected interrupt signals. + [15:14] + read-write + + + + + HOST_LVL2_SEL + Host Interrupt Level 2 Selection Register + 0x804 + 32 + read-write + 0x0 + 0xFF0 + + + EP1_DRQ_SEL + These bits assign EP1_DRQ interrupt flag to selected interrupt signals. + [5:4] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + N/A + 3 + + + + + EP1_SPK_SEL + These bits assign EP1_SPK interrupt flag to selected interrupt signals. + [7:6] + read-write + + + EP2_DRQ_SEL + These bits assign EP2_DRQ interrupt flag to selected interrupt signals. + [9:8] + read-write + + + EP2_SPK_SEL + These bits assign EP2_SPK interrupt flag to selected interrupt signals. + [11:10] + read-write + + + + + INTR_USBHOST_CAUSE_HI + Interrupt USB Host Cause High Register + 0x900 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_MED + Interrupt USB Host Cause Medium Register + 0x904 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_LO + Interrupt USB Host Cause Low Register + 0x908 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_HOST_EP_CAUSE_HI + Interrupt USB Host Endpoint Cause High Register + 0x920 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_MED + Interrupt USB Host Endpoint Cause Medium Register + 0x924 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_LO + Interrupt USB Host Endpoint Cause Low Register + 0x928 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_USBHOST + Interrupt USB Host Register + 0x940 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQ + If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Does not issue an interrupt request by starting a SOF token. +'1' : Issues an interrupt request by starting a SOF token. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + DIRQ + If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device disconnection. +'1' : Issues an interrupt request by detecting a device disconnection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:1] + read-write + + + CNNIRQ + If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by detecting a device connection. +'1' : Issues an interrupt request by detecting a device connection. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + CMPIRQ + If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by token completion. +'1' : Issues an interrupt request by token completion. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. +- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [3:3] + read-write + + + URIRQ + If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by USB bus resetting. +'1' : Issues an interrupt request by USB bus resetting. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + RWKIRQ + If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. +'0' : Issues no interrupt request by restart. +'1' : Issues an interrupt request by restart. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCAN + If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. +'0' : Does not cancel token sending. +'1' : Cancels token sending. +Note : +- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + INTR_USBHOST_SET + Interrupt USB Host Set Register + 0x944 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQS + This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [0:0] + read-write + + + DIRQS + This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [1:1] + read-write + + + CNNIRQS + This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [2:2] + read-write + + + CMPIRQS + This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [3:3] + read-write + + + URIRQS + This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [4:4] + read-write + + + RWKIRQS + This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANS + This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. + [7:7] + read-write + + + + + INTR_USBHOST_MASK + Interrupt USB Host Mask Register + 0x948 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQM + This bit masks the interrupt by SOF flag. +'0' : Disables +'1' : Enables + [0:0] + read-write + + + DIRQM + This bit masks the interrupt by DIRQ flag. +'0' : Disables +'1' : Enables + [1:1] + read-write + + + CNNIRQM + This bit masks the interrupt by CNNIRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + CMPIRQM + This bit masks the interrupt by CMPIRQ flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + URIRQM + This bit masks the interrupt by URIRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + RWKIRQM + This bit masks the interrupt by RWKIRQ flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANM + This bit masks the interrupt by TCAN flag. +'0' : Disables +'1' : Enables + [7:7] + read-write + + + + + INTR_USBHOST_MASKED + Interrupt USB Host Masked Register + 0x94C + 32 + read-only + 0x0 + 0xFF + + + SOFIRQED + This bit indicates the interrupt by SOF flag. +'0' : Doesn't request the interrupt by SOF +'1' : Request the interrupt by SOF + [0:0] + read-only + + + DIRQED + This bit indicates the interrupt by DIRQ flag. +'0' : Doesn't request the interrupt by DIRQ +'1' : Request the interrupt by DIRQ + [1:1] + read-only + + + CNNIRQED + This bit indicates the interrupt by CNNIRQ flag. +'0' : Doesn't request the interrupt by CNNIRQ +'1' : Request the interrupt by CNNIRQ + [2:2] + read-only + + + CMPIRQED + This bit indicates the interrupt by CMPIRQ flag. +'0' : Doesn't request the interrupt by CMPIRQ +'1' : Request the interrupt by CMPIRQ + [3:3] + read-only + + + URIRQED + This bit indicates the interrupt by URIRQ flag. +'0' : Doesn't request the interrupt by URIRQ +'1' : Request the interrupt by URIRQ + [4:4] + read-only + + + RWKIRQED + This bit indicates the interrupt by RWKIRQ flag. +'0' : Doesn't request the interrupt by RWKIRQ +'1' : Request the interrupt by RWKIRQ + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCANED + This bit indicates the interrupt by TCAN flag. +'0' : Doesn't request the interrupt by TCAN +'1' : Request the interrupt by TCAN + [7:7] + read-only + + + + + INTR_HOST_EP + Interrupt USB Host Endpoint Register + 0xA00 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQ + This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [2:2] + read-write + + + EP1SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The EP1SPK bit is not set during data transfer in the OUT direction. + [3:3] + read-write + + + EP2DRQ + This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [4:4] + read-write + + + EP2SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The SPK bit is not set during data transfer in the OUT direction. + [5:5] + read-write + + + + + INTR_HOST_EP_SET + Interrupt USB Host Endpoint Set Register + 0xA04 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQS + This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. + [2:2] + read-write + + + EP1SPKS + This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. + [3:3] + read-write + + + EP2DRQS + This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. + [4:4] + read-write + + + EP2SPKS + This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. + [5:5] + read-write + + + + + INTR_HOST_EP_MASK + Interrupt USB Host Endpoint Mask Register + 0xA08 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQM + This bit masks the interrupt by EP1DRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + EP1SPKM + This bit masks the interrupt by EP1SPK flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + EP2DRQM + This bit masks the interrupt by EP2DRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + EP2SPKM + This bit masks the interrupt by EP2SPK flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + + + INTR_HOST_EP_MASKED + Interrupt USB Host Endpoint Masked Register + 0xA0C + 32 + read-only + 0x0 + 0x3C + + + EP1DRQED + This bit indicates the interrupt by EP1DRQ flag. +'0' : Doesn't request the interrupt by EP1DRQ +'1' : Request the interrupt by EP1DRQ + [2:2] + read-only + + + EP1SPKED + This bit indicates the interrupt by EP1SPK flag. +'0' : Doesn't request the interrupt by EP1SPK +'1' : Request the interrupt by EP1SPK + [3:3] + read-only + + + EP2DRQED + This bit indicates the interrupt by EP2DRQ flag. +'0' : Doesn't request the interrupt by EP2DRQ +'1' : Request the interrupt by EP2DRQ + [4:4] + read-only + + + EP2SPKED + This bit indicates the interrupt by EP2SPK flag. +'0' : Doesn't request the interrupt by EP2SPK +'1' : Request the interrupt by EP2SPK + [5:5] + read-only + + + + + HOST_DMA_ENBL + Host DMA Enable Register + 0xB00 + 32 + read-write + 0x0 + 0xC + + + DM_EP1DRQE + This bit enables DMA Request by EP1DRQ. +'0' : Disable +'1' : Enable + [2:2] + read-write + + + DM_EP2DRQE + This bit enables DMA Request by EP2DRQ. +'0' : Disable +'1' : Enable + [3:3] + read-write + + + + + HOST_EP1_BLK + Host Endpoint 1 Block Register + 0xB20 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') + [31:16] + read-write + + + + + HOST_EP2_BLK + Host Endpoint 2 Block Register + 0xB30 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') + [31:16] + read-write + + + + + + + + SMIF0 + Serial Memory Interface + SMIF + 0x40420000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x3000 + 0x81073001 + + + XIP_MODE + Mode of operation. + +Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. + [0:0] + read-write + + + MMIO_MODE + '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. + 0 + + + XIP_MODE + 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. + 1 + + + + + CLOCK_IF_RX_SEL + Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. +'0': 'spi_clk_out' (internal clock) +'1': !'spi_clk_out' (internal clock) +'2': 'spi_clk_in' (feedback clock) +'3': !'spi_clk_in' (feedback clock) + +Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. + [13:12] + read-write + + + DESELECT_DELAY + Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: +'0': 1 interface clock cycle. +'1': 2 interface clock cycles. +'2': 3 interface clock cycles. +'3': 4 interface clock cycles. +'4': 5 interface clock cycles. +'5': 6 interface clock cycles. +'6': 7 interface clock cycles. +'7': 8 interface clock cycles. + +During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. + [18:16] + read-write + + + BLOCK + Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. + +This field is not used for test controller accesses. + [24:24] + read-write + + + BUS_ERROR + 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). + 0 + + + WAIT_STATES + 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). + 1 + + + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. +'1': Enabled. + +Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + Cache, cryptography, XIP, device interface or any other logic busy in the IP: +'0': not busy +'1': busy +When BUSY is '0', the IP can be safely disabled without: +- the potential loss of transient write data. +- the potential risk of aborting an inflight SPI device interface transfer. +When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. + [31:31] + read-only + + + + + TX_CMD_FIFO_STATUS + Transmitter command FIFO status + 0x44 + 32 + read-only + 0x0 + 0x7 + + + USED3 + Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. + [2:0] + read-only + + + + + TX_CMD_FIFO_WR + Transmitter command FIFO write + 0x50 + 32 + write-only + 0x0 + 0xFFFFF + + + DATA20 + Command data. The higher two bits DATA[19:18] specify the specific command +'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. +- DATA[17:16] specifies the width of the data transfer: + - '0': 1 bit/cycle (single data transfer). + - '1': 2 bits/cycle (dual data transfer). + - '2': 4 bits/cycle (quad data transfer). + - '3': 8 bits/cycle (octal data transfer). +- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. +- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. + - '0': device deselected + - '1': device selected +- DATA[7:0] specifies the transmitted Byte. + +'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. + +'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. + +'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. +- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. + [19:0] + write-only + + + + + TX_DATA_FIFO_CTL + Transmitter data FIFO control + 0x80 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. + [2:0] + read-write + + + + + TX_DATA_FIFO_STATUS + Transmitter data FIFO status + 0x84 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_DATA_FIFO_WR1 + Transmitter data FIFO write + 0x90 + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + TX_DATA_FIFO_WR2 + Transmitter data FIFO write + 0x94 + 32 + write-only + 0x0 + 0xFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + + + TX_DATA_FIFO_WR4 + Transmitter data FIFO write + 0x98 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + DATA2 + TX data (written to TX data FIFO, third byte). + [23:16] + write-only + + + DATA3 + TX data (written to TX data FIFO, fourth byte). + [31:24] + write-only + + + + + RX_DATA_FIFO_CTL + Receiver data FIFO control + 0xC0 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. + [2:0] + read-write + + + + + RX_DATA_FIFO_STATUS + Receiver data FIFO status + 0xC4 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + RX_DATA_FIFO_RD1 + Receiver data FIFO read + 0xD0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + RX_DATA_FIFO_RD2 + Receiver data FIFO read + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + + + RX_DATA_FIFO_RD4 + Receiver data FIFO read + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + DATA2 + RX data (read from RX data FIFO, third byte). + [23:16] + read-only + + + DATA3 + RX data (read from RX data FIFO, fourth byte). + [31:24] + read-only + + + + + RX_DATA_FIFO_RD1_SILENT + Receiver data FIFO silent read + 0xE0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + SLOW_CA_CTL + Slow cache control + 0x100 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. + [25:24] + read-write + + + PREF_EN + Prefetch enable: +'0': Disabled. +'1': Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + ENABLED + Cache enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + SLOW_CA_CMD + Slow cache command + 0x108 + 32 + read-write + 0x0 + 0x1 + + + INV + Cache and prefetch buffer invalidation. +SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. +Note, +A write access will invalidate the prefetch buffer automatically in hardware. +A write access should invalidate both fast and slow caches, by firmware. +Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. + [0:0] + read-write + + + + + FAST_CA_CTL + Fast cache control + 0x180 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + See SLOW_CA_CTL.WAY. + [17:16] + read-write + + + SET_ADDR + See SLOW_CA_CTL.SET_ADDR. + [25:24] + read-write + + + PREF_EN + See SLOW_CA_CTL.PREF_EN. + [30:30] + read-write + + + ENABLED + See SLOW_CA_CTL.ENABLED. + [31:31] + read-write + + + + + FAST_CA_CMD + Fast cache command + 0x188 + 32 + read-write + 0x0 + 0x1 + + + INV + See SLOW_CA_CMD.INV. + [0:0] + read-write + + + + + CRYPTO_CMD + Cryptography Command + 0x200 + 32 + read-write + 0x0 + 0x1 + + + START + SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. + +The operation takes roughly 13 clk_hf clock cycles. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + + + CRYPTO_INPUT0 + Cryptography input 0 + 0x220 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT1 + Cryptography input 1 + 0x224 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT2 + Cryptography input 2 + 0x228 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT3 + Cryptography input 3 + 0x22C + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_KEY0 + Cryptography key 0 + 0x240 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY1 + Cryptography key 1 + 0x244 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY2 + Cryptography key 2 + 0x248 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY3 + Cryptography key 3 + 0x24C + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_OUTPUT0 + Cryptography output 0 + 0x260 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT1 + Cryptography output 1 + 0x264 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT2 + Cryptography output 2 + 0x268 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT3 + Cryptography output 3 + 0x26C + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. + [31:0] + read-write + + + + + INTR + Interrupt register + 0x7C0 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. + [0:0] + read-write + + + TR_RX_REQ + Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Activated in XIP mode, if: +- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. +- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. + +Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. + [5:5] + read-write + + + + + INTR_SET + Interrupt set register + 0x7C4 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x7C8 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x7CC + 32 + read-only + 0x0 + 0x3F + + + TR_TX_REQ + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TR_RX_REQ + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + XIP_ALIGNMENT_ERROR + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TX_CMD_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + TX_DATA_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + RX_DATA_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + 3 + 128 + DEVICE[%s] + Device (only used in XIP mode) + 0x00000800 + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80030101 + + + WR_EN + Write enable: +'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. +'1': write transfers are allowed to this device. + [0:0] + read-write + + + CRYPTO_EN + Cryptography on read/write accesses: +'0': disabled. +'1': enabled. + [8:8] + read-write + + + DATA_SEL + Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): +'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. +'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. +'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. +'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. + [17:16] + read-write + + + ENABLED + Device enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + ADDR + Device region base address + 0x8 + 32 + read-write + 0x0 + 0x0 + + + ADDR + Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. + +In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. + +The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. + [31:8] + read-write + + + + + MASK + Device region mask + 0xC + 32 + read-write + 0x0 + 0x0 + + + MASK + Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. + +The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. + +Note: a transfer request that is not in any device region results in an AHB-Lite bus error. + [31:8] + read-write + + + + + ADDR_CTL + Address control + 0x20 + 32 + read-write + 0x0 + 0x103 + + + SIZE2 + Specifies the size of the XIP device address in Bytes: +'0': 1 Byte address. +'1': 2 Byte address. +'2': 3 Byte address. +'3': 4 Byte address. +The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [1:0] + read-write + + + DIV2 + Specifies if the AHB-Lite bus transfer address is divided by 2 or not: +'0': No divide by 2. +'1': Divide by 2. + +This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [8:8] + read-write + + + + + RD_CMD_CTL + Read command control + 0x40 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of data transfer: +'0': 1 bit/cycle (single data transfer). +'1': 2 bits/cycle (dual data transfer). +'2': 4 bits/cycle (quad data transfer). +'3': 8 bits/cycle (octal data transfer). + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_ADDR_CTL + Read address control + 0x44 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + RD_MODE_CTL + Read mode control + 0x48 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DUMMY_CTL + Read dummy control + 0x4C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + +Note: this field specifies dummy cycles, not dummy Bytes! + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DATA_CTL + Read data control + 0x50 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_CMD_CTL + Write command control + 0x60 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_ADDR_CTL + Write address control + 0x64 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_MODE_CTL + Write mode control + 0x68 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DUMMY_CTL + Write dummy control + 0x6C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DATA_CTL + Write data control + 0x70 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + + + + CANFD0 + CAN Controller + CANFD + 0x40520000 + + 0 + 131072 + registers + + + + CH + FIFO wrapper around M_TTCAN 3PIP, to enable DMA + 0x00000000 + + M_TTCAN + TTCAN 3PIP, includes FD + 0x00000000 + + CREL + Core Release Register + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAY + Time Stamp Day +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [7:0] + read-only + + + MON + Time Stamp Month +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [15:8] + read-only + + + YEAR + Time Stamp Year +One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [19:16] + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded. + [23:20] + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + [27:24] + read-only + + + REL + Core Release +One digit, BCD-coded. + [31:28] + read-only + + + + + ENDN + Endian Register + 0x4 + 32 + read-only + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness Test Value +The endianness test value is 0x87654321. + [31:0] + read-only + + + + + DBTP + Data Bit Timing & Prescaler Register + 0xC + 32 + read-write + 0xA33 + 0x9F1FFF + + + DSJW + Data (Re)Synchronization Jump Width +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [3:0] + read-write + + + DTSEG2 + Data time segment after sample point +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [7:4] + read-write + + + DTSEG1 + Data time segment before sample point +0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [12:8] + read-write + + + DBRP + Data Bit Rate Prescaler +0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [20:16] + read-write + + + TDC + Transmitter Delay Compensation +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + [23:23] + read-write + + + + + TEST + Test Register + 0x10 + 32 + read-write + 0x0 + 0x7F + + + TAM + ASC is not supported by M_TTCAN +Test ASC Multiplexer Control +Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_ascm controlled by FSE +1= Level at pin m_ttcan_ascm = '1' + [0:0] + read-write + + + TAT + ASC is not supported by M_TTCAN +Test ASC Transmit Control +Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_asct controlled by FSE +1= Level at pin m_ttcan_asct = '1' + [1:1] + read-write + + + CAM + ASC is not supported by M_TTCAN +Check ASC Multiplexer Control +Monitors level at output pin m_ttcan_ascm. +0= Output pin m_ttcan_ascm = '0' +1= Output pin m_ttcan_ascm = '1' + [2:2] + read-write + + + CAT + ASC is not supported by M_TTCAN +Check ASC Transmit Control +Monitors level at output pin m_ttcan_asct. +0= Output pin m_ttcan_asct = '0' + [3:3] + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) + [4:4] + read-write + + + TX + Control of Transmit Pin +00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_ttcan_tx +10 Dominant ('0') level at pin m_ttcan_tx +11 Recessive ('1') at pin m_ttcan_tx + [6:5] + read-write + + + RX + Receive Pin +Monitors the actual value of pin m_ttcan_rx +0= The CAN bus is dominant (m_ttcan_rx = '0') +1= The CAN bus is recessive (m_ttcan_rx = '1') + [7:7] + read-only + + + + + RWD + RAM Watchdog + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is +disabled. + [7:0] + read-write + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + [15:8] + read-only + + + + + CCCR + CC Control Register + 0x18 + 32 + read-write + 0x1 + 0xF3FF + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + [0:0] + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + [1:1] + read-write + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + [2:2] + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk + [3:3] + read-write + + + CSR + Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after +all pending transfer requests have been completed and the CAN bus reached idle. + [4:4] + read-write + + + MON_ + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + [5:5] + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + [6:6] + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + [7:7] + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + [8:8] + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled + [9:9] + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled + [12:12] + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + [13:13] + read-write + + + TXP + Transmit Pause +If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission +after itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + [14:14] + read-write + + + NISO + Non ISO Operation +If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD + [15:15] + read-write + + + + + NBTP + Nominal Bit Timing & Prescaler Register + 0x1C + 32 + read-write + 0x6000A03 + 0xFFFFFF7F + + + NTSEG2 + Nominal Time segment after sample point +0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [6:0] + read-write + + + NTSEG1 + Nominal Time segment before sample point +0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [15:8] + read-write + + + NBRP + Nominal Bit Rate Prescaler +0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [24:16] + read-write + + + NSJW + Nominal (Re)Synchronization Jump Width +0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [31:25] + read-write + + + + + TSCC + Timestamp Counter Configuration + 0x20 + 32 + read-write + 0x0 + 0xF0003 + + + TSS + Timestamp Select, should always be set to external timestamp counter +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as '00' + [1:0] + read-write + + + TCP + Timestamp Counter Prescaler (still used for TOCC) +0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times +[1...16]. The actual interpretation by the hardware of this value is such that one more +than the value programmed here is used. + [19:16] + read-write + + + + + TSCV + Timestamp Counter Value + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + TSC + Timestamp Counter, not used for M_TTCAN +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). +When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times +[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. +Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external +Timestamp Counter value. A write access has no impact. + [15:0] + read-write + + + + + TOCC + Timeout Counter Configuration + 0x28 + 32 + read-write + 0xFFFF0000 + 0xFFFF0007 + + + ETOC + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + [0:0] + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured +by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the +FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting +is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + [2:1] + read-write + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + [31:16] + read-write + + + + + TOCV + Timeout Counter Value + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the +configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the +Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + [15:0] + read-write + + + + + ECR + Error Counter Register + 0x40 + 32 + read-only + 0x0 + 0xFFFFFF + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 + [7:0] + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + [14:8] + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + [15:15] + read-only + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter +or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops +at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. + [23:16] + read-only + + + + + PSR + Protocol Status Register + 0x44 + 32 + read-only + 0x707 + 0x7F7FFF + + + LEC + Last Error Code, +Set on Read0 +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' +when a message has been transferred (reception or transmission) without error. + +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus + value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or +overload flag), the device wanted to send a dominant level (data or identifier bit logical value +0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set +each time a sequence of 11 recessive bits has been monitored. This enables the CPU to +monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming +message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. +When the LEC shows the value '7', no CAN bus event was detected since the last CPU read +access to the Protocol Status Register. + [2:0] + read-only + + + ACT + Activity +Monitors the module's CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter + [4:3] + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + [5:5] + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + [6:6] + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + [7:7] + read-only + + + DLEC + Data Phase Last Error Code +, Set on Read +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + [10:8] + read-only + + + RESI + ESI flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set + [11:11] + read-only + + + RBRS + BRS flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set + [12:12] + read-only + + + RFDF + Received a CAN FD Message +, Reset on Read +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received + [13:13] + read-only + + + PXE + Protocol Exception Event +, Reset on Read +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred + [14:14] + read-only + + + TDCV + Transmitter Delay Compensation Value +0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + [22:16] + read-only + + + + + TDCR + Transmitter Delay Compensation Register + 0x48 + 32 + read-write + 0x0 + 0x7F7F + + + TDCF + Transmitter Delay Compensation Filter Window Length +0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx +that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than +TDCO. Valid values are 0 to 127 mtq + [6:0] + read-write + + + TDCO + Transmitter Delay Compensation Offset +0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to +m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. + [14:8] + read-write + + + + + IR + Interrupt Register + 0x50 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + [0:0] + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + [1:1] + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [2:2] + read-write + + + RF0L_ + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [3:3] + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + [4:4] + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + [5:5] + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [6:6] + read-write + + + RF1L_ + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [7:7] + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + [8:8] + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + [9:9] + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + [10:10] + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + [11:11] + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + [12:12] + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + [13:13] + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [14:14] + read-write + + + TEFL_ + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + [15:15] + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + [16:16] + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. +- was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM +in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted +Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + [17:17] + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + [18:18] + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into a Rx Buffer + [19:19] + read-write + + + BEC + M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. +Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] +generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + [20:20] + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] +generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected +Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + [21:21] + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + [22:22] + read-write + + + EP_ + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + [23:23] + read-write + + + EW_ + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + [24:24] + read-write + + + BO_ + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + [25:25] + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + [26:26] + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) + [27:27] + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC != 0,7) + [28:28] + read-write + + + ARA + N/A + [29:29] + read-write + + + + + IE + Interrupt Enable + 0x54 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + [0:0] + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + [1:1] + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + [2:2] + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + [3:3] + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + [4:4] + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + [5:5] + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + [6:6] + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + [7:7] + read-write + + + HPME + High Priority Message Interrupt Enable + [8:8] + read-write + + + TCE + Transmission Completed Interrupt Enable + [9:9] + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + [10:10] + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + [11:11] + read-write + + + TEFNE + Tx Event FIDO New Entry Interrupt Enable + [12:12] + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + [13:13] + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + [14:14] + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + [15:15] + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + [16:16] + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + [17:17] + read-write + + + TOOE + Timeout Occurred Interrupt Enable + [18:18] + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + [19:19] + read-write + + + BECE + Bit Error Corrected Interrupt Enable (not used in M_TTCAN) + [20:20] + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + [21:21] + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + [22:22] + read-write + + + EPE + Error Passive Interrupt Enable + [23:23] + read-write + + + EWE + Warning Status Interrupt Enable + [24:24] + read-write + + + BOE + Bus_Off Status Interrupt Enable + [25:25] + read-write + + + WDIE + Watchdog Interrupt Enable + [26:26] + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + [27:27] + read-write + + + PEDE + Protocol Error in Data Phase Enable + [28:28] + read-write + + + ARAE + N/A + [29:29] + read-write + + + + + ILS + Interrupt Line Select + 0x58 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + [0:0] + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + [1:1] + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + [2:2] + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + [3:3] + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + [4:4] + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + [5:5] + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + [6:6] + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + [7:7] + read-write + + + HPML + High Priority Message Interrupt Line + [8:8] + read-write + + + TCL + Transmission Completed Interrupt Line + [9:9] + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + [10:10] + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + [11:11] + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + [12:12] + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + [13:13] + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + [14:14] + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + [15:15] + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + [16:16] + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + [17:17] + read-write + + + TOOL + Timeout Occurred Interrupt Line + [18:18] + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + [19:19] + read-write + + + BECL + Bit Error Corrected Interrupt Line (not used in M_TTCAN) + [20:20] + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + [21:21] + read-write + + + ELOL + Error Logging Overflow Interrupt Line + [22:22] + read-write + + + EPL + Error Passive Interrupt Line + [23:23] + read-write + + + EWL + Warning Status Interrupt Line + [24:24] + read-write + + + BOL + Bus_Off Status Interrupt Line + [25:25] + read-write + + + WDIL + Watchdog Interrupt Line + [26:26] + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + [27:27] + read-write + + + PEDL + Protocol Error in Data Phase Line + [28:28] + read-write + + + ARAL + N/A + [29:29] + read-write + + + + + ILE + Interrupt Line Enable + 0x5C + 32 + read-write + 0x0 + 0x3 + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_ttcan_int0 disabled +1= Interrupt line m_ttcan_int0 enabled + [0:0] + read-write + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_ttcan_int1 disabled +1= Interrupt line m_ttcan_int1 enabled + [1:1] + read-write + + + + + GFC + Global Filter Configuration + 0x80 + 32 + read-write + 0x0 + 0x3F + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + [0:0] + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + [1:1] + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [3:2] + read-write + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [5:4] + read-write + + + + + SIDFC + Standard ID Filter Configuration + 0x84 + 32 + read-write + 0x0 + 0xFFFFFC + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +128= Values greater than 128 are interpreted as 128 + [23:16] + read-write + + + + + XIDFC + Extended ID Filter Configuration + 0x88 + 32 + read-write + 0x0 + 0x7FFFFC + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + XIDAM + Extended ID AND Mask + 0x90 + 32 + read-write + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message +ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all +bits set to one the mask is not active. + [28:0] + read-write + + + + + HPMS + High Priority Message Status + 0x94 + 32 + read-only + 0x0 + 0xFFFF + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. + [5:0] + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + [7:6] + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + [14:8] + read-only + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + [15:15] + read-only + + + + + NDAT1 + New Data 1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + NDAT2 + New Data 2 + 0x9C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + RXF0C + Rx FIFO 0 Configuration + 0xA0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + [22:16] + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + [31:31] + read-write + + + + + RXF0S + Rx FIFO 0 Status + 0xA4 + 32 + read-only + 0x0 + 0x33F3F7F + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + [6:0] + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. +This field is updated by the software writing to RxF0A.F0AI + [13:8] + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + [21:16] + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [24:24] + read-only + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [25:25] + read-only + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0xA8 + 32 + read-write + 0x0 + 0x3F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the + buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index + RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + [5:0] + read-write + + + + + RXBC + Rx Buffer Configuration + 0xAC + 32 + read-write + 0x0 + 0xFFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +Also used to reference debug messages A,B,C. + [15:2] + read-write + + + + + RXF1C + Rx FIFO 1 Configuration + 0xB0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + [22:16] + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + [31:31] + read-write + + + + + RXF1S + Rx FIFO 1 Status + 0xB4 + 32 + read-only + 0x0 + 0xC33F3F7F + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + [6:0] + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. +This field is updated by the software writing to RxF1A.FAI + [13:8] + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + [21:16] + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [24:24] + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [25:25] + read-only + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + [31:30] + read-only + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0xB8 + 32 + read-write + 0x0 + 0x3F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the + buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index + RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + [5:0] + read-write + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0xBC + 32 + read-write + 0x0 + 0x777 + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [6:4] + read-write + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [10:8] + read-write + + + + + TXBC + Tx Buffer Configuration + 0xC0 + 32 + read-write + 0x0 + 0x7F3FFFFC + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +32= Values greater than 32 are interpreted as 32 + [21:16] + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +32= Values greater than 32 are interpreted as 32 + [29:24] + read-write + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + [30:30] + read-write + + + + + TXFQS + Tx FIFO/Queue Status + 0xC4 + 32 + read-only + 0x0 + 0x3F1F3F + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when +Tx Queue operation is configured (TXBC.TFQM = '1') + [5:0] + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +TXBC.TFQM = '1'). + [12:8] + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + [20:16] + read-only + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + [21:21] + read-only + + + + + TXESC + Tx Buffer Element Size Configuration + 0xC8 + 32 + read-write + 0x0 + 0x7 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + + + TXBRP + Tx Buffer Request Pending + 0xCC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. +The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, +a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register +TXBRP. In case a transmission has already been started when a cancellation is requested, this is +done at the end of the transmission, regardless whether the transmission was successful or not. The +cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signaled via TXBCF +after successful transmission together with the corresponding TXBTO bit +when the transmission has not yet been started at the point of cancellation +when the transmission has been aborted due to lost arbitration +when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The +corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending + [31:0] + read-only + + + + + TXBAR + Tx Buffer Add Request + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request +bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan +process has completed. +0= No transmission request added +1= Transmission requested added + [31:0] + read-write + + + + + TXBCR + Tx Buffer Cancellation Request + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding +Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation +requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx +Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + [31:0] + read-write + + + + + TXBTO + Tx Buffer Transmission Occurred + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding +TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission +is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + [31:0] + read-only + + + + + TXBCF + Tx Buffer Cancellation Finished + 0xDC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding +TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding +TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a +new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + [31:0] + read-only + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + [31:0] + read-write + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0xE4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + [31:0] + read-write + + + + + TXEFC + Tx Event FIFO Configuration + 0xF0 + 32 + read-write + 0x0 + 0x3F3FFFFC + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS-1 + [21:16] + read-write + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +32= Watermark interrupt disabled + [29:24] + read-write + + + + + TXEFS + Tx Event FIFO Status + 0xF4 + 32 + read-only + 0x0 + 0x31F1F3F + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + [5:0] + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + [12:8] + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + [20:16] + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [24:24] + read-only + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + [25:25] + read-only + + + + + TXEFA + Tx Event FIFO Acknowledge + 0xF8 + 32 + read-write + 0x0 + 0x1F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write +the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + [4:0] + read-write + + + + + TTTMC + TT Trigger Memory Configuration + 0x100 + 32 + read-write + 0x0 + 0x7FFFFC + + + TMSA + Trigger Memory Start Address +Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + TME + Trigger Memory Elements +0= No Trigger Memory +1-64= Number of Trigger Memory elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + TTRMC + TT Reference Message Configuration + 0x104 + 32 + read-write + 0x0 + 0xDFFFFFFF + + + RID + Reference Identifier +Identifier transmitted with reference message and used for reference message filtering. Standard or +extended reference identifier depending on bit XTD. A standard identifier has to be written to +ID[28:18]. + [28:0] + read-write + + + XTD + Extended Identifier +0= 11-bit standard identifier +1= 29-bit extended identifier + [30:30] + read-write + + + RMPS + Reference Message Payload Select +Ignored in case of time slaves. +0= Reference message has no additional payload +1= The following elements are taken from Tx Buffer 0: +Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB +Level 1: bytes 2-8, Level 0,2: bytes 5-8) + [31:31] + read-write + + + + + TTOCF + TT Operation Configuration + 0x108 + 32 + read-write + 0x10000 + 0x7FFFFFB + + + OM + Operation Mode +00= Event-driven CAN communication, default +01= TTCAN level 1 +10= TTCAN level 2 +11= TTCAN level 0 + [1:0] + read-write + + + GEN + Gap Enable +0= Strictly time-triggered operation +1= External event-synchronized time-triggered operation + [3:3] + read-write + + + TM + Time Master +0= Time Master function disabled +1= Potential Time Master + [4:4] + read-write + + + LDSDL + LD of Synchronization Deviation Limit +The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = +2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. +0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) + [7:5] + read-write + + + IRTO + Initial Reference Trigger Offset +0x00-7F Positive offset, range from 0 to 127 + [14:8] + read-write + + + EECS + Enable External Clock Synchronization +If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. +0= External clock synchronization in TTCAN Level 0,2 disabled +1= External clock synchronization in TTCAN Level 0,2 enabled + [15:15] + read-write + + + AWL + Application Watchdog Limit +The application watchdog can be disabled by programming AWL to 0x00. +0x00-FF Maximum time after which the application has to serve the application watchdog. +The application watchdog is incremented once each 256 NTUs. + [23:16] + read-write + + + EGTF + Enable Global Time Filtering +0= Global time filtering in TTCAN Level 0,2 is disabled +1= Global time filtering in TTCAN Level 0,2 is enabled + [24:24] + read-write + + + ECC + Enable Clock Calibration +0= Automatic clock calibration in TTCAN Level 0,2 is disabled +1= Automatic clock calibration in TTCAN Level 0,2 is enabled + [25:25] + read-write + + + EVTP + Event Trigger Polarity +0= Rising edge trigger +1= Falling edge trigger + [26:26] + read-write + + + + + TTMLM + TT Matrix Limits + 0x10C + 32 + read-write + 0x0 + 0xFFF0FFF + + + CCM + N/A + [5:0] + read-write + + + CSS + N/A + [7:6] + read-write + + + TXEW + Tx Enable Window +0x0-F Length of Tx enable window, 1-16 NTU cycles + [11:8] + read-write + + + ENTT + Expected Number of Tx Triggers +0x000-FFF Expected number of Tx Triggers in one Matrix Cycle + [27:16] + read-write + + + + + TURCF + TUR Configuration + 0x110 + 32 + read-write + 0x10000000 + 0xBFFFFFFF + + + NCL + Numerator Configuration Low +Write access to the TUR Numerator Configuration Low is only possible during configuration with +TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new +value for NCL is written outside TT Configuration Mode, the new value takes effect when +TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. +0x0000-FFFF Numerator Configuration Low + [15:0] + read-write + + + DC + Denominator Configuration +0x0000 Illegal value +0x0001-3FFF Denominator Configuration + [29:16] + read-write + + + ELT + Enable Local Time +0= Local time is stopped, default +1= Local time is enabled + [31:31] + read-write + + + + + TTOCN + TT Operation Control + 0x114 + 32 + read-write + 0x0 + 0xBFFF + + + SGT + Set Global time +Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one +Host clock period. The global time preset takes effect when the node transmits the next reference +message with the Master_Ref_Mark modified by the preset value written to TTGTP. + [0:0] + read-write + + + ECS + External Clock Synchronization +Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one +Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. + [1:1] + read-write + + + SWP + Stop Watch Polarity +0= Rising edge trigger +1= Falling edge trigger + [2:2] + read-write + + + SWS + Stop Watch Source +00= Stop Watch disabled +01= Actual value of cycle time is copied to TTCPT.SWV +10= Actual value of local time is copied to TTCPT.SWV +11= Actual value of global time is copied to TTCPT.SWV + [4:3] + read-write + + + RTIE + Register Time Mark Interrupt Pulse Enable +Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse +with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or +global) equals TTTMK.TM, independent of the synchronization state. +0= Register Time Mark Interrupt output m_ttcan_rtp disabled +1= Register Time Mark Interrupt output m_ttcan_rtp enabled + [5:5] + read-write + + + TMC + Register Time Mark Compare +00= No Register Time Mark Interrupt generated +01= Register Time Mark Interrupt if Time Mark = cycle time +10= Register Time Mark Interrupt if Time Mark = local time +11= Register Time Mark Interrupt if Time Mark = global time + [7:6] + read-write + + + TTIE + Trigger Time Mark Interrupt Pulse Enable +External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A +trigger time mark interrupt pulse is generated when the trigger memory element becomes active, +and the M_TTCAN is in synchronization state In_Schedule or In_Gap. +0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled +1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled + [8:8] + read-write + + + GCS + Gap Control Select +0= Gap control independent from m_ttcan_evt +1= Gap control by input pin m_ttcan_evt + [9:9] + read-write + + + FGP + Finish Gap +Set by the CPU, reset by each reference message +0= No reference message requested +1= Application requested start of reference message + [10:10] + read-write + + + TMG + Time Mark Gap +0= Reset by each reference message +1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated + [11:11] + read-write + + + NIG + Next is Gap +This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for +external event-synchronized time-triggered operation (TTOCF.GEN = '1') +0= No action, reset by reception of any reference message +1= Transmit next reference message with Next_is_Gap = '1' + [12:12] + read-write + + + ESCN + External Synchronization Control +If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising +edge at pin m_ttcan_evt (see Section 4.11). +0= External synchronization disabled +1= External synchronization enabled + [13:13] + read-write + + + LCKC + TT Operation Control Register Locked +Set by a write access to register TTOCN. Reset when the updated configuration has been +synchronized into the CAN clock domain. +0= Write access to TTOCN enabled +1= Write access to TTOCN locked + [15:15] + read-only + + + + + TTGTP + TT Global Time Preset + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TP + N/A + [15:0] + read-write + + + CTP + Cycle Time Target Phase +CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). +0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected + [31:16] + read-write + + + + + TTTMK + TT Time Mark + 0x11C + 32 + read-write + 0x0 + 0x807FFFFF + + + TM_ + Time Mark +0x0000-FFFF Time Mark + [15:0] + read-write + + + TICC + Time Mark Cycle Code +Cycle count for which the time mark is valid. +0b000000x valid for all cycles +0b000001c valid every second cycle at cycle count mod2 = c +0b00001cc valid every fourth cycle at cycle count mod4 = cc +0b0001ccc valid every eighth cycle at cycle count mod8 = ccc +0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc +0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc +0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc + [22:16] + read-write + + + LCKM + TT Time Mark Register Locked +Always set by a write access to registers TTOCN. Set by write access to register TTTMK when +TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. +0= Write access to TTTMK enabled +1= Write access to TTTMK locked + [31:31] + read-only + + + + + TTIR + TT Interrupt Register + 0x120 + 32 + read-write + 0x0 + 0x7FFFF + + + SBC + Start of Basic Cycle +0= No Basic Cycle started since bit has been reset +1= Basic Cycle started + [0:0] + read-write + + + SMC + Start of Matrix Cycle +0= No Matrix Cycle started since bit has been reset +1= Matrix Cycle started + [1:1] + read-write + + + CSM_ + Change of Synchronization Mode +0= No change in master to slave relation or schedule synchronization +1= Master to slave relation or schedule synchronization changed, +also set when TTOST.SPL is reset + [2:2] + read-write + + + SOG + Start of Gap +0= No reference message seen with Next_is_Gap bit set +1= Reference message with Next_is_Gap bit set becomes valid + [3:3] + read-write + + + RTMI + Register Time Mark Interrupt +Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent +of the synchronization state. +0= Time mark not reached +1= Time mark reached + [4:4] + read-write + + + TTMI + Trigger Time Mark Event Internal +Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set +when the trigger memory element becomes active, and the M_TTCAN is in synchronization state +In_Gap or In_Schedule. +0= Time mark not reached +1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) + [5:5] + read-write + + + SWE + Stop Watch Event +0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected +1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected + [6:6] + read-write + + + GTW + Global Time Wrap +0= No global time wrap occurred +1= Global time wrap from 0xFFFF to 0x0000 occurred + [7:7] + read-write + + + GTD + Global Time Discontinuity +0= No discontinuity of global time +1= Discontinuity of global time + [8:8] + read-write + + + GTE + Global Time Error +Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. +0= Synchronization deviation within limit +1= Synchronization deviation exceeded limit + [9:9] + read-write + + + TXU + Tx Count Underflow +0= Number of Tx Trigger as expected +1= Less Tx trigger than expected in one matrix cycle + [10:10] + read-write + + + TXO + Tx Count Overflow +0= Number of Tx Trigger as expected +1= More Tx trigger than expected in one matrix cycle + [11:11] + read-write + + + SE1 + Scheduling Error 1 +0= No scheduling error 1 +1= Scheduling error 1 occurred + [12:12] + read-write + + + SE2 + Scheduling Error 2 +0= No scheduling error 2 +1= Scheduling error 2 occurred + [13:13] + read-write + + + ELC + Error Level Changed +Not set when error level changed during initialization. +0= No change in error level +1= Error level changed + [14:14] + read-write + + + IWT + Initialization Watch Trigger +The initialization is restarted by resetting IWT. +0= No missing reference message during system startup +1= No system startup due to missing reference message + [15:15] + read-write + + + WT + Watch Trigger +0= No missing reference message +1= Missing reference message (Level 0: cycle time 0xFF00) + [16:16] + read-write + + + AW + Application Watchdog +0= Application watchdog served in time +1= Application watchdog not served in time + [17:17] + read-write + + + CER + Configuration Error +Trigger out of order. +0= No error found in trigger list +1= Error found in trigger list + [18:18] + read-write + + + + + TTIE + TT Interrupt Enable + 0x124 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCE + Start of Basic Cycle Interrupt Enable + [0:0] + read-write + + + SMCE + Start of Matrix Cycle Interrupt Enable + [1:1] + read-write + + + CSME + Change of Synchronization Mode Interrupt Enable + [2:2] + read-write + + + SOGE + Start of Gap Interrupt Enable + [3:3] + read-write + + + RTMIE + Register Time Mark Interrupt Enable + [4:4] + read-write + + + TTMIE + Trigger Time Mark Event Internal Enable + [5:5] + read-write + + + SWEE + Stop Watch Event Interrupt Enable + [6:6] + read-write + + + GTWE + Global Time Wrap Interrupt Enable + [7:7] + read-write + + + GTDE + Global Time Discontinuity Interrupt Enable + [8:8] + read-write + + + GTEE + Global Time Error Interrupt Enable + [9:9] + read-write + + + TXUE + Tx Count Underflow Interrupt Enable + [10:10] + read-write + + + TXOE + Tx Count Overflow Interrupt Enable + [11:11] + read-write + + + SE1E + Scheduling Error 1 Interrupt Enable + [12:12] + read-write + + + SE2E + Scheduling Error 2 Interrupt Enable + [13:13] + read-write + + + ELCE + Change Error Level Interrupt Enable + [14:14] + read-write + + + IWTE + Initialization Watch Trigger Interrupt Enable + [15:15] + read-write + + + WTE + Watch Trigger Interrupt Enable + [16:16] + read-write + + + AWE_ + Application Watchdog Interrupt Enable + [17:17] + read-write + + + CERE + Configuration Error Interrupt Enable + [18:18] + read-write + + + + + TTILS + TT Interrupt Line Select + 0x128 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCL + Start of Basic Cycle Interrupt Line + [0:0] + read-write + + + SMCL + Start of Matrix Cycle Interrupt Line + [1:1] + read-write + + + CSML + Change of Synchronization Mode Interrupt Line + [2:2] + read-write + + + SOGL + Start of Gap Interrupt Line + [3:3] + read-write + + + RTMIL + Register Time Mark Interrupt Line + [4:4] + read-write + + + TTMIL + Trigger Time Mark Event Internal Line + [5:5] + read-write + + + SWEL + Stop Watch Event Interrupt Line + [6:6] + read-write + + + GTWL + Global Time Wrap Interrupt Line + [7:7] + read-write + + + GTDL + Global Time Discontinuity Interrupt Line + [8:8] + read-write + + + GTEL + Global Time Error Interrupt Line + [9:9] + read-write + + + TXUL + Tx Count Underflow Interrupt Line + [10:10] + read-write + + + TXOL + Tx Count Overflow Interrupt Line + [11:11] + read-write + + + SE1L + Scheduling Error 1 Interrupt Line + [12:12] + read-write + + + SE2L + Scheduling Error 2 Interrupt Line + [13:13] + read-write + + + ELCL + Change Error Level Interrupt Line + [14:14] + read-write + + + IWTL + Initialization Watch Trigger Interrupt Line + [15:15] + read-write + + + WTL + Watch Trigger Interrupt Line + [16:16] + read-write + + + AWL_ + Application Watchdog Interrupt Line + [17:17] + read-write + + + CERL + Configuration Error Interrupt Line + [18:18] + read-write + + + + + TTOST + TT Operation Status + 0x12C + 32 + read-only + 0x0 + 0xFFC0FFFF + + + EL + Error Level +00= Severity 0 - No Error +01= Severity 1 - Warning +10= Severity 2 - Error +11= Severity 3 - Severe Error + [1:0] + read-only + + + MS + Master State +00= Master_Off, no master properties relevant +01= Operating as Time Slave +10= Operating as Backup Time Master +11= Operating as current Time Master + [3:2] + read-only + + + SYS + Synchronization State +00= Out of Synchronization +01= Synchronizing to TTCAN communication +10= Schedule suspended by Gap (In_Gap) +11= Synchronized to schedule (In_Schedule) + [5:4] + read-only + + + QGTP + Quality of Global Time Phase +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. +0= Global time not valid +1= Global time in phase with Time Master + [6:6] + read-only + + + QCS + Quality of Clock Speed +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. +0= Local clock speed not synchronized to Time Master clock speed +1= Synchronization Deviation <= SDL + [7:7] + read-only + + + RTO + Reference Trigger Offset +The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). +There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes +Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and +CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. +0x00-FF Actual Reference Trigger offset value + [15:8] + read-only + + + WGTD + Wait for Global Time Discontinuity +0= No global time preset pending +1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted +a reference message with Disc_Bit = '1' or after it received a reference message. + [22:22] + read-only + + + GFI + Gap Finished Indicator +Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin +m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another +node sending a reference message. +0= Reset at the end of each reference message +1= Gap finished by M_TTCAN + [23:23] + read-only + + + TMP + Time Master Priority +0x0-7 Priority of actual Time Master + [26:24] + read-only + + + GSI + Gap Started Indicator +0= No Gap in schedule, reset by each reference message and for all time slaves +1= Gap time after Basic Cycle has started + [27:27] + read-only + + + WFE + Wait for Event +0= No Gap announced, reset by a reference message with Next_is_Gap = '0' +1= Reference message with Next_is_Gap = '1' received + [28:28] + read-only + + + AWE + Application Watchdog Event +The application watchdog is served by reading TTOST. When the watchdog is not served in time, +bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring +Mode. +0= Application Watchdog served in time +1= Failed to serve Application Watchdog in time + [29:29] + read-only + + + WECS + Wait for External Clock Synchronization +0= No external clock synchronization pending +1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the +next basic cycle. + [30:30] + read-only + + + SPL + Schedule Phase Lock +The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it +signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the +rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). +0= Phase outside range +1= Phase inside range + [31:31] + read-only + + + + + TURNA + TUR Numerator Actual + 0x130 + 32 + read-only + 0x10000 + 0x3FFFF + + + NAV + N/A + [17:0] + read-only + + + + + TTLGT + TT Local & Global Time + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + LT + Local Time +Non-fractional part of local time, incremented once each local NTU (see Section 4.5). +0x0000-FFFF Local time value of TTCAN node + [15:0] + read-only + + + GT + Global Time +Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). +0x0000-FFFF Global time value of TTCAN network + [31:16] + read-only + + + + + TTCTC + TT Cycle Time & Count + 0x138 + 32 + read-only + 0x3F0000 + 0x3FFFFF + + + CT + Cycle Time +Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). +0x0000-FFFF Cycle time value of TTCAN Basic Cycle + [15:0] + read-only + + + CC + Cycle Count +0x00-3F Number of actual Basic Cycle in the System Matrix + [21:16] + read-only + + + + + TTCPT + TT Capture Time + 0x13C + 32 + read-only + 0x0 + 0xFFFF003F + + + CCV + Cycle Count Value +Cycle count value captured together with SWV. +0x00-3F Captured cycle count value + [5:0] + read-only + + + SWV + Stop Watch Value +On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected +by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. +0x0000-FFFF Captured Stop Watch value + [31:16] + read-only + + + + + TTCSM + TT Cycle Sync Mark + 0x140 + 32 + read-only + 0x0 + 0xFFFF + + + CSM + Cycle Sync Mark +The Cycle Sync Mark is measured + [15:0] + read-only + + + + + + RXFTOP_CTL + Receive FIFO Top control + 0x180 + 32 + read-write + 0x0 + 0x3 + + + F0TPE + FIFO 0 Top Pointer Enable. +This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. +This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). +When this logic is disabled a Read from RXFTOP0_DATA is undefined. + [0:0] + read-write + + + F1TPE + FIFO 1 Top Pointer Enable. + [1:1] + read-write + + + + + RXFTOP0_STAT + Receive FIFO 0 Top Status + 0x1A0 + 32 + read-only + 0x0 + 0xFFFF + + + F0TA + Current FIFO 0 Top Address. +This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) +FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC + [15:0] + read-only + + + + + RXFTOP0_DATA + Receive FIFO 0 Top Data + 0x1A8 + 32 + read-only + 0x0 + 0x0 + + + F0TD + When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: +- M_TTCAN not being reconfigured (CCCR.CCE=0) +- FIFO Top Pointer logic is enabled (FnTPE=1) +- FIFO is not empty (FnFL!=0) +The read side effect is as follows: +- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI +- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) +- the FIFO top address FnTA is incremented (with FIFO wrap around) +When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. + [31:0] + read-only + + + + + RXFTOP1_STAT + Receive FIFO 1 Top Status + 0x1B0 + 32 + read-only + 0x0 + 0xFFFF + + + F1TA + See F0TA description + [15:0] + read-only + + + + + RXFTOP1_DATA + Receive FIFO 1 Top Data + 0x1B8 + 32 + read-only + 0x0 + 0x0 + + + F1TD + See F0TD description + [31:0] + read-only + + + + + + CTL + Global CAN control register + 0x1000 + 32 + read-write + 0x0 + 0x800000FF + + + STOP_REQ + Clock Stop Request for each TTCAN IP . +The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. + [7:0] + read-write + + + MRAM_OFF + MRAM off +0= Default MRAM on (with MRAM retained in DeepSleep). +1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. +When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). +After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. + +To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. + [31:31] + read-write + + + + + STATUS + Global CAN status register + 0x1004 + 32 + read-only + 0x0 + 0xFF + + + STOP_ACK + Clock Stop Acknowledge for each TTCAN IP. +These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. +When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write + [7:0] + read-only + + + + + INTR0_CAUSE + Consolidated interrupt0 cause register + 0x1010 + 32 + read-only + 0x0 + 0xFF + + + INT0 + Show pending m_ttcan_int0 of each channel + [7:0] + read-only + + + + + INTR1_CAUSE + Consolidated interrupt1 cause register + 0x1014 + 32 + read-only + 0x0 + 0xFF + + + INT1 + Show pending m_ttcan_int1 of each channel + [7:0] + read-only + + + + + TS_CTL + Time Stamp control register + 0x1020 + 32 + read-write + 0x0 + 0x8000FFFF + + + PRESCALE + Time Stamp counter prescale value. +When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. + [15:0] + read-write + + + ENABLED + Counter enable bit +0 = Count disabled. Stop counting up and keep the counter value +1 = Count enabled. Start counting up from the current value + [31:31] + read-write + + + + + TS_CNT + Time Stamp counter value + 0x1024 + 32 + read-write + 0x0 + 0xFFFF + + + VALUE + The counter value of the Time Stamp Counter. +When enabled this counter will count Time Stamp clock ticks from the pre-scaler. +When written this counter and the pre-scaler will reset to 0 (write data is ignored). + [15:0] + read-write + + + + + ECC_CTL + ECC control + 0x1080 + 32 + read-write + 0x0 + 0x10000 + + + ECC_EN + Enable ECC for CANFD SRAM +When disabled also all error injection functionality is disabled. + [16:16] + read-write + + + + + ECC_ERR_INJ + ECC error injection + 0x1084 + 32 + read-write + 0xFFFC + 0x7F10FFFC + + + ERR_ADDR + Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. +When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. +When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. +Note that error reporting to the fault structure cannot be suppressed. + [15:2] + read-write + + + ERR_EN + Enable error injection (ECC_EN must be 1). +When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. +When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). +When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. + [20:20] + read-write + + + ERR_PAR + ECC Parity bits to use for ECC error injection at address ERR_ADDR. + [30:24] + read-write + + + + + + + SCB0 + Serial Communications Block (SPI/UART/I2C) + SCB + 0x40600000 + + 0 + 65536 + registers + + + + CTRL + Generic control + 0x0 + 32 + read-write + 0x300000F + 0x83031F0F + + + OVS + N/A + [3:0] + read-write + + + EC_AM_MODE + Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field should be '0'. + [8:8] + read-write + + + EC_OP_MODE + Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). + +In UART mode this field should be '0'. + [9:9] + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field should be '0'. + [10:10] + read-write + + + BYTE_MODE + Determines the number of bits per FIFO data element: +'0': 16-bit FIFO data elements. +'1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. + [11:11] + read-write + + + CMD_RESP_MODE + Determines CMD_RESP mode of operation: +'0': CMD_RESP mode disabled. +'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). + [12:12] + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). + +In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. + +In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. + [16:16] + read-write + + + BLOCK + Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. + [17:17] + read-write + + + MODE + N/A + [25:24] + read-write + + + I2C + Inter-Integrated Circuits (I2C) mode. + 0 + + + SPI + Serial Peripheral Interface (SPI) mode. + 1 + + + UART + Universal Asynchronous Receiver/Transmitter (UART) mode. + 2 + + + + + ENABLED + IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: +- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL to enable IP, select the specific operation mode and oversampling factor. +When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + [31:31] + read-write + + + + + STATUS + Generic status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. + [0:0] + read-only + + + + + CMD_RESP_CTRL + Command/response control + 0x8 + 32 + read-write + 0x0 + 0x1FF01FF + + + BASE_RD_ADDR + I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. + [8:0] + read-write + + + BASE_WR_ADDR + I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. + [24:16] + read-write + + + + + CMD_RESP_STATUS + Command/response status + 0xC + 32 + read-only + 0x0 + 0x0 + + + CURR_RD_ADDR + I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [8:0] + read-only + + + CURR_WR_ADDR + I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). + +This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. + [24:16] + read-only + + + CMD_RESP_EC_BUS_BUSY + Indicates whether there is an ongoing bus transfer to the IP. +'0': no ongoing bus transfer. +'1': ongoing bus transfer. + +For SPI, the field is '1' when the slave is selected. + +For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. + [30:30] + read-only + + + CMD_RESP_EC_BUSY + Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: +- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. +- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. + Note that this update lasts one I2C clock cycle, or two SPI clock cycles. + [31:31] + read-only + + + + + SPI_CTRL + SPI control + 0x20 + 32 + read-write + 0x3000000 + 0x8F010F3F + + + SSEL_CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. + +When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. + +When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames. + [0:0] + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. + +When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. + +When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. + [1:1] + read-write + + + CPHA + Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: +- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. +- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. +- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. + +In SPI Motorola submode, all four CPOL/CPHA modes are valid. +in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. +in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. + [2:2] + read-write + + + CPOL + Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: +- CPOL is '0': SCLK is '0' when not transmitting data. +- CPOL is '1': SCLK is '1' when not transmitting data. + [3:3] + read-write + + + LATE_MISO_SAMPLE + Changes the SCLK edge on which MISO is captured. Only used in master mode. + +When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). + +When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. + [4:4] + read-write + + + SCLK_CONTINUOUS + Only applicable in master mode. +'0': SCLK is generated, when the SPI master is enabled and data is transmitted. +'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. + [5:5] + read-write + + + SSEL_POLARITY0 + Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: +'0': slave select is low/'0' active. +'1': slave select is high/'1' active. +For Texas Instruments submode: +'0': high/'1' active precede/coincide pulse. +'1': low/'0' active precede/coincide pulse. + [8:8] + read-write + + + SSEL_POLARITY1 + Slave select polarity. + [9:9] + read-write + + + SSEL_POLARITY2 + Slave select polarity. + [10:10] + read-write + + + SSEL_POLARITY3 + Slave select polarity. + [11:11] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. +'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. +'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + SPI_MOTOROLA + SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 0 + + + SPI_TI + SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. + 1 + + + SPI_NS + SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 2 + + + + + SSEL + Selects one of the four incoming/outgoing SPI slave select signals: +- 0: Slave 0, SSEL[0]. +- 1: Slave 1, SSEL[1]. +- 2: Slave 2, SSEL[2]. +- 3: Slave 3, SSEL[3]. +The IP should be disabled when changes are made to this field. + [27:26] + read-write + + + MASTER_MODE + Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. + [31:31] + read-write + + + + + SPI_STATUS + SPI status + 0x24 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. + [0:0] + read-only + + + SPI_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. + [1:1] + read-only + + + CURR_EZ_ADDR + SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + UART_CTRL + UART control + 0x40 + 32 + read-write + 0x3000000 + 0x3010000 + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. + +This allows a SCB UART transmitter to communicate with its receiver counterpart. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + UART_STD + Standard UART submode. + 0 + + + UART_SMARTCARD + SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. + 1 + + + UART_IRDA + Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. + 2 + + + + + + + UART_TX_CTRL + UART transmitter control + 0x44 + 32 + read-write + 0x2 + 0x137 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware + [5:5] + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + [8:8] + read-write + + + + + UART_RX_CTRL + UART receiver control + 0x48 + 32 + read-write + 0xA0002 + 0xF3777 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + +Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. + [5:5] + read-write + + + POLARITY + Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + [6:6] + read-write + + + DROP_ON_PARITY_ERROR + Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). + [8:8] + read-write + + + DROP_ON_FRAME_ERROR + Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + [9:9] + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. + [10:10] + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [12:12] + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. + [13:13] + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. + [19:16] + read-write + + + + + UART_RX_STATUS + UART receiver status + 0x4C + 32 + read-only + 0x0 + 0x0 + + + BR_COUNTER + Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. + [11:0] + read-only + + + + + UART_FLOW_CTRL + UART flow control + 0x50 + 32 + read-write + 0x0 + 0x30100FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). + [7:0] + read-write + + + RTS_POLARITY + Polarity of the RTS output signal 'uart_rts_out': +'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. +'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. + +During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. + [16:16] + read-write + + + CTS_POLARITY + Polarity of the CTS input signal 'uart_cts_in': +'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. +'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. + [24:24] + read-write + + + CTS_ENABLED + Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: +'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. +'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. + +If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). + [25:25] + read-write + + + + + I2C_CTRL + I2C control + 0x60 + 32 + read-write + 0xFB88 + 0xC001FBFF + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. + [3:0] + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. + [7:4] + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. + [8:8] + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). + [9:9] + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. + [11:11] + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [12:12] + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. + [13:13] + read-write + + + S_NOT_READY_ADDR_NACK + For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: +- EC_AM is '0', EC_OP is '0' and non EZ mode. +Functionality is as follows: +- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + +For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): +- EC_AM is '1' and EC_OP is '0'. +- EC_AM is '1' and general call address match. +- EC_AM is '1' and non EZ mode. +Functionality is as follows: +- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). +- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. + [14:14] + read-write + + + S_NOT_READY_DATA_NACK + For internally clocked logic only. Only used when: +- non EZ mode. +Functionality is as follows: +- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + [15:15] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. + [16:16] + read-write + + + SLAVE_MODE + Slave mode enabled ('1') or not ('0'). + [30:30] + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. + [31:31] + read-write + + + + + I2C_STATUS + I2C status + 0x64 + 32 + read-only + 0x0 + 0x31 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). + +For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). + +For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). + [0:0] + read-only + + + I2C_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. + [1:1] + read-only + + + S_READ + I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. + [4:4] + read-only + + + M_READ + I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. + [5:5] + read-only + + + CURR_EZ_ADDR + I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + I2C_M_CMD + I2C master command + 0x68 + 32 + read-write + 0x0 + 0x1F + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. + [0:0] + read-write + + + M_START_ON_IDLE + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. + [1:1] + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + [2:2] + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + [3:3] + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. + I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. + [4:4] + read-write + + + + + I2C_S_CMD + I2C slave command + 0x6C + 32 + read-write + 0x0 + 0x3 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). + [0:0] + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. + [1:1] + read-write + + + + + I2C_CFG + I2C configuration + 0x70 + 32 + read-write + 0x2A1013 + 0x303F1313 + + + SDA_IN_FILT_TRIM + Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + +SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. +1: enable clock_scb_en, has no effect on ec_busy_pp +0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) + [1:0] + read-write + + + SDA_IN_FILT_SEL + Selection of 'i2c_sda_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [4:4] + read-write + + + SCL_IN_FILT_TRIM + Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [9:8] + read-write + + + SCL_IN_FILT_SEL + Selection of 'i2c_scl_in' filter delay: +'0': 0 ns. +'1: 50 ns (filter enabled). + [12:12] + read-write + + + SDA_OUT_FILT0_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [17:16] + read-write + + + SDA_OUT_FILT1_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [19:18] + read-write + + + SDA_OUT_FILT2_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values. + [21:20] + read-write + + + SDA_OUT_FILT_SEL + Selection of cumulative 'i2c_sda_out' filter delay: +'0': 0 ns. +'1': 50 ns (filter 0 enabled). +'2': 100 ns (filters 0 and 1 enabled). +'3': 150 ns (filters 0, 1 and 2 enabled). + [29:28] + read-write + + + + + TX_CTRL + Transmitter control + 0x200 + 32 + read-write + 0x107 + 0x1010F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + OPEN_DRAIN + Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. +'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. +'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). + +The open drain mode is supported for: +- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. +- UART mode, 'uart_tx' IO cell (SPI slave). +- SPI mode, 'spi_miso' IO cell. + [16:16] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control + 0x204 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + [17:17] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status + 0x208 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + [31:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write + 0x240 + 32 + write-only + 0x0 + 0xFFFF + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. + [15:0] + write-only + + + + + RX_CTRL + Receiver control + 0x300 + 32 + read-write + 0x107 + 0x30F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. + [9:9] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control + 0x304 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + [17:17] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status + 0x308 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + [31:24] + read-only + + + + + RX_MATCH + Slave address and mask + 0x310 + 32 + read-write + 0x0 + 0xFF00FF + + + ADDR + Slave device address. + +In UART multi-processor mode, all 8 bits are used. + +In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). + [7:0] + read-write + + + MASK + Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). + [23:16] + read-write + + + + + RX_FIFO_RD + Receiver FIFO read + 0x340 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read silent + 0x344 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + INTR_CAUSE + Active clocked interrupt signal + 0xE00 + 32 + read-only + 0x0 + 0x3F + + + M + Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. + [0:0] + read-only + + + S + Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. + [1:1] + read-only + + + TX + Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. + [2:2] + read-only + + + RX + Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. + [3:3] + read-only + + + I2C_EC + Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. + [4:4] + read-only + + + SPI_EC + Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. + [5:5] + read-only + + + + + INTR_I2C_EC + Externally clocked I2C interrupt request + 0xE80 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (I2C STOP). + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask + 0xE88 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_I2C_EC_MASKED + Externally clocked I2C interrupt masked + 0xE8C + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_SPI_EC + Externally clocked SPI interrupt request + 0xEC0 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + +Only used when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (SPI deselection). + +Only available in EZ and CMD_RESP mode and when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. + +Only used in EZ and CMD_RESP modes and when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask + 0xEC8 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked + 0xECC + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_M + Master interrupt request + 0xF00 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + [0:0] + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + [1:1] + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + [2:2] + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + [4:4] + read-write + + + I2C_BUS_ERROR + I2C master bus error (unexpected detection of START or STOP condition). + [8:8] + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. + [9:9] + read-write + + + + + INTR_M_SET + Master interrupt set request + 0xF04 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASK + Master interrupt mask + 0xF08 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASKED + Master interrupt masked request + 0xF0C + 32 + read-only + 0x0 + 0x317 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + + + INTR_S + Slave interrupt request + 0xF40 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [0:0] + read-write + + + I2C_NACK + I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). + [1:1] + read-write + + + I2C_ACK + I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). + [2:2] + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. + +In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). + [3:3] + read-write + + + I2C_STOP + I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. + [4:4] + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. + [5:5] + read-write + + + I2C_ADDR_MATCH + I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [6:6] + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [7:7] + read-write + + + I2C_BUS_ERROR + I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + SPI slave deselected after a write EZ SPI transfer occurred. + [9:9] + read-write + + + SPI_EZ_STOP + SPI slave deselected after any EZ SPI transfer occurred. + [10:10] + read-write + + + SPI_BUS_ERROR + SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [11:11] + read-write + + + + + INTR_S_SET + Slave interrupt set request + 0xF44 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASK + Slave interrupt mask + 0xF48 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASKED + Slave interrupt masked request + 0xF4C + 32 + read-only + 0x0 + 0xFFF + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_START + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + SPI_EZ_STOP + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + SPI_BUS_ERROR + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + INTR_TX + Transmitter interrupt request + 0xF80 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_FULL + TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries != FF_DATA_NR/2. +BYTE_MODE is '1': # entries != FF_DATA_NR. + +Only used in FIFO mode. + [1:1] + read-write + + + EMPTY + TX FIFO is empty; i.e. it has 0 entries. + +Only used in FIFO mode. + [4:4] + read-write + + + OVERFLOW + Attempt to write to a full TX FIFO. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + UART_NACK + UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. + [8:8] + read-write + + + UART_DONE + UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. + [9:9] + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + + + INTR_TX_SET + Transmitter interrupt set request + 0xF84 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASK + Transmitter interrupt mask + 0xF88 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASKED + Transmitter interrupt masked request + 0xF8C + 32 + read-only + 0x0 + 0x7F3 + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + UART_NACK + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + UART_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + INTR_RX + Receiver interrupt request + 0xFC0 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. + +Only used in FIFO mode. + [0:0] + read-write + + + NOT_EMPTY + RX FIFO is not empty. + +Only used in FIFO mode. + [2:2] + read-write + + + FULL + RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) +BYTE_MODE is '0': # entries == FF_DATA_NR/2. +BYTE_MODE is '1': # entries == FF_DATA_NR. + +Only used in FIFO mode. + [3:3] + read-write + + + OVERFLOW + Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. + +Only used in FIFO mode. + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty RX FIFO. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + FRAME_ERROR + Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: +Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. +Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. + +A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. + [8:8] + read-write + + + PARITY_ERROR + Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. + [9:9] + read-write + + + BAUD_DETECT + LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. + [10:10] + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. + [11:11] + read-write + + + + + INTR_RX_SET + Receiver interrupt set request + 0xFC4 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt status register. + [2:2] + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt status register. + [3:3] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt status register. + [7:7] + read-write + + + FRAME_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [8:8] + read-write + + + PARITY_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [9:9] + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [10:10] + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [11:11] + read-write + + + + + INTR_RX_MASK + Receiver interrupt mask + 0xFC8 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + FRAME_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + PARITY_ERROR + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_RX_MASKED + Receiver interrupt masked request + 0xFCC + 32 + read-only + 0x0 + 0xFED + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + FULL + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + FRAME_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + PARITY_ERROR + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + BAUD_DETECT + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + BREAK_DETECT + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + + + SCB1 + 0x40610000 + + + SCB2 + 0x40620000 + + + SCB4 + 0x40640000 + + + SCB5 + 0x40650000 + + + SCB6 + 0x40660000 + + + CTBM0 + Continuous Time Block Mini + CTBM + 0x40900000 + + 0 + 65536 + registers + + + + CTB_CTRL + global CTB and power control + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + DEEPSLEEP_ON + - 0: CTB IP disabled off during DeepSleep power mode +- 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + - 0: CTB IP disabled (put analog in power down, open all switches) +- 1: CTB IP enabled + [31:31] + read-write + + + + + OA_RES0_CTRL + Opamp0 and resistor0 control + 0x4 + 32 + read-write + 0x0 + 0x1BFF + + + OA0_PWR_MODE + Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver + [2:0] + read-write + + + OFF + Off + 0 + + + LOW + Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x) + 1 + + + MEDIUM + Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x) + 2 + + + HIGH + High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x) + 3 + + + RSVD + N/A + 4 + + + PS_LOW + Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is disabled) + 5 + + + PS_MEDIUM + Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled) + 6 + + + PS_HIGH + Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled) + 7 + + + + + OA0_DRIVE_STR_SEL + Opamp0 output strength select 0=1x, 1=10x +This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM + [3:3] + read-write + + + OA0_COMP_EN + Opamp0 comparator enable + [4:4] + read-write + + + OA0_HYST_EN + Opamp0 hysteresis enable (10mV) + [5:5] + read-write + + + OA0_BYPASS_DSI_SYNC + Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async) + [6:6] + read-write + + + OA0_DSI_LEVEL + Opamp0 comparator DSI (trigger) out level : +0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI +1=level, DSI output is a synchronized version of the comparator output + [7:7] + read-write + + + OA0_COMPINT + Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger) + [9:8] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + OA0_PUMP_EN + Opamp0 pump enable + [11:11] + read-write + + + OA0_BOOST_EN + Opamp0 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 + [12:12] + read-write + + + + + OA_RES1_CTRL + Opamp1 and resistor1 control + 0x8 + 32 + read-write + 0x0 + 0x1BFF + + + OA1_PWR_MODE + Opamp1 power level: see description of OA0_PWR_MODE + [2:0] + read-write + + + OA1_DRIVE_STR_SEL + Opamp1 output strength select 0=1x, 1=10x +This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM + [3:3] + read-write + + + OA1_COMP_EN + Opamp1 comparator enable + [4:4] + read-write + + + OA1_HYST_EN + Opamp1 hysteresis enable (10mV) + [5:5] + read-write + + + OA1_BYPASS_DSI_SYNC + Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass + [6:6] + read-write + + + OA1_DSI_LEVEL + Opamp1 comparator DSI (trigger) out level : +0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI +1=level, DSI output is a synchronized version of the comparator output + [7:7] + read-write + + + OA1_COMPINT + Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger) + [9:8] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + OA1_PUMP_EN + Opamp1 pump enable + [11:11] + read-write + + + OA1_BOOST_EN + Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 + [12:12] + read-write + + + + + COMP_STAT + Comparator status + 0xC + 32 + read-only + 0x0 + 0x10001 + + + OA0_COMP + Opamp0 current comparator status + [0:0] + read-only + + + OA1_COMP + Opamp1 current comparator status + [16:16] + read-only + + + + + INTR + Interrupt request register + 0x20 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + Interrupt request set register + 0x24 + 32 + read-write + 0x0 + 0x3 + + + COMP0_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + Interrupt request mask + 0x28 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + Interrupt request masked + 0x2C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + OA0_SW + Opamp0 switch control + 0x80 + 32 + read-write + 0x0 + 0x24410D + + + OA0P_A00 + Opamp0 positive terminal amuxbusa + [0:0] + read-write + + + OA0P_A20 + Opamp0 positive terminal P0 + [2:2] + read-write + + + OA0P_A30 + Opamp0 positive terminal ctbbus0 + [3:3] + read-write + + + OA0M_A11 + Opamp0 negative terminal P1 + [8:8] + read-write + + + OA0M_A81 + Opamp0 negative terminal Opamp0 output + [14:14] + read-write + + + OA0O_D51 + Opamp0 output sarbus0 (ctbbus2 in CTB) + [18:18] + read-write + + + OA0O_D81 + Opamp0 output switch to short 1x with 10x drive + [21:21] + read-write + + + + + OA0_SW_CLEAR + Opamp0 switch control clear + 0x84 + 32 + read-write + 0x0 + 0x24410D + + + OA0P_A00 + see corresponding bit in OA0_SW + [0:0] + read-write + + + OA0P_A20 + see corresponding bit in OA0_SW + [2:2] + read-write + + + OA0P_A30 + see corresponding bit in OA0_SW + [3:3] + read-write + + + OA0M_A11 + see corresponding bit in OA0_SW + [8:8] + read-write + + + OA0M_A81 + see corresponding bit in OA0_SW + [14:14] + read-write + + + OA0O_D51 + see corresponding bit in OA0_SW + [18:18] + read-write + + + OA0O_D81 + see corresponding bit in OA0_SW + [21:21] + read-write + + + + + OA1_SW + Opamp1 switch control + 0x88 + 32 + read-write + 0x0 + 0x2C4193 + + + OA1P_A03 + Opamp1 positive terminal amuxbusb + [0:0] + read-write + + + OA1P_A13 + Opamp1 positive terminal P5 + [1:1] + read-write + + + OA1P_A43 + Opamp1 positive terminal ctbbus1 + [4:4] + read-write + + + OA1P_A73 + Opamp1 positive terminal to vref1 + [7:7] + read-write + + + OA1M_A22 + Opamp1 negative terminal P4 + [8:8] + read-write + + + OA1M_A82 + Opamp1 negative terminal Opamp1 output + [14:14] + read-write + + + OA1O_D52 + Opamp1 output sarbus0 (ctbbus2 in CTB) + [18:18] + read-write + + + OA1O_D62 + Opamp1 output sarbus1 (ctbbus3 in CTB) + [19:19] + read-write + + + OA1O_D82 + Opamp1 output switch to short 1x with 10x drive + [21:21] + read-write + + + + + OA1_SW_CLEAR + Opamp1 switch control clear + 0x8C + 32 + read-write + 0x0 + 0x2C4193 + + + OA1P_A03 + see corresponding bit in OA1_SW + [0:0] + read-write + + + OA1P_A13 + see corresponding bit in OA1_SW + [1:1] + read-write + + + OA1P_A43 + see corresponding bit in OA1_SW + [4:4] + read-write + + + OA1P_A73 + see corresponding bit in OA1_SW + [7:7] + read-write + + + OA1M_A22 + see corresponding bit in OA1_SW + [8:8] + read-write + + + OA1M_A82 + see corresponding bit in OA1_SW + [14:14] + read-write + + + OA1O_D52 + see corresponding bit in OA1_SW + [18:18] + read-write + + + OA1O_D62 + see corresponding bit in OA1_SW + [19:19] + read-write + + + OA1O_D82 + see corresponding bit in OA1_SW + [21:21] + read-write + + + + + CTD_SW + CTDAC connection switch control + 0xA0 + 32 + read-write + 0x0 + 0xF732 + + + CTDD_CRD + CTDAC Reference opamp output to ctdrefdrive + [1:1] + read-write + + + CTDS_CRS + ctdrefsense to opamp input + [4:4] + read-write + + + CTDS_COR + ctdvout to opamp input + [5:5] + read-write + + + CTDO_C6H + P6 pin to Hold capacitor + [8:8] + read-write + + + CTDO_COS + ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set + [9:9] + read-write + + + CTDH_COB + Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation + [10:10] + read-write + + + CTDH_CHD + Hold capacitor connect + [12:12] + read-write + + + CTDH_CA0 + Hold capacitor to opamp input + [13:13] + read-write + + + CTDH_CIS + Hold capacitor isolation (from all the other switches) + [14:14] + read-write + + + CTDH_ILR + Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage) + [15:15] + read-write + + + + + CTD_SW_CLEAR + CTDAC connection switch control clear + 0xA4 + 32 + read-write + 0x0 + 0xF732 + + + CTDD_CRD + see corresponding bit in CTD_SW + [1:1] + read-write + + + CTDS_CRS + see corresponding bit in CTD_SW + [4:4] + read-write + + + CTDS_COR + see corresponding bit in CTD_SW + [5:5] + read-write + + + CTDO_C6H + see corresponding bit in CTD_SW + [8:8] + read-write + + + CTDO_COS + see corresponding bit in CTD_SW + [9:9] + read-write + + + CTDH_COB + see corresponding bit in CTD_SW + [10:10] + read-write + + + CTDH_CHD + see corresponding bit in CTD_SW + [12:12] + read-write + + + CTDH_CA0 + see corresponding bit in CTD_SW + [13:13] + read-write + + + CTDH_CIS + see corresponding bit in CTD_SW + [14:14] + read-write + + + CTDH_ILR + see corresponding bit in CTD_SW + [15:15] + read-write + + + + + CTB_SW_DS_CTRL + CTB bus switch control + 0xC0 + 32 + read-write + 0x0 + 0x80000C00 + + + P2_DS_CTRL23 + for P22, D51 (dsi_out[2]) + [10:10] + read-write + + + P3_DS_CTRL23 + for P33, D52, D62 (dsi_out[3]) + [11:11] + read-write + + + CTD_COS_DS_CTRL + Hold capacitor Sample switch (COS) + [31:31] + read-write + + + + + CTB_SW_SQ_CTRL + CTB bus switch Sar Sequencer control + 0xC4 + 32 + read-write + 0x0 + 0xC00 + + + P2_SQ_CTRL23 + for D51 + [10:10] + read-write + + + P3_SQ_CTRL23 + for D52, D62 + [11:11] + read-write + + + + + CTB_SW_STATUS + CTB bus switch control status + 0xC8 + 32 + read-only + 0x0 + 0xF0000000 + + + OA0O_D51_STAT + see OA0O_D51 bit in OA0_SW + [28:28] + read-only + + + OA1O_D52_STAT + see OA1O_D52 bit in OA1_SW + [29:29] + read-only + + + OA1O_D62_STAT + see OA1O_D62 bit in OA1_SW + [30:30] + read-only + + + CTD_COS_STAT + see COS bit in CTD_SW + [31:31] + read-only + + + + + OA0_OFFSET_TRIM + Opamp0 trim control + 0xF00 + 32 + read-write + 0x0 + 0x3F + + + OA0_OFFSET_TRIM + Opamp0 offset trim + [5:0] + read-write + + + + + OA0_SLOPE_OFFSET_TRIM + Opamp0 trim control + 0xF04 + 32 + read-write + 0x0 + 0x3F + + + OA0_SLOPE_OFFSET_TRIM + Opamp0 slope offset drift trim + [5:0] + read-write + + + + + OA0_COMP_TRIM + Opamp0 trim control + 0xF08 + 32 + read-write + 0x0 + 0x3 + + + OA0_COMP_TRIM + Opamp0 Compensation Capacitor Trim. +Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 + [1:0] + read-write + + + + + OA1_OFFSET_TRIM + Opamp1 trim control + 0xF0C + 32 + read-write + 0x0 + 0x3F + + + OA1_OFFSET_TRIM + Opamp1 offset trim + [5:0] + read-write + + + + + OA1_SLOPE_OFFSET_TRIM + Opamp1 trim control + 0xF10 + 32 + read-write + 0x0 + 0x3F + + + OA1_SLOPE_OFFSET_TRIM + Opamp1 slope offset drift trim + [5:0] + read-write + + + + + OA1_COMP_TRIM + Opamp1 trim control + 0xF14 + 32 + read-write + 0x0 + 0x3 + + + OA1_COMP_TRIM + Opamp1 Compensation Capacitor Trim. +Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 + [1:0] + read-write + + + + + + + CTDAC0 + Continuous Time DAC + CTDAC + 0x40940000 + + 0 + 65536 + registers + + + + CTDAC_CTRL + Global CTDAC control + 0x0 + 32 + read-write + 0x0 + 0xFBC0033F + + + DEGLITCH_CNT + To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles. + [5:0] + read-write + + + DEGLITCH_CO6 + Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles. + [8:8] + read-write + + + DEGLITCH_COS + Force CTB.COS switch open after each VALUE change for the set number of clock cycles. + [9:9] + read-write + + + OUT_EN + Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : +0: output disabled, the output is either: + - Tri-state (DISABLED_MODE=0) + - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) + - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) +1: output enabled, CTDAC output drives the programmed VALUE + [22:22] + read-write + + + CTDAC_RANGE + By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 +0: Range is [0, 4095] * Vref / 4096 +1: Range is [1, 4096] * Vref / 4096 + [23:23] + read-write + + + CTDAC_MODE + DAC mode, this determines the Value decoding + [25:24] + read-write + + + UNSIGNED12 + Unsigned 12-bit VDAC, i.e. no value decoding. + 0 + + + VIRT_SIGNED12 + Virtual signed 12-bits' VDAC. Value decoding: +add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers. + 1 + + + RSVD2 + N/A + 2 + + + RSVD3 + N/A + 3 + + + + + DISABLED_MODE + Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) +0: Tri-state CTDAC output when disabled +1: output Vssa or Vref when disabled (see OUT_EN description) + [27:27] + read-write + + + DSI_STROBE_EN + DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. +0: Ignore DSI strobe input +1: Only do a CTDAC update if allowed by the DSI strobe (throttle), see below for level or edge + [28:28] + read-write + + + DSI_STROBE_LEVEL + Select level or edge detect for DSI strobe +- 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock +- 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock. + [29:29] + read-write + + + DEEPSLEEP_ON + - 0: CTDAC IP disabled off during DeepSleep power mode +- 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + 0: CTDAC IP disabled (put analog in power down, open all switches) +1: CTDAC IP enabled + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x20 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY + VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt request set register + 0x24 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt request mask + 0x28 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt request masked + 0x2C + 32 + read-only + 0x0 + 0x1 + + + VDAC_EMPTY_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + + + CTDAC_SW + CTDAC switch control + 0xB0 + 32 + read-write + 0x0 + 0x101 + + + CTDD_CVD + VDDA supply to ctdrefdrive + [0:0] + read-write + + + CTDO_CO6 + ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set + [8:8] + read-write + + + + + CTDAC_SW_CLEAR + CTDAC switch control clear + 0xB4 + 32 + read-write + 0x0 + 0x101 + + + CTDD_CVD + see corresponding bit in CTD_SW + [0:0] + read-write + + + CTDO_CO6 + see corresponding bit in CTD_SW + [8:8] + read-write + + + + + CTDAC_VAL + DAC Value + 0x100 + 32 + read-write + 0x0 + 0xFFF + + + VALUE + Value, in CTDAC_MODE 1 this value is decoded + [11:0] + read-write + + + + + CTDAC_VAL_NXT + Next DAC value (double buffering) + 0x104 + 32 + read-write + 0x0 + 0xFFF + + + VALUE + Next value for CTDAC_VAL.VALUE + [11:0] + read-write + + + + + + + SAR0 + SAR ADC with Sequencer + SAR + 0x409B0000 + + 0 + 65536 + registers + + + + CTRL + Analog control register. + 0x0 + 32 + read-write + 0x10000000 + 0xFF3FEEF7 + + + PWR_CTRL_VREF + VREF buffer low power mode. + [2:0] + read-write + + + PWR_100 + full power (100 percent) (default), bypass cap, max clk_sar is 18MHz. + 0 + + + PWR_80 + 80 percent power + 1 + + + PWR_60 + 60 percent power + 2 + + + PWR_50 + 50 percent power + 3 + + + PWR_40 + 40 percent power + 4 + + + PWR_30 + 30 percent power + 5 + + + PWR_20 + 20 percent power + 6 + + + PWR_10 + 10 percent power + 7 + + + + + VREF_SEL + SARADC internal VREF selection. + [6:4] + read-write + + + VREF0 + VREF0 from PRB (VREF buffer on) + 0 + + + VREF1 + VREF1 from PRB (VREF buffer on) + 1 + + + VREF2 + VREF2 from PRB (VREF buffer on) + 2 + + + VREF_AROUTE + VREF from AROUTE (VREF buffer on) + 3 + + + VBGR + 1.024V from BandGap (VREF buffer on) + 4 + + + VREF_EXT + External precision Vref direct from a pin (low impedance path). + 5 + + + VDDA_DIV_2 + Vdda/2 (VREF buffer on) + 6 + + + VDDA + Vdda. + 7 + + + + + VREF_BYP_CAP_EN + VREF bypass cap enable for when VREF buffer is on + [7:7] + read-write + + + NEG_SEL + SARADC internal NEG selection for Single ended conversion + [11:9] + read-write + + + VSSA_KELVIN + NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high. + 0 + + + ART_VSSA + NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC + 1 + + + P1 + NEG input of SARADC is connected to P1 pin of SARMUX + 2 + + + P3 + NEG input of SARADC is connected to P3 pin of SARMUX + 3 + + + P5 + NEG input of SARADC is connected to P5 pin of SARMUX + 4 + + + P7 + NEG input of SARADC is connected to P7 pin of SARMUX + 5 + + + ACORE + NEG input of SARADC is connected to an ACORE in AROUTE + 6 + + + VREF + NEG input of SARADC is shorted with VREF input of SARADC. + 7 + + + + + SAR_HW_CTRL_NEGVREF + Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. + [13:13] + read-write + + + COMP_DLY + Set the comparator latch delay in accordance with SAR conversion rate + [15:14] + read-write + + + D2P5 + 2.5ns delay, use this for 2.5Msps + 0 + + + D4 + 4.0ns delay, use this for 2.0Msps + 1 + + + D10 + 10ns delay, use this for 1.5Msps + 2 + + + D12 + 12ns delay, use this for 1.0Msps or less + 3 + + + + + SPARE + Spare controls, not yet designated, for late changes done with an ECO + [19:16] + read-write + + + BOOSTPUMP_EN + deprecated + [20:20] + read-write + + + REFBUF_EN + For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. +Setting this bit is critical to proper function of switches inside SARREF block. + [21:21] + read-write + + + COMP_PWR + Comparator power mode. (Sample rate TBD) + [26:24] + read-write + + + P100 + Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz + 0 + + + P80 + N/A + 1 + + + P60 + Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz. + 2 + + + P50 + N/A + 3 + + + P40 + N/A + 4 + + + P30 + N/A + 5 + + + P20 + Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz + 6 + + + P10 + N/A + 7 + + + + + DEEPSLEEP_ON + - 0: SARMUX IP disabled off during DeepSleep power mode +- 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) + [27:27] + read-write + + + DSI_SYNC_CONFIG + - 0: bypass clock domain synchronization of the DSI config signals. +- 1: synchronize the DSI config signals to peripheral clock domain. + [28:28] + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) +- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations +- 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored + [29:29] + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) +- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations +- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX + [30:30] + read-write + + + ENABLED + - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgating) on write. +- 1: SAR IP enabled. + [31:31] + read-write + + + + + SAMPLE_CTRL + Sample control register. + 0x4 + 32 + read-write + 0x80008 + 0xDFCF01FE + + + LEFT_ALIGN + Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. + [1:1] + read-write + + + SINGLE_ENDED_SIGNED + Output data from a single ended conversion as a signed value + +If AVG_MODE = 1 (Interleaved averaging), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED. + [2:2] + read-write + + + UNSIGNED + Default: result data is unsigned (zero extended if needed) + 0 + + + SIGNED + result data is signed (sign extended if needed) + 1 + + + + + DIFFERENTIAL_SIGNED + Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 + +If AVG_MODE = 1 (Interleaved averaging), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED. + [3:3] + read-write + + + UNSIGNED + result data is unsigned (zero extended if needed) + 0 + + + SIGNED + Default: result data is signed (sign extended if needed) + 1 + + + + + AVG_CNT + Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. +- In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). +- In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). + [6:4] + read-write + + + AVG_SHIFT + Averaging shifting: after averaging the result is shifted right to fit in 12 bits. + [7:7] + read-write + + + AVG_MODE + Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. + [8:8] + read-write + + + ACCUNDUMP + Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged + 0 + + + INTERLEAVED + Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans. Interleaved averaging cannot be set by SAR_CLOCK_SEL.CLOCK_SEL =1. + 1 + + + + + CONTINUOUS + - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. +- 1: Continuously scan enabled channels, ignore triggers. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [16:16] + read-write + + + DSI_TRIGGER_EN + - 0: firmware trigger only: disable hardware trigger tr_sar_in. +- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). + [17:17] + read-write + + + DSI_TRIGGER_LEVEL + - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. +- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [18:18] + read-write + + + DSI_SYNC_TRIGGER + - 0: bypass clock domain synchronization of the trigger signal. +- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. + [19:19] + read-write + + + UAB_SCAN_MODE + Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored. + [22:22] + read-write + + + UNSCHEDULED + Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable. + 0 + + + SCHEDULED + Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. +This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator. + 1 + + + + + REPEAT_INVALID + For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: +- 0: use the last known valid sample for that channel and clear the NEWVALUE flag +- 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling) + [23:23] + read-write + + + VALID_SEL + Static UAB Valid select +0=UAB0 half 0 Valid output +1=UAB0 half 1 Valid output +2=UAB1 half 0 Valid output +3=UAB1 half 1 Valid output +4=UAB2 half 0 Valid output +5=UAB2 half 1 Valid output +6=UAB3 half 0 Valid output +7=UAB3 half 1 Valid output + [26:24] + read-write + + + VALID_SEL_EN + Enable static UAB Valid selection (override Hardware) + [27:27] + read-write + + + VALID_IGNORE + Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above + [28:28] + read-write + + + TRIGGER_OUT_EN + SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1). + [30:30] + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. + [31:31] + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x10 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. + [9:0] + read-write + + + SAMPLE_TIME1 + Sample time1 + [25:16] + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x14 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME2 + Sample time2 + [9:0] + read-write + + + SAMPLE_TIME3 + Sample time3 + [25:16] + read-write + + + + + RANGE_THRES + Global range detect threshold register. + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RANGE_LOW + Low threshold for range detect. + [15:0] + read-write + + + RANGE_HIGH + High threshold for range detect. + [31:16] + read-write + + + + + RANGE_COND + Global range detect mode register. + 0x1C + 32 + read-write + 0x0 + 0xC0000000 + + + RANGE_COND + Range condition select. + [31:30] + read-write + + + BELOW + result < RANGE_LOW + 0 + + + INSIDE + RANGE_LOW <= result < RANGE_HIGH + 1 + + + ABOVE + RANGE_HIGH <= result + 2 + + + OUTSIDE + result < RANGE_LOW || RANGE_HIGH <= result + 3 + + + + + + + CHAN_EN + Enable bits for the channels + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CHAN_EN + Channel enable. +- 0: the corresponding channel is disabled. +- 1: the corresponding channel is enabled, it will be included in the next scan. + [15:0] + read-write + + + + + START_CTRL + Start control register (firmware trigger). + 0x24 + 32 + read-write + 0x0 + 0x1 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. This fiel+G201d cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [0:0] + read-write + + + + + 16 + 4 + CHAN_CONFIG[%s] + Channel configuration register. + 0x80 + 32 + read-write + 0x0 + 0x81773577 + + + POS_PIN_ADDR + Address of the pin to be sampled by this channel (connected to Vplus) + [2:0] + read-write + + + POS_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel (connected to Vplus) + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + DIFFERENTIAL_EN + Differential enable for this channel. +If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + SAMPLE_TIME_SEL + Sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + NEG_PIN_ADDR + Address of the neg pin to be sampled by this channel. + [18:16] + read-write + + + NEG_PORT_ADDR + Address of the neg port that contains the pin to be sampled by this channel. + [22:20] + read-write + + + SARMUX + SARMUX pins. + 0 + + + AROUTE_VIRT2 + AROUTE virtual port2 (VPORT2) + 5 + + + AROUTE_VIRT1 + AROUTE virtual port1 (VPORT1) + 6 + + + SARMUX_VIRT + SARMUX virtual port (VPORT0) + 7 + + + + + NEG_ADDR_EN + 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. + [24:24] + read-write + + + DSI_OUT_EN + DSI data output enable for this channel. +- 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. +- 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. + [31:31] + read-write + + + + + 16 + 4 + CHAN_WORK[%s] + Channel working data register + 0x100 + 32 + read-only + 0x0 + 0x88000000 + + + WORK + SAR conversion working data of the channel. The data is written here right after sampling this channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + CHAN_WORK_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [27:27] + read-only + + + CHAN_WORK_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [31:31] + read-only + + + + + 16 + 4 + CHAN_RESULT[%s] + Channel result data register + 0x180 + 32 + read-only + 0x0 + 0xE8000000 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + CHAN_RESULT_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [27:27] + read-only + + + SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_SATURATE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [29:29] + read-only + + + RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_RANGE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [30:30] + read-only + + + CHAN_RESULT_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [31:31] + read-only + + + + + CHAN_WORK_UPDATED + Channel working data register 'updated' bits + 0x200 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_UPDATED + If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + + + CHAN_RESULT_UPDATED + Channel result data register 'updated' bits + 0x204 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_UPDATED + If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + + + CHAN_WORK_NEWVALUE + Channel working data register 'new value' bits + 0x208 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_NEWVALUE + If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + + + CHAN_RESULT_NEWVALUE + Channel result data register 'new value' bits + 0x20C + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_NEWVALUE + If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + + + INTR + Interrupt request register. + 0x210 + 32 + read-write + 0x0 + 0xFF + + + EOS_INTR + End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. + [0:0] + read-write + + + OVERFLOW_INTR + Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [1:1] + read-write + + + FW_COLLISION_INTR + Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [2:2] + read-write + + + DSI_COLLISION_INTR + DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [3:3] + read-write + + + INJ_EOC_INTR + Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [4:4] + read-write + + + INJ_SATURATE_INTR + Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [5:5] + read-write + + + INJ_RANGE_INTR + Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [6:6] + read-write + + + INJ_COLLISION_INTR + Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. + [7:7] + read-write + + + + + INTR_SET + Interrupt set request register + 0x214 + 32 + read-write + 0x0 + 0xFF + + + EOS_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_SET + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask register. + 0x218 + 32 + read-write + 0x0 + 0xFF + + + EOS_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + OVERFLOW_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + FW_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + DSI_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + INJ_EOC_MASK + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + INJ_SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + INJ_RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + INJ_COLLISION_MASK + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x21C + 32 + read-only + 0x0 + 0xFF + + + EOS_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + OVERFLOW_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + FW_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + DSI_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + INJ_EOC_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + INJ_SATURATE_MASKED + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + INJ_RANGE_MASKED + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + INJ_COLLISION_MASKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + + + SATURATE_INTR + Saturate interrupt request register. + 0x220 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_INTR + Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [15:0] + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x224 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register. + 0x228 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x22C + 32 + read-only + 0x0 + 0xFFFF + + + SATURATE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + RANGE_INTR + Range detect interrupt request register. + 0x230 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_INTR + Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [15:0] + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x234 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register. + 0x238 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x23C + 32 + read-only + 0x0 + 0xFFFF + + + RANGE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + INTR_CAUSE + Interrupt cause register + 0x240 + 32 + read-only + 0x0 + 0xC00000FF + + + EOS_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [0:0] + read-only + + + OVERFLOW_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [1:1] + read-only + + + FW_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [2:2] + read-only + + + DSI_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [3:3] + read-only + + + INJ_EOC_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [4:4] + read-only + + + INJ_SATURATE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [5:5] + read-only + + + INJ_RANGE_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [6:6] + read-only + + + INJ_COLLISION_MASKED_MIR + Mirror copy of corresponding bit in SAR_INTR_MASKED + [7:7] + read-only + + + SATURATE_MASKED_RED + Reduction OR of all SAR_SATURATION_INTR_MASKED bits + [30:30] + read-only + + + RANGE_MASKED_RED + Reduction OR of all SAR_RANGE_INTR_MASKED bits + [31:31] + read-only + + + + + INJ_CHAN_CONFIG + Injection channel configuration register. + 0x280 + 32 + read-write + 0x0 + 0xC0003577 + + + INJ_PIN_ADDR + Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. + [2:0] + read-write + + + INJ_PORT_ADDR + Address of the port that contains the pin to be sampled by this channel. + [6:4] + read-write + + + SARMUX + SARMUX pins. + 0 + + + CTB0 + CTB0 + 1 + + + CTB1 + CTB1 + 2 + + + CTB2 + CTB2 + 3 + + + CTB3 + CTB3 + 4 + + + AROUTE_VIRT + AROUTE virtual port + 6 + + + SARMUX_VIRT + SARMUX virtual port + 7 + + + + + INJ_DIFFERENTIAL_EN + Differential enable for this channel. +- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. +- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored). + [8:8] + read-write + + + INJ_AVG_EN + Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) + [10:10] + read-write + + + INJ_SAMPLE_TIME_SEL + Injection sample time select: select which of the 4 global sample times to use for this channel + [13:12] + read-write + + + INJ_TAILGATING + Injection channel tailgating. +- 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set if the SAR is not busy. If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan. +- 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. + [30:30] + read-write + + + INJ_START_EN + Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [31:31] + read-write + + + + + INJ_RESULT + Injection channel result register + 0x290 + 32 + read-only + 0x0 + 0xF8000000 + + + INJ_RESULT + SAR conversion result of the channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:0] + read-only + + + INJ_NEWVALUE + The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [27:27] + read-only + + + INJ_COLLISION_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [28:28] + read-only + + + INJ_SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [29:29] + read-only + + + INJ_RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [30:30] + read-only + + + INJ_EOC_INTR_MIR + mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [31:31] + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x2A0 + 32 + read-only + 0x0 + 0xC000001F + + + CUR_CHAN + current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [4:0] + read-only + + + SW_VREF_NEG + the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [30:30] + read-only + + + BUSY + If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. + [31:31] + read-only + + + + + AVG_STAT + Current averaging status (for debug) + 0x2A4 + 32 + read-only + 0x0 + 0xFF8FFFFF + + + CUR_AVG_ACCU + the current value of the averaging accumulator. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [19:0] + read-only + + + INTRLV_BUSY + If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. +This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. + [23:23] + read-only + + + CUR_AVG_CNT + the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [31:24] + read-only + + + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x300 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit. + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit. + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit. + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit. + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit. + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit. + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit. + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit. + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit. + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit. + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit. + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit. + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit. + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit. + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit. + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit. + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit. + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, (also powers on the temperature sensor if AREF_CTRL.EN=1 (active mode) and AREF_CTRL.DEEPSLEEP=1 and AREF_CTRL.DEEPSLEEP_MODE=2 or 3 (required for deepsleep mode only). The Write with '1' to set bit. + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit. + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit. + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit. + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit. + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit. + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit. + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit. + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit. + [29:29] + read-write + + + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x304 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [0:0] + read-write + + + MUX_FW_P1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [1:1] + read-write + + + MUX_FW_P2_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [2:2] + read-write + + + MUX_FW_P3_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [3:3] + read-write + + + MUX_FW_P4_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [4:4] + read-write + + + MUX_FW_P5_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [5:5] + read-write + + + MUX_FW_P6_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [6:6] + read-write + + + MUX_FW_P7_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [7:7] + read-write + + + MUX_FW_P0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [8:8] + read-write + + + MUX_FW_P1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [9:9] + read-write + + + MUX_FW_P2_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [10:10] + read-write + + + MUX_FW_P3_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [11:11] + read-write + + + MUX_FW_P4_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [12:12] + read-write + + + MUX_FW_P5_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [13:13] + read-write + + + MUX_FW_P6_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [14:14] + read-write + + + MUX_FW_P7_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + Write '1' to clear corresponding bit in MUX_SWITCH0 + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + Write '1' to clear corresponding bit in MUX_SWITCH0 + [29:29] + read-write + + + + + MUX_SWITCH_SQ_CTRL + SARMUX switch Sar Sequencer control + 0x344 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_SQ_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_SQ_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_SQ_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_SQ_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_SQ_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_SQ_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_SQ_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_SQ_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_SQ_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_SQ_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_SQ_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_SQ_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_SQ_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_SQ_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x348 + 32 + read-only + 0x0 + 0x3FFFFFF + + + MUX_FW_P0_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [0:0] + read-only + + + MUX_FW_P1_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [1:1] + read-only + + + MUX_FW_P2_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [2:2] + read-only + + + MUX_FW_P3_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [3:3] + read-only + + + MUX_FW_P4_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [4:4] + read-only + + + MUX_FW_P5_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [5:5] + read-only + + + MUX_FW_P6_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [6:6] + read-only + + + MUX_FW_P7_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [7:7] + read-only + + + MUX_FW_P0_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [8:8] + read-only + + + MUX_FW_P1_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [9:9] + read-only + + + MUX_FW_P2_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [10:10] + read-only + + + MUX_FW_P3_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [11:11] + read-only + + + MUX_FW_P4_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [12:12] + read-only + + + MUX_FW_P5_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [13:13] + read-only + + + MUX_FW_P6_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [14:14] + read-only + + + MUX_FW_P7_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [15:15] + read-only + + + MUX_FW_VSSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [16:16] + read-only + + + MUX_FW_TEMP_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [17:17] + read-only + + + MUX_FW_AMUXBUSA_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [18:18] + read-only + + + MUX_FW_AMUXBUSB_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [19:19] + read-only + + + MUX_FW_AMUXBUSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [20:20] + read-only + + + MUX_FW_AMUXBUSB_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [21:21] + read-only + + + MUX_FW_SARBUS0_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [22:22] + read-only + + + MUX_FW_SARBUS1_VPLUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [23:23] + read-only + + + MUX_FW_SARBUS0_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [24:24] + read-only + + + MUX_FW_SARBUS1_VMINUS + switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [25:25] + read-only + + + + + + + SAR1 + 0x409C0000 + + + PASS + PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) + 0x409F0000 + + 0 + 65536 + registers + + + + INTR_CAUSE + Interrupt cause register + 0x0 + 32 + read-only + 0x0 + 0xFFFF + + + CTB0_INT + CTB0 interrupt pending + [0:0] + read-only + + + CTB1_INT + CTB1 interrupt pending + [1:1] + read-only + + + CTB2_INT + CTB2 interrupt pending + [2:2] + read-only + + + CTB3_INT + CTB3 interrupt pending + [3:3] + read-only + + + CTDAC0_INT + CTDAC0 interrupt pending + [4:4] + read-only + + + CTDAC1_INT + CTDAC1 interrupt pending + [5:5] + read-only + + + CTDAC2_INT + CTDAC2 interrupt pending + [6:6] + read-only + + + CTDAC3_INT + CTDAC3 interrupt pending + [7:7] + read-only + + + SAR0_INT + SAR0 interrupt pending + [8:8] + read-only + + + SAR1_INT + SAR1 interrupt pending + [9:9] + read-only + + + SAR2_INT + SAR2 interrupt pending + [10:10] + read-only + + + SAR3_INT + SAR3 interrupt pending + [11:11] + read-only + + + FIFO0_INT + FIFO0 interrupt pending + [12:12] + read-only + + + FIFO1_INT + FIFO1 interrupt pending + [13:13] + read-only + + + FIFO2_INT + FIFO2 interrupt pending + [14:14] + read-only + + + FIFO3_INT + FIFO3 interrupt pending + [15:15] + read-only + + + + + DPSLP_CLOCK_SEL + Deepsleep clock select + 0x10 + 32 + read-write + 0x20 + 0x71 + + + DPSLP_CLOCK_SEL + Select source for PASS DPSLP Clock + [0:0] + read-write + + + CLK_LPOSC + CLK_DPSLP is set to CLK_LPOSC + 0 + + + CLK_MF + CLK_DPSLP is set to CLK_MF + 1 + + + + + DPSLP_CLOCK_DIV + CLK_DPSLP divider + [6:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + RSVD_0 + N/A + 5 + + + RSVD_1 + N/A + 6 + + + RSVD_2 + N/A + 7 + + + + + + + ANA_PWR_CFG + Analog power configuration + 0x14 + 32 + read-write + 0x0 + 0xFFF + + + PWR_UP_DELAY + Power up time for analog blocks. Fastest power up time is achieved with a setting of 0. Additional time can be added to allow for analog settling. The power up time is in clk_dpslp cycles. This field is only applicable when SAR_CLOCK_SEL.CLOCK_SEL =1. + [7:0] + read-write + + + DUTY_CYCLE_SAR_ACT_EN + Enable for powering down (duty cycling) a SAR in chip active mode. This is a risk mitigation bit for power reduction in chip active mode. In order for this field affect SAR operation, the SAR must be configured for deepsleep clocking (SAR_CLOCK_SEL.CLOCK_SEL set to 1), and the SAR must be set for Timer-based hardware triggering (either by following the guidlines in SAR_OVR_CTRL.HW_TR_TIMER_SEL or SAR_SIMULT_CTRL.SIMULT_HW_TIMER_SEL). + +If this bit is set for a given SAR, the Timer is the only valid trigger source. Non-timer based Hardware (DSI) triggers cannot be used nor can Firmware based triggers (FW,Continuous,Injection). Furthermore, trigger collision functionality will be limited to interrupt generation only. + +-0: Legacy (SAR not duty cycled in chip active mode +-1: SAR duty cycled in chip active mode + +<0>: Active Mode Duty Cycle enable for SAR0 +<1>: Active Mode Duty Cycle enable for SAR1 +<2>: Active Mode Duty Cycle enable for SAR2 +<3>: Active Mode Duty Cycle enable for SAR3 + +This field is only applicable when SAR_CLOCK_SEL.CLOCK_SEL =1. + +This field can also affect LPOSC functionality in Active Mode (see LPOSC CONFIG.DEEPSLEEP_MODE field for details) + [11:8] + read-write + + + + + CTBM_CLOCK_SEL + Clock select for CTBm + 0x20 + 32 + read-write + 0x0 + 0x1 + + + PUMP_CLOCK_SEL + Select source for CTBm Pump Clock. + [0:0] + read-write + + + LEGACY + CTBm pump clock set by AREF.CTRL.CLOCK_PUMP_PERI_SEL (Legacy). + +When configured for legacy operation, the CTBm deeplseep functionality is determined solely by the CTRL.DEEPSLEEP_ON bit. + 0 + + + CLK_DPSLP + CTBm pump clock sourced from CLK_DPSLP + +When configured for CLK_DPSLP operation, the CTBm deepsleep functionality is determined by the CTRL.DEEPSLEEP_ON bit AND SAR(s) operation (i.e. CTBm is duty cycled with the SAR(s)). In this mode, the CTBm should only be used as a buffer/gain stage for the SAR(s). + 1 + + + + + + + 2 + 4 + SAR_DPSLP_CTRL[%s] + Deepsleep control for SARv3 + 0x30 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + enable for SAR deepsleep operation. SAR_CLOCK_SEL.CLOCK_SEL must be set to 1 for this field to affect SAR operation. + +- 0: SAR deeepsleep operation disabled +- 1: SAR deepsleep operation enabled. + [31:31] + read-write + + + + + 2 + 4 + SAR_CLOCK_SEL[%s] + Clock select for SARv3 + 0x40 + 32 + read-write + 0x0 + 0x40000000 + + + CLOCK_SEL + SAR clock select + [30:30] + read-write + + + LEGACY + - 0: legacy: SAR clock source is CLK_PERI (SAR is only operational in chip ACTIVE mode) + 0 + + + CLK_DPSLP + - 1: SAR clock source is CLK_DPSLP (SAR can be operational in both chip ACTIVE and DEEPSLEEP modes) + 1 + + + + + + + 2 + 4 + SAR_TR_SCAN_CNT_STATUS[%s] + SAR trigger scan control status + 0x50 + 32 + read-only + 0x0 + 0xFF + + + SCAN_CNT_STATUS + A read from this register returns the current sample count (possible values are 1 through SCAN_TR_SCAN_CNT.SCAN_CNT+1). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. + [7:0] + read-only + + + + + SAR_TR_SCAN_CNT + SAR trigger scan control + 0x60 + 32 + read-write + 0x0 + 0xFF + + + SCAN_CNT + SAR trigger sample counter. This field determines the number of samples a SAR will take when triggered. The number of samples is SCAN_COUNT+1. + +This feature can be enabled for individual SARs by setting the appropriate bit of SAR_TR_CTRL.TR_SCAN_CNT_SEL. + +This feature can be enabled for simultaneously sampled SARs by setting SAR_SIMULT_TR_CTRL.SIMULT_TR_SCAN_CNT_SEL. + +If SAR.SAMPLE_CTRL.AVG_MODE is set to INTERLEAVED, the SCAN_CNT must be set an integer multiple of (1<<AVG_CNTR+1). + [7:0] + read-write + + + + + SAR_OVR_CTRL + SAR HW trigger override + 0x64 + 32 + read-write + 0x0 + 0xFFF + + + HW_TR_TIMER_SEL + SAR hardware trigger source select (one bit per SAR). SAR must be configured for hardware triggering (SAR.SAMPLE_CTRL.DSI_TRIGGER_EN must be set to 1). + +-0: Legacy (tr_sar_in_<N>) +-1: Timer trigger + +<0>: HW Trigger source for SAR0 +<1>: HW Trigger source for SAR1 +<2>: HW Trigger source for SAR2 +<3>: HW Trigger source for SAR3 + [3:0] + read-write + + + TR_SCAN_CNT_SEL + SAR trigger sample select (one bit per SAR). + +-0: Disabled +-1: Enabled, SAR takes SAR_TR_SCAN_CNT per trigger (valid for both Firmware and Edge Senstive Hardware triggering, but ignored for Level Sensitive Hardware triggering and CONTINUOUS triggering). This feature cannot be enabled if the SAR is configured for Non-Tailgating Injection (SAR.INJ_CHAN_CONFIG.INJ_TAILGATING=0 while SAR.INJ_CHAN_CONFIG.INJ_START_EN=1) + +<0>: trigger sample select for SAR0 +<1>: trigger sample select for SAR1 +<2>: trigger sample select for SAR2 +<3>: trigger sample select for SAR3 + [7:4] + read-write + + + EOS_INTR_SCAN_CNT_SEL + SAR EOS interrupt source select (one bit per SAR). This feature is not available for FW or Continuous triggering. + +-0: Legacy (SAR EOS is the source of the SAR EOS interrupt) +-1: Enabled, SAR EOS interrupt only occurs for the EOS when sample=SAR_TR_SCAN_CNT.SCAN_CNT. + +<0>: EOS interrupt sample count select for SAR0 +<1>: EOS interrupt sample count select for SAR1 +<2>: EOS interrupt sample count select for SAR2 +<3>: EOS interrupt sample count select for SAR3 + [11:8] + read-write + + + + + SAR_SIMULT_CTRL + SAR simultaneous trigger control + 0x68 + 32 + read-write + 0x80000 + 0x3C013F + + + SIMULT_HW_TR_EN + SAR simultaneous hardware triggering enable (one bit per SAR) +-0: disabled +-1: SAR trigger override enabled (SAR trigger set by SAR_OVR_CTRL register) + +<0>: Simultaneuous sampling enable for SAR0 +<1>: Simultaneuous sampling enable for SAR1 +<2>: Simultaneuous sampling enable for SAR2 +<3>: Simultaneuous sampling enable for SAR3 + +Simultaneous sampling requires at least two bits in this field to be set. +If less than two bits are set, this register will not affect SAR operation. + [3:0] + read-write + + + SIMULT_HW_TR_SRC + Source for Simult Hardware trigger + [5:4] + read-write + + + SAR_TR_IN_0 + SAR 0 HW Trigger Input + 0 + + + SAR_TR_IN_1 + SAR 1 HW Trigger Input + 1 + + + SAR_TR_IN_2 + SAR 2 HW Trigger Input + 2 + + + SAR_TR_IN_3 + SAR 3 HW Trigger Input + 3 + + + + + SIMULT_HW_TR_TIMER_SEL + SAR hardware trigger source select +-0: SIMULT_HW_TR_SRC +-1: Timer trigger + [8:8] + read-write + + + SIMULT_HW_TR_LEVEL + - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. +- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [18:18] + read-write + + + SIMULT_HW_SYNC_TR + - 0: bypass clock domain synchronization of the Simult trigger signal. +- 1: synchronize the Simult trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. + [19:19] + read-write + + + SIMULT_TR_SCAN_CNT_SEL + Simultaneous trigger sample select +-0: Disabled +-1: Enabled, SAR takes SAR_TR_SCAN_CNT per trigger (valid for both Firmware and Edge Senstive Hardware triggering, but ignored for Level Sensitive Hardware triggering and CONTINUOUS triggering) This feature cannot be enabled if either SAR is configured for Non-Tailgating Injection (SAR.INJ_CHAN_CONFIG.INJ_TAILGATING=0 while SAR.INJ_CHAN_CONFIG.INJ_START_EN=1) + [20:20] + read-write + + + SIMULT_EOS_INTR_SCAN_CNT_SEL + Simultaneous SAR EOS interrupt source select. This feature is not available for FW or Continuous triggering. + +-0: Legacy (SAR EOS is the source of the SAR EOS interrupt) +-1: Enabled, SAR EOS interrupt only occurs for the EOS when sample=SAR_TR_SCAN_CNT.SCAN_CNT. + [21:21] + read-write + + + + + SAR_SIMULT_FW_START_CTRL + SAR simultaneous start control + 0x6C + 32 + read-write + 0x0 + 0xF000F + + + FW_TRIGGER + This field is used to simultaneously FW trigger two or more SARs. + +<0>: Firmware trigger for SAR0 +<1>: Firmware trigger for SAR1 +<2>: Firmware trigger for SAR2 +<3>: Firmware trigger for SAR3 + +If less than two bits are set, this field has no effect. + +When firmware writes to this field it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [3:0] + read-write + + + CONTINUOUS + This field is used to configure two or more SARs for continuous operation. + +-0: Continuous mode disabled +-1: Continuously scan enabled channels, ignore triggers. + +<0>: Continuous Mode for SAR0 +<1>: Continuous Mode for SAR1 +<2>: Continuous Mode for SAR2 +<3>: Continuous Mode for SAR3 + +If less than two bits are set, this field has no effect. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. + [19:16] + read-write + + + + + SAR_TR_OUT_CTRL + SAR trigger out control + 0x70 + 32 + read-write + 0x0 + 0xF + + + SAR0_TR_OUT_SEL + SAR0 Trigger Out Source Select + [0:0] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + SAR1_TR_OUT_SEL + SAR1 Trigger Out Source Select + [1:1] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + SAR2_TR_OUT_SEL + SAR2 Trigger Out Source Select + [2:2] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + SAR3_TR_OUT_SEL + SAR3 Trigger Out Source Select + [3:3] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + + + TIMER + Programmable Analog Subsystem + 0x00000100 + + CTRL + Timer trigger control register + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + 0=disabled, 1=enabled + +Upon enable, the timer will immediately generate a trigger pulse (lasting for one clock cycle of the selected CONFIF.CLOCK_SEL) and will generate subsequent trigger pulses (again lasting one clock cycle) whenever the timer reaches terminal count. If PERIOD.PER_VAL is set to 0, the timer trigger output will remain high as long as the timer is enabled. + [31:31] + read-write + + + + + CONFIG + Timer trigger configuration register + 0x4 + 32 + read-write + 0x0 + 0x3 + + + CLOCK_SEL + Select Clock source of the Timer + [1:0] + read-write + + + CLK_PERI + Timer clocked from CLK_PERI + 0 + + + CLK_DPSLP + Timer clocked from CLK_DPSLP + 1 + + + CLK_LF + Timer clocked from CLK_LF + 2 + + + TBD + N/A + 3 + + + + + + + PERIOD + Timer trigger period register + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + PER_VAL + Actual timer period is PER_VAL+1 (1 to 65536). + +Only non-zero PER_VAL are supported. (i.e. PER_VAL=0 is considered invalid). + [15:0] + read-write + + + + + + LPOSC + LPOSC configuration + 0x00000200 + + CTRL + Low Power Oscillator control + 0x0 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLED + Master enable for LPOSC oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the LPOSC during DEEPSLEEP (unless DEEPSLEEP_MODE is set) + [31:31] + read-write + + + + + CONFIG + Low Power Oscillator configuration register + 0x4 + 32 + read-write + 0x0 + 0x1 + + + DEEPSLEEP_MODE + LPOSC functionality while in DEEPSLEEP. + +If the ANA_PWR_CFG.DUTY_CYCLE_SAR_ACT_EN bit of a Deepsleep configured SAR is set, the DEEPSLEEP_MODE field for the LPOSC also applies to chip active mode (i.e. the LPOSC will get duty cycled in chip active mode if DEEPSLEEP_MODE=0 and DUTY_CYLE_SAR_ACT_EN=1 for all Deepsleep enabled SAR(s)) + [0:0] + read-write + + + DUTYCYCLED + LPOSC enabled by TIMER trigger + 0 + + + ALWAYS_ON + LPOSC always on in deepsleep + 1 + + + + + + + ADFT + Retention, Hidden + 0x8 + 32 + read-write + 0x0 + 0x3 + + + ADFT_SEL + ADFT selection for LPOSC. +0: DFT disabled +1: Measure Vdo; expect ~0.8V +2: Measure Ibias_ptat; expect ~250nA +3: Measure Ibias_ctat; expect ~550nA + [1:0] + read-write + + + + + + 2 + 256 + FIFO[%s] + FIFO configuration + 0x00000300 + + CTRL + FIFO control register + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + Enable for SAR FIFO functionality. If CONFIG.CHAIN_TO_NXT is set, the ENABLED bit of the NEXT FIFO is set when FIFO[0] is enabled. +- 0: FIFO disabled +- 1: FIFO enabled + [31:31] + read-write + + + + + CONFIG + FIFO configuration register + 0x4 + 32 + read-write + 0x0 + 0x7 + + + CHAN_ID_EN + channel number (ID) enable bit + +-0: CHAN_ID field in RD_DATA is disabled. A read from RD_DATA will result in (4'b0,16'b RESULT) + +-1: CHAN_ID field in RD_DATA is enabled. A read from RD_DATA will result in (4'b CHAN_ID, 16'b RESULT) + + +If CHAIN_EN is enabled, only FIFO[0].config.chan_id_en should be configured and the other FIFOs in the chain will inherit the FIFO[0] config. + [0:0] + read-write + + + CHAIN_TO_NXT + Chain FIFO to next FIFO (i.e. chain FIFO0 and FIFO1). +- 0: FIFO not chained . FIFO operates independently (FIFO depth of 64) and only operates on result data from its associated SAR. +- 1: FIFO chained to next FIFO. FIFO is part of a chain of FIFOs (effectively extending the FIFO depth beyond 64) and only operates on result data from SAR0. + [1:1] + read-write + + + TR_INTR_CLR_RD_EN + Enable for FIFO read clearing the FIFO level trigger and level interrupt. +- 0: Disabled, FIFO level trigger and level interrupt generation follows LEVEL.LEVEL. +- 1: Enabled, after initial FIFO level trigger and level interrupt generation, subsequent FIFO level triggers and level interrupts are blocked until at least FIFO.LEVEL+1 reads have occurred. + +If CHAIN_TO_NXT is enabled, only FIFO[0].CONFIG. TR_CLR_RD_EN should be configured. + [2:2] + read-write + + + + + CLEAR + FIFO clear register + 0x8 + 32 + read-write + 0x0 + 0x1 + + + CLEAR + When firmware writes a 1 here it will trigger and clearing of the FIFO status registers (excluding interrupts), hardware clears this bit. + [0:0] + read-write + + + + + LEVEL + FIFO level register + 0xC + 32 + read-write + 0x0 + 0xFF + + + LEVEL + FIFO level set. A trigger (and optional interrupt) event occurs when USED.USED = LEVEL+1. (Trigger generation is also affect by CONFIG.TR_CLR_RD_EN). + +If CHAIN_TO_NXT is disabled, the Max LEVEL is limited to 63. + +If CHAIN_TO_NXT is enabled, only FIFO[0].config.level should be configured and the Max LEVEL is set by the number of FIFOs in the chain. + [7:0] + read-write + + + + + USED + FIFO used register + 0x10 + 32 + read-only + 0x0 + 0xFF + + + USED + Number of used/occupied entries in the FIFO. + +If CONFIG.CHAIN_EN is disabled, the field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].USED.USED should be read to detemine the used status. + [7:0] + read-only + + + + + STATUS + FIFO status register + 0x14 + 32 + read-only + 0x0 + 0xFFFF + + + RD_PTR + FIFO read pointer: FIFO location from which a data is read. + +Note: This functionality is intended for debugging purposes. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].STATUS.RD_PTR should be read to detemine the read pointer location of the chained FIFO. + [7:0] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data is written by the hardware. + +Note: This functionality is intended for debugging purposes. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].STATUS.WR_PTR should be read to detemine the write pointer location of the chained FIFO. + [15:8] + read-only + + + + + RD_DATA + FIFO read data register + 0x18 + 32 + read-only + 0x0 + 0xFFFFF + + + RESULT + SAR result. Results from all enabled channels are stored in the buffer. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].RD_DATA.RESULT should be read. + [15:0] + read-only + + + CHAN_ID + Channel number for a given SAR result. Requires CTRL.CHAN_ID_EN to be set. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].RD_DATA.CHAN_ID should be read. + [19:16] + read-only + + + + + INTR + Interrupt register + 0x20 + 32 + read-write + 0x0 + 0x7 + + + FIFO_LEVEL + HW sets this field to '1', when STATUS.USED >= CTRL.LEVEL+1 + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR.FIFO_LEVEL is updated by hardware. Write with '1' to clear bit. + [0:0] + read-write + + + FIFO_OVERFLOW + HW sets this field to '1', when writing to a full FIFO (FIFO_STATUS.USED is '64'). + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR.FIFO_OVERFLOW is updated by hardware. Write with '1' to clear bit. + [1:1] + read-write + + + FIFO_UNDERFLOW + HW sets this field to '1', when reading from an empty FIFO. HW tracks underflow after FIFO is being written to and FIFO_CTL.ENABLE==1. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR.FIFO_UNDERFLOW is updated by hardware. Write with '1' to clear bit. + [2:2] + read-write + + + + + INTR_SET + Interrupt set register + 0x24 + 32 + read-write + 0x0 + 0x7 + + + FIFO_LEVEL + Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + FIFO_OVERFLOW + Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). + [1:1] + read-write + + + FIFO_UNDERFLOW + Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x28 + 32 + read-write + 0x0 + 0x7 + + + FIFO_LEVEL + Mask for corresponding field in INTR register. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR_MASK.FIFO_LEVEL should be set. + [0:0] + read-write + + + FIFO_OVERFLOW + Mask for corresponding field in INTR register. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR_MASK.FIFO_OVERFLOW should be set. + [1:1] + read-write + + + FIFO_UNDERFLOW + Mask for corresponding field in INTR register. + +If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR_MASK.FIFO_UNDERFLOW should be set. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x2C + 32 + read-only + 0x0 + 0x7 + + + FIFO_LEVEL + Logical AND of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + FIFO_OVERFLOW + Logical AND of corresponding INTR and INTR_MASK fields. + [1:1] + read-only + + + FIFO_UNDERFLOW + Logical AND of corresponding INTR and INTR_MASK fields. + [2:2] + read-only + + + + + + AREFV2 + AREF configuration + 0x00000E00 + + AREF_CTRL + global AREF control + 0x0 + 32 + read-write + 0x0 + 0xF039FFFD + + + AREF_MODE + Control bit to trade off AREF settling and noise performance + [0:0] + read-write + + + NORMAL + Nominal noise normal startup mode (meets normal mode settling and noise specifications) + 0 + + + FAST_START + High noise fast startup mode (meets fast mode settling and noise specifications) + 1 + + + + + AREF_BIAS_SCALE + BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) +0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) +1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) +2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) +3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) + [3:2] + read-write + + + AREF_RMB + AREF control signals (RMB). + +Bit 0: Manual VBG startup circuit enable + 0: normal VBG startup circuit operation + 1: VBG startup circuit is forced 'always on' + +Bit 1: Manual disable of IPTAT2 DAC + 0: normal IPTAT2 DAC operation + 1: PTAT2 DAC is disabled while VBG startup is active + +Bit 2: Manual enable of VBG offset correction DAC + 0: normal VBG offset correction DAC operation + 1: VBG offset correction DAC is enabled while VBG startup is active + [6:4] + read-write + + + CTB_IPTAT_SCALE + CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). +0: 1uA +1: 100nA + [7:7] + read-write + + + CTB_IPTAT_REDIRECT + Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). +0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT +1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT + +*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. + [15:8] + read-write + + + IZTAT_SEL + iztat current select control + [16:16] + read-write + + + SRSS + Use 250nA IZTAT from SRSS + 0 + + + LOCAL + Use locally generated 250nA + 1 + + + + + CLOCK_PUMP_PERI_SEL + CTBm charge pump clock source select. This field has nothing to do with the AREF. +0: Use the dedicated pump clock from SRSS (default) +1: Use one of the CLK_PERI dividers + [19:19] + read-write + + + VREF_SEL + bandgap voltage select control + [21:20] + read-write + + + SRSS + Use 0.8V Vref from SRSS + 0 + + + LOCAL + Use locally generated Vref + 1 + + + EXTERNAL + Use externally supplied Vref (aref_ext_vref) + 2 + + + + + DEEPSLEEP_MODE + AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) + [29:28] + read-write + + + OFF + All blocks 'OFF' in DeepSleep + 0 + + + IPTAT + IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) + 1 + + + IPTAT_IZTAT + IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) + +*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep + 2 + + + IPTAT_IZTAT_VREF + IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. + 3 + + + + + DEEPSLEEP_ON + - 0: AREF IP disabled/off during DeepSleep power mode +- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + Disable AREF + [31:31] + read-write + + + + + + VREF_TRIM0 + VREF Trim bits + 0xF00 + 32 + read-write + 0x0 + 0xFF + + + VREF_ABS_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM1 + VREF Trim bits + 0xF04 + 32 + read-write + 0x0 + 0xFF + + + VREF_TEMPCO_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM2 + VREF Trim bits + 0xF08 + 32 + read-write + 0x0 + 0xFF + + + VREF_CURV_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM3 + VREF Trim bits + 0xF0C + 32 + read-write + 0x0 + 0xF + + + VREF_ATTEN_TRIM + Obsolete + [3:0] + read-write + + + + + IZTAT_TRIM0 + VREF Trim bits + 0xF10 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_ABS_TRIM + N/A + [7:0] + read-write + + + + + IZTAT_TRIM1 + IZTAT Trim bits + 0xF14 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_TC_TRIM + IZTAT temperature correction trim (RMB) +0x00 : No IZTAT temperature correction +0xFF : Maximum IZTAT temperature correction + +As this is a Risk Mitigation Register, it should be loaded with 0x08. + [7:0] + read-write + + + + + IPTAT_TRIM0 + IPTAT Trim bits + 0xF18 + 32 + read-write + 0x0 + 0xFF + + + IPTAT_CORE_TRIM + IPTAT trim +0x0 : Minimum IPTAT current (~150nA at room) +0xF : Maximum IPTAT current (~350nA at room) + [3:0] + read-write + + + IPTAT_CTBM_TRIM + CTMB PTAT Current Trim +0x0 : Minimum CTMB IPTAT Current (~875nA) +0xF : Maximum CTMB IPTAT Current (~1.1uA) + [7:4] + read-write + + + + + ICTAT_TRIM0 + ICTAT Trim bits + 0xF1C + 32 + read-write + 0x0 + 0xF + + + ICTAT_TRIM + ICTAT trim +0x00 : Minimum ICTAT current (~150nA at room) +0x0F : Maximum ICTAT current (~350nA at room) + [3:0] + read-write + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct new file mode 100644 index 0000000000..69055f87ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct @@ -0,0 +1,292 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct new file mode 100644 index 0000000000..31611cbf60 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -0,0 +1,311 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct new file mode 100644 index 0000000000..6cf57aa0da --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -0,0 +1,311 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct new file mode 100644 index 0000000000..8f43a22ccc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -0,0 +1,311 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct new file mode 100644 index 0000000000..7ddff2b33a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -0,0 +1,311 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct new file mode 100644 index 0000000000..efbc09f9ff --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -0,0 +1,311 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct new file mode 100644 index 0000000000..daa0dce464 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -0,0 +1,288 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08020000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct new file mode 100644 index 0000000000..0647631181 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -0,0 +1,307 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08020000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct new file mode 100644 index 0000000000..2b79783b24 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -0,0 +1,307 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x080E0000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000000..09d6b4ccfe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -0,0 +1,261 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..2ebb953cfd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S new file mode 100644 index 0000000000..ba67c4bd39 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000000..9aaf9db0cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld new file mode 100644 index 0000000000..8359c7c0b0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld @@ -0,0 +1,457 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld new file mode 100644 index 0000000000..17a240286c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -0,0 +1,472 @@ +/***************************************************************************//** +* \file cy8c6xx5_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld new file mode 100644 index 0000000000..7197e3c889 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld @@ -0,0 +1,472 @@ +/***************************************************************************//** +* \file cy8c6xx6_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld new file mode 100644 index 0000000000..2fbf05e7c5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -0,0 +1,472 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld new file mode 100644 index 0000000000..ef8bb501e9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld @@ -0,0 +1,472 @@ +/***************************************************************************//** +* \file cy8c6xx8_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld new file mode 100644 index 0000000000..d85bdee03d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -0,0 +1,472 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld new file mode 100644 index 0000000000..5e459d6844 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld @@ -0,0 +1,458 @@ +/***************************************************************************//** +* \file cyb06xx5_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08020000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld new file mode 100644 index 0000000000..15cbb117c2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -0,0 +1,473 @@ +/***************************************************************************//** +* \file cyb06xx7_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08020000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld new file mode 100644 index 0000000000..d3504a4b20 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -0,0 +1,473 @@ +/***************************************************************************//** +* \file cyb06xxa_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00010000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x080E0000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0000C000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000000..b46556a8a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S @@ -0,0 +1,399 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..3fed47b01f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S @@ -0,0 +1,367 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S new file mode 100644 index 0000000000..b30decaac8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S @@ -0,0 +1,367 @@ +/**************************************************************************//** + * @file startup_psoc6_03_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000000..fb65f353f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S @@ -0,0 +1,367 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf new file mode 100644 index 0000000000..a6f7e8d9c2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf @@ -0,0 +1,282 @@ +/******************************************************************************* +* \file cy8c6xx4_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf new file mode 100644 index 0000000000..bcd5743017 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -0,0 +1,289 @@ +/******************************************************************************* +* \file cy8c6xx5_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf new file mode 100644 index 0000000000..9ef4eca2dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -0,0 +1,289 @@ +/******************************************************************************* +* \file cy8c6xx6_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf new file mode 100644 index 0000000000..06bc219b50 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -0,0 +1,289 @@ +/******************************************************************************* +* \file cy8c6xx7_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf new file mode 100644 index 0000000000..a373650d51 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -0,0 +1,289 @@ +/******************************************************************************* +* \file cy8c6xx8_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf new file mode 100644 index 0000000000..d309fb2139 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -0,0 +1,289 @@ +/******************************************************************************* +* \file cy8c6xxa_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf new file mode 100644 index 0000000000..0ae9213afd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf @@ -0,0 +1,283 @@ +/******************************************************************************* +* \file cyb06xx5_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00010000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08020000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0000C000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf new file mode 100644 index 0000000000..f071853ffe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -0,0 +1,290 @@ +/******************************************************************************* +* \file cyb06xx7_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00010000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08020000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0000C000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf new file mode 100644 index 0000000000..737ca42dbc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -0,0 +1,290 @@ +/******************************************************************************* +* \file cyb06xxa_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00010000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x080E0000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0000C000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000000..e926966cf7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S @@ -0,0 +1,413 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK NvicMux8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux8_IRQHandler + B NvicMux8_IRQHandler + + PUBWEAK NvicMux9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux9_IRQHandler + B NvicMux9_IRQHandler + + PUBWEAK NvicMux10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux10_IRQHandler + B NvicMux10_IRQHandler + + PUBWEAK NvicMux11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux11_IRQHandler + B NvicMux11_IRQHandler + + PUBWEAK NvicMux12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux12_IRQHandler + B NvicMux12_IRQHandler + + PUBWEAK NvicMux13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux13_IRQHandler + B NvicMux13_IRQHandler + + PUBWEAK NvicMux14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux14_IRQHandler + B NvicMux14_IRQHandler + + PUBWEAK NvicMux15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux15_IRQHandler + B NvicMux15_IRQHandler + + PUBWEAK NvicMux16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux16_IRQHandler + B NvicMux16_IRQHandler + + PUBWEAK NvicMux17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux17_IRQHandler + B NvicMux17_IRQHandler + + PUBWEAK NvicMux18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux18_IRQHandler + B NvicMux18_IRQHandler + + PUBWEAK NvicMux19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux19_IRQHandler + B NvicMux19_IRQHandler + + PUBWEAK NvicMux20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux20_IRQHandler + B NvicMux20_IRQHandler + + PUBWEAK NvicMux21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux21_IRQHandler + B NvicMux21_IRQHandler + + PUBWEAK NvicMux22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux22_IRQHandler + B NvicMux22_IRQHandler + + PUBWEAK NvicMux23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux23_IRQHandler + B NvicMux23_IRQHandler + + PUBWEAK NvicMux24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux24_IRQHandler + B NvicMux24_IRQHandler + + PUBWEAK NvicMux25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux25_IRQHandler + B NvicMux25_IRQHandler + + PUBWEAK NvicMux26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux26_IRQHandler + B NvicMux26_IRQHandler + + PUBWEAK NvicMux27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux27_IRQHandler + B NvicMux27_IRQHandler + + PUBWEAK NvicMux28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux28_IRQHandler + B NvicMux28_IRQHandler + + PUBWEAK NvicMux29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux29_IRQHandler + B NvicMux29_IRQHandler + + PUBWEAK NvicMux30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux30_IRQHandler + B NvicMux30_IRQHandler + + PUBWEAK NvicMux31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux31_IRQHandler + B NvicMux31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..3b77acffe3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S @@ -0,0 +1,317 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S new file mode 100644 index 0000000000..50a1194adb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S @@ -0,0 +1,317 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000000..e2adca7641 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S @@ -0,0 +1,317 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c new file mode 100644 index 0000000000..babda47592 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -0,0 +1,536 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.90.1 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) + +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + CY_SECTION_SHAREDMEM + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + #if defined(CY_DEVICE_SECURE) + /* Initialize Protected Regsiter Access driver. */ + Cy_PRA_Init(); + #endif /* defined(CY_DEVICE_SECURE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); + + if (0UL != locHf0Clock) + { + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; + } +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct new file mode 100644 index 0000000000..28f6720ae6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct @@ -0,0 +1,295 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00040000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct new file mode 100644 index 0000000000..6360c10148 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00080000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0003D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct new file mode 100644 index 0000000000..ace8f2ff92 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00080000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct new file mode 100644 index 0000000000..5a0607e56b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct new file mode 100644 index 0000000000..fddb5ee642 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0007D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct new file mode 100644 index 0000000000..79223e1aa4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00200000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000FD800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct new file mode 100644 index 0000000000..3a746a20ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct @@ -0,0 +1,298 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00030000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08001800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001E800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct new file mode 100644 index 0000000000..ec2853f71f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -0,0 +1,317 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00068000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08001800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001E800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct new file mode 100644 index 0000000000..1c064f3bdb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -0,0 +1,317 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x000E8000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08001800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000DE800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000..fa2247ebe9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,638 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..114d71efb8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,701 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT scb_9_interrupt_IRQHandler [WEAK] + EXPORT scb_10_interrupt_IRQHandler [WEAK] + EXPORT scb_11_interrupt_IRQHandler [WEAK] + EXPORT scb_12_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] + EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +scb_9_interrupt_IRQHandler +scb_10_interrupt_IRQHandler +scb_11_interrupt_IRQHandler +scb_12_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dmac_2_IRQHandler +cpuss_interrupts_dmac_3_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_0_interrupt_i2s_IRQHandler +audioss_0_interrupt_pdm_IRQHandler +audioss_1_interrupt_i2s_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +sdhc_1_interrupt_wakeup_IRQHandler +sdhc_1_interrupt_general_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S new file mode 100644 index 0000000000..f4739ec195 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S @@ -0,0 +1,645 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT canfd_0_interrupt0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts0_0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_29_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_30_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_31_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +pass_interrupt_sar_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +canfd_0_interrupt0_IRQHandler +canfd_0_interrupts0_0_IRQHandler +canfd_0_interrupts1_0_IRQHandler +cpuss_interrupts_dw1_29_IRQHandler +cpuss_interrupts_dw1_30_IRQHandler +cpuss_interrupts_dw1_31_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S new file mode 100644 index 0000000000..0cf51836d8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S @@ -0,0 +1,652 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctbs_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_0_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_1_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_0_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_1_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_256_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_257_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_258_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_259_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_260_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_261_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_262_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_263_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT canfd_0_interrupt0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts0_0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_29_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_30_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_31_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_29_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +pass_interrupt_sar_0_IRQHandler +pass_interrupt_sar_1_IRQHandler +pass_interrupt_ctbs_IRQHandler +pass_interrupt_fifo_0_IRQHandler +pass_interrupt_fifo_1_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_256_IRQHandler +tcpwm_0_interrupts_257_IRQHandler +tcpwm_0_interrupts_258_IRQHandler +tcpwm_0_interrupts_259_IRQHandler +tcpwm_0_interrupts_260_IRQHandler +tcpwm_0_interrupts_261_IRQHandler +tcpwm_0_interrupts_262_IRQHandler +tcpwm_0_interrupts_263_IRQHandler +pass_interrupt_dacs_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +canfd_0_interrupt0_IRQHandler +canfd_0_interrupts0_0_IRQHandler +canfd_0_interrupts1_0_IRQHandler +cpuss_interrupts_dw1_29_IRQHandler +cpuss_interrupts_dw1_30_IRQHandler +cpuss_interrupts_dw1_31_IRQHandler +cpuss_interrupts_dw0_29_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld new file mode 100644 index 0000000000..8da0601f2f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld @@ -0,0 +1,452 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00040000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld new file mode 100644 index 0000000000..4ce34d8138 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -0,0 +1,467 @@ +/***************************************************************************//** +* \file cy8c6xx5_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00080000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0003D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld new file mode 100644 index 0000000000..03434c59ac --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld @@ -0,0 +1,467 @@ +/***************************************************************************//** +* \file cy8c6xx6_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00080000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000000..6d51891f5e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,467 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld new file mode 100644 index 0000000000..b9b893c94c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld @@ -0,0 +1,467 @@ +/***************************************************************************//** +* \file cy8c6xx8_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0007D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld new file mode 100644 index 0000000000..1c33d606e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -0,0 +1,467 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00200000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000FD800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld new file mode 100644 index 0000000000..69ba7efc2e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld @@ -0,0 +1,455 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00030000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08001800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001E800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld new file mode 100644 index 0000000000..32bf3ce003 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -0,0 +1,470 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00068000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08001800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001E800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld new file mode 100644 index 0000000000..b5fae9bf89 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld @@ -0,0 +1,470 @@ +/***************************************************************************//** +* \file cyb06xxa_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x000E8000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08001800 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x000DE800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000..3c2f44d1e0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,631 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..1ebcac39f8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S new file mode 100644 index 0000000000..73ac0b71a9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S @@ -0,0 +1,648 @@ +/**************************************************************************//** + * @file startup_psoc6_03_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S new file mode 100644 index 0000000000..c1ebe83949 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S @@ -0,0 +1,652 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + .long pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + .long pass_interrupt_ctbs_IRQHandler /* individual interrupt per CTB */ + .long 0 /* Reserved */ + .long pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + .long pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long 0 /* Reserved */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + .long tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + .long tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + .long tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + .long tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + .long tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + .long tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + .long tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + .long cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + def_irq_handler pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* individual interrupt per CTB */ + def_irq_handler pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + def_irq_handler pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + def_irq_handler tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + def_irq_handler tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + def_irq_handler tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + def_irq_handler tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + def_irq_handler tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + def_irq_handler tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + def_irq_handler tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + def_irq_handler cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf new file mode 100644 index 0000000000..f5c49669fa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf @@ -0,0 +1,285 @@ +/******************************************************************************* +* \file cy8c6xx4_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00040000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0001D800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf new file mode 100644 index 0000000000..98bcf70ec1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -0,0 +1,292 @@ +/******************************************************************************* +* \file cy8c6xx5_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00080000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0003D800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf new file mode 100644 index 0000000000..aea6359a49 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf @@ -0,0 +1,292 @@ +/******************************************************************************* +* \file cy8c6xx6_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00080000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0001D800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000000..ab63f737ed --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,292 @@ +/******************************************************************************* +* \file cy8c6xx7_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00100000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00045800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf new file mode 100644 index 0000000000..990a264ff4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf @@ -0,0 +1,292 @@ +/******************************************************************************* +* \file cy8c6xx8_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00100000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0007D800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf new file mode 100644 index 0000000000..324140cc11 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -0,0 +1,292 @@ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00200000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x000FD800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf new file mode 100644 index 0000000000..00a578457f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf @@ -0,0 +1,288 @@ +/******************************************************************************* +* \file cyb06xx5_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x00000400; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00030000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08001800; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0001E800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START + BOOT_HEADER_SIZE; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf new file mode 100644 index 0000000000..a818015d38 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -0,0 +1,295 @@ +/******************************************************************************* +* \file cyb06xx7_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x00000400; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00068000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08001800; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0001E800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START + BOOT_HEADER_SIZE; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf new file mode 100644 index 0000000000..4149437d90 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf @@ -0,0 +1,295 @@ +/******************************************************************************* +* \file cyb06xxa_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x00000400; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x000E8000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08001800; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x000DE800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START + BOOT_HEADER_SIZE; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000..f4ca47b457 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -0,0 +1,1137 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..3257b6f20c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S @@ -0,0 +1,1263 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK scb_9_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_9_interrupt_IRQHandler + B scb_9_interrupt_IRQHandler + + PUBWEAK scb_10_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_10_interrupt_IRQHandler + B scb_10_interrupt_IRQHandler + + PUBWEAK scb_11_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_11_interrupt_IRQHandler + B scb_11_interrupt_IRQHandler + + PUBWEAK scb_12_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_12_interrupt_IRQHandler + B scb_12_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_2_IRQHandler + B cpuss_interrupts_dmac_2_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_3_IRQHandler + B cpuss_interrupts_dmac_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_0_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_i2s_IRQHandler + B audioss_0_interrupt_i2s_IRQHandler + + PUBWEAK audioss_0_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_pdm_IRQHandler + B audioss_0_interrupt_pdm_IRQHandler + + PUBWEAK audioss_1_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_1_interrupt_i2s_IRQHandler + B audioss_1_interrupt_i2s_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_wakeup_IRQHandler + B sdhc_1_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_1_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_general_IRQHandler + B sdhc_1_interrupt_general_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S new file mode 100644 index 0000000000..ad74139c85 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S @@ -0,0 +1,1114 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK canfd_0_interrupt0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupt0_IRQHandler + B canfd_0_interrupt0_IRQHandler + + PUBWEAK canfd_0_interrupts0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts0_0_IRQHandler + B canfd_0_interrupts0_0_IRQHandler + + PUBWEAK canfd_0_interrupts1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts1_0_IRQHandler + B canfd_0_interrupts1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_29_IRQHandler + B cpuss_interrupts_dw1_29_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_30_IRQHandler + B cpuss_interrupts_dw1_30_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_31_IRQHandler + B cpuss_interrupts_dw1_31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S new file mode 100644 index 0000000000..59ff419440 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S @@ -0,0 +1,1130 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctbs_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK pass_interrupt_sar_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_0_IRQHandler + B pass_interrupt_sar_0_IRQHandler + + PUBWEAK pass_interrupt_sar_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_1_IRQHandler + B pass_interrupt_sar_1_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK pass_interrupt_fifo_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_0_IRQHandler + B pass_interrupt_fifo_0_IRQHandler + + PUBWEAK pass_interrupt_fifo_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_1_IRQHandler + B pass_interrupt_fifo_1_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_256_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_256_IRQHandler + B tcpwm_0_interrupts_256_IRQHandler + + PUBWEAK tcpwm_0_interrupts_257_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_257_IRQHandler + B tcpwm_0_interrupts_257_IRQHandler + + PUBWEAK tcpwm_0_interrupts_258_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_258_IRQHandler + B tcpwm_0_interrupts_258_IRQHandler + + PUBWEAK tcpwm_0_interrupts_259_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_259_IRQHandler + B tcpwm_0_interrupts_259_IRQHandler + + PUBWEAK tcpwm_0_interrupts_260_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_260_IRQHandler + B tcpwm_0_interrupts_260_IRQHandler + + PUBWEAK tcpwm_0_interrupts_261_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_261_IRQHandler + B tcpwm_0_interrupts_261_IRQHandler + + PUBWEAK tcpwm_0_interrupts_262_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_262_IRQHandler + B tcpwm_0_interrupts_262_IRQHandler + + PUBWEAK tcpwm_0_interrupts_263_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_263_IRQHandler + B tcpwm_0_interrupts_263_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK canfd_0_interrupt0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupt0_IRQHandler + B canfd_0_interrupt0_IRQHandler + + PUBWEAK canfd_0_interrupts0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts0_0_IRQHandler + B canfd_0_interrupts0_0_IRQHandler + + PUBWEAK canfd_0_interrupts1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts1_0_IRQHandler + B canfd_0_interrupts1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_29_IRQHandler + B cpuss_interrupts_dw1_29_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_30_IRQHandler + B cpuss_interrupts_dw1_30_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_31_IRQHandler + B cpuss_interrupts_dw1_31_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_29_IRQHandler + B cpuss_interrupts_dw0_29_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c new file mode 100644 index 0000000000..1d24a9ab1a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c @@ -0,0 +1,400 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.90.1 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default FastClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) + +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + /* Initialize Protected Register Access driver */ + Cy_PRA_Init(); +#endif /* defined(CY_DEVICE_SECURE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); + + if (0UL != locHf0Clock) + { + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; + } +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/system_psoc6.h new file mode 100644 index 0000000000..f90da8e19c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/system_psoc6.h @@ -0,0 +1,721 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.90.1 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* ARM Compiler\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.sct', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00002000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00002000 +* \endcode +* - 'xx_cm4_dual.sct', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \note Correct operation of malloc and related functions depends on the working +* implementation of the 'sbrk' function. Newlib-nano (default C runtime library +* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that +* doesn't check for heap and stack collisions during excessive memory allocations. +* To ensure the heap always remains within the range defined by __HeapBase and +* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: +* \snippet startup/snippet/main.c snippet_sbrk +* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include +* clib-support library that provides newlib-compatible implementations of +* 'sbrk', '__malloc_lock' and '__malloc_unlock': +*
+* https://github.com/cypresssemiconductorco/clib-support. +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler +* - Editing source code files\n +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.90.1Updated \ref group_system_config_heap_stack_config_gcc section with the note +* on the dynamic memory allocation for ARM GCC.Documentation update.
Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro.Improve configuration flexibility.
Updated attribute usage for the linker section placement in CM0+ startup codeEnhancement based on usability feedback.
Renamed the '.cy_xip' linker script region as 'cy_xip'Enable access to the XIP region start/end addresses from the C code.
2.90Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.Flash allocation adjustment.
2.80Updated linker scripts for PSoC 64 Secure MCU devices.Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates +* in accordance with the PSoC 64 Secure Boot SDK policies.
Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.Provided support for SysPM driver updates.
Updated the linker scripts.Reserved FLASH area for the MCU boot headers.
Added System Pipe initialization for all devices. Improved PDL usability according to user experience.
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. Defect fixing.
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +/* + * Include optional application-specific configuration header. + * + * For example, custom system_psoc6_config.h can be included here + * by adding the below macro definition to the build system: + * DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"' + */ +#if defined(CY_SYSTEM_PSOC6_CONFIG) +#include CY_SYSTEM_PSOC6_CONFIG +#endif + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macros. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct new file mode 100644 index 0000000000..0a565fcc18 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct @@ -0,0 +1,253 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct new file mode 100644 index 0000000000..033a4d8afe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -0,0 +1,272 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct new file mode 100644 index 0000000000..1761321647 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -0,0 +1,272 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct new file mode 100644 index 0000000000..a54383f554 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -0,0 +1,272 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct new file mode 100644 index 0000000000..39ac0a6aee --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -0,0 +1,272 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct new file mode 100644 index 0000000000..8349ba5c97 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -0,0 +1,272 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct new file mode 100644 index 0000000000..1012af7cfc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -0,0 +1,244 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08020000 +#define RAM_SIZE 0x0000C000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +#define PUBLIC_RAM_SIZE 0x800 +#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct new file mode 100644 index 0000000000..29ad25ae8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -0,0 +1,263 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08020000 +#define RAM_SIZE 0x0000C000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +#define PUBLIC_RAM_SIZE 0x800 +#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct new file mode 100644 index 0000000000..434a59bb4e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -0,0 +1,263 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm0plus.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x080E0000 +#define RAM_SIZE 0x0000C000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +#define PUBLIC_RAM_SIZE 0x800 +#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000000..9e78deadef --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s @@ -0,0 +1,271 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s new file mode 100644 index 0000000000..332737ec48 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s @@ -0,0 +1,223 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s new file mode 100644 index 0000000000..ea55834527 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s @@ -0,0 +1,223 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s new file mode 100644 index 0000000000..0305d1e220 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s @@ -0,0 +1,223 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000000..aef119ccae --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S @@ -0,0 +1,285 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + + .section __STACK, __stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..89e4f1544a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S @@ -0,0 +1,253 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + + .section __STACK, __stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S new file mode 100644 index 0000000000..bb7bea9ceb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S @@ -0,0 +1,253 @@ +/**************************************************************************//** + * @file startup_psoc6_03_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + + .section __STACK, __stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000000..a192309683 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S @@ -0,0 +1,253 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + + .section __STACK, __stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld new file mode 100644 index 0000000000..54bc2202c0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld @@ -0,0 +1,425 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld new file mode 100644 index 0000000000..ee5dcd0b36 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -0,0 +1,440 @@ +/***************************************************************************//** +* \file cy8c6xx5_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld new file mode 100644 index 0000000000..ef853e9308 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld @@ -0,0 +1,440 @@ +/***************************************************************************//** +* \file cy8c6xx6_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld new file mode 100644 index 0000000000..74eec15f42 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -0,0 +1,440 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld new file mode 100644 index 0000000000..00fffdc707 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld @@ -0,0 +1,440 @@ +/***************************************************************************//** +* \file cy8c6xx8_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld new file mode 100644 index 0000000000..bcc201d110 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -0,0 +1,440 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld new file mode 100644 index 0000000000..5efc5f58e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld @@ -0,0 +1,423 @@ +/***************************************************************************//** +* \file cyb06xx5_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* The size of the unprotected public RAM to place an objects that require a full access from both cores */ +PUBLIC_RAM_SIZE = 0x800; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + public_ram (rw) : ORIGIN = 0x08000000, LENGTH = PUBLIC_RAM_SIZE + ram (rwx) : ORIGIN = 0x08020000, LENGTH = 0xC000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + __sdata_start__ = .; + *(.data*) + __sdata_end__ = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Unprotected public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld new file mode 100644 index 0000000000..b0c098cb1d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -0,0 +1,438 @@ +/***************************************************************************//** +* \file cyb06xx7_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* The size of the unprotected public RAM to place an objects that require a full access from both cores */ +PUBLIC_RAM_SIZE = 0x800; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + public_ram (rw) : ORIGIN = 0x08000000, LENGTH = PUBLIC_RAM_SIZE + ram (rwx) : ORIGIN = 0x08020000, LENGTH = 0xC000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + __sdata_start__ = .; + *(.data*) + __sdata_end__ = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Unprotected public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld new file mode 100644 index 0000000000..82ce5b1b65 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -0,0 +1,438 @@ +/***************************************************************************//** +* \file cyb06xxa_cm0plus.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* The size of the unprotected public RAM to place an objects that require a full access from both cores */ +PUBLIC_RAM_SIZE = 0x800; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + public_ram (rw) : ORIGIN = 0x08000000, LENGTH = PUBLIC_RAM_SIZE + ram (rwx) : ORIGIN = 0x080E0000, LENGTH = 0xC000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + __sdata_start__ = .; + *(.data*) + __sdata_end__ = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Unprotected public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000000..e26df0adf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S @@ -0,0 +1,404 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..2641f62389 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S @@ -0,0 +1,372 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S new file mode 100644 index 0000000000..36a054ce03 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S @@ -0,0 +1,372 @@ +/**************************************************************************//** + * @file startup_psoc6_03_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000000..fbc1654770 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S @@ -0,0 +1,372 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf new file mode 100644 index 0000000000..71fbb00104 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf @@ -0,0 +1,246 @@ +/******************************************************************************* +* \file cy8c6xx4_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf new file mode 100644 index 0000000000..eb5b9a3ce2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -0,0 +1,253 @@ +/******************************************************************************* +* \file cy8c6xx5_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf new file mode 100644 index 0000000000..ba540bfe46 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -0,0 +1,253 @@ +/******************************************************************************* +* \file cy8c6xx6_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf new file mode 100644 index 0000000000..d59ccf723f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -0,0 +1,253 @@ +/******************************************************************************* +* \file cy8c6xx7_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf new file mode 100644 index 0000000000..738a3350d0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -0,0 +1,253 @@ +/******************************************************************************* +* \file cy8c6xx8_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf new file mode 100644 index 0000000000..b9cf813e3f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -0,0 +1,253 @@ +/******************************************************************************* +* \file cy8c6xxa_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf new file mode 100644 index 0000000000..b78b235178 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf @@ -0,0 +1,233 @@ +/******************************************************************************* +* \file cyb06xx5_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08020000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802BFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1000FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x080007FF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf new file mode 100644 index 0000000000..12c459bf0a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -0,0 +1,240 @@ +/******************************************************************************* +* \file cyb06xx7_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08020000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802BFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1000FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x080007FF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf new file mode 100644 index 0000000000..048fb05d6b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -0,0 +1,240 @@ +/******************************************************************************* +* \file cyb06xxa_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x080E0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080EBFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1000FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x080007FF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000000..dbba869be4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s @@ -0,0 +1,427 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK NvicMux8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux8_IRQHandler + B NvicMux8_IRQHandler + + PUBWEAK NvicMux9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux9_IRQHandler + B NvicMux9_IRQHandler + + PUBWEAK NvicMux10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux10_IRQHandler + B NvicMux10_IRQHandler + + PUBWEAK NvicMux11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux11_IRQHandler + B NvicMux11_IRQHandler + + PUBWEAK NvicMux12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux12_IRQHandler + B NvicMux12_IRQHandler + + PUBWEAK NvicMux13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux13_IRQHandler + B NvicMux13_IRQHandler + + PUBWEAK NvicMux14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux14_IRQHandler + B NvicMux14_IRQHandler + + PUBWEAK NvicMux15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux15_IRQHandler + B NvicMux15_IRQHandler + + PUBWEAK NvicMux16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux16_IRQHandler + B NvicMux16_IRQHandler + + PUBWEAK NvicMux17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux17_IRQHandler + B NvicMux17_IRQHandler + + PUBWEAK NvicMux18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux18_IRQHandler + B NvicMux18_IRQHandler + + PUBWEAK NvicMux19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux19_IRQHandler + B NvicMux19_IRQHandler + + PUBWEAK NvicMux20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux20_IRQHandler + B NvicMux20_IRQHandler + + PUBWEAK NvicMux21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux21_IRQHandler + B NvicMux21_IRQHandler + + PUBWEAK NvicMux22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux22_IRQHandler + B NvicMux22_IRQHandler + + PUBWEAK NvicMux23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux23_IRQHandler + B NvicMux23_IRQHandler + + PUBWEAK NvicMux24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux24_IRQHandler + B NvicMux24_IRQHandler + + PUBWEAK NvicMux25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux25_IRQHandler + B NvicMux25_IRQHandler + + PUBWEAK NvicMux26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux26_IRQHandler + B NvicMux26_IRQHandler + + PUBWEAK NvicMux27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux27_IRQHandler + B NvicMux27_IRQHandler + + PUBWEAK NvicMux28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux28_IRQHandler + B NvicMux28_IRQHandler + + PUBWEAK NvicMux29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux29_IRQHandler + B NvicMux29_IRQHandler + + PUBWEAK NvicMux30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux30_IRQHandler + B NvicMux30_IRQHandler + + PUBWEAK NvicMux31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux31_IRQHandler + B NvicMux31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s new file mode 100644 index 0000000000..3fa2e866e7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s @@ -0,0 +1,331 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s new file mode 100644 index 0000000000..56c38a97ed --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s @@ -0,0 +1,331 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s new file mode 100644 index 0000000000..a520420369 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s @@ -0,0 +1,331 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c new file mode 100644 index 0000000000..babda47592 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -0,0 +1,536 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.90.1 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) + +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + CY_SECTION_SHAREDMEM + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + #if defined(CY_DEVICE_SECURE) + /* Initialize Protected Regsiter Access driver. */ + Cy_PRA_Init(); + #endif /* defined(CY_DEVICE_SECURE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); + + if (0UL != locHf0Clock) + { + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; + } +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct new file mode 100644 index 0000000000..11a7a4ee3f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct @@ -0,0 +1,240 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0001F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00040000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct new file mode 100644 index 0000000000..6dce04f50d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct @@ -0,0 +1,258 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0001D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00040000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct new file mode 100644 index 0000000000..9bbf13faf0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct @@ -0,0 +1,259 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0003F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct new file mode 100644 index 0000000000..1c6cfbfdc8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx5_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0003D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct new file mode 100644 index 0000000000..3e03b2f407 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct @@ -0,0 +1,259 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0001F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct new file mode 100644 index 0000000000..70899dbd9f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx6_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0001D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00080000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct new file mode 100644 index 0000000000..434aa5330f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct @@ -0,0 +1,259 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00047780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct new file mode 100644 index 0000000000..7610e3bda3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x00045800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct new file mode 100644 index 0000000000..6703237ff6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct @@ -0,0 +1,259 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0007F780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct new file mode 100644 index 0000000000..078de4f4d6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx8_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0007D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct new file mode 100644 index 0000000000..23fa7670bd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct @@ -0,0 +1,259 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x000FF780 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct new file mode 100644 index 0000000000..459ccd9751 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x000FD800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct new file mode 100644 index 0000000000..7cb4319de7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct @@ -0,0 +1,241 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x0001E800 +; Flash +#define FLASH_START 0x10020000 +#define FLASH_SIZE 0x00020000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct new file mode 100644 index 0000000000..631904c421 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct @@ -0,0 +1,256 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x0001E800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00030000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The size of the Cortex-M0+ application image (including MCU boot header area) +#define FLASH_CM0P_SIZE 0x10000 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct new file mode 100644 index 0000000000..1bcd33a75f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -0,0 +1,260 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x0001E800 +; Flash +#define FLASH_START 0x10060000 +#define FLASH_SIZE 0x00030000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct new file mode 100644 index 0000000000..eb7673a106 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -0,0 +1,275 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x0001E800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00068000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The size of the Cortex-M0+ application image (including MCU boot header area) +#define FLASH_CM0P_SIZE 0x10000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct new file mode 100644 index 0000000000..c4c5586db1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -0,0 +1,260 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x000DE800 +; Flash +#define FLASH_START 0x100E0000 +#define FLASH_SIZE 0x00070000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct new file mode 100644 index 0000000000..82312016fe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -0,0 +1,275 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4_dual.sct +;* \version 2.90.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08001800 +#define RAM_SIZE 0x000DE800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x000E8000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The size of the Cortex-M0+ application image (including MCU boot header area) +#define FLASH_CM0P_SIZE 0x10000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s new file mode 100644 index 0000000000..dd04a07d30 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s @@ -0,0 +1,645 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s new file mode 100644 index 0000000000..4d54e8bed1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s @@ -0,0 +1,708 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT scb_9_interrupt_IRQHandler [WEAK] + EXPORT scb_10_interrupt_IRQHandler [WEAK] + EXPORT scb_11_interrupt_IRQHandler [WEAK] + EXPORT scb_12_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] + EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +scb_9_interrupt_IRQHandler +scb_10_interrupt_IRQHandler +scb_11_interrupt_IRQHandler +scb_12_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dmac_2_IRQHandler +cpuss_interrupts_dmac_3_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_0_interrupt_i2s_IRQHandler +audioss_0_interrupt_pdm_IRQHandler +audioss_1_interrupt_i2s_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +sdhc_1_interrupt_wakeup_IRQHandler +sdhc_1_interrupt_general_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s new file mode 100644 index 0000000000..ddc59d4e74 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s @@ -0,0 +1,652 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT canfd_0_interrupt0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts0_0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_29_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_30_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_31_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +pass_interrupt_sar_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +canfd_0_interrupt0_IRQHandler +canfd_0_interrupts0_0_IRQHandler +canfd_0_interrupts1_0_IRQHandler +cpuss_interrupts_dw1_29_IRQHandler +cpuss_interrupts_dw1_30_IRQHandler +cpuss_interrupts_dw1_31_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s new file mode 100644 index 0000000000..edd9cbab16 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s @@ -0,0 +1,659 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctbs_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_0_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_1_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_0_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_1_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_256_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_257_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_258_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_259_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_260_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_261_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_262_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_263_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT canfd_0_interrupt0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts0_0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_29_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_30_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_31_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_29_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +pass_interrupt_sar_0_IRQHandler +pass_interrupt_sar_1_IRQHandler +pass_interrupt_ctbs_IRQHandler +pass_interrupt_fifo_0_IRQHandler +pass_interrupt_fifo_1_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_256_IRQHandler +tcpwm_0_interrupts_257_IRQHandler +tcpwm_0_interrupts_258_IRQHandler +tcpwm_0_interrupts_259_IRQHandler +tcpwm_0_interrupts_260_IRQHandler +tcpwm_0_interrupts_261_IRQHandler +tcpwm_0_interrupts_262_IRQHandler +tcpwm_0_interrupts_263_IRQHandler +pass_interrupt_dacs_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +canfd_0_interrupt0_IRQHandler +canfd_0_interrupts0_0_IRQHandler +canfd_0_interrupts1_0_IRQHandler +cpuss_interrupts_dw1_29_IRQHandler +cpuss_interrupts_dw1_30_IRQHandler +cpuss_interrupts_dw1_31_IRQHandler +cpuss_interrupts_dw0_29_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4.mk new file mode 100644 index 0000000000..74380368f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4.mk @@ -0,0 +1,60 @@ +################################################################################ +# \file cy8c6xx4_cm4.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10000000 +export RAM_VECT_BASE_CM4 := 0x08000000 +export VECT_SIZE_CM4 := 0x000002FC +export TEXT_BASE_CM4 := 0x100002FC +export TEXT_SIZE_CM4 := 0x00040000 +export RAM_BASE_CM4 := 0x080002FC +export RAM_SIZE_CM4 := 0x0001F780 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk new file mode 100644 index 0000000000..492ae0352b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xx4_cm4_dual.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x00000080 +export TEXT_BASE_CM0P := 0x10000080 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x08000080 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x000002FC +export TEXT_BASE_CM4 := 0x100022FC +export TEXT_SIZE_CM4 := 0x0003E000 +export RAM_BASE_CM4 := 0x080022FC +export RAM_SIZE_CM4 := 0x0001D800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4.mk new file mode 100644 index 0000000000..542ba3b895 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4.mk @@ -0,0 +1,60 @@ +################################################################################ +# \file cy8c6xx5_cm4.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10000000 +export RAM_VECT_BASE_CM4 := 0x08000000 +export VECT_SIZE_CM4 := 0x000002F8 +export TEXT_BASE_CM4 := 0x100002F8 +export TEXT_SIZE_CM4 := 0x00080000 +export RAM_BASE_CM4 := 0x080002F8 +export RAM_SIZE_CM4 := 0x0003F780 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk new file mode 100644 index 0000000000..d031928396 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xx5_cm4_dual.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x00000080 +export TEXT_BASE_CM0P := 0x10000080 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x08000080 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x000002F8 +export TEXT_BASE_CM4 := 0x100022F8 +export TEXT_SIZE_CM4 := 0x0007E000 +export RAM_BASE_CM4 := 0x080022F8 +export RAM_SIZE_CM4 := 0x0003D800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk new file mode 100644 index 0000000000..a507d55b1c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk @@ -0,0 +1,60 @@ +################################################################################ +# \file cy8c6xx6_cm4.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10000000 +export RAM_VECT_BASE_CM4 := 0x08000000 +export VECT_SIZE_CM4 := 0x0000028C +export TEXT_BASE_CM4 := 0x1000028C +export TEXT_SIZE_CM4 := 0x00080000 +export RAM_BASE_CM4 := 0x0800028C +export RAM_SIZE_CM4 := 0x0001F780 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk new file mode 100644 index 0000000000..bd9f398670 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xx6_cm4_dual.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x000000C0 +export TEXT_BASE_CM0P := 0x100000C0 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x080000C0 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x0000028C +export TEXT_BASE_CM4 := 0x1000228C +export TEXT_SIZE_CM4 := 0x0007E000 +export RAM_BASE_CM4 := 0x0800228C +export RAM_SIZE_CM4 := 0x0001D800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk new file mode 100644 index 0000000000..de435e9a24 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk @@ -0,0 +1,60 @@ +################################################################################ +# \file cy8c6xx7_cm4.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10000000 +export RAM_VECT_BASE_CM4 := 0x08000000 +export VECT_SIZE_CM4 := 0x0000028C +export TEXT_BASE_CM4 := 0x1000028C +export TEXT_SIZE_CM4 := 0x00100000 +export RAM_BASE_CM4 := 0x0800028C +export RAM_SIZE_CM4 := 0x00047780 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk new file mode 100644 index 0000000000..33708e358e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xx7_cm4_dual.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x000000C0 +export TEXT_BASE_CM0P := 0x100000C0 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x080000C0 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x0000028C +export TEXT_BASE_CM4 := 0x1000228C +export TEXT_SIZE_CM4 := 0x000FE000 +export RAM_BASE_CM4 := 0x0800228C +export RAM_SIZE_CM4 := 0x00045800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4.mk new file mode 100644 index 0000000000..5ec325ece8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4.mk @@ -0,0 +1,60 @@ +################################################################################ +# \file cy8c6xx8_cm4.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10000000 +export RAM_VECT_BASE_CM4 := 0x08000000 +export VECT_SIZE_CM4 := 0x000002E0 +export TEXT_BASE_CM4 := 0x100002E0 +export TEXT_SIZE_CM4 := 0x00100000 +export RAM_BASE_CM4 := 0x080002E0 +export RAM_SIZE_CM4 := 0x0007F780 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk new file mode 100644 index 0000000000..efc83ac856 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xx8_cm4_dual.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x00000080 +export TEXT_BASE_CM0P := 0x10000080 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x08000080 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x000002E0 +export TEXT_BASE_CM4 := 0x100022E0 +export TEXT_SIZE_CM4 := 0x000FE000 +export RAM_BASE_CM4 := 0x080022E0 +export RAM_SIZE_CM4 := 0x0007D800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4.mk new file mode 100644 index 0000000000..d5bcb23c83 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4.mk @@ -0,0 +1,60 @@ +################################################################################ +# \file cy8c6xxa_cm4.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10000000 +export RAM_VECT_BASE_CM4 := 0x08000000 +export VECT_SIZE_CM4 := 0x000002E0 +export TEXT_BASE_CM4 := 0x100002E0 +export TEXT_SIZE_CM4 := 0x00200000 +export RAM_BASE_CM4 := 0x080002E0 +export RAM_SIZE_CM4 := 0x000FF780 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk new file mode 100644 index 0000000000..fedc6c7acf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xxa_cm4_dual.mk +# \version 2.90.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x00000080 +export TEXT_BASE_CM0P := 0x10000080 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x08000080 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x000002E0 +export TEXT_BASE_CM4 := 0x100022E0 +export TEXT_SIZE_CM4 := 0x001FE000 +export RAM_BASE_CM4 := 0x080022E0 +export RAM_SIZE_CM4 := 0x000FD800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000..75205b046d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S @@ -0,0 +1,522 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..02d2c6694a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S @@ -0,0 +1,564 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S new file mode 100644 index 0000000000..45ba41c723 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S @@ -0,0 +1,539 @@ +/**************************************************************************//** + * @file startup_psoc6_03_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S new file mode 100644 index 0000000000..34ddffcb76 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S @@ -0,0 +1,543 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + .long pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + .long pass_interrupt_ctbs_IRQHandler /* individual interrupt per CTB */ + .long 0 /* Reserved */ + .long pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + .long pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long 0 /* Reserved */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + .long tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + .long tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + .long tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + .long tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + .long tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + .long tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + .long tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + .long cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + def_irq_handler pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* individual interrupt per CTB */ + def_irq_handler pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + def_irq_handler pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + def_irq_handler tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + def_irq_handler tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + def_irq_handler tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + def_irq_handler tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + def_irq_handler tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + def_irq_handler tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + def_irq_handler tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + def_irq_handler cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4.ld new file mode 100644 index 0000000000..bf4cbc6c6c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4.ld @@ -0,0 +1,405 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x1F780 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x40000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text : + { + /* Cortex-M4 flash vector table */ + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld new file mode 100644 index 0000000000..3c046dd08e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld @@ -0,0 +1,427 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x1D800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x40000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4.ld new file mode 100644 index 0000000000..7b26f2f0ae --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cy8c6xx5_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x3F780 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text : + { + /* Cortex-M4 flash vector table */ + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld new file mode 100644 index 0000000000..2c0be16355 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -0,0 +1,442 @@ +/***************************************************************************//** +* \file cy8c6xx5_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x3D800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld new file mode 100644 index 0000000000..92ee7b9ae3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cy8c6xx6_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x1F780 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text : + { + /* Cortex-M4 flash vector table */ + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld new file mode 100644 index 0000000000..4daef45948 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld @@ -0,0 +1,442 @@ +/***************************************************************************//** +* \file cy8c6xx6_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x1D800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00080000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld new file mode 100644 index 0000000000..6c4de726a0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x47780 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text : + { + /* Cortex-M4 flash vector table */ + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000000..0a083018d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,442 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4.ld new file mode 100644 index 0000000000..eec3c9b4b8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cy8c6xx8_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x7F780 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text : + { + /* Cortex-M4 flash vector table */ + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld new file mode 100644 index 0000000000..9a6a8a7bbf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld @@ -0,0 +1,442 @@ +/***************************************************************************//** +* \file cy8c6xx8_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x7D800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4.ld new file mode 100644 index 0000000000..ddaebd34d9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0xFF780 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text : + { + /* Cortex-M4 flash vector table */ + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld new file mode 100644 index 0000000000..b9dc4ef605 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -0,0 +1,442 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld new file mode 100644 index 0000000000..a75a1dcd00 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld @@ -0,0 +1,407 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = 0x08001800, LENGTH = 0x1E800 + flash (rx) : ORIGIN = 0x10020000, LENGTH = 0x20000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld new file mode 100644 index 0000000000..fcf147083b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld @@ -0,0 +1,424 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* The size of the Cortex-M0+ application image (including MCU boot header area) */ +FLASH_CM0P_SIZE = 0x10000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08001800, LENGTH = 0x1E800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x30000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld new file mode 100644 index 0000000000..c7d8a84a71 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -0,0 +1,422 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = 0x08001800, LENGTH = 0x1E800 + flash (rx) : ORIGIN = 0x10060000, LENGTH = 0x30000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld new file mode 100644 index 0000000000..efe451f7ae --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -0,0 +1,439 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* The size of the Cortex-M0+ application image (including MCU boot header area) */ +FLASH_CM0P_SIZE = 0x10000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08001800, LENGTH = 0x1E800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x68000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld new file mode 100644 index 0000000000..59b097811c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -0,0 +1,422 @@ +/***************************************************************************//** +* \file cyb06xxa_cm4.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = 0x08001800, LENGTH = 0xDE800 + flash (rx) : ORIGIN = 0x100E0000, LENGTH = 0x70000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld new file mode 100644 index 0000000000..1502446983 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld @@ -0,0 +1,439 @@ +/***************************************************************************//** +* \file cyb06xxa_cm4_dual.ld +* \version 2.90.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* The size of the Cortex-M0+ application image (including MCU boot header area) */ +FLASH_CM0P_SIZE = 0x10000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08001800, LENGTH = 0xDE800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0xE8000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000..7f13728750 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,655 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + bl main + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..3eb9dab08f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + bl main + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S new file mode 100644 index 0000000000..2a8e8b440f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S @@ -0,0 +1,672 @@ +/**************************************************************************//** + * @file startup_psoc6_03_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + bl main + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S new file mode 100644 index 0000000000..ecdfd4d7a6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S @@ -0,0 +1,676 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + .long pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + .long pass_interrupt_ctbs_IRQHandler /* individual interrupt per CTB */ + .long 0 /* Reserved */ + .long pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + .long pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long 0 /* Reserved */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + .long tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + .long tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + .long tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + .long tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + .long tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + .long tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + .long tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + .long cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + bl main + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + def_irq_handler pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* individual interrupt per CTB */ + def_irq_handler pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + def_irq_handler pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + def_irq_handler tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + def_irq_handler tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + def_irq_handler tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + def_irq_handler tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + def_irq_handler tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + def_irq_handler tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + def_irq_handler tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + def_irq_handler cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4.icf new file mode 100644 index 0000000000..6cbc43d19b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4.icf @@ -0,0 +1,226 @@ +/******************************************************************************* +* \file cy8c6xx4_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F77F; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1003FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; + +define block RO { first section .intvec, readonly }; + +define block cy_xip { section .cy_xip }; + + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf new file mode 100644 index 0000000000..3881175dd4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf @@ -0,0 +1,240 @@ +/******************************************************************************* +* \file cy8c6xx4_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1003FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4.icf new file mode 100644 index 0000000000..fa7281218e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4.icf @@ -0,0 +1,233 @@ +/******************************************************************************* +* \file cy8c6xx5_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0803F77F; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; + +define block RO { first section .intvec, readonly }; + +define block cy_xip { section .cy_xip }; + + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf new file mode 100644 index 0000000000..3436ec7aa0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -0,0 +1,247 @@ +/******************************************************************************* +* \file cy8c6xx5_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0803F7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf new file mode 100644 index 0000000000..a034c84de8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf @@ -0,0 +1,233 @@ +/******************************************************************************* +* \file cy8c6xx6_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F77F; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; + +define block RO { first section .intvec, readonly }; + +define block cy_xip { section .cy_xip }; + + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf new file mode 100644 index 0000000000..bc00b81b4b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf @@ -0,0 +1,247 @@ +/******************************************************************************* +* \file cy8c6xx6_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00080000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf new file mode 100644 index 0000000000..f3e0592d57 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf @@ -0,0 +1,233 @@ +/******************************************************************************* +* \file cy8c6xx7_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0804777F; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; + +define block RO { first section .intvec, readonly }; + +define block cy_xip { section .cy_xip }; + + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000000..0d60d85c29 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,247 @@ +/******************************************************************************* +* \file cy8c6xx7_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4.icf new file mode 100644 index 0000000000..8357e49dcd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4.icf @@ -0,0 +1,233 @@ +/******************************************************************************* +* \file cy8c6xx8_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0807F77F; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; + +define block RO { first section .intvec, readonly }; + +define block cy_xip { section .cy_xip }; + + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf new file mode 100644 index 0000000000..c4be79ea5d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf @@ -0,0 +1,247 @@ +/******************************************************************************* +* \file cy8c6xx8_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0807F7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4.icf new file mode 100644 index 0000000000..aab365f3d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4.icf @@ -0,0 +1,233 @@ +/******************************************************************************* +* \file cy8c6xxa_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + */ + +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF77F; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; + +define block RO { first section .intvec, readonly }; + +define block cy_xip { section .cy_xip }; + + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf new file mode 100644 index 0000000000..6f75405a10 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -0,0 +1,247 @@ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf new file mode 100644 index 0000000000..55e716490c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf @@ -0,0 +1,224 @@ +/******************************************************************************* +* \file cyb06xx5_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08001800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801FFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10020000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1003FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf new file mode 100644 index 0000000000..2cdef9e5e1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf @@ -0,0 +1,237 @@ +/******************************************************************************* +* \file cyb06xx5_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08001800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801FFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1002FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + +/* The size of the Cortex-M0+ application image (including MCU boot header area) */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + FLASH_CM0P_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf new file mode 100644 index 0000000000..cb29e681c0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -0,0 +1,231 @@ +/******************************************************************************* +* \file cyb06xx7_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08001800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801FFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10060000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1008FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf new file mode 100644 index 0000000000..da9b2b6fe3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -0,0 +1,244 @@ +/******************************************************************************* +* \file cyb06xx7_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08001800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801FFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10067FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + +/* The size of the Cortex-M0+ application image (including MCU boot header area) */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + FLASH_CM0P_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf new file mode 100644 index 0000000000..4a7daf21dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -0,0 +1,231 @@ +/******************************************************************************* +* \file cyb06xxa_cm4.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08001800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080DFFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x100E0000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1014FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf new file mode 100644 index 0000000000..1d2e817fd5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf @@ -0,0 +1,244 @@ +/******************************************************************************* +* \file cyb06xxa_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08001800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080DFFFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100E7FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + +/* The size of the Cortex-M0+ application image (including MCU boot header area) */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + FLASH_CM0P_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s new file mode 100644 index 0000000000..678f9c6aae --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s @@ -0,0 +1,1154 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s new file mode 100644 index 0000000000..8f1e4a57e5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s @@ -0,0 +1,1280 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK scb_9_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_9_interrupt_IRQHandler + B scb_9_interrupt_IRQHandler + + PUBWEAK scb_10_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_10_interrupt_IRQHandler + B scb_10_interrupt_IRQHandler + + PUBWEAK scb_11_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_11_interrupt_IRQHandler + B scb_11_interrupt_IRQHandler + + PUBWEAK scb_12_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_12_interrupt_IRQHandler + B scb_12_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_2_IRQHandler + B cpuss_interrupts_dmac_2_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_3_IRQHandler + B cpuss_interrupts_dmac_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_0_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_i2s_IRQHandler + B audioss_0_interrupt_i2s_IRQHandler + + PUBWEAK audioss_0_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_pdm_IRQHandler + B audioss_0_interrupt_pdm_IRQHandler + + PUBWEAK audioss_1_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_1_interrupt_i2s_IRQHandler + B audioss_1_interrupt_i2s_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_wakeup_IRQHandler + B sdhc_1_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_1_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_general_IRQHandler + B sdhc_1_interrupt_general_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s new file mode 100644 index 0000000000..1d212b8638 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s @@ -0,0 +1,1131 @@ +;/**************************************************************************//** +; * @file startup_psoc6_03_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK canfd_0_interrupt0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupt0_IRQHandler + B canfd_0_interrupt0_IRQHandler + + PUBWEAK canfd_0_interrupts0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts0_0_IRQHandler + B canfd_0_interrupts0_0_IRQHandler + + PUBWEAK canfd_0_interrupts1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts1_0_IRQHandler + B canfd_0_interrupts1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_29_IRQHandler + B cpuss_interrupts_dw1_29_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_30_IRQHandler + B cpuss_interrupts_dw1_30_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_31_IRQHandler + B cpuss_interrupts_dw1_31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s new file mode 100644 index 0000000000..539a811e2e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s @@ -0,0 +1,1147 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctbs_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK pass_interrupt_sar_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_0_IRQHandler + B pass_interrupt_sar_0_IRQHandler + + PUBWEAK pass_interrupt_sar_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_1_IRQHandler + B pass_interrupt_sar_1_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK pass_interrupt_fifo_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_0_IRQHandler + B pass_interrupt_fifo_0_IRQHandler + + PUBWEAK pass_interrupt_fifo_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_1_IRQHandler + B pass_interrupt_fifo_1_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_256_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_256_IRQHandler + B tcpwm_0_interrupts_256_IRQHandler + + PUBWEAK tcpwm_0_interrupts_257_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_257_IRQHandler + B tcpwm_0_interrupts_257_IRQHandler + + PUBWEAK tcpwm_0_interrupts_258_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_258_IRQHandler + B tcpwm_0_interrupts_258_IRQHandler + + PUBWEAK tcpwm_0_interrupts_259_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_259_IRQHandler + B tcpwm_0_interrupts_259_IRQHandler + + PUBWEAK tcpwm_0_interrupts_260_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_260_IRQHandler + B tcpwm_0_interrupts_260_IRQHandler + + PUBWEAK tcpwm_0_interrupts_261_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_261_IRQHandler + B tcpwm_0_interrupts_261_IRQHandler + + PUBWEAK tcpwm_0_interrupts_262_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_262_IRQHandler + B tcpwm_0_interrupts_262_IRQHandler + + PUBWEAK tcpwm_0_interrupts_263_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_263_IRQHandler + B tcpwm_0_interrupts_263_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK canfd_0_interrupt0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupt0_IRQHandler + B canfd_0_interrupt0_IRQHandler + + PUBWEAK canfd_0_interrupts0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts0_0_IRQHandler + B canfd_0_interrupts0_0_IRQHandler + + PUBWEAK canfd_0_interrupts1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts1_0_IRQHandler + B canfd_0_interrupts1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_29_IRQHandler + B cpuss_interrupts_dw1_29_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_30_IRQHandler + B cpuss_interrupts_dw1_30_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_31_IRQHandler + B cpuss_interrupts_dw1_31_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_29_IRQHandler + B cpuss_interrupts_dw0_29_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c new file mode 100644 index 0000000000..1d24a9ab1a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c @@ -0,0 +1,400 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.90.1 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default FastClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) + +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + /* Initialize Protected Register Access driver */ + Cy_PRA_Init(); +#endif /* defined(CY_DEVICE_SECURE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); + + if (0UL != locHf0Clock) + { + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; + } +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/system_psoc6.h new file mode 100644 index 0000000000..6db0b46159 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/system_psoc6.h @@ -0,0 +1,725 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.90.1 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* ARM Compiler\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.sct', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00002000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00002000 +* \endcode +* - 'xx_cm4_dual.sct', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \note Correct operation of malloc and related functions depends on the working +* implementation of the 'sbrk' function. Newlib-nano (default C runtime library +* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that +* doesn't check for heap and stack collisions during excessive memory allocations. +* To ensure the heap always remains within the range defined by __HeapBase and +* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: +* \snippet startup/snippet/main.c snippet_sbrk +* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include +* clib-support library that provides newlib-compatible implementations of +* 'sbrk', '__malloc_lock' and '__malloc_unlock': +*
+* https://github.com/cypresssemiconductorco/clib-support. +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler +* - Editing source code files\n +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.90.1Updated \ref group_system_config_heap_stack_config_gcc section with the note +* on the dynamic memory allocation for ARM GCC.Documentation update.
Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro.Improve configuration flexibility.
Updated attribute usage for the linker section placement in CM0+ startup codeEnhancement based on usability feedback.
Renamed the '.cy_xip' linker script region as 'cy_xip'Enable access to the XIP region start/end addresses from the C code.
2.90Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.Flash allocation adjustment.
2.80Updated linker scripts for PSoC 64 Secure MCU devices.Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates +* in accordance with the PSoC 64 Secure Boot SDK policies.
Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.Provided support for SysPM driver updates.
Updated the linker scripts.Reserved FLASH area for the MCU boot headers.
Added System Pipe initialization for all devices. Improved PDL usability according to user experience.
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. Defect fixing.
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +/* + * Include optional application-specific configuration header. + * + * For example, custom system_psoc6_config.h can be included here + * by adding the below macro definition to the build system: + * DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"' + */ +#if defined(CY_SYSTEM_PSOC6_CONFIG) +#include CY_SYSTEM_PSOC6_CONFIG +#endif + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +#if defined(__ARMCC_VERSION) + extern void SystemInit(void) __attribute__((constructor)); +#else + extern void SystemInit(void); +#endif /* (__ARMCC_VERSION) */ + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macros. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cdn_errno.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cdn_errno.h deleted file mode 100644 index b636a537c8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cdn_errno.h +++ /dev/null @@ -1,92 +0,0 @@ -/********************************************************************** - * Copyright (C) 2014-2015 Cadence Design Systems, Inc. - * All rights reserved worldwide. - *********************************************************************** - * cdn_errno.h - * Cadence error codes - ***********************************************************************/ - -#ifndef __INCLUDE_CDN_ERRNO_H__ -#define __INCLUDE_CDN_ERRNO_H__ - -#ifndef ERRNO_H_NOT_PRESENT -#include -#endif //ERRNO_H_NOT_PRESENT - -#ifndef EOK -#define EOK 0 /* no error */ -#endif //EOK - -#ifndef EPERM -#define EPERM 1 /* Operation not permitted */ -#endif //EPERM - -#ifndef ENOENT -#define ENOENT 2 /* No such file or directory */ -#endif //ENOENT - -#ifndef EIO -#define EIO 5 /* I/O error */ -#endif //EIO - -#ifndef ENOEXEC -#define ENOEXEC 8 /* Exec format error */ -#endif //ENOEXEC - -#ifndef EAGAIN -#define EAGAIN 11 /* Try again */ -#endif //EAGAIN - -#ifndef ENOMEM -#define ENOMEM 12 /* Out of memory */ -#endif //ENOMEM - -#ifndef EFAULT -#define EFAULT 14 /* Bad address */ -#endif //EFAULT - -#ifndef EBUSY -#define EBUSY 16 /* Device or resource busy */ -#endif //EBUSY - -#ifndef EINVAL -#define EINVAL 22 /* Invalid argument */ -#endif //EINVAL - -#ifndef ENOSPC -#define ENOSPC 28 /* No space left on device */ -#endif //ENOSPC - -#ifndef EBADSLT -#define EBADSLT 57 /* Invalid slot */ -#endif //EBADSLT - -#ifndef EPROTO -#define EPROTO 71 /* Protocol error */ -#endif //EPROTO - -#ifndef EOVERFLOW -#define EOVERFLOW 75 /* Value too large for defined data type */ -#endif //EOVERFLOW - -#ifndef EOPNOTSUPP -#define EOPNOTSUPP 95 /* Operation not supported */ -#endif //EOPNOTSUPP - -#ifndef EINPROGRESS -#define EINPROGRESS 115 /* Operation now in progress */ -#endif //EINPROGRESS - -#ifndef EDQUOT -#define EDQUOT 122 /* Quota exceeded */ -#endif //EDQUOT - -#ifndef ENOTSUP -#define ENOTSUP EOPNOTSUPP -#endif //ENOTSUP - -#ifndef ECANCELED -#define ECANCELED 126 /* Cancelled */ -#endif //ECANCELED - -#endif //__INCLUDE_CDN_ERRNO_H__ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cdn_stdint.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cdn_stdint.h deleted file mode 100644 index 50f626f784..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cdn_stdint.h +++ /dev/null @@ -1,24 +0,0 @@ -#include - -/* NOTE - The driver uses fixed width types as defined in C99 - - If not provided by your environment, these are typical definitions for the - * fixed width types used in the driver, and should be provided here. - * typedef signed char int8_t - * typedef unsigned char uint8_t - * typedef signed short int16_t - * typedef unsigned short uint16_t - * typedef signed long int int32_t - * typedef unsigned long int uint32_t - * typedef signed long long int int64_t - * typedef unsigned long long int uint64_t - * typedef int32_t intptr_t - * typedef uint32_t uintptr_t - - * These definitions are for a 32bit system with 32bit int, and should be adjusted - * for your actual target system and toolchain. - - Under Linux, these will be available in: - #include - -*/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cedi.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cedi.h deleted file mode 100644 index a61bb4bd78..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cedi.h +++ /dev/null @@ -1,3549 +0,0 @@ -/********************************************************************** - * Copyright (C) 2013-2015 Cadence Design Systems, Inc. - * All rights reserved worldwide. - ********************************************************************** - * WARNING: This file is auto-generated using api-generator utility. - * Do not edit it manually. - ********************************************************************** - * Cadence Core Driver for the Cadence Ethernet MAC (EMAC) core. This - * header file lists the API providing a HAL (hardware abstraction - * layer) interface for the EMAC core, GEM_GXL part no. IP7014 - **********************************************************************/ - -#ifndef _CEDI_H_ -#define _CEDI_H_ - -#include "cdn_stdint.h" - -/** @defgroup ConfigInfo Configuration and Hardware Operation Information - * The following definitions specify the driver operation environment that - * is defined by hardware configuration or client code. These defines are - * located in the header file of the core driver. - * @{ - */ - -/********************************************************************** -* Defines -**********************************************************************/ -/** - * General config. - * @xmlonly 4 REMOVE_ME @endxmlonly - * Max number of Rx priority queues supported by driver -*/ -#define CEDI_MAX_RX_QUEUES (16) - -/** Max number of Tx priority queues supported by driver */ -#define CEDI_MAX_TX_QUEUES (16) - -/** Allows en/disabling of events on all priority queues */ -#define CEDI_ALL_QUEUES (255) - -/** Max size of each Rx buffer descriptor list */ -#define CEDI_MAX_RBQ_LENGTH (1000) - -/** max size of each Tx buffer descriptor list */ -#define CEDI_MAX_TBQ_LENGTH (1000) - -/** Bit-flags to specify DMA endianism. @xmlonly 1 REMOVE_ME @endxmlonly */ -#define CEDI_END_SWAP_DESC (0x01) - -#define CEDI_END_SWAP_DATA (0x02) - -/** Bit-flags to specify DMA config register bits 24-27; see EMAC User Guide for details. @xmlonly 3 REMOVE_ME @endxmlonly */ -#define CEDI_CFG_DMA_DISC_RXP (0x01) - -#define CEDI_CFG_DMA_FRCE_RX_BRST (0x02) - -#define CEDI_CFG_DMA_FRCE_TX_BRST (0x04) - -/** - * Bit-flags to specify checksum offload operation. - * @xmlonly 1 REMOVE_ME @endxmlonly -*/ -#define CEDI_CFG_CHK_OFF_TX (0x01) - -#define CEDI_CFG_CHK_OFF_RX (0x02) - -/** - * Bit-flags for selecting interrupts to enable/disable/read. - * @xmlonly 28 REMOVE_ME @endxmlonly - * Frame has been transmitted successfully -*/ -#define CEDI_EV_TX_COMPLETE (0x00000001) - -/** Used bit set has been read in Tx descriptor list */ -#define CEDI_EV_TX_USED_READ (0x00000002) - -/** Tx underrun */ -#define CEDI_EV_TX_UNDERRUN (0x00000004) - -/** Retry limit exceeded or late collision */ -#define CEDI_EV_TX_RETRY_EX_LATE_COLL (0x00000008) - -/** Tx frame corruption */ -#define CEDI_EV_TX_FR_CORRUPT (0x00000010) - -/** Frame received successfully and stored */ -#define CEDI_EV_RX_COMPLETE (0x00000020) - -/** Used bit set has been read in Rx descriptor list */ -#define CEDI_EV_RX_USED_READ (0x00000040) - -/** Rx overrun error */ -#define CEDI_EV_RX_OVERRUN (0x00000080) - -/** DMA hresp not OK */ -#define CEDI_EV_HRESP_NOT_OK (0x00000100) - -/** PCS auto-negotiation link partner page received */ -#define CEDI_EV_PCS_LP_PAGE_RX (0x00000200) - -/** PCS auto-negotiation has completed */ -#define CEDI_EV_PCS_AN_COMPLETE (0x00000400) - -/** Link status change detected by PCS */ -#define CEDI_EV_PCS_LINK_CHANGE_DET (0x00000800) - -/** Pause frame transmitted */ -#define CEDI_EV_PAUSE_FRAME_TX (0x00001000) - -/** Pause time reaches zero or zeroq pause frame received */ -#define CEDI_EV_PAUSE_TIME_ZERO (0x00002000) - -/** Pause frame with non-zero quantum received */ -#define CEDI_EV_PAUSE_NZ_QU_RX (0x00004000) - -/** PTP delay_req frame transmitted */ -#define CEDI_EV_PTP_TX_DLY_REQ (0x00008000) - -/** PTP sync frame transmitted */ -#define CEDI_EV_PTP_TX_SYNC (0x00010000) - -/** PTP pdelay_req frame transmitted */ -#define CEDI_EV_PTP_TX_PDLY_REQ (0x00020000) - -/** PTP pdelay_resp frame transmitted */ -#define CEDI_EV_PTP_TX_PDLY_RSP (0x00040000) - -/** PTP delay_req frame received */ -#define CEDI_EV_PTP_RX_DLY_REQ (0x00080000) - -/** PTP sync frame received */ -#define CEDI_EV_PTP_RX_SYNC (0x00100000) - -/** PTP pdelay_req frame received */ -#define CEDI_EV_PTP_RX_PDLY_REQ (0x00200000) - -/** PTP pdelay_resp frame received */ -#define CEDI_EV_PTP_RX_PDLY_RSP (0x00400000) - -/** TSU seconds register increment */ -#define CEDI_EV_TSU_SEC_INC (0x00800000) - -/** TSU timer count match */ -#define CEDI_EV_TSU_TIME_MATCH (0x01000000) - -/** Management Frame Sent */ -#define CEDI_EV_MAN_FRAME (0x02000000) - -/** LPI indication status bit change received */ -#define CEDI_EV_LPI_CH_RX (0x04000000) - -/** Wake on LAN event received */ -#define CEDI_EV_WOL_RX (0x08000000) - -/** External input interrupt detected */ -#define CEDI_EV_EXT_INTR (0x10000000) - -/** Bit-flags for indicating functionality supported by the driver/EMAC @xmlonly 3 REMOVE_ME @endxmlonly Large Segmentation Offload */ -#define CEDI_CAP_LSO (0x00000001) - -/** Receive Side Coalescing offload */ -#define CEDI_CAP_RSC (0x00000002) - -/** Receive Side Scaling offload */ -#define CEDI_CAP_RSS (0x00000004) - -/** Bit-flags for selecting Tx Status fields to reset. @xmlonly 7 REMOVE_ME @endxmlonly */ -#define CEDI_TXS_USED_READ (0x0001) - -#define CEDI_TXS_COLLISION (0x0002) - -#define CEDI_TXS_RETRY_EXC (0x0004) - -#define CEDI_TXS_FRAME_ERR (0x0010) - -#define CEDI_TXS_TX_COMPLETE (0x0020) - -#define CEDI_TXS_UNDERRUN (0x0040) - -#define CEDI_TXS_LATE_COLL (0x0080) - -#define CEDI_TXS_HRESP_ERR (0x0100) - -/** - * Bit-flags for selecting Rx Status fields to reset. - * @xmlonly 3 REMOVE_ME @endxmlonly -*/ -#define CEDI_RXS_NO_BUFF (0x0001) - -#define CEDI_RXS_FRAME_RX (0x0002) - -#define CEDI_RXS_OVERRUN (0x0004) - -#define CEDI_RXS_HRESP_ERR (0x0008) - -/** - * Transmit IP/TCP/UDP checksum generation offload errors - * reported in Tx descriptor status. - * @xmlonly 7 REMOVE_ME @endxmlonly -*/ -#define CEDI_TXD_CHKOFF_NO_ERROR (0) - -#define CEDI_TXD_CHKOFF_VLAN_HDR_ERR (1) - -#define CEDI_TXD_CHKOFF_SNAP_HDR_ERR (2) - -#define CEDI_TXD_CHKOFF_INVALID_IP (3) - -#define CEDI_TXD_CHKOFF_INVALID_PKT (4) - -#define CEDI_TXD_CHKOFF_PKT_FRAGMENT (5) - -#define CEDI_TXD_CHKOFF_NON_TCP_UDP (6) - -#define CEDI_TXD_CHKOFF_PREM_END_PKT (7) - -/** - * Bit-flags to control queueTxBuf/qTxBuf behaviour. - * @xmlonly 5 REMOVE_ME @endxmlonly - * Indicates last buffer in frame -*/ -#define CEDI_TXB_LAST_BUFF (0x01) - -/** EMAC will not calculate & insert frame CRC. */ -#define CEDI_TXB_NO_AUTO_CRC (0x02) - -/** - * Prevents transmission being started automatically - * after queueing the last buffer in the frame; - * has no effect if CEDI_TXB_LAST_BUFF not also present. -*/ -#define CEDI_TXB_NO_AUTO_START (0x04) - -/** select TCP encapsulation for the current frame - must be set for first and second buffers in frame, ie header and first data buffers */ -#define CEDI_TXB_TCP_ENCAP (0x08) - -/** select UFO fragmentation for the current frame - only relevant for first buffer in frame, which includes the header only; Ignored if CEDI_TXB_TCP_ENCAP is set. */ -#define CEDI_TXB_UDP_ENCAP (0x10) - -/** - * select auto sequence-number generation, based on the current value of - * the EMAC sequence number counter for this stream -*/ -#define CEDI_TXB_TSO_AUTO_SEQ (0x20) - -/** Max length accepted by queueTxBuf */ -#define CEDI_TXD_LMASK ((1 << 14) - 1) - -/** TCP flags (standard, some used to control RSC) @xmlonly 5 REMOVE_ME @endxmlonly */ -#define CEDI_TCP_FLG_FIN (0x0001) - -#define CEDI_TCP_FLG_SYN (0x0002) - -#define CEDI_TCP_FLG_RST (0x0004) - -#define CEDI_TCP_FLG_PSH (0x0008) - -#define CEDI_TCP_FLG_ACK (0x0010) - -#define CEDI_TCP_FLG_URG (0x0020) - -/** - * Bit-flags to control MDIO write/read operations. - * @xmlonly 2 REMOVE_ME @endxmlonly -*/ -#define CEDI_MDIO_FLG_CLAUSE_45 (0x01) - -#define CEDI_MDIO_FLG_SET_ADDR (0x02) - -#define CEDI_MDIO_FLG_INC_ADDR (0x04) - -/** - * PFC Priority based pause frame support: - * Maximum number of quantum priorities supported. -*/ -#define CEDI_QUANTA_PRIORITY_MAX 8 - -/** - * @} - */ - -#define CEDI_EVSET_ALL_Q0_EVENTS (CEDI_EV_TX_COMPLETE|CEDI_EV_TX_USED_READ| CEDI_EV_TX_UNDERRUN|CEDI_EV_TX_FR_CORRUPT| CEDI_EV_TX_RETRY_EX_LATE_COLL| CEDI_EV_RX_COMPLETE|CEDI_EV_RX_USED_READ|CEDI_EV_RX_OVERRUN|CEDI_EV_HRESP_NOT_OK| CEDI_EV_PCS_LP_PAGE_RX|CEDI_EV_PCS_AN_COMPLETE|CEDI_EV_PCS_LINK_CHANGE_DET| CEDI_EV_PAUSE_FRAME_TX|CEDI_EV_PAUSE_TIME_ZERO|CEDI_EV_PAUSE_NZ_QU_RX| CEDI_EV_PTP_TX_DLY_REQ|CEDI_EV_PTP_TX_SYNC|CEDI_EV_PTP_TX_PDLY_REQ| CEDI_EV_PTP_TX_PDLY_RSP|CEDI_EV_PTP_RX_DLY_REQ|CEDI_EV_PTP_RX_SYNC| CEDI_EV_PTP_RX_PDLY_REQ|CEDI_EV_PTP_RX_PDLY_RSP| CEDI_EV_TSU_SEC_INC|CEDI_EV_TSU_TIME_MATCH| CEDI_EV_MAN_FRAME|CEDI_EV_LPI_CH_RX|CEDI_EV_WOL_RX| CEDI_EV_EXT_INTR ) - -#define CEDI_EVSET_ALL_QN_EVENTS (CEDI_EV_TX_COMPLETE| CEDI_EV_TX_RETRY_EX_LATE_COLL| CEDI_EV_TX_FR_CORRUPT|CEDI_EV_RX_COMPLETE| CEDI_EV_RX_USED_READ|CEDI_EV_HRESP_NOT_OK) - -#define CEDI_EVSET_TX_RX_EVENTS (CEDI_EV_TX_COMPLETE|CEDI_EV_TX_USED_READ|CEDI_EV_TX_UNDERRUN| CEDI_EV_TX_RETRY_EX_LATE_COLL| CEDI_EV_TX_FR_CORRUPT|CEDI_EV_RX_COMPLETE| CEDI_EV_RX_USED_READ|CEDI_EV_RX_OVERRUN| CEDI_EV_HRESP_NOT_OK) - - -/** @defgroup DataStructure Dynamic Data Structures - * This section defines the data structures used by the driver to provide - * hardware information, modification and dynamic operation of the driver. - * These data structures are defined in the header file of the core driver - * and utilized by the API. - * @{ - */ - -/********************************************************************** - * Forward declarations - **********************************************************************/ -struct CEDI_Config; -struct CEDI_SysReq; -struct CEDI_TxStatus; -struct CEDI_RxStatus; -struct CEDI_BuffAddr; -struct CEDI_TimeStampData; -struct CEDI_TxDescData; -struct CEDI_TxDescStat; -struct CEDI_RxDescData; -struct CEDI_RxDescStat; -struct CEDI_qTxBufParams; -struct CEDI_FrameSize; -struct CEDI_MacAddress; -struct CEDI_Statistics; -struct CEDI_NumScreeners; -struct CEDI_T1Screen; -struct CEDI_T2Screen; -struct CEDI_T2Compare; -struct CEDI_1588TimerVal; -struct CEDI_TsuTimerVal; -struct CEDI_TimerIncrement; -struct CEDI_AnAdvPage; -struct CEDI_defLpAbility; -struct CEDI_sgmLpAbility; -union CEDI_LpAbility; -struct CEDI_LpAbilityPage; -struct CEDI_AnNextPage; -struct CEDI_LpNextPage; -union CEDI_LpPage; -struct CEDI_LpPageRx; -struct CEDI_NetAnStatus; -struct CEDI_WakeOnLanReg; -struct CEDI_LpiStats; -struct CEDI_DesignCfg; -struct CEDI_Callbacks; - -/********************************************************************** - * Enumerations - **********************************************************************/ -/** @defgroup DataStructure Dynamic Data Structures This section defines the data structures used by the driver to provide hardware information, modification, and dynamic operation of the driver. These data structures are defined in the header file of the core driver and utilized by the API. @{ */ -typedef enum -{ - CEDI_DMA_BUS_WIDTH_32 = 0, - CEDI_DMA_BUS_WIDTH_64 = 1, - CEDI_DMA_BUS_WIDTH_128 = 2, -} CEDI_BusWidth; - -typedef enum -{ - CEDI_DMA_DBUR_LEN_1 = 0, - CEDI_DMA_DBUR_LEN_4 = 1, - CEDI_DMA_DBUR_LEN_8 = 2, - CEDI_DMA_DBUR_LEN_16 = 3, -} CEDI_DmaDatBLen; - -typedef enum -{ - CEDI_MDC_DIV_BY_8 = 0, - CEDI_MDC_DIV_BY_16 = 1, - CEDI_MDC_DIV_BY_32 = 2, - CEDI_MDC_DIV_BY_48 = 3, - CEDI_MDC_DIV_BY_64 = 4, - CEDI_MDC_DIV_BY_96 = 5, - CEDI_MDC_DIV_BY_128 = 6, - CEDI_MDC_DIV_BY_224 = 7, -} CEDI_MdcClkDiv; - -typedef enum -{ - CEDI_MDIO_DEV_PMD_PMA = 1, - CEDI_MDIO_DEV_WIS = 2, - CEDI_MDIO_DEV_PCS = 3, - CEDI_MDIO_DEV_PHY_XS = 4, - CEDI_MDIO_DEV_DTE_XS = 5, -} CEDI_MdioDevType; - -typedef enum -{ - CEDI_IFSP_10M_MII = 0, - CEDI_IFSP_100M_MII = 1, - CEDI_IFSP_1000M_GMII = 2, - CEDI_IFSP_10M_SGMII = 3, - CEDI_IFSP_100M_SGMII = 4, - CEDI_IFSP_1000M_SGMII = 5, - CEDI_IFSP_1000BASE_X = 6, -} CEDI_Interface; - -typedef enum -{ - CEDI_TX_TS_DISABLED = 0, - CEDI_TX_TS_PTP_EVENT_ONLY = 1, - CEDI_TX_TS_PTP_ALL = 2, - CEDI_TX_TS_ALL = 3, -} CEDI_TxTsMode; - -typedef enum -{ - CEDI_RX_TS_DISABLED = 0, - CEDI_RX_TS_PTP_EVENT_ONLY = 1, - CEDI_RX_TS_PTP_ALL = 2, - CEDI_RX_TS_ALL = 3, -} CEDI_RxTsMode; - -/** Enum defining speed selection or indication */ -typedef enum -{ - CEDI_SPEED_10M = 0, - CEDI_SPEED_100M = 1, - CEDI_SPEED_1000M = 2, -} CEDI_IfSpeed; - -/** Enum defining Tx free descriptor call status */ -typedef enum -{ - CEDI_TXDATA_1ST_NOT_LAST = 0, - CEDI_TXDATA_1ST_AND_LAST = 1, - CEDI_TXDATA_MID_BUFFER = 2, - CEDI_TXDATA_LAST_BUFFER = 3, - CEDI_TXDATA_NONE_FREED = 4, -} CEDI_TxFreeDStat; - -/** Enum defining Rx data buffer read status */ -typedef enum -{ - CEDI_RXDATA_SOF_EOF = 0, - CEDI_RXDATA_SOF_ONLY = 1, - CEDI_RXDATA_NO_FLAG = 2, - CEDI_RXDATA_EOF_ONLY = 3, - CEDI_RXDATA_NODATA = 4, -} CEDI_RxRdStat; - -/** enum defining offset for screener type 2 compare values. Note the offset is applied after the specified point, e.g. T2COMP_OFF_ETYPE denotes the ethertype field, so an offset of 12 bytes from this would be the source IP address in an IP header. */ -typedef enum -{ - CEDI_T2COMP_OFF_SOF = 0, - CEDI_T2COMP_OFF_ETYPE = 1, - CEDI_T2COMP_OFF_IPHDR = 2, - CEDI_T2COMP_OFF_TCPUDP = 3, -} CEDI_T2Offset; - -/** enum defining pause capability in auto-negotiation */ -typedef enum -{ - CEDI_AN_PAUSE_CAP_NONE = 0, - CEDI_AN_PAUSE_CAP_SYM = 1, - CEDI_AN_PAUSE_CAP_ASYM = 2, - CEDI_AN_PAUSE_CAP_BOTH = 3, -} CEDI_PauseCap; - -/** enum defining loopback mode selection */ -typedef enum -{ - CEDI_NO_LOOPBACK = 0, - CEDI_LOCAL_LOOPBACK = 1, - CEDI_SERDES_LOOPBACK = 2, -} CEDI_LoopbackMode; - -/** enum defining remote fault indication by link partner in auto-negotiation */ -typedef enum -{ - CEDI_AN_REM_FLT_NONE = 0, - CEDI_AN_REM_FLT_LNK_FAIL = 1, - CEDI_AN_REM_FLT_OFFLINE = 2, - CEDI_AN_REM_FLT_AN_ERR = 3, -} CEDI_RemoteFault; - -/********************************************************************** - * Callbacks - **********************************************************************/ -/** - * Reports PHY Management frame tx complete. - * Params: read = 1 if a read operation, = 0 if a write operation, and - * readData - data from the PHY, if read operation. -*/ -typedef void (*CEDI_CbPhyManComplete)(void* pD, uint8_t read, uint16_t readData); - -/** - * Reports Tx completed / Tx used bit read events. - * Params: event - indicates two types of event, which are OR'd together if both - * occurred (CEDI_EV_TX_COMPLETE: frame has been transmitted successfully, - * and CEDI_EV_TX_USED_READ: used bit set has been read in Tx descriptor list), - * and queueNum- the priority queue number (only relevant to TX_COMPLETE) - * range 0 to txQs-1. -*/ -typedef void (*CEDI_CbTxEvent)(void* pD, uint32_t event, uint8_t queueNum); - -/** - * Reports Tx errors. Params: error - indicates one or more of three - * possible events, OR'd together (CEDI_EV_TX_UNDERRUN: Tx underrun, - * CEDI_EV_TX_RETRY_EX_LATE_COLL: retry limit exceeded or late collision, - * CEDI_EV_TX_FR_CORRUPT: Tx frame corruption), and queueNum - the priority - * queue number, range 0 to txQs-1 (not relevant to TX_UNDERRUN). -*/ -typedef void (*CEDI_CbTxError)(void* pD, uint32_t error, uint8_t queueNum); - -/** - * Reports Frame Rx completed successfully. Param: queueNum - the priority - * queue number, range 0 to rxQs-1. -*/ -typedef void (*CEDI_CbRxFrame)(void* pD, uint8_t queueNum); - -/** - * Reports Rx errors. Params: error - one or more of two possible errors, - * together (CEDI_EV_RX_USED_READ: used bit set has been read in Rx descriptor - * list; CEDI_EV_RX_OVERRUN: Rx overrun error), - * and queueNum - the priority queue number, range 0 to rxQs-1. -*/ -typedef void (*CEDI_CbRxError)(void* pD, uint32_t error, uint8_t queueNum); - -/** - * Reports Hresp not OK error. Param: queueNum - number of the Tx or Rx - * queue being accessed (range 0 to rxQs-1). -*/ -typedef void (*CEDI_CbHrespError)(void* pD, uint8_t queueNum); - -/** - * Reports PCS auto-negotiation page received. Param: pageRx - pointer to a - * struct containing the link partner base or next page data. -*/ -typedef void (*CEDI_CbLpPageRx)(void* pD, struct CEDI_LpPageRx* pageRx); - -/** - * Reports PCS auto-negotiation completed. Param: netStat - pointer to a - * struct with the network resolution status. -*/ -typedef void (*CEDI_CbAnComplete)(void* pD, struct CEDI_NetAnStatus* netStat); - -/** - * Reports Link Status Changed. Param: linkState - link status: if - * auto-negotiation enabled, when =1 link is up, else link is down; - * if auto-negotiation not enabled, this will indicate the synchronisation - * status. If link status has gone down, the value will not return to 1 - * until after it has been read, therefore to see current state must - * re-read with a getLinkStatus call. -*/ -typedef void (*CEDI_CbLinkChange)(void* pD, uint8_t linkState); - -/** - * Reports TSU Event occurred. Param: event - indicates one of two events, - * OR'd together (CEDI_EV_TSU_SEC_INC: TSU seconds register increment; - * CEDI_EV_TSU_TIME_MATCH: TSU timer count match). -*/ -typedef void (*CEDI_CbTsuEvent)(void* pD, uint32_t event); - -/** - * Reports Pause Event occurred. Param: event - indicates one or more of - * three event types, OR'd together (CEDI_EV_PAUSE_FRAME_TX: Pause frame - * transmitted; CEDI_EV_PAUSE_TIME_ZERO: Pause time zero; - * CEDI_EV_PAUSE_NZ_QU_RX: Pause frame with non-zero quantum received). -*/ -typedef void (*CEDI_CbPauseEvent)(void* pD, uint32_t event); - -/** - * Reports PTP Primary Frame transmitted. Params: type - indicates - * one of two frame types, OR'd together (CEDI_EV_PTP_TX_DLY_REQ: - * delay_req; CEDI_EV_PTP_TX_SYNC: sync) - * , and time: pointer to - * a struct containing the time latched when the frame was - * transmitted. This is not set if IP config param tsu=0. -*/ -typedef void (*CEDI_CbPtpPriFrameTx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); - -/** - * Reports PTP Peer Frame transmitted. Params: type - indicates - * one of two frame types, OR'd together (CEDI_EV_PTP_TX_PDLY_REQ: - * pdelay_req; CEDI_EV_PTP_TX_PDLY_RSP: pdelay_rsp) - * , and time: pointer to - * a struct containing the time latched when the frame was - * transmitted. This is not set if IP config param tsu=0. -*/ -typedef void (*CEDI_CbPtpPeerFrameTx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); - -/** - * Reports PTP Primary Frame received. Params: type - indicates - * one of two frame types, OR'd together (CEDI_EV_PTP_RX_DLY_REQ: - * delay_req; CEDI_EV_PTP_RX_SYNC: sync) - * , and time: pointer to - * a struct containing the time latched when the frame was - * received. This is not set if IP config param tsu=0. -*/ -typedef void (*CEDI_CbPtpPriFrameRx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); - -/** - * Reports PTP Peer Frame received. Params: type - indicates - * one of two frame types, OR'd together (CEDI_EV_PTP_RX_PDLY_REQ: - * pdelay_req; CEDI_EV_PTP_RX_PDLY_RSP: pdelay_rsp) - * , and time: pointer to - * a struct containing the time latched when the frame was - * received. This is not set if IP config param tsu=0. -*/ -typedef void (*CEDI_CbPtpPeerFrameRx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); - -/** Reports LPI Status changed. */ -typedef void (*CEDI_CbLpiStatus)(void* pD); - -/** Reports Wake On LAN event received. */ -typedef void (*CEDI_CbWolEvent)(void* pD); - -/** Reports External input interrupt occurred. */ -typedef void (*CEDI_CbExtInpIntr)(void* pD); - -/********************************************************************** - * Structures and unions - **********************************************************************/ -/** - * Configuration parameters passed to probe & init. - * Note that only the first eight fields are required for the probe call; - * all are required by init -*/ -typedef struct CEDI_Config -{ - /** base address of EMAC registers */ - uintptr_t regBase; - /** - * number of Rx priority queues, up to 1 more than - * highest defined dma_priority_queueN value - * (for example, =4 if highest is dma_priority_queue3) - */ - uint8_t rxQs; - /** number of Tx priority queues, same limit as for rxQs */ - uint8_t txQs; - /** - * number of descriptors in each Tx - * descriptor queue - */ - uint16_t txQLen[16]; - /** - * number of descriptors in each Rx - * descriptor queue - */ - uint16_t rxQLen[16]; - /** DMA address bus width. 0=32b , 1=64b */ - uint8_t dmaAddrBusWidth; - /** enable Tx extended BD mode */ - uint8_t enTxExtBD; - /** enable Rx extended BD mode */ - uint8_t enRxExtBD; - /** - * sets endian swap for data buffers and descriptors - * accesses: OR'd combination of CEDI_END_SWAP_DESC - * and CEDI_END_SWAP_DATA - */ - uint8_t dmaEndianism; - /** DMA bus width: 32, 64 or 128 bits */ - CEDI_BusWidth dmaBusWidth; - /** - * events to enable on start, OR together bit-flags - * defined in Interrupt control - */ - uint32_t intrEnable; - /** - * Upper 32 bits of physical address of Tx descriptor queues. - * Used only if DMA configured for 64-bit addressing. - * This is the single upper address used for Tx & Rx descriptors by older - * MAC h/w, in GEM_GXL before r1p06f2, and XGM_GXL up to r1p01 - */ - uint32_t upper32BuffTxQAddr; - /** - * Upper 32 bits of physical address of Rx descriptor queues. - * Used only if DMA configured for 64-bit addressing - */ - uint32_t upper32BuffRxQAddr; - /** - * start address of Tx descriptor queues (contiguous - * block for all queues) - */ - uintptr_t txQAddr; - /** physical address of Tx descriptor queues */ - uint32_t txQPhyAddr; - /** - * start address of Rx descriptor queues (contiguous - * block for all queues) - */ - uintptr_t rxQAddr; - /** physical address of Rx descriptor queues */ - uint32_t rxQPhyAddr; - /** - * length of rx buffers, as a multiple of 64 bytes, - * e.g. 2 = 128 bytes - */ - uint8_t rxBufLength[16]; - /** transmit packet buffer size select */ - uint8_t txPktBufSize; - /** receive packet buffer size select */ - uint8_t rxPktBufSize; - /** fixed burst length for DMA data transfers */ - CEDI_DmaDatBLen dmaDataBurstLen; - /** - * DMA config register bits 24, 25 & 26. - * OR the following bit-flags to set corresponding bits - - * CEDI_CFG_DMA_DISC_RXP, - * CEDI_CFG_DMA_FRCE_RX_BRST, - * CEDI_CFG_DMA_FRCE_TX_BRST - */ - uint8_t dmaCfgFlags; - /** - * set to 1 to initialise with MDIO enabled, or 0 to - * disable - */ - uint8_t enableMdio; - /** divisor to generate MDC from pclk */ - CEDI_MdcClkDiv mdcPclkDiv; - /** MII/GMII/SGMII and speed selection */ - CEDI_Interface ifTypeSel; - /** - * enable alternative SGMII mode (auto-negotiation - * ACK driven differently) - */ - uint8_t altSgmiiEn; - /** full/half duplex operation */ - uint8_t fullDuplex; - /** enable Rx in half-duplex while Tx */ - uint8_t enRxHalfDupTx; - /** enable external address match interface */ - uint8_t extAddrMatch; - /** start-of-frame offset for writing Rx data (0 to 3 bytes) */ - uint8_t rxBufOffset; - /** enable discard of frames with length field error */ - uint8_t rxLenErrDisc; - /** disable copying Rx pause frames to memory */ - uint8_t disCopyPause; - /** enable uni-direction Tx operation */ - uint8_t uniDirEnable; - /** - * enable checksum offload operation - OR bit-flags - * to enable in Tx and/or Rx: - * CEDI_CFG_CHK_OFF_TX, CEDI_CFG_CHK_OFF_RX - */ - uint8_t chkSumOffEn; - /** enable Rx of frames up to 1536 bytes */ - uint8_t rx1536ByteEn; - /** enable Rx of jumbo frames */ - uint8_t rxJumboFrEn; - /** enable Rx frames with non-standard preamble */ - uint8_t enRxBadPreamble; - /** ignore IPG rx_er (NetCfg b30) */ - uint8_t ignoreIpgRxEr; - /** - * replace CRC upper 16 bits with offset to UDP/TCP - * header for Rx frames - */ - uint8_t storeUdpTcpOffset; - /** enable external TSU timer port */ - uint8_t enExtTsuPort; - /** - * Maximum number of outstanding AXI write requests, - * that can be issued by DMA via the AW channel. - * Must not be = 0 if using AXI as this would disable writes - */ - uint8_t aw2wMaxPipeline; - /** - * Maximum number of outstanding AXI read requests, - * that can be issued by DMA via the AR channel. - * Must not be = 0 if using AXI as this would disable reads - */ - uint8_t ar2rMaxPipeline; - /** enable pfc multiple quantum (8 different priorities) */ - uint8_t pfcMultiQuantum; - /** - * address of CEDI_Statistics struct for driver to fill out: ignored if - * no_stats = 1 - */ - uintptr_t statsRegs; -} CEDI_Config; - -/** System requirements returned by probe */ -typedef struct CEDI_SysReq -{ - /** size of memory required for driver's private data */ - uint32_t privDataSize; - /** size of contiguous block of Tx descriptor lists */ - uint32_t txDescListSize; - /** size of contiguous block of Rx descriptor lists */ - uint32_t rxDescListSize; - /** - * size of memory for storing statistics register contents: - * returned as 0 if no_stats was set to 1 - */ - uint32_t statsSize; -} CEDI_SysReq; - -/** struct for returning contents of the Tx Status register */ -typedef struct CEDI_TxStatus -{ - uint8_t usedBitRead; - uint8_t collisionOcc; - uint8_t retryLimExc; - uint8_t txActive; - uint8_t txFrameErr; - uint8_t txComplete; - uint8_t txUnderRun; - uint8_t lateCollision; - uint8_t hRespNotOk; -} CEDI_TxStatus; - -/** Bit-field struct for returning contents of the Rx Status register */ -typedef struct CEDI_RxStatus -{ - uint8_t buffNotAvail; - uint8_t frameRx; - uint8_t rxOverrun; - uint8_t hRespNotOk; -} CEDI_RxStatus; - -/** Struct for virtual & physical addresses of DMA-addressable data buffer */ -typedef struct CEDI_BuffAddr -{ - uintptr_t vAddr; - uintptr_t pAddr; -} CEDI_BuffAddr; - -/** Struct describing time stamp data allocated in descriptor */ -typedef struct CEDI_TimeStampData -{ - /** TS valid - set to 1 if valid data stored */ - uint8_t tsValid; - /** Timestamp nanoseconds[29:0] - word2/4[29:0] */ - uint32_t tsNanoSec; - /** Timestamp seconds[1:0] from word2/4[31:30], seconds[5:2]from word3/5[5:2] */ - uint32_t tsSecs; -} CEDI_TimeStampData; - -/** struct for returning tx descriptor data */ -typedef struct CEDI_TxDescData -{ - /** physical & virtual addresses of buffer freed up */ - struct CEDI_BuffAddr bufAdd; - /** Tx descriptor status word - only valid if first buffer of frame */ - uint32_t txDescStat; - /** descriptor queue status, see freeTxDesc for description */ - uint8_t status; - /** Tx descriptor timestamp when valid (txTsData.tsValid will be set to 1) */ - struct CEDI_TimeStampData txTsData; -} CEDI_TxDescData; - -/** struct for returning tx descriptor status fields */ -typedef struct CEDI_TxDescStat -{ - /** IP/TCP/UDP checksum offload errors - see CEDI_TXD_CHKOFF_ constants */ - uint8_t chkOffErr; - /** late collision Tx error detected */ - uint8_t lateColl; - /** DMA frame corruption */ - uint8_t frameCorr; - /** Tx Underrun error detected */ - uint8_t txUnderrun; - /** Tx error, retries limit exceeded */ - uint8_t retryExc; -} CEDI_TxDescStat; - -/** struct for returning rx descriptor data */ -typedef struct CEDI_RxDescData -{ - /** Rx descriptor status word */ - uint32_t rxDescStat; - /** Rx data status, see readRxBuf for description */ - uint8_t status; - /** Rx descriptor timestamp when valid (rxTsData.tsValid will be set to 1) */ - struct CEDI_TimeStampData rxTsData; -} CEDI_RxDescData; - -/** struct for rx descriptor status fields */ -typedef struct CEDI_RxDescStat -{ - /** valid when eoh (length of header) or eof (total frame length) - includes b13 if not ignore fcs enabled */ - uint16_t bufLen; - /** ignore if jumbo frames enabled */ - uint8_t fcsStatus; - /** Start Of Frame in this buffer */ - uint8_t sof; - /** End Of Frame in this buffer */ - uint8_t eof; - /** Header-data split: header buffer */ - uint8_t header; - /** Header-data split: End Of Header in this buffer */ - uint8_t eoh; - /** Canonical Format Indicator */ - uint8_t cfi; - /** VLAN Priority */ - uint8_t vlanPri; - /** Priority tag detected */ - uint8_t priTagDet; - /** VLAN tag detected */ - uint8_t vlanTagDet; - /** only set if rx chksum offload disabled */ - uint8_t typeIdMatch; - /** Type ID match register if typeIdMatch set (RegNumber-1, i.e. 0 => reg. 1 ) */ - uint8_t typeMatchReg; - /** ignore if rx chksum offload disabled */ - uint8_t snapNoVlanCfi; - /** chksum offload checking status */ - uint8_t chkOffStat; - /** - * specific address register match (b27 OR b28) - * If packet buffer mode and extra specific address - * registers are used, this indicates match in - * one of the first eight registers - */ - uint8_t specAddMatch; - /** - * specific addr match register if specAddMatch set - * (RegNumber-1, i.e. 0 => reg. 1 ) - */ - uint8_t specAddReg; - /** external address match */ - uint8_t extAddrMatch; - /** unicast hash match */ - uint8_t uniHashMatch; - /** multicast hash match */ - uint8_t multiHashMatch; - /** all-1's broadcast address detected */ - uint8_t broadcast; -} CEDI_RxDescStat; - -/** parameters for qTxBuf function */ -typedef struct CEDI_qTxBufParams -{ - /** number of Tx queue */ - uint8_t queueNum; - /** pointer to struct containing physical & virtual addresses of buffer - virtual field is for upper layer use only, can contain other reference/status if required */ - struct CEDI_BuffAddr* bufAdd; - /** length of data in buffer */ - uint32_t length; - /** bit-flags (CEDI_TXB_xx) specifying last buffer/auto CRC and LSO controls */ - uint8_t flags; - /** Segment/fragment size (MSS for TCP or MFS for UDP) - used for all data descriptors */ - uint16_t mssMfs; - /** TCP Stream number, determines which auto-sequence counter to use - only for first (header) descriptor used when flags includes CEDI_TXB_TSO_AUTO_SEQ and CEDI_TXB_TCP_ENCAP */ - uint8_t tcpStream; -} CEDI_qTxBufParams; - -/** Q buffer sizes */ -typedef struct CEDI_FrameSize -{ - /** array of sizes per queue */ - uint32_t FrameSize[16]; -} CEDI_FrameSize; - -/** struct for MAC address */ -typedef struct CEDI_MacAddress -{ - uint8_t byte[6]; -} CEDI_MacAddress; - -/** struct containing all statistics register values (144 bytes long) */ -typedef struct CEDI_Statistics -{ - /** b31:0 of octets transmitted */ - uint32_t octetsTxLo; - /** b47:32 of octets transmitted */ - uint16_t octetsTxHi; - uint32_t framesTx; - uint32_t broadcastTx; - uint32_t multicastTx; - uint16_t pauseFrTx; - uint32_t fr64byteTx; - uint32_t fr65_127byteTx; - uint32_t fr128_255byteTx; - uint32_t fr256_511byteTx; - uint32_t fr512_1023byteTx; - uint32_t fr1024_1518byteTx; - uint32_t fr1519_byteTx; - uint16_t underrunFrTx; - uint32_t singleCollFrTx; - uint32_t multiCollFrTx; - uint16_t excessCollFrTx; - uint16_t lateCollFrTx; - uint32_t deferredFrTx; - uint16_t carrSensErrsTx; - /** b31:0 of octets received */ - uint32_t octetsRxLo; - /** b47:32 of octets received */ - uint16_t octetsRxHi; - uint32_t framesRx; - uint32_t broadcastRx; - uint32_t multicastRx; - uint16_t pauseFrRx; - uint32_t fr64byteRx; - uint32_t fr65_127byteRx; - uint32_t fr128_255byteRx; - uint32_t fr256_511byteRx; - uint32_t fr512_1023byteRx; - uint32_t fr1024_1518byteRx; - uint32_t fr1519_byteRx; - uint16_t undersizeFrRx; - uint16_t oversizeFrRx; - uint16_t jabbersRx; - uint16_t fcsErrorsRx; - uint16_t lenChkErrRx; - uint16_t rxSymbolErrs; - uint16_t alignErrsRx; - uint32_t rxResourcErrs; - uint16_t overrunFrRx; - uint16_t ipChksumErrs; - uint16_t tcpChksumErrs; - uint16_t udpChksumErrs; - uint16_t dmaRxPBufFlush; -} CEDI_Statistics; - -/** struct for returning number of screening registers */ -typedef struct CEDI_NumScreeners -{ - /** number of Type1 screener registers */ - uint8_t type1ScrRegs; - /** number of Type2 screener registers */ - uint8_t type2ScrRegs; - /** number of ethtype registers */ - uint8_t ethtypeRegs; - /** number of compare registers */ - uint8_t compareRegs; -} CEDI_NumScreeners; - -/** struct for writing/reading Type1 screening registers */ -typedef struct CEDI_T1Screen -{ - /** the priority queue allocated if match found, */ - uint8_t qNum; - /** if =1, enable UDP port matching */ - uint8_t udpEnable; - /** UDP port number to match if udpEnable=1 (ignored otherwise) */ - uint16_t udpPort; - /** if =1, enable DS/TC field matching */ - uint8_t dstcEnable; - /** DS field (IPv4) or TC field (IPv6) value to match against */ - uint8_t dstcMatch; -} CEDI_T1Screen; - -/** struct for writing/reading Type2 screening registers */ -typedef struct CEDI_T2Screen -{ - /** the priority queue allocated if match found, */ - uint8_t qNum; - /** if =1, enable VLAN priority matching */ - uint8_t vlanEnable; - /** VLAN priority to match if vlanEnable=1 (ignored otherwise) */ - uint8_t vlanPriority; - /** if =1, enable EtherType field matching */ - uint8_t eTypeEnable; - /** Index of EtherType match register: when supported up to: CEDI_DesignCfg.num_scr2_ethtype_regs */ - uint8_t ethTypeIndex; - /** if =1, enable compare A matching */ - uint8_t compAEnable; - /** Index of compare register for compare A match. When supported up to: CEDI_DesignCfg.num_scr2_compare_regs */ - uint8_t compAIndex; - /** if =1, enable compare B matching */ - uint8_t compBEnable; - /** Index of compare register for compare B match. When supported up to: CEDI_DesignCfg.num_scr2_compare_regs */ - uint8_t compBIndex; - /** if =1, enable compare C matching */ - uint8_t compCEnable; - /** Index of compare register for compare C match. When supported up to: CEDI_DesignCfg.num_scr2_compare_regs */ - uint8_t compCIndex; -} CEDI_T2Screen; - -/** struct for writing/reading screener Type 2 compare registers */ -typedef struct CEDI_T2Compare -{ - /** Mask Value field (or 1st 16 bits of compare when disableMask set) */ - uint16_t compMask; - /** Compare Value field (or 2nd 16 bits of compare when disableMask set) */ - uint16_t compValue; - /** Offset value */ - uint8_t offsetVal; - /** Position in frame to apply offset */ - CEDI_T2Offset offsetPosition; - /** Disable mask value function, to extend compare value to 4 bytes. Set to 1 to disable mask. */ - uint8_t disableMask; -} CEDI_T2Compare; - -/** struct for writing/reading 1588 timer */ -typedef struct CEDI_1588TimerVal -{ - /** Upper 16 bits of seconds value */ - uint16_t secsUpper; - /** Lower 32 bits of seconds value */ - uint32_t secsLower; - /** Nanoseconds value (30 bits) */ - uint32_t nanosecs; -} CEDI_1588TimerVal; - -/** struct for writing/reading TSU timer */ -typedef struct CEDI_TsuTimerVal -{ - /** Upper 16 bits of seconds value */ - uint16_t secsUpper; - /** Lower 32 bits of seconds value */ - uint32_t secsLower; - /** Upper 22 bits of nanoseconds value */ - uint32_t nanosecs; -} CEDI_TsuTimerVal; - -/** struct for writing/reading the 1588 timer increment registers */ -typedef struct CEDI_TimerIncrement -{ - /** Whole nanoseconds to increment timer each clock cycle */ - uint8_t nanoSecsInc; - /** Sub-nanoseconds to increment the timer (16 bits) */ - uint16_t subNsInc; - /** Lower 8 bits of sub-nanoseconds to increment the timer */ - uint8_t lsbSubNsInc; - /** Number of increments before changing to alternative increment. If = 0 then never use alternative increment. */ - uint8_t altIncCount; - /** Alternative nanoseconds increment to apply */ - uint8_t altNanoSInc; -} CEDI_TimerIncrement; - -/** - * struct for returning contents of the auto-negotiation advertisement - * register -*/ -typedef struct CEDI_AnAdvPage -{ - /** full duplex capability */ - uint8_t fullDuplex; - /** half duplex capability */ - uint8_t halfDuplex; - /** pause capability */ - CEDI_PauseCap pauseCap; - /** remote fault condition */ - CEDI_RemoteFault remFlt; - /** next page exchange required */ - uint8_t nextPage; -} CEDI_AnAdvPage; - -/** struct for default (non-SGMII) auto-negotiation link partner abilities */ -typedef struct CEDI_defLpAbility -{ - /** full duplex capability */ - uint8_t fullDuplex; - /** half duplex capability */ - uint8_t halfDuplex; - /** pause capability */ - CEDI_PauseCap pauseCap; - /** remote fault condition */ - CEDI_RemoteFault remFlt; - /** link partner acknowledge indication */ - uint8_t lpAck; - /** next page exchange required */ - uint8_t lpNextPage; -} CEDI_defLpAbility; - -/** struct for SGMII mode auto-negotiation link partner abilities */ -typedef struct CEDI_sgmLpAbility -{ - /** speed, = 10/100/1000Mbps */ - CEDI_IfSpeed speed; - /** - * duplex capability, = 0 for half duplex, - * =1 for full duplex - */ - uint8_t duplex; - /** link partner acknowledge indication */ - uint8_t lpAck; - /** =0 if link down, =1 if link up */ - uint8_t linkStatus; -} CEDI_sgmLpAbility; - -/** - * union of two possible link partner ability structs, - * one for default configuration and one for SGMII configuration -*/ -typedef union CEDI_LpAbility -{ - struct CEDI_defLpAbility defLpAbl; - struct CEDI_sgmLpAbility sgmLpAbl; -} CEDI_LpAbility; - -/** Struct for link partner ability page info. If sgmii =0 then read default ability page struct from ablInfo. If sgmii =1 then read SGMII mode ability page struct from ablInfo. */ -typedef struct CEDI_LpAbilityPage -{ - union CEDI_LpAbility ablInfo; - uint8_t sgmii; -} CEDI_LpAbilityPage; - -/** Struct for auto-negotiation next page register data */ -typedef struct CEDI_AnNextPage -{ - /** message data as defined by message page indicator (11 bits) */ - uint16_t message; - /** acknowledge 2 */ - uint8_t ack2; - /** message page indicator */ - uint8_t msgPage; - /** set if another next page to transmit */ - uint8_t np; -} CEDI_AnNextPage; - -/** struct for auto-negotiation link partner next page data */ -typedef struct CEDI_LpNextPage -{ - /** message data as defined by message page indicator (11 bits) */ - uint16_t message; - /** toggles for each received page */ - uint8_t toggle; - /** acknowledge 2 */ - uint8_t ack2; - /** message page indicator */ - uint8_t msgPage; - /** - * indicates if link partner successfully - * received last message - */ - uint8_t ack; - /** set if another next page to transmit */ - uint8_t np; -} CEDI_LpNextPage; - -/** union for link partner page data - ability page or next page */ -typedef union CEDI_LpPage -{ - struct CEDI_LpAbilityPage lpBasePage; - struct CEDI_LpNextPage lpNextPage; -} CEDI_LpPage; - -/** Struct for returning page data from link partner. If nextPage = 0 then read link partner base page from lpPage.lpBasePage, else read next page from lpPage.lpNextPage */ -typedef struct CEDI_LpPageRx -{ - union CEDI_LpPage lpPageDat; - uint8_t nextPage; -} CEDI_LpPageRx; - -/** Struct for returning network status related to auto-negotiation */ -typedef struct CEDI_NetAnStatus -{ - /** - * if auto-negotiation enabled: = 1 if LINK up, - * = 0 if LINK down - * else synchronisation status - */ - uint8_t linkState; - /** if = 1 then both devices full duplex */ - uint8_t duplexRes; - /** enable pause Tx */ - uint8_t pauseTxRes; - /** enable pause Rx */ - uint8_t pauseRxRes; -} CEDI_NetAnStatus; - -/** Struct for writing/reading the Wake On LAN register */ -typedef struct CEDI_WakeOnLanReg -{ - /** Least significant 16 bits of target IP address to match */ - uint16_t wolReqAddr; - /** Magic packet events cause WOL assert (equal 1 means enabled) */ - uint8_t magPktEn; - /** ARP request events cause WOL assert (equal 1 means enabled) */ - uint8_t arpEn; - /** Specific address 1 events cause WOL assert (equal 1 means enabled) */ - uint8_t specAd1En; - /** Multicast hash events cause WOL assert (equal 1 means enabled) */ - uint8_t multiHashEn; -} CEDI_WakeOnLanReg; - -/** Struct for returning the LPI Tx and Rx statistics */ -typedef struct CEDI_LpiStats -{ - /** Number of transitions to Rx low power idle */ - uint16_t rxLpiTrans; - /** Counts time in Rx LPI indication */ - uint32_t rxLpiTime; - /** Number of transitions to LPI Tx enable */ - uint16_t txLpiTrans; - /** Counts time in LPI Tx enable */ - uint32_t txLpiTime; -} CEDI_LpiStats; - -/** Struct containing all design configuration fields, plus some other features which are revision-dependent, e.g. intrp_mod */ -typedef struct CEDI_DesignCfg -{ - uint16_t moduleId; - uint16_t moduleRev; - uint8_t fixNumber; - uint8_t numQueues; - uint8_t no_pcs; - uint8_t serdes; - uint8_t RDC_50; - uint8_t TDC_50; - uint8_t int_loopback; - uint8_t no_int_loopback; - uint8_t ext_fifo_interface; - uint8_t apb_rev1; - uint8_t apb_rev2; - uint8_t user_io; - uint8_t user_out_width; - uint8_t user_in_width; - uint8_t no_scan_pins; - uint8_t no_stats; - uint8_t no_snapshot; - uint8_t irq_read_clear; - uint8_t exclude_cbs; - uint8_t num_spec_add_filters; - uint8_t dma_bus_width; - uint8_t axi_cache_value; - uint16_t jumbo_max_length; - uint8_t hprot_value; - uint8_t rx_pkt_buffer; - uint8_t tx_pkt_buffer; - uint8_t rx_pbuf_addr; - uint8_t tx_pbuf_addr; - uint8_t axi; - uint8_t rx_fifo_cnt_width; - uint8_t tx_fifo_cnt_width; - uint8_t tsu; - uint8_t phy_ident; - uint8_t dma_bus_width_def; - uint8_t mdc_clock_div; - uint8_t endian_swap_def; - uint8_t rx_pbuf_size_def; - uint8_t tx_pbuf_size_def; - uint8_t rx_buffer_length_def; - uint8_t tsu_clk; - uint8_t axi_prot_value; - uint8_t tx_pbuf_queue_segment_size; - uint8_t ext_tsu_timer; - uint8_t tx_add_fifo_if; - uint8_t host_if_soft_select; - uint8_t tx_pbuf_num_segments_q0; - uint8_t tx_pbuf_num_segments_q1; - uint8_t tx_pbuf_num_segments_q2; - uint8_t tx_pbuf_num_segments_q3; - uint8_t tx_pbuf_num_segments_q4; - uint8_t tx_pbuf_num_segments_q5; - uint8_t tx_pbuf_num_segments_q6; - uint8_t tx_pbuf_num_segments_q7; - uint8_t dma_addr_width; - uint8_t tx_pbuf_num_segments_q8; - uint8_t tx_pbuf_num_segments_q9; - uint8_t tx_pbuf_num_segments_q10; - uint8_t tx_pbuf_num_segments_q11; - uint8_t tx_pbuf_num_segments_q12; - uint8_t tx_pbuf_num_segments_q13; - uint8_t tx_pbuf_num_segments_q14; - uint8_t tx_pbuf_num_segments_q15; - uint8_t num_type1_screeners; - uint8_t num_type2_screeners; - uint8_t num_scr2_ethtype_regs; - uint8_t num_scr2_compare_regs; - uint8_t axi_access_pipeline_bits; - uint8_t pfc_multi_quantum; - uint8_t pbuf_rsc; - uint8_t pbuf_lso; - uint8_t intrpt_mod; - uint8_t hdr_split; - uint8_t rx_pbuf_data; - uint8_t tx_pbuf_data; -} CEDI_DesignCfg; - -/** - * struct containing function pointers for event notification callbacks issued - * by isr(). - * Each call passes the driver's privateData (pD) pointer for instance - * identification if necessary, and may also pass data related to the event. -*/ -typedef struct CEDI_Callbacks -{ - CEDI_CbPhyManComplete phyManComplete; - CEDI_CbTxEvent txEvent; - CEDI_CbTxError txError; - CEDI_CbRxFrame rxFrame; - CEDI_CbRxError rxError; - CEDI_CbHrespError hrespError; - CEDI_CbLpPageRx lpPageRx; - CEDI_CbAnComplete anComplete; - CEDI_CbLinkChange linkChange; - CEDI_CbTsuEvent tsuEvent; - CEDI_CbPauseEvent pauseEvent; - CEDI_CbPtpPriFrameTx ptpPriFrameTx; - CEDI_CbPtpPeerFrameTx ptpPeerFrameTx; - CEDI_CbPtpPriFrameRx ptpPriFrameRx; - CEDI_CbPtpPeerFrameRx ptpPeerFrameRx; - CEDI_CbLpiStatus lpiStatus; - CEDI_CbWolEvent wolEvent; - CEDI_CbExtInpIntr extInpIntr; -} CEDI_Callbacks; - -/** - * @} - */ - -/** @defgroup DriverObject Driver API Object - * API listing for the driver. The API is contained in the object as - * function pointers in the object structure. As the actual functions - * resides in the Driver Object, the client software must first use the - * global GetInstance function to obtain the Driver Object Pointer. - * The actual APIs then can be invoked using obj->(api_name)() syntax. - * These functions are defined in the header file of the core driver - * and utilized by the API. - * @{ - */ - -/********************************************************************** - * API methods - **********************************************************************/ -typedef struct CEDI_OBJ -{ - /** - * Get the driver's memory requirements to support the given - * configuration. If config->txQs or config->rxQs specify more than - * the number of queues available in the h/w configuration, they will - * be reduced to match the latter value, and the memReq values will - * be based on this. - * @param[out] memReq returns the size of memory allocations required - * @param[in] config driver/hardware configuration required - * @return EOK on success (requirements struct filled) - * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints - * @return EINVAL if config is NULL, or hardware not present - */ - uint32_t (*probe)(CEDI_Config* config, CEDI_SysReq* memReq); - - /** - * Initialise the driver instance and state, configure the EMAC as - * specified in the 'config' settings, set up Tx & Rx descriptor - * lists. - * @param[in] callbacks client-supplied callback functions - * @param[in,out] config specifies driver/hardware configuration - * @param[in] pD driver state info specific to this instance - * @return EOK on success - * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters - * @return EIO if driver encountered an error accessing hardware - * @return EINVAL if illegal/inconsistent values in 'config' - */ - uint32_t (*init)(void* pD, const CEDI_Config* config, CEDI_Callbacks* callbacks); - - /** - * Destroy the driver (automatically performs a stop) - * @param[in] pD driver state info specific to this instance - */ - void (*destroy)(void* pD); - - /** - * Start the EMAC driver, enabling interrupts and PCS auto- - * negotiation. - * @param[in] pD driver state info specific to this instance - */ - void (*start)(void* pD); - - /** - * Stop the driver. This should disable the hardware, including its - * interrupt at the source, and make a best-effort to cancel any - * pending transactions. - * @param[in] pD driver state info specific to this instance - */ - void (*stop)(void* pD); - - /** - * Driver ISR. Platform-specific code is responsible for ensuring - * this gets called when the corresponding hardware's interrupt is - * asserted. Registering the ISR should be done after calling init, - * and before calling start. The driver's ISR will not attempt to - * lock any locks, but will perform client callbacks. If the client - * wishes to defer processing to non-interrupt time, it is - * responsible for doing so. - * @param[in] pD driver state info specific to this instance - * @return EOK if any interrupt detected (and callback) - * @return ECANCELED if no interrupt bit detected - * @return EINVAL for invalid pD pointer - */ - uint32_t (*isr)(void* pD); - - /** - * Enable or disable the specified interrupts. mechanical test will - * always fail as no callback pointers are given - * @param[in] enable if =1 enable the events, if =0 then disable - * @param[in] events OR'd combination of bit-flags selecting the events to be enabled or disabled - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum between 0 and config->rxQs-1, or = CEDI_ALL_QUEUES - * - number of Tx or Rx priority queue, - * relevant to some of Tx and Rx events: CEDI_EV_TX_COMPLETE, CEDI_EV_TX_RETRY_EX_LATE_COLL, CEDI_EV_TX_FR_CORRUPT, CEDI_EV_RX_COMPLETE, - * CEDI_EV_RX_USED_READ, CEDI_EV_RX_OVERRUN, CEDI_EV_HRESP_NOT_OK. - * Must be = 0 or CEDI_ALL_QUEUES for other events. - * To dis/enable on all available Qs, set queueNum to CEDI_ALL_QUEUES - * and set events to CEDI_EVSET_ALL_Q0_EVENTS. - * @return EOK for success - * @return EINVAL for invalid queueNum - */ - uint32_t (*setEventEnable)(void* pD, uint32_t events, uint8_t enable, uint8_t queueNum); - - /** - * Read the enabled state of the specifed interrupts. OR the returned - * event value with the CEDI_EV_ event bit-flags to determine if - * event(s) are enabled. - * @param[out] event returned enabled events - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum Tx or Rx priority queue to report events for - * @return EOK for success - * @return EINVAL for invalid pointer or queueNum - */ - uint32_t (*getEventEnable)(void* pD, uint8_t queueNum, uint32_t* event); - - /** - * Set the value of the Tx & Rx interrupt moderation register fields. - * A non-zero value in either field introduces an interrupt stand-off - * delay of the 8-bit value in units of 800ns before the - * corresponding frame complete event causes an interrupt, limiting - * the interrupt rate. - * @param[in] txIntDelay Interrupt delay to apply to Tx frame complete - * @param[in] rxIntDelay Interrupt delay to apply to Rx frame complete - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*setIntrptModerate)(void* pD, uint8_t txIntDelay, uint8_t rxIntDelay); - - /** - * Read the values of the interrupt moderation register fields - * @param[out] txIntDelay Interrupt delay to apply to Tx frame complete - * @param[out] rxIntDelay Interrupt delay to apply to Rx frame complete - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointers - */ - uint32_t (*getIntrptModerate)(void* pD, uint8_t* txIntDelay, uint8_t* rxIntDelay); - - /** - * Select 10/100/1000Mbps operation speed. - * @param[in] speedSel a CEDI_IfSpeed enum indicating Tx/Rx speed - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*setIfSpeed)(void* pD, CEDI_IfSpeed speedSel); - - /** - * Read selected operation speed - * @param[out] speedSel returns CEDI_IfSpeed enum indicating Tx/Rx speed " - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if invalid parameter - */ - uint32_t (*getIfSpeed)(void* pD, CEDI_IfSpeed* speedSel); - - /** - * Enable/disable reception of jumbo frames - * @param[in] enable if =1 then enable jumbo frames accept, if =0 disable. - * @param[in] pD driver private state info specific to this instance - */ - void (*setJumboFramesRx)(void* pD, uint8_t enable); - - /** - * Read jumbo frames enable status - * @param[out] enable equal 1 if jumbo frames accept enabled; equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getJumboFramesRx)(void* pD, uint8_t* enable); - - /** - * Set maximum length of jumbo frames to be received. (This is - * initialised to gem_jumbo_max_length bytes.) Disables jumbo frame - * reception temporarily while changing max length. - * @param[in] length max. length to receive, in bytes. Maximum is 16383 - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if length greater than 16383 - */ - uint32_t (*setJumboFrameRxMaxLen)(void* pD, uint16_t length); - - /** - * Read maximum length of jumbo frames to be received - * @param[out] length returns max. length to receive, in bytes - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getJumboFrameRxMaxLen)(void* pD, uint16_t* length); - - /** - * Enable/disable uni-direction transmit operation. - * @param[in] enable if =1 enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setUniDirEnable)(void* pD, uint8_t enable); - - /** - * Read enable status for uni-direction transmit operation - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getUniDirEnable)(void* pD, uint8_t* enable); - - /** - * Enable/disable Tx IP, TCP and UDP checksum generation offload. - * Only valid if using DMA packet buffering mode. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if packet buffering not enabled or null pointer - */ - uint32_t (*setTxChecksumOffload)(void* pD, uint8_t enable); - - /** - * Read enable/disable of Tx IP, TCP and UDP checksum generation - * offload - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getTxChecksumOffload)(void* pD, uint8_t* enable); - - /** - * Set Rx buffer offset for writing start of frame. - * @param[in] pD driver private state info specific to this instance - * @param[in] offset offset to use, range 0 to 3 bytes - * @return EOK for success - * @return EINVAL if offset invalid or null pointer - */ - uint32_t (*setRxBufOffset)(void* pD, uint8_t offset); - - /** - * Read Rx buffer offset for writing start of frame - * @param[in] pD driver private state info specific to this instance - * @param[out] offset offset in use, range 0 to 3 bytes - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRxBufOffset)(void* pD, uint8_t* offset); - - /** - * Enable/disable reception of frames up to 1536 bytes, instead of - * normal 1518 bytes limit - * @param[in] enable if =1 then enable 1536-byte frames accept, if =0 disable - * @param[in] pD driver private state info specific to this instance - */ - void (*set1536ByteFramesRx)(void* pD, uint8_t enable); - - /** - * Read 1536-byte frames Rx enable status - * @param[out] enable equal 1 if 1536-byte frames accept enabled equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*get1536ByteFramesRx)(void* pD, uint8_t* enable); - - /** - * Enable/disable Rx IP, TCP and UDP checksum offload. When enabled, - * frames with bad IP, TCP or UDP checksums will be discarded. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setRxChecksumOffload)(void* pD, uint8_t enable); - - /** - * Read enable/disable of Rx IP, TCP and UDP checksum offload - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRxChecksumOffload)(void* pD, uint8_t* enable); - - /** - * Enable/disable FCS remove feature. When enabled, received frames - * will be written without frame check sequence (last four bytes). - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setFcsRemove)(void* pD, uint8_t enable); - - /** - * Read enable/disable status for FCS remove feature - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getFcsRemove)(void* pD, uint8_t* enable); - - /** - * Enable/disable partial store and forward Tx mode if possible - * @param[in] enable if =1 then enables partial store and forward Tx mode, if =0 then disables - * @param[in] pD driver private state info specific to this instance - * @param[in] watermark value to control data forwarding - ignored if enable==0 - * @return EOK if successful - * @return ENOTSUP if not in tx packet buffer mode - * @return EINVAL if parameter invalid - */ - uint32_t (*setTxPartialStFwd)(void* pD, uint32_t watermark, uint8_t enable); - - /** - * Get watermark value for partial store and forward Tx mode - * @param[out] enable =1 if partial store and forward Tx mode enabled - * @param[in] pD driver private state info specific to this instance - * @param[out] watermark returns value to control data forwarding if partial store and forward Tx mode enabled - * @return EOK for success - * @return ENOTSUP if not in tx packet buffer mode - * @return EINVAL if invalid parameter - */ - uint32_t (*getTxPartialStFwd)(void* pD, uint32_t* watermark, uint8_t* enable); - - /** - * Enable/disable partial store and forward Rx mode if possible - * @param[in] enable if =1 then enables partial store and forward Rx mode, if =0 then disables - * @param[in] pD driver private state info specific to this instance - * @param[in] watermark value to control data forwarding - * @return EOK if successful - * @return ENOTSUP if not in rx packet buffer mode - * @return EINVAL if invalid parameter - */ - uint32_t (*setRxPartialStFwd)(void* pD, uint32_t watermark, uint8_t enable); - - /** - * Get watermark value for partial store and forward Rx mode - * @param[out] enable =1 if partial store and forward Rx mode enabled - * @param[in] pD driver private state info specific to this instance - * @param[out] watermark pointer for returning watermark value set (undefined if partial store & forward not enabled) - * @return EOK for success - * @return ENOTSUP if not in rx packet buffer mode - * @return EINVAL if invalid parameter - */ - uint32_t (*getRxPartialStFwd)(void* pD, uint32_t* watermark, uint8_t* enable); - - /** - * Set the fields of the Rx DMA Data Buffer Address Mask register, - * which allows any/all of bits 31:28 of rx data buffer address to be - * forced to a particular value - * @param[in] bitValues 4-bit field specifying values to force address bits 31:28 to, if corresponding bit in enableBit is set to 1 - * @param[in] pD driver private state info specific to this instance - * @param[in] enableBit 4-bit field selecting bits to force value on - * @return EOK if successful - * @return EINVAL if parameter value invalid - */ - uint32_t (*setRxDmaDataAddrMask)(void* pD, uint8_t enableBit, uint8_t bitValues); - - /** - * Read the fields of the Rx DMA Data Buffer Address Mask register, - * which allows any/all of bits 31:28 of rx data buffer address to be - * forced to a particular value - * @param[out] bitValues pointer for returning 4-bit field specifying values to force address bits to, if corresponding bit in enableBit is set to 1 - * @param[in] pD driver private state info specific to this instance - * @param[out] enableBit pointer for returning 4-bit field selecting bits to force value on - * @return EOK if successful - * @return EINVAL if any parameter equal NULL - */ - uint32_t (*getRxDmaDataAddrMask)(void* pD, uint8_t* enableBit, uint8_t* bitValues); - - /** - * Enable/disable receive bad preamble feature. When enabled, frames - * with non-standard preamble will not be rejected. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setRxBadPreamble)(void* pD, uint8_t enable); - - /** - * Read enable/disable status for receive bad preamble feature - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRxBadPreamble)(void* pD, uint8_t* enable); - - /** - * Select full/half duplex operation. - * @param[in] enable if =1 select full duplex operation if =0 select half duplex. - * @param[in] pD driver private state info specific to this instance - */ - void (*setFullDuplex)(void* pD, uint8_t enable); - - /** - * Read full/half duplex operation - * @param[out] enable equal 1 if full duplex operation enabled equal 0 if half duplex. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getFullDuplex)(void* pD, uint8_t* enable); - - /** - * Enable/disable ignore FCS feature. When enabled, frames with - * FCS/CRC errors will not be rejected. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setIgnoreFcsRx)(void* pD, uint8_t enable); - - /** - * Read enable/disable status for FCS ignore feature - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getIgnoreFcsRx)(void* pD, uint8_t* enable); - - /** - * Enable/disable frame Rx in half-duplex mode while transmitting. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setRxHalfDuplexInTx)(void* pD, uint8_t enable); - - /** - * Read enable status for frame Rx in half-duplex mode while - * transmitting - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRxHalfDuplexInTx)(void* pD, uint8_t* enable); - - /** - * Return capabilities supported by the driver/EMAC hardware - * @param[out] cap pointer for returning supported capabilities, OR combination of CEDI_CAP_XXX flags - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getIfCapabilities)(void* pD, uint32_t* cap); - - /** - * Enable or disable loop back mode in the EMAC. - * @param[in] mode enum selecting mode enable/disable. =CEDI_SERDES_LOOPBACK: select loopback mode in PHY transceiver, if available; =CEDI_LOCAL_LOOPBACK: select internal loopback mode. Tx and Rx should be disabled when enabling or disabling this mode. Only available if int_loopback defined; =CEDI_NO_LOOPBACK: disable loopback mode - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if CEDI_SERDES_LOOPBACK selected and no_pcs defined, or if CEDI_LOCAL_LOOPBACK selected and either (no_int_loopback defined or PCS mode is selected) - */ - uint32_t (*setLoopback)(void* pD, uint8_t mode); - - /** - * Return loopback mode, same values as for setLoopbackMode. - * @param[out] mode returns enum for mode enable/disable. =CEDI_SERDES_LOOPBACK: selected loopback mode in PHY transceiver, if available; =CEDI_LOCAL_LOOPBACK: selected internal loopback mode. Only available if int_loopback defined; =CEDI_NO_LOOPBACK: disabled loopback mode - * @param[in] pD driver private state info specific to this instance - */ - uint32_t (*getLoopback)(void* pD, uint8_t* mode); - - /** - * Identify max Tx pkt size for queues. When using full store & - * forward packet buffering, this is based on the sram size for each - * queue, otherwise it is limited by an internal counter to 16kB. - * @param[out] maxTxSize pointer for returning array of sizes for queues - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if any parameter equal NULL - */ - uint32_t (*calcMaxTxFrameSize)(void* pD, CEDI_FrameSize* maxTxSize); - - /** - * Add a buffer containing Tx data to the end of the transmit queue. - * Use repeated calls for multi-buffer frames, setting lastBuffer on - * the last call, to indicate the end of the frame. - * @param[in] bufAdd pointer to address of buffer - * @param[in] flags bit-flags (CEDI_TXB_xx) specifying last buffer/auto CRC - * @param[in] length length of data in buffer - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of Tx queue - * @return EOK if successful - * @return ENOENT if no available descriptors - * @return EINVAL if invalid queueNum, length or buffer alignment, NULL pointers or buffer address - */ - uint32_t (*queueTxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* bufAdd, uint32_t length, uint8_t flags); - - /** - * Add a buffer containing Tx data to the end of the transmit queue. - * Use repeated calls for multi-buffer frames, setting - * CEDI_TXB_LAST_BUFF in the flags on the last call, to indicate the - * end of the frame. This function is required for utilising TSO/UFO. - * @param[in] params pointer to struct for all parameters required by the function - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOENT if no available descriptors - * @return EINVAL if invalid queueNum, length or buffer alignment, NULL pointers or buffer address or prm->flags specifies CEDI_TXB_LAST_BUFF at same time as CEDI_TXB_TCP_ENCAP or CEDI_TXB_UDP_ENCAP - */ - uint32_t (*qTxBuf)(void* pD, CEDI_qTxBufParams* params); - - /** - * Remove buffer from head of transmit queue in case of error during - * queueing and free the corresponding descriptor. Caller must have - * knowledge of queueing status, i.e. latest frame has not been - * completed for transmission (first used bit still set) and how many - * descriptors have been queued for untransmitted frame. - * @param[in, out] params pointer to struct for parameters to be returned. Not all fields are used - queueNum must be specified, and bufAdd and length are returned - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOENT if no unfree descriptors - * @return EINVAL if invalid queueNum or NULL parameters - */ - uint32_t (*deQTxBuf)(void* pD, CEDI_qTxBufParams* params); - - /** - * Get number of free descriptors in specified Tx queue - * @param[out] numFree pointer for returning number of free descriptors - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of Tx queue - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*txDescFree)(void* pD, uint8_t queueNum, uint16_t* numFree); - - /** - * Read Tx descriptor queue and free used descriptor.\n Struct - * fields:\n CEDI_BuffAddr bufAdd - addresses of buffer freed up - * uint32_t txDescStat - descriptor status word. Only valid if first - * buffer of frame. uint8_t status - descriptor queue status, one of - * the following values: CEDI_TXDATA_1ST_NOT_LAST :a first descriptor - * was freed, frame not finished: - * bufAdd & txDescStat are valid CEDI_TXDATA_1ST_AND_LAST :a first - * descriptor was freed, frame is finished: - * bufAdd & txDescStat are valid CEDI_TXDATA_MID_BUFFER :a - * descriptor was freed, (not first in - * frame), frame not finished: bufAdd valid, - * txDescStat not valid CEDI_TXDATA_LAST_BUFFER :a descriptor was - * freed, frame is finished: bufAdd valid, - * txDescStat not valid CEDI_TXDATA_NONE_FREED :no used descriptor - * to free: bufAdd & txDescStat not valid - * CEDI_TimeStampData txTsData - Tx descriptor timestamp when valid - * (txTsData->tsValid will be set to 1). - * @param[out] descData pointer for returning status & descriptor data - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of Tx queue - * @return EOK if successful (and status is set) - * @return ENOENT if the queue is empty (status equal CEDI_TXDATA_NONE_FREED) - * @return EIO if an incomplete frame was detected (no lastBuffer flag in queue) - * @return EINVAL if any parameter invalid - */ - uint32_t (*freeTxDesc)(void* pD, uint8_t queueNum, CEDI_TxDescData* descData); - - /** - * Decode the Tx descriptor status into a bit-field struct - * @param[in] txDStatWord - Tx descriptor status word - * @param[in] pD driver private state info specific to this instance - * @param[out] txDStat - pointer to bit-field struct for decoded status fields - */ - void (*getTxDescStat)(void* pD, uint32_t txDStatWord, CEDI_TxDescStat* txDStat); - - /** - * Provides the size of Tx descriptor calculated for current - * configuration. - * @param[out] txDescSize - pointer to Tx descriptor size - * @param[in] pD driver private state info specific to this instance - */ - void (*getTxDescSize)(void* pD, uint32_t* txDescSize); - - /** - * Reset transmit buffer queue. Any untransmitted buffer data will be - * discarded and must be re-queued. Transmission must be disabled - * before calling this function. - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of Tx queue - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*resetTxQ)(void* pD, uint8_t queueNum); - - /** - * Enable & start the transmit circuit. Not required during normal - * operation, as queueTxBuf will automatically start Tx when complete - * frame has been queued, but may be used to restart after a Tx - * error. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ECANCELED if no entries in buffer - */ - uint32_t (*startTx)(void* pD); - - /** - * Halt transmission as soon as current frame Tx has finished - * @param[in] pD driver private state info specific to this instance - */ - void (*stopTx)(void* pD); - - /** - * Immediately disable transmission without waiting for completion. - * Since the EMAC will reset to point to the start of transmit - * descriptor list, the buffer queues may have to be reset after this - * call. - * @param[in] pD driver private state info specific to this instance - */ - void (*abortTx)(void* pD); - - /** - * Get state of transmitter - * @param[in] pD driver private state info specific to this instance - * @return 1 if active - * @return 0 if idle or pD equal NULL - */ - uint32_t (*transmitting)(void* pD); - - /** - * Enable the transmit circuit. This will be done automatically when - * call startTx, but it may be desirable to call this earlier, since - * some functionality depends on transmit being enabled. - * @param[in] pD driver private state info specific to this instance - */ - void (*enableTx)(void* pD); - - /** - * Get state of transmision enabled - * @param[in] pD driver private state info specific to this instance - * @return 1 if transmission enabled - * @return 0 if transmission disabled or pD equal NULL - */ - uint32_t (*getTxEnabled)(void* pD); - - /** - * Get the content of EMAC transmit status register - * @param[out] status pointer to struct with fields for each flag - * @param[in] pD driver private state info specific to this instance - * @return 0 if no status bits set or status equal NULL - * @return number raw Tx status value read - */ - uint32_t (*getTxStatus)(void* pD, CEDI_TxStatus* status); - - /** - * Reset the bits of EMAC transmit status register as selected in - * resetStatus - * @param[in] resetStatus OR'd combination of CEDI_TXS_ bit-flags - * @param[in] pD driver private state info specific to this instance - */ - void (*clearTxStatus)(void* pD, uint32_t resetStatus); - - /** - * Enable credit-based shaping (CBS) on the specified queue. If - * already enabled then first disables, sets a new idle slope value - * for the queue, and re-enables CBS - * @param[in] idleSlope new idle slope value (in bytes/sec) - * @param[in] pD driver private state info specific to this instance - * @param[in] qSel if =0 selects highest priority queue (queue A), if =1 selects next-highest priority queue (queue B) - * @return EOK if successful - * @return ENOTSUP if CBS not present in h/w config - * @return EINVAL if priority queueing not enabled (i.e. only one Tx queue) or invalid parameter - */ - uint32_t (*enableCbs)(void* pD, uint8_t qSel, uint32_t idleSlope); - - /** - * Disable CBS on the specified queue - * @param[in] pD driver private state info specific to this instance - * @param[in] qSel if =0 selects highest priority queue (queue A), if =1 selectsnext-highest priority queue (queue B) - */ - void (*disableCbs)(void* pD, uint8_t qSel); - - /** - * Read CBS setting for the specified queue. - * @param[out] enable returns: 1 if CBS enabled for the specified queue 0 if not enabled - * @param[out] idleSlope pointer for returning the idleSlope value for selected queue. - * @param[in] pD driver private state info specific to this instance - * @param[in] qSel if =0 selects highest priority queue (queue A), if =1 selects next-highest priority queue (queue B) - * @return EOK for success - * @return ENOTSUP if CBS not present in h/w config - * @return EINVAL for invalid pointer - */ - uint32_t (*getCbsQSetting)(void* pD, uint8_t qSel, uint8_t* enable, uint32_t* idleSlope); - - /** - * Enable/disable the inter-packet gap (IPG) stretch function. - * @param[in] enable if =1 then enable IPG stretch, if =0 then disable - * @param[in] divisor after multiplying previous frame length, divide by (divisor+1) - if result>96 bits, - * this is used for the Tx IPG. Ignored if enable equal 0. - * @param[in] pD driver private state info specific to this instance - * @param[in] multiplier multiplying factor applied to previous Tx frame length. Ignored if enable equal 0. - * @return EOK if successful - * @return EINVAL if pD equal NULL - */ - uint32_t (*setIpgStretch)(void* pD, uint8_t enable, uint8_t multiplier, uint8_t divisor); - - /** - * Read the inter-packet gap (IPG) stretch settings. - * @param[out] enable pointer for returning enabled state: returns 1 if IPG stretch enabled, 0 if disabled. - * @param[out] divisor pointer for returning IPG divisor - * @param[in] pD driver private state info specific to this instance - * @param[out] multiplier pointer for returning IPG multiplying factor - * @return EOK if successful - * @return EINVAL if any parameter equal NULL - */ - uint32_t (*getIpgStretch)(void* pD, uint8_t* enable, uint8_t* multiplier, uint8_t* divisor); - - /** - * Identify max Rx pkt size for queues - determined by size of Rx - * packet buffer (if using full store & forward mode), and the - * current maximum frame size, e.g. 1518, 1536 or jumbo frame. - * @param[out] maxSize pointer for returning max frame size same for each Rx queue - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if NULL parameters - */ - uint32_t (*calcMaxRxFrameSize)(void* pD, uint32_t* maxSize); - - /** - * Add a buffer (size determined by rxBufLength in CEDI_Config) to - * the end of the receive buffer queue. This function is intended to - * be used during setting up the receive buffers, and should not be - * called while Rx is enabled or unread data remains in the queue. - * Note that one extra descriptor is reserved, to provide wrap-around - * protection (must always have one used bit set). - * @param[in] init if >0 then initialise the buffer data to all zeros - * @param[in] buf pointer to address of buffer. Checked for word-alignment in 64/128-bit width cases. - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of the Rx queue - * @return EOK if successful - * @return EINVAL if invalid queueNum, buffer alignment, or bufStart pointer/addresses - */ - uint32_t (*addRxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* buf, uint8_t init); - - /** - * Get the total number of buffers/descriptors present in the - * specified Rx queue. - * @param[out] numBufs pointer for returning number of descriptors - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of the Rx queue - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*numRxBufs)(void* pD, uint8_t queueNum, uint16_t* numBufs); - - /** - * Get the number of buffers/descriptors marked "used" in the - * specified Rx queue, i.e. those holding unread data. - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of the Rx queue - * @return 0 if invalid parameter or NULL pointer - * @return number of used buffers - */ - uint32_t (*numRxUsed)(void* pD, uint8_t queueNum); - - /** - * Read first unread descriptor (at tail of queue): if new data is - * available it swaps out the buffer and replaces it with a new one, - * clears the descriptor for re-use, then updates the driver queue- - * pointer. Checks for Start Of Frame (SOF) and End Of Frame (EOF) - * flags in the descriptors, passing back in status parameter. If EOF - * set, the descriptor status is returned via rxDescStat. Struct - * fields: uint32_t rxDescStat - Rx descriptor status word - * uint8_t status - Rx data status, one of the following values: - * CEDI_RXDATA_SOF_EOF :data available, single-buffer frame (SOF & - * EOF set) CEDI_RXDATA_SOF_ONLY - * :data available, start of multi-buffer frame - * CEDI_RXDATA_NO_FLAG :data available, intermediate buffer of - * multi- buffer frame - * CEDI_RXDATA_EOF_ONLY :data available, end of multi-buffer frame - * CEDI_RXDATA_NODATA :no data available CEDI_TimeStampData - * rxTsData - Rx descriptor timestamp when valid - * (rxTsData->tsValid will be set to 1) - * @param[in] init if >0 then initialise the (new) buffer data to all zeros. Ignored if no data available. - * @param[out] descData pointer for returning status & descriptor data - * @param[in,out] buf pointer to address of memory for new buffer to add to Rx descriptor queue; if data is available the buffer addresses for this are returned in buf, else if no data available then the new buffer can be re-used. Physical address of buffer is checked for word-alignment in 64/128-bit width cases. - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of the Rx queue - * @return EOK if successful - * @return EINVAL if invalid queueNum, buf, rxDescStat or status parameters - */ - uint32_t (*readRxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* buf, uint8_t init, CEDI_RxDescData* descData); - - /** - * Decode the Rx descriptor status into a bit-field struct. Note - * that most of these fields are only valid when End Of Frame bit15 - * is set - see hardware user guide - * @param[in] rxDStatWord - Rx descriptor status word - * @param[in] pD driver private state info specific to this instance - * @param[out] rxDStat pointer to bit-field struct for decoded status fields - */ - void (*getRxDescStat)(void* pD, uint32_t rxDStatWord, CEDI_RxDescStat* rxDStat); - - /** - * Provides the size of Rx descriptor calculated for current - * configuration. - * @param[out] rxDescSize - pointer to Rx descriptor size - * @param[in] pD driver private state info specific to this instance - */ - void (*getRxDescSize)(void* pD, uint32_t* rxDescSize); - - /** - * Get state of receiver - * @param[in] pD driver private state info specific to this instance - * @return 1 if enabled - * @return 0 if disabled or pD equal NULL - */ - uint32_t (*rxEnabled)(void* pD); - - /** - * Enable the receive circuit. - * @param[in] pD driver private state info specific to this instance - */ - void (*enableRx)(void* pD); - - /** - * Disable the receive circuit. - * @param[in] pD driver private state info specific to this instance - */ - void (*disableRx)(void* pD); - - /** - * Remove a buffer from the end of the receive buffer queue. This - * function is intended to be used when shutting down the driver, - * prior to deallocating the receive buffers, and should not be - * called while Rx is enabled or unread data remains in the queue. - * @param[out] buf pointer to struct for returning virtual and physical addresses of buffer. - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of the Rx queue - * @return EOK if successful - * @return ENOENT if no buffers left to free (mechanical success) - * @return EINVAL if invalid queueNum - */ - uint32_t (*removeRxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* buf); - - /** - * Reset Rx buffer descriptor list to initial empty state (if - * ptrsOnly=0), clearing all descriptors. For use after a fatal - * error. Disables receive circuit. - * @param[in] ptrsOnly "flag to allow full queue to be reset after link down/up (enableRx). - * if =1 then only reset tail & stop pointers and clear used bits" - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of the Rx queue - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*resetRxQ)(void* pD, uint8_t queueNum, uint8_t ptrsOnly); - - /** - * Return the content of EMAC receive status register - * @param[out] status pointer to struct with fields for each flag - * @param[in] pD driver private state info specific to this instance - * @return 1 if any flags set - * @return 0 if not or status equal NULL - */ - uint32_t (*getRxStatus)(void* pD, CEDI_RxStatus* status); - - /** - * Reset the bits of EMAC receive status register as selected in - * resetStatus - * @param[in] resetStatus OR'd combination of CEDI_RXS_ bit-flags - * @param[in] pD driver private state info specific to this instance - */ - void (*clearRxStatus)(void* pD, uint32_t resetStatus); - - /** - * Enable/disable header-data split feature. When enabled, frame - * L2/L3/L4 headers will written to separate buffer, before data - * starts in a second buffer (if not zero payload) - * @param[in] enable if =1 then enable; if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK if success - * @return EINVAL if invalid parameter - */ - uint32_t (*setHdrDataSplit)(void* pD, uint8_t enable); - - /** - * Read enable/disable status for header-data split feature - * @param[out] enable pointer for returning enabled status - * @param[in] pD driver private state info specific to this instance - * @return EOK successful - * @return EINVAL if invalid parameter - */ - uint32_t (*getHdrDataSplit)(void* pD, uint8_t* enable); - - /** - * Enable/disable Receive Segment Coalescing function. When enabled, - * consecutive TCP/IP frames on a priority queue will be combined to - * form a single large frame - * @param[in] queue priority queue to enable or disable RSC on - * @param[in] enable if =1 enable RSC on selected priority queue(s); else disable it - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if feature not available - * @return EINVAL for invalid parameter - */ - uint32_t (*setRscEnable)(void* pD, uint8_t queue, uint8_t enable); - - /** - * Read enabled status of RSC on a specified priority queue - * @param[in] queue priority queue to read RSC enabled status for - * @param[out] enable pointer for returning enabled status - * @param[in] pD driver private state info specific to this instance - * @return EOK successful - * @return ENOTSUP if feature not available - * @return EINVAL if invalid parameter - */ - uint32_t (*getRscEnable)(void* pD, uint8_t queue, uint8_t* enable); - - /** - * "Set/Clear Mask of Receive Segment Coalescing disabling. When mask - * is set and RSC is enabled, the RSC operation is not disabled by - * receipt of frame with an end-coalesce flag set (SYN/FIN/RST/URG)" - * @param[in] pD driver private state info specific to this instance - * @param[in] setMask if =1 prevents RSC disabling by end-coalesce flags (SYN/FIN/RST/URG) - applies to all queues - * @return EOK for success - * @return ENOTSUP if feature not available - * @return EINVAL for invalid pointer - */ - uint32_t (*setRscClearMask)(void* pD, uint8_t setMask); - - /** - * Set specific address register to the given address value - * @param[in] specFilterType flag specifying whether to use MAC source or destination address to be compared for filtering. Source filter when =1. - * @param[in] addrNum number of specific address filter, in range 1 - num_spec_add_filters - * @param[in] addr pointer to the 6-byte MAC address value to write - * @param[in] pD driver private state info specific to this instance - * @param[in] byteMask Bits masking out bytes of specific address from comparison. - * @return EOK if success - * @return ENOTSUP if no specific address registers available - * @return EINVAL if invalid parameter - */ - uint32_t (*setSpecificAddr)(void* pD, uint8_t addrNum, CEDI_MacAddress* addr, uint8_t specFilterType, uint8_t byteMask); - - /** - * Get the value of a specific address register destination address - * for filtering. When set to 1 use source address. - * @param[out] specFilterType flag specifying whether to use MAC source or destination address to be - * compared for filtering. =1 for source address - * @param[in] addrNum number of specific address filter, in range 1 - num_spec_add_filters - * @param[out] addr pointer to a 6-byte MAC address struct for returning the address value - * @param[in] pD driver private state info specific to this instance - * @param[out] byteMask "Bits masking out bytes of specific address from comparison. When high, - * the associated address byte will be ignored. e.g. LSB of byteMask=1 - * implies first byte received should not be compared." - * @return EOK if success - * @return ENOTSUP if no specific address registers available - * @return EINVAL if invalid parameter - */ - uint32_t (*getSpecificAddr)(void* pD, uint8_t addrNum, CEDI_MacAddress* addr, uint8_t* specFilterType, uint8_t* byteMask); - - /** - * Set the specific address 1 mask register to the given value, - * allowing address matching against a portion of the specific - * address 1 register - * @param[in] mask pointer to the address mask value to write - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 - * @return EINVAL if mask equal NULL - */ - uint32_t (*setSpecificAddr1Mask)(void* pD, CEDI_MacAddress* mask); - - /** - * Get the value of specific address 1 mask register - * @param[out] mask pointer to a 6-byte MAC address struct for returning the mask value - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 - * @return EINVAL if mask equal NULL - */ - uint32_t (*getSpecificAddr1Mask)(void* pD, CEDI_MacAddress* mask); - - /** - * Disable the specific address match stored at given register, by - * writing 0 to lower address register - * @param[in] addrNum - number of specific address filters, in range 1 - num_spec_add_filters - * @param[in] pD - driver private state info specific to this instance - * @return EOK if successful - * @return ENOTSUP if (CEDI_DesignCfg.num_spec_add_filters==0) - * @return EINVAL if ((addrNum==0) || (addrNum>CEDI_DesignCfg.num_spec_add_filters)) - */ - uint32_t (*disableSpecAddr)(void* pD, uint8_t addrNum); - - /** - * En/Disable Type ID match field of the specified register, and set - * type Id value if enabling - * @param[in] typeId the Type ID match value to write ignored if enable equal 0 - * @param[in] enable if =1 enables the type matching for this ID, if =0 then disables type matching for this ID - * @param[in] matchSel number of TypeID Match register, range 1 - 4 - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if matchSel invalid - */ - uint32_t (*setTypeIdMatch)(void* pD, uint8_t matchSel, uint16_t typeId, uint8_t enable); - - /** - * Read the specified Type ID match register settings - * @param[out] typeId pointer for returning the Type ID match value read ignored if disabled - * @param[out] enable "pointer for returning enabled status: equal 1 if typeId matching is - * enabled for this register, equal 0 if disabled" - * @param[in] matchSel number of TypeID Match register, range 1 - 4 - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if matchSel invalid - */ - uint32_t (*getTypeIdMatch)(void* pD, uint8_t matchSel, uint16_t* typeId, uint8_t* enable); - - /** - * En/disable reception of unicast frames when hash register matched - * @param[in] enable if =1 enables reception, if =0 then disables - * @param[in] pD driver private state info specific to this instance - */ - void (*setUnicastEnable)(void* pD, uint8_t enable); - - /** - * Return state of unicast frame matching - * @param[out] enable equal 1 if reception enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getUnicastEnable)(void* pD, uint8_t* enable); - - /** - * En/disable reception of multicast frames when hash register - * matched - * @param[in] enable if =1 enables, if =0 then disables - * @param[in] pD driver private state info specific to this instance - */ - void (*setMulticastEnable)(void* pD, uint8_t enable); - - /** - * Return state of multicast frame matching - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getMulticastEnable)(void* pD, uint8_t* enable); - - /** - * Dis/Enable receipt of broadcast frames - * @param[in] pD driver private state info specific to this instance - * @param[in] reject if =0 broadcasts are accepted, if =1 they are rejected. - */ - void (*setNoBroadcast)(void* pD, uint8_t reject); - - /** - * Return broadcast rejection setting - * @param[in] pD driver private state info specific to this instance - * @param[out] reject returns 0 if broadcasts are accepted, 1 if they are rejected - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getNoBroadcast)(void* pD, uint8_t* reject); - - /** - * En/Disable receipt of only frames which have been VLAN tagged - * @param[in] enable if =1 reject non-VLAN-tagged frames, if =0 then accept - * @param[in] pD driver private state info specific to this instance - */ - void (*setVlanOnly)(void* pD, uint8_t enable); - - /** - * Return VLAN-tagged filter setting - * @param[out] enable returns 1 if non-VLAN-tagged frames rejected - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getVlanOnly)(void* pD, uint8_t* enable); - - /** - * En/Disable stacked VLAN processing mode. - * @param[in] enable if =1 enables stacked VLAN processing, if =0 disables it - * @param[in] pD driver private state info specific to this instance - * @param[in] vlanType sets user defined VLAN type for matching first VLAN tag. Ignored if enable equal 0. - */ - void (*setStackedVlanReg)(void* pD, uint8_t enable, uint16_t vlanType); - - /** - * Reads stacked VLAN register settings. - * @param[out] enable pointer for returning Enabled field equal 1 if enabled equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @param[out] vlanType pointer for returning VLAN type field - */ - void (*getStackedVlanReg)(void* pD, uint8_t* enable, uint16_t* vlanType); - - /** - * En/Disable copy all frames mode - * @param[in] enable if =1 enables copy all frames mode, if =0 then this is disabled - * @param[in] pD driver private state info specific to this instance - */ - void (*setCopyAllFrames)(void* pD, uint8_t enable); - - /** - * Get "copy all" setting - * @param[out] enable equal 1 if copy all frames mode enabled equal 0 if this is disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getCopyAllFrames)(void* pD, uint8_t* enable); - - /** - * Set the hash address register. - * @param[in] hAddrBot least significant 32 bits of hash register - * @param[in] hAddrTop most significant 32 bits of hash register - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if pD equal NULL - */ - uint32_t (*setHashAddr)(void* pD, uint32_t hAddrTop, uint32_t hAddrBot); - - /** - * Read the hash address register. - * @param[out] hAddrBot pointer for returning least significant 32 bits of hash register - * @param[out] hAddrTop pointer for returning most significant 32 bits of hash register - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if any parameter equal NULL - */ - uint32_t (*getHashAddr)(void* pD, uint32_t* hAddrTop, uint32_t* hAddrBot); - - /** - * Enable/disable discard of frames with length shorter than given in - * length field - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setLenErrDiscard)(void* pD, uint8_t enable); - - /** - * Read enable/disable status for discard of frames with length - * shorter than given in length field. - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getLenErrDiscard)(void* pD, uint8_t* enable); - - /** - * Read numbers of screener, ethtype & compare registers - * @param[out] regNums points to a CEDI_NumScreeners struct for returning the numbers of registers - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*getNumScreenRegs)(void* pD, CEDI_NumScreeners* regNums); - - /** - * Write Rx frame matching values to a Type 1 screening register, for - * allocating to a priority queue. - * @param[in] regNum Type 1 register number, range 0 to CEDI_DesignCfg.num_type1_screeners-1 - * @param[in] regVals points to a CEDI_T1Screen struct with the match parameters to be written - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*setType1ScreenReg)(void* pD, uint8_t regNum, CEDI_T1Screen* regVals); - - /** - * Read Rx frame matching values from a Type1 screening register - * @param[in] regNum Type 1 register number, range 0 to CEDI_DesignCfg.num_type1_screeners-1 - * @param[out] regVals points to a CEDI_T1Screen struct for returning the match parameters - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*getType1ScreenReg)(void* pD, uint8_t regNum, CEDI_T1Screen* regVals); - - /** - * Write Rx frame matching values to a Type 2 screening register, for - * allocating to a priority queue. - * @param[in] regNum Type 2 register number, range 0 to CEDI_DesignCfg.num_type2_screeners-1 - * @param[in] regVals points to a CEDI_T2Screen struct with the match parameters to be written - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*setType2ScreenReg)(void* pD, uint8_t regNum, CEDI_T2Screen* regVals); - - /** - * Read Rx frame matching values from a Type 2 screening register - * @param[in] regNum Type 2 register number, range 0 to CEDI_DesignCfg.num_type2_screeners-1 - * @param[out] regVals points to a CEDI_T2Screen struct for returning the match parameters - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*getType2ScreenReg)(void* pD, uint8_t regNum, CEDI_T2Screen* regVals); - - /** - * Write the ethertype compare value at the given index in the - * Ethertype registers - * @param[in] index Type 2 ethertype register number, range 0 to CEDI_DesignCfg.num_scr2_ethtype_regs-1 - * @param[in] eTypeVal Ethertype compare value to write - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*setType2EthertypeReg)(void* pD, uint8_t index, uint16_t eTypeVal); - - /** - * Read the ethertype compare value at the given index in the - * Ethertype registers - * @param[in] index Type 2 ethertype register number, range 0 to CEDI_DesignCfg.num_scr2_ethtype_regs-1 - * @param[out] eTypeVal pointer for returning the Ethertype compare value - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*getType2EthertypeReg)(void* pD, uint8_t index, uint16_t* eTypeVal); - - /** - * Write the compare value at the given index in the Type 2 compare - * register - * @param[in] index Type 2 compare register number, range 0 to CEDI_DesignCfg.num_scr2_compare_regs-1 - * @param[in] regVals points to a CEDI_T2Compare struct with the compare parameters to be written - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*setType2CompareReg)(void* pD, uint8_t index, CEDI_T2Compare* regVals); - - /** - * Read the compare value at the given index in the Type 2 compare - * register - * @param[in] index Type 2 compare register number, range 0 to CEDI_DesignCfg.num_scr2_compare_regs-1 - * @param[out] regVals points to a CEDI_T2Compare struct for returning the compare parameters - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if parameter invalid - */ - uint32_t (*getType2CompareReg)(void* pD, uint8_t index, CEDI_T2Compare* regVals); - - /** - * Enable/disable pausing after valid non-zero (non-PFC) pause frame - * received - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setPauseEnable)(void* pD, uint8_t enable); - - /** - * Read enable/disable of pausing after valid non-zero (non-PFC) - * pause frame received. - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getPauseEnable)(void* pD, uint8_t* enable); - - /** - * Transmit a normal pause frame - * @param[in] pD driver private state info specific to this instance - */ - void (*txPauseFrame)(void* pD); - - /** - * Transmit a pause frame with zero quantum value - * @param[in] pD driver private state info specific to this instance - */ - void (*txZeroQPause)(void* pD); - - /** - * Return the current value of received pause quantum - * @param[out] value returns transmit pause quantum value - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRxPauseQuantum)(void* pD, uint16_t* value); - - /** - * Set the pause quantum value to use when transmitting non-zero - * quantum pause frame. - * @param[in] qpriority quantum priority, the priority for the pause quantum - * @param[in] value transmit pause quantum value - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if invalid parameter - */ - uint32_t (*setTxPauseQuantum)(void* pD, uint16_t value, uint8_t qpriority); - - /** - * Read the non-zero transmit pause quantum value - * @param[in] qpriority quantum priority,the priority for the pause quantum - * @param[out] value returns transmit pause quantum value - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if invalid parameter - */ - uint32_t (*getTxPauseQuantum)(void* pD, uint16_t* value, uint8_t qpriority); - - /** - * Disable/Enable copying of valid Rx pause frames to memory. - * @param[in] disable if =1 disable, if =0 enable - * @param[in] pD driver private state info specific to this instance - */ - void (*setCopyPauseDisable)(void* pD, uint8_t disable); - - /** - * Read disable/enable state for copying of valid Rx pause frames to - * memory. - * @param[out] disable if =1 disabled, if =0 enabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getCopyPauseDisable)(void* pD, uint8_t* disable); - - /** - * Enable/disable PFC negotiation and reception of priority based - * pause frames. - * @param[in] enable if =1 enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setPfcPriorityBasedPauseRx)(void* pD, uint8_t enable); - - /** - * Read enable/disable state of reception for priority based pause - * frames, and negotiation state. value can be decoded with two - * constants: if (OR with CEDI_PFC_PBP_RX_EN) not equal 0 then - * PFC priority based pause frame Rx enabled if (OR with - * CEDI_PFC_PBP_NEG) not equal 0 then PFC priority based pause - * has been negotiated - * @param[out] enable returns combined enabled Rx state and negotiated state - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getPfcPriorityBasedPauseRx)(void* pD, uint8_t* enable); - - /** - * Transmit PFC Priority Based Pause Frame, taking field values as - * defined by setTxPfcPauseFrameFields. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if NULL pointer or not using full duplex mode or if transmission is disabled (mechanical success) - */ - uint32_t (*txPfcPriorityBasedPause)(void* pD); - - /** - * Set priority enable vector and zero quantum select vector fields - * of the Tx PFC Pause Frame (see User Guide for description) - * @param[in] priEnVector written to priority enable vector of PFC priority based pause frame - * @param[in] zeroQSelVector selects pause quantum fields to set to zero - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if pD equal NULL - */ - uint32_t (*setTxPfcPauseFrameFields)(void* pD, uint8_t priEnVector, uint8_t zeroQSelVector); - - /** - * Read priority enable vector and zero quantum select vector fields - * selected by setTxPfcPauseFrameFields. - * @param[out] priEnVector pointer for returning priority enable vector to be written to PFC priority based pause frame - * @param[out] zeroQSelVector pointer for returning vector selecting pause quantum fields to set to zero - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if any parameter equal NULL - */ - uint32_t (*getTxPfcPauseFrameFields)(void* pD, uint8_t* priEnVector, uint8_t* zeroQSelVector); - - /** - * Set Enable bit for multiple PFC pause quantums, one per pause - * priority. - * @param[in] enMultiPfcPause set this field to 1 to enable multiple PFC pause quantums. - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if pD equal NULL - */ - uint32_t (*setEnableMultiPfcPauseQuantum)(void* pD, uint8_t enMultiPfcPause); - - /** - * Get the Enable bit for multiple PFC pause quantums, one per pause - * priority. - * @param[out] enMultiPfcPause equal 1 if multiple PFC pause quantums enabled - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if any parameter equal NULL - */ - uint32_t (*getEnableMultiPfcPauseQuantum)(void* pD, uint8_t* enMultiPfcPause); - - /** - * Enable/disable detection of unicast PTP frames. - * @param[in] enable if =1 enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setUnicastPtpDetect)(void* pD, uint8_t enable); - - /** - * Read enable/disable state for detection of unicast PTP frames. - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getUnicastPtpDetect)(void* pD, uint8_t* enable); - - /** - * Set Unicast IP destination address for detection of PTP Rx frames. - * Unicast PTP frame recognition must be disabled. - * @param[in] rxAddr IP destination address - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOTSUP if unicast PTP frame recognition enabled - * @return EINVAL if pD = NULL - */ - uint32_t (*setPtpRxUnicastIpAddr)(void* pD, uint32_t rxAddr); - - /** - * Read Unicast IP destination address for detection of PTP Rx - * frames. - * @param[out] rxAddr returns IP destination address - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getPtpRxUnicastIpAddr)(void* pD, uint32_t* rxAddr); - - /** - * Set Unicast IP destination address for detection of PTP Tx frames. - * Unicast PTP frame recognition must be disabled. - * @param[in] txAddr IP destination address - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOTSUP if unicast PTP frame recognition enabled - * @return EINVAL if pD = NULL - */ - uint32_t (*setPtpTxUnicastIpAddr)(void* pD, uint32_t txAddr); - - /** - * Returns Unicast IP destination address for detection of PTP Tx - * frames. - * @param[out] txAddr returns IP destination address - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getPtpTxUnicastIpAddr)(void* pD, uint32_t* txAddr); - - /** - * Write 1588 timer registers. - * @param[in] pD driver private state info specific to this instance - * @param[in] time pointer to CEDI_1588TimerVal struct with values to write to timer registers - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - * @return EINVAL if either parameter equal NULL, or nanosecs >0x3FFFFFFF - */ - uint32_t (*set1588Timer)(void* pD, CEDI_1588TimerVal* time); - - /** - * Read 1588 timer registers. - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_1588TimerVal struct for returning timer registers contents - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - * @return EINVAL if either parameter NULL - */ - uint32_t (*get1588Timer)(void* pD, CEDI_1588TimerVal* time); - - /** - * Adjust the 1588 timer by adding or subtracting the specified - * number of nanoseconds. - * @param[in] nSecAdjust nanoseconds to adjust timer by: - if =1, enable time stamp storing, else disable (restore normal operation) - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - * @return EINVAL if invalid parameter - */ - uint32_t (*adjust1588Timer)(void* pD, int32_t nSecAdjust); - - /** - * Set 1588 timer initial and alternative increments, and when to - * switch to alternative increment. The initial, or normal, increment - * is how many nanoseconds are added to the timer value on each pclk - * or tsu_clk cycle (if tsu_clk equal 1 in DesignCfgReg5). If - * altIncCount>0, after altIncCount increments the altNanoSInc value - * is used for one cycle, then the increment returns to the initial - * value. See EMAC User Guide [01] for further description. - * @param[in] incSettings pointer to CEDI_TimerIncrement struct for defining how much to increment the timer each clock cycle - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - * @return EINVAL if either parameter equal NULL - */ - uint32_t (*set1588TimerInc)(void* pD, CEDI_TimerIncrement* incSettings); - - /** - * Read 1588 timer increment settings. - * @param[out] incSettings pointer to a CEDI_TimerIncrement struct for returning how the timer increment values - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*get1588TimerInc)(void* pD, CEDI_TimerIncrement* incSettings); - - /** - * Write TSU timer comparison value. - * @param[in] pD driver private state info specific to this instance - * @param[in] time pointer to CEDI_TsuTimerVal struct with values to write to comparison registers - * @return EOK for success - * @return ENOTSUP if tsu equal 0, or nanosecs >0x003FFFFF - */ - uint32_t (*setTsuTimerCompVal)(void* pD, CEDI_TsuTimerVal* time); - - /** - * Read TSU timer comparison value. - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_TsuTimerVal struct for returning comparison registers settings - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - * @return EINVAL if either param equal NULL - */ - uint32_t (*getTsuTimerCompVal)(void* pD, CEDI_TsuTimerVal* time); - - /** - * Read 1588 timer value latched when SFD of PTP transmit primary - * event crosses MII interface. - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*getPtpFrameTxTime)(void* pD, CEDI_1588TimerVal* time); - - /** - * Read 1588 timer value latched when SFD of PTP receive primary - * event crosses MII interface. - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*getPtpFrameRxTime)(void* pD, CEDI_1588TimerVal* time); - - /** - * Read 1588 timer value latched when SFD of PTP transmit peer event - * crosses MII interface. - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*getPtpPeerFrameTxTime)(void* pD, CEDI_1588TimerVal* time); - - /** - * Read 1588 timer value latched when SFD of PTP receive peer event - * crosses MII interface. - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*getPtpPeerFrameRxTime)(void* pD, CEDI_1588TimerVal* time); - - /** - * Read nanoseconds and seconds (lo & hi words) from 1588 Timer Sync - * Strobe registers - * @param[in] pD driver private state info specific to this instance - * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*get1588SyncStrobeTime)(void* pD, CEDI_1588TimerVal* time); - - /** - * Enable/disable use of external time stamp port. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if ext_tsu_timer equal 0 - * @return EINVAL if invalid parameter - */ - uint32_t (*setExtTsuPortEnable)(void* pD, uint8_t enable); - - /** - * Read enable status for use of external time stamp port. - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getExtTsuPortEnable)(void* pD, uint8_t* enable); - - /** - * Enable/disable one-step Tx sync mode in which timestamp field of - * every transmitted 1588 sync frame is replaced with the current TSU - * timestamp. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return ENOTSUP if tsu equal 0 - * @return EINVAL if invalid parameter - */ - uint32_t (*set1588OneStepTxSyncEnable)(void* pD, uint8_t enable); - - /** - * Read enable/disable state of one-step 1588 Tx sync mode. - * @param[out] enable pointer for returning state equal 1 if enabled equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*get1588OneStepTxSyncEnable)(void* pD, uint8_t* enable); - - /** - * Set the descriptor time stamp mode. - * @param[in] txMode TX Descriptor timestamp insertion mode - * @param[in] rxMode RX Descriptor timestamp insertion mode - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if pD is NULL/parameters out of range - */ - uint32_t (*setDescTimeStampMode)(void* pD, CEDI_TxTsMode txMode, CEDI_RxTsMode rxMode); - - /** - * Get the descriptor time stamp mode. - * @param[out] txMode TX Descriptor timestamp insertion mode - * @param[out] rxMode RX Descriptor timestamp insertion mode - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if pD is NULL - */ - uint32_t (*getDescTimeStampMode)(void* pD, CEDI_TxTsMode* txMode, CEDI_RxTsMode* rxMode); - - /** - * Enable/disable storing of nanoseconds field of Rx time stamp in - * CRC field of received frame. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if tsu equal 0 - */ - uint32_t (*setStoreRxTimeStamp)(void* pD, uint8_t enable); - - /** - * Read Enable/disable state for storing nanoseconds Rx time stamp in - * CRC field of received frame. - * @param[out] enable equal 1 if time stamp storing enabled equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getStoreRxTimeStamp)(void* pD, uint8_t* enable); - - /** - * Does a PCS reset. After this, software can monitor getPcsReady to - * determine when this has finished. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_pcs defined - */ - uint32_t (*resetPcs)(void* pD); - - /** - * Read PCS software reset bit, which goes high when resetPcs is - * called, and returns low when the reset has completed, provided PCS - * is enabled. - * @param[out] ready pointer for returning 1 when PCS ready, i.e. reset has gone low or 0 if still in reset. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if PCS not enabled - * @return EINVAL for invalid pointer - */ - uint32_t (*getPcsReady)(void* pD, uint8_t* ready); - - /** - * Enables and restarts auto-negotiation after writing the specified - * abilities to the auto-negotiation advertisement register. After - * this, normal progress of auto-negotiation will lead to a lpPageRx - * callback, which includes the ability register data received from - * the link partner. - * @param[in] advDat pointer to CEDI_AnAdvPage struct for setting the advertised abilities register - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_pcs defined or in SGMII mode - * @return EBUSY if auto-negotiation already in progress - * @return EINVAL if NULL parameter, invalid struct fields or completion event not enabled - */ - uint32_t (*startAutoNegotiation)(void* pD, CEDI_AnAdvPage* advDat); - - /** - * Enable/disable PCS auto-negotiation functionality. If auto- - * negotiation is in progress, disabling will halt it. If enabling - * while underway, an error is returned. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EBUSY if enable = 1 when auto-negotiation is under way - * @return EOK for success - * @return ENOTSUP if in SGMII mode - * @return EINVAL if pD equal NULL - */ - uint32_t (*setAutoNegEnable)(void* pD, uint8_t enable); - - /** - * Read enable/disable of PCS auto-negotiation functionality. - * @param[out] enable pointer for returning state, equal 1 if enabled equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter - */ - uint32_t (*getAutoNegEnable)(void* pD, uint8_t* enable); - - /** - * If auto-negotiation is enabled, this reads the status of - * connection to link partner, else it reads the synchronisation - * status. If link goes down, status remains low until this is read. - * The driver will remember the low condition when read from register - * (by this or other PCS functions), and this will only update to - * current state when this function is called (i.e. after reading the - * value to return), or when link status is reported via the - * AnComplete callback. Therefore, if getLinkStatus reports link - * down, the function should be called again if the current status is - * required. - * @param[out] status pointer returning 1 if link up (or sync) 0 if link down. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getLinkStatus)(void* pD, uint8_t* status); - - /** - * Read the remote fault status reported by link partner. Driver will - * remember the high state when read from register, and only reset - * when this function is called. - * @param[out] status pointer returning 1 if remote fault indicated by link partner, 0 otherwise. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getAnRemoteFault)(void* pD, uint8_t* status); - - /** - * Read the auto-negotiation complete status. Completion will also be - * reported by the anComplete callback, provided the - * CEDI_EV_PCS_AN_COMPLETE interrupt is enabled. - * @param[out] status pointer returning 1 if auto-negotiation complete 0 if incomplete. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL for invalid pointer - */ - uint32_t (*getAnComplete)(void* pD, uint8_t* status); - - /** - * Set advertisement base page fields. - * @param[in] advDat - pointer to advertisement register data - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter - */ - uint32_t (*setAnAdvPage)(void* pD, CEDI_AnAdvPage* advDat); - - /** - * Get advertisement base page fields, extracted into a - * CEDI_AnAdvPage struct - * @param[out] advDat - pointer for returning the advertisement register data - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter - */ - uint32_t (*getAnAdvPage)(void* pD, CEDI_AnAdvPage* advDat); - - /** - * Get link partner ability page fields, extracted into a - * CEDI_LpAbilityPage struct. This is a union of two different - * structs, since the format depends on whether SGMII mode is in use - * (network config bit 27) - * @param[out] lpAbl pointer for returning the link partner ability data - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter - */ - uint32_t (*getLpAbilityPage)(void* pD, CEDI_LpAbilityPage* lpAbl); - - /** - * Read flag from auto-negotiation expansion register, indicating a - * base or next page has been received from the link partner. - * @param[in] pD driver private state info specific to this instance - * @return 1 if page received and no_pcs not defined - * @return 0 if page not received or invalid pointer - */ - uint32_t (*getPageRx)(void* pD); - - /** - * Set next page register fields for auto-negotiation with fields - * specified in a CEDI_AnNextPage struct. - * @param[in] npDat - pointer to struct containing next page data to transmit - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter or invalid struct fields - */ - uint32_t (*setNextPageTx)(void* pD, CEDI_AnNextPage* npDat); - - /** - * Read next page register field data. - * @param[out] npDat - pointer to struct for returning next page register data. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter - */ - uint32_t (*getNextPageTx)(void* pD, CEDI_AnNextPage* npDat); - - /** - * Read next page data received from link partner. - * @param[out] npDat - pointer to CEDI_LpNextPage struct for returning link partner next page data. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) - * @return EINVAL if NULL parameter - */ - uint32_t (*getLpNextPage)(void* pD, CEDI_LpNextPage* npDat); - - /** - * Get PCS PHY upper ID (= EMAC Module ID) & PCS PHY lower ID (= EMAC - * Rev) - * @param[in] pD driver private state info specific to this instance - * @param[out] phyId composed of PCS PHY upper ID (= EMAC Module ID) in the upper 16 bits, and PCS PHY - * lower ID (= EMAC Rev) in the lower 16 bits. - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getPhyId)(void* pD, uint32_t* phyId); - - /** - * Enable/disable MDIO interface - * @param[in] enable if =1 enable MDIO interface, if =0 then disable it - * @param[in] pD driver private state info specific to this instance - */ - void (*setMdioEnable)(void* pD, uint8_t enable); - - /** - * Get en/disable state of MDIO interface - * @param[in] pD driver private state info specific to this instance - * @return 1 if MDIO interface enabled - * @return 0 if MDIO interface disabled or pD equal NULL, or NULL parameter - */ - uint32_t (*getMdioEnable)(void* pD); - - /** - * Initiate a write or set address operation on the MDIO interface. - * Clause 45 devices require a call to set the register address (if - * this is changing since last access), and then a write or read - * operation. The command writes to the shift register, which starts - * output on the MDIO interface. Write completion is signalled by the - * phyManComplete callback, or by polling getMdioIdle. - * @param[in] addrData register address (if CEDI_MDIO_FLG_SET_ADDR) or data to write - * @param[in] phyAddr PHY address - * @param[in] flags Combination of 2 bit-flags: if CEDI_MDIO_FLG_CLAUSE_45 present, specifies - * clause 45 PHY (else clause 22); - * if CEDI_MDIO_FLG_SET_ADDR present, specifies a set address operation (else - * do a write operation) - if not clause 45, this will be ignored. - * @param[in] pD driver private state info specific to this instance - * @param[in] devReg device type (clause 45) or register address (clause 22) - enum CEDI_MdioDevType - * is available to specify the device type - */ - void (*phyStartMdioWrite)(void* pD, uint8_t flags, uint8_t phyAddr, uint8_t devReg, uint16_t addrData); - - /** - * Initiate a read operation on the MDIO interface. If clause 45, - * the register address will need to be set by a preceding - * phyStartMdioWrite call, unless same as for last operation. - * Completion is signalled by the phyManComplete callback, which will - * return the read data by a pointer parameter. Alternatively polling - * getMdioIdle will indicate when the operation completes, then - * getMdioReadDat will return the data. - * @param[in] phyAddr PHY address - * @param[in] flags Combination of 2 bit-flags: if CEDI_MDIO_FLG_CLAUSE_45 present, - * specifies clause 45 PHY (else clause 22); - * If CEDI_MDIO_FLG_INC_ADDR present, and clause 45, then address will be - * incremented after the read operation. - * @param[in] pD driver private state info specific to this instance - * @param[in] devReg device type (clause 45) or register address (clause 22) - enum CEDI_MdioDevType - * is available to specify the device type - */ - void (*phyStartMdioRead)(void* pD, uint8_t flags, uint8_t phyAddr, uint8_t devReg); - - /** - * Get data read from the PHY during a read operation. - * @param[out] readData PHY read data, from in lower 16 bits of maintenance register - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getMdioReadData)(void* pD, uint16_t* readData); - - /** - * Read status of PHY management logic - * @param[in] pD driver private state info specific to this instance - * @return 1 for idle (mechanical success) - * @return 0 for busy, or pD equal NULL - */ - uint32_t (*getMdioIdle)(void* pD); - - /** - * Copy the statistics registers contents into the statsRegs struct - * reserved by client - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_stats defined - */ - uint32_t (*readStats)(void* pD); - - /** - * Clear the statistics registers. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_stats defined - */ - uint32_t (*clearStats)(void* pD); - - /** - * Record snapshot of current statistics counts into snapshot - * registers. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_snapshot or no_stats defined - */ - uint32_t (*takeSnapshot)(void* pD); - - /** - * Define action taken when statistics registers are read - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_snapshot or no_stats defined - */ - uint32_t (*setReadSnapshot)(void* pD, uint8_t enable); - - /** - * Read state of ReadSnapshot flag - * @param[out] enable pointer for returning ReadSnapshot flag: if =1 then read - * snapshot is enabled; if =0 registers will show current statistics - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_snapshot or no_stats defined - */ - uint32_t (*getReadSnapshot)(void* pD, uint8_t* enable); - - /** - * Set Wake On LAN (WOL) register using CEDI_WakeOnLanReg struct - * @param[in] regVals pointer to CEDI_WakeOnLanReg struct for register values to set - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*setWakeOnLanReg)(void* pD, CEDI_WakeOnLanReg* regVals); - - /** - * Read Wake On LAN register using CEDI_WakeOnLanReg struct - * @param[out] regVals pointer to CEDI_WakeOnLanReg struct for returning WOL register contents - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*getWakeOnLanReg)(void* pD, CEDI_WakeOnLanReg* regVals); - - /** - * Enable/disable low power indication (LPI) transmission. - * @param[in] enable if =1 then enable, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*setLpiTxEnable)(void* pD, uint8_t enable); - - /** - * Get LPI transmission status - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid parameter - */ - uint32_t (*getLpiTxEnable)(void* pD, uint8_t* enable); - - /** - * Read LPI transitions & time in both Tx and Rx directions. The - * registers are all cleared on read. - * @param[out] lpiStats pointer to a CEDI_LpiStats struct for returning the LPI statistics. - * @param[in] pD driver private state info specific to this instance - * @return EOK if successful - * @return EINVAL if invalid parameter - */ - uint32_t (*getLpiStats)(void* pD, CEDI_LpiStats* lpiStats); - - /** - * Copies all design configuration register fields into a - * CEDI_DesignCfg struct declared by client software. - * @param[out] hwCfg pointer to struct for receiving configuration data - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if any parameters =NULL - */ - uint32_t (*getDesignConfig)(void* pD, CEDI_DesignCfg* hwCfg); - - /** - * Enable/disable writing to the statistics registers for debugging. - * @param[in] enable if =1 enable writing, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if no_stats defined - */ - uint32_t (*setWriteStatsEnable)(void* pD, uint8_t enable); - - /** - * Read enable/disable state of writing to the statistics registers - * for debugging. - * @param[out] enable pointer for returning state: equal 1 if writing enabled equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if no_stats defined - */ - uint32_t (*getWriteStatsEnable)(void* pD, uint8_t* enable); - - /** - * Increments all statistics registers contents by 1 for debugging. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if no_stats defined - */ - uint32_t (*incStatsRegs)(void* pD); - - /** - * Enable/disable back pressure to force collisions an all received - * frames in 10M or 100M half duplex mode. - * @param[in] enable if =1 enable back pressure, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setRxBackPressure)(void* pD, uint8_t enable); - - /** - * Read Enable/disable state of back pressure to force collisions an - * all received frames in 10M or 100M half duplex mode. - * @param[out] enable equal 1 if enabled, equal 0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRxBackPressure)(void* pD, uint8_t* enable); - - /** - * Enable/disable forcing collisions by PCS on transmit. - * @param[in] enable if =1 enable forcing collisions, if =0 then disable - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_pcs defined - */ - uint32_t (*setCollisionTest)(void* pD, uint8_t enable); - - /** - * Read enable/disable state for forcing collisions by PCS on - * transmit. - * @param[out] enable pointer for returning state: equal 1 if forcing collisions enabled, equal 0 if disabled. - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if no_pcs defined - */ - uint32_t (*getCollisionTest)(void* pD, uint8_t* enable); - - /** - * Enable/disable functionality to set backoff between collisions to - * one slot time. This helps test for too many retries, and also - * shortens pause countdown time in pause frame tests. - * @param[in] enable if =1 enable retry test, if =0 then disable - * @param[in] pD driver private state info specific to this instance - */ - void (*setRetryTest)(void* pD, uint8_t enable); - - /** - * Read enable/disable status of retry test functionality. - * @param[out] enable =1 if retry test enabled, =0 if disabled - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getRetryTest)(void* pD, uint8_t* enable); - - /** - * Write to the user_out_width user outputs. - * @param[in] pD driver private state info specific to this instance - * @param[in] outVal value to write to the user outputs - * @return EOK for success - * @return ENOTSUP if user_io not defined - * @return EINVAL if pD equal NULL - */ - uint32_t (*writeUserOutputs)(void* pD, uint16_t outVal); - - /** - * Read from the user_out_width user outputs. - * @param[in] pD driver private state info specific to this instance - * @param[out] outVal pointer for returning value read from the user outputs - * @return EOK for success - * @return ENOTSUP if user_io not defined - * @return EINVAL if NULL parameters - */ - uint32_t (*readUserOutputs)(void* pD, uint16_t* outVal); - - /** - * Set the state of the specified user output pin. - * @param[in] state level to set on the pin 1 for high, 0 for low - * @param[in] pin pin number to set, range 0 to user_out_width-1 - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if user_io not defined - * @return EINVAL if pin out of range, or pD equal NULL - */ - uint32_t (*setUserOutPin)(void* pD, uint8_t pin, uint8_t state); - - /** - * Read from the user_in_width user inputs. - * @param[in] pD driver private state info specific to this instance - * @param[out] inVal pointer for returning value read from the user inputs - * @return EOK for success - * @return ENOTSUP if user_io not defined - * @return EINVAL if NULL parameter - */ - uint32_t (*readUserInputs)(void* pD, uint16_t* inVal); - - /** - * Get the state of the specified user input pin. - * @param[out] state pointer for returning level present on the pin, 1 for high, 0 for low - * @param[in] pin pin number to read - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return ENOTSUP if user_io not defined - * @return EINVAL if pin out of range, or pD equal NULL - */ - uint32_t (*getUserInPin)(void* pD, uint8_t pin, uint8_t* state); - - /** - * Read the state of the MDIO pin - * @param[out] state 1 for high, 0 for low - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL for invalid pointer - */ - uint32_t (*getMdioInState)(void* pD, uint8_t* state); - - /** - * Direct read of register contents - * @param[in] offs address offset to register - * @param[out] data pointer for returning data read - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if offs out of range, or pD equal NULL - */ - uint32_t (*readReg)(void* pD, uint32_t offs, uint32_t* data); - - /** - * Direct write to register - * @param[in] offs address offset to register - * @param[in] data data to write - * @param[in] pD driver private state info specific to this instance - * @return EOK for success - * @return EINVAL if offs out of range, or pD equal NULL - */ - uint32_t (*writeReg)(void* pD, uint32_t offs, uint32_t data); - -} CEDI_OBJ; - -/** - * In order to access the CEDI APIs, the upper layer software must call - * this global function to obtain the pointer to the driver object. - * @return CEDI_OBJ* Driver Object Pointer - */ -extern CEDI_OBJ *CEDI_GetInstance(void); - -/** - * @} - */ - - -#endif /* _CEDI_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cps_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cps_v2.h deleted file mode 100644 index ca68fea7c9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cps_v2.h +++ /dev/null @@ -1,131 +0,0 @@ -/********************************************************************** - * copyright (C) 2011-2015 Cadence Design Systems - * All rights reserved. - *********************************************************************** - * cps_v2.h - * Interface for Cadence Platform Services (CPS), version 2 - * - * This is the "hardware abstraction layer" upon which all drivers are built. - * It must be implemented for each platform. - ***********************************************************************/ -#ifndef _CPS_H_ -#define _CPS_H_ - -#include "cdn_stdint.h" - -/**************************************************************************** - * Types - ***************************************************************************/ - -/** A lock handle */ -typedef void* CPS_LockHandle; - -/**************************************************************************** - * Prototypes - ***************************************************************************/ - -/** - * Check that sufficient locks are available - * @param[in] lockCount number of locks requested - * @return 0 on success (locks available) - * @return ENOENT if insufficient locks are available - */ -extern uint32_t CPS_ProbeLocks(uint32_t lockCount); - -/** - * Initialize a lock - * @param[out] lock where to store the allocated, initialized lock - * @return 0 on success (lock is allocated and initialized) - * @return ENOENT if insufficient locks are available - */ -extern uint32_t CPS_InitLock(CPS_LockHandle* lock); - -/** - * Free a lock - * @param[in] lock the lock - */ -extern void CPS_FreeLock(CPS_LockHandle lock); - -/** - * Lock a lock, pending the current thread/task if necessary until the lock is available - * @param[in] lock the lock - */ -extern uint32_t CPS_Lock(CPS_LockHandle lock); - -/** - * Unlock a lock, readying the next highest-priority thread/task pended on it if any - * @param[in] lock the lock - */ -extern uint32_t CPS_Unlock(CPS_LockHandle lock); - -/** - * Read a byte, bypassing the cache - * @param[in] address the address - * @return the byte at the given address - */ -extern uint8_t CPS_UncachedRead8(volatile uint8_t* address); - -/** - * Read a short, bypassing the cache - * @param[in] address the address - * @return the short at the given address - */ -extern uint16_t CPS_UncachedRead16(volatile uint16_t* address); - -/** - * Read a (32-bit) word, bypassing the cache - * @param[in] address the address - * @return the word at the given address - */ -extern uint32_t CPS_UncachedRead32(volatile uint32_t* address); - -/** - * Read a (32-bit) address value, bypassing the cache. - * This function is for reading an address value, i.e. something that - * is seen as an address by hardware, and therefore might need to be - * translated from a physical bus address to a CPU address. - * @param[in] location - * @return the CPU address of the physical bus address at the given (CPU) location - */ -extern uint32_t CPS_ReadPhysAddress32(volatile uint32_t* location); - -/** - * Write a byte to memory, bypassing the cache - * @param[in] address the address - * @param[in] value the byte to write - */ -extern void CPS_UncachedWrite8(volatile uint8_t* address, uint8_t value); - -/** - * Write a short to memory, bypassing the cache - * @param[in] address the address - * @param[in] value the short to write - */ -extern void CPS_UncachedWrite16(volatile uint16_t* address, uint16_t value); - -/** - * Write a (32-bit) word to memory, bypassing the cache - * @param[in] address the address - * @param[in] value the word to write - */ -extern void CPS_UncachedWrite32(volatile uint32_t* address, uint32_t value); - -/** - * Write a (32-bit) address value to memory, bypassing the cache. - * This function is for writing an address value, i.e. something that - * will be treated as an address by hardware, and therefore might need - * to be translated to a physical bus address. - * @param[in] location the (CPU) location where to write the address value - * @param[in] addrValue the address value to write - */ -extern void CPS_WritePhysAddress32(volatile uint32_t* location, uint32_t addrValue); - -/** - * Hardware specific memcpy. - * @param[in] src src address - * @param[in] dst destination address - * @param[in] size size of the copy - */ -extern void CPS_BufferCopy(volatile uint8_t *dst, volatile uint8_t *src, uint32_t size); - -#endif /* multiple inclusion protection */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_adc.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_adc.h deleted file mode 100644 index 21d3fca3a8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_adc.h +++ /dev/null @@ -1,228 +0,0 @@ -#if !defined (CY_ADC_H) -#define CY_ADC_H - -#include "cy_device_headers.h" - -#if defined (CY_IP_MXS28ADCCOMP) - -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - -/**< ADC PDL ID */ -#define CY_ADC_ID CY_PDL_DRV_ID(0x46U) - -/** -* \addtogroup group_comp_macros_interrupt_masks Interrupt Masks -* \{ -*/ - -/** ADC interrupt mask. */ -#define CY_ADC_CIC (MXS28ADCCOMP_INTR_INTERRUPT_CIC_Msk) - -/** \} group_comp_macros_interrupt_masks */ - - -/** ADC enable mask. */ -#define CY_ADC (MXS28ADCCOMP_PD_CTRL_PD_ADC_Msk) -/** GmC calibration mask. */ -#define CY_ADC_GMC_CAL (MXS28ADCCOMP_PD_CTRL_PD_ADC_GMC_CAL_Msk) -/** DC calibration mask. */ -#define CY_ADC_DC_CAL (MXS28ADCCOMP_PD_CTRL_PD_ADC_DC_CAL_Msk) - - - -/** The ADC error codes. */ -typedef enum -{ - CY_ADC_SUCCESS = 0x00u, /**< Successful */ - CY_ADC_BAD_PARAM = CY_ADC_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ - CY_ADC_UNKNOWN = CY_ADC_ID | CY_PDL_STATUS_ERROR | 0xFFu, /**< Unknown failure */ -} cy_en_adc_status_t; - -typedef enum -{ - CY_ADC_CIC_CLK_DIV2_1 = 0UL, /**< Divide by 1 for clock frequency 1024 kHz or 2048 kHz */ - CY_ADC_CIC_CLK_DIV2_2 = 1UL, /**< Divide by 2 for clock frequency 2048 kHz or 4096 kHz */ - CY_ADC_CIC_CLK_DIV2_1_SHIFT = 2UL, /**< Divide by 1 for clock frequency 1024 kHz or 2048 kHz shifted */ - CY_ADC_CIC_CLK_DIV2_2_SHIFT = 3UL /**< Divide by 2 for clock frequency 2048 kHz or 4096 kHz shifted */ -}cy_en_adc_cic_clk_div2_ctrl_t; - -typedef enum -{ - CY_ADC_CLK_DIV2_1 = 0UL, /**< Divide by 1 for clock frequency 1024 kHz or 2048 kHz */ - CY_ADC_CLK_DIV2_2 = 1UL /**< Divide by 2 for clock frequency 2048 kHz or 4096 kHz */ -}cy_en_adc_clk_in_div2_ctrl_t; - - -typedef struct -{ - cy_en_adc_clk_in_div2_ctrl_t clkDiv2; - uint16_t trigDelay; - bool trigClr; -} cy_stc_adc_cic_config_t; - -typedef struct -{ - cy_en_adc_clk_in_div2_ctrl_t clkInDiv2; - cy_stc_adc_cic_config_t * cicConfig; -} cy_stc_adc_config_t; - - -cy_en_adc_status_t Cy_ADC_Init(MXS28ADCCOMP_Type * base, cy_stc_adc_config_t const * config); -void Cy_ADC_Enable(MXS28ADCCOMP_Type * base, uint32_t pdMsk); -void Cy_ADC_Disable(MXS28ADCCOMP_Type * base, uint32_t pdMsk); - - - - -/******************************************************************************* -* Function Name: Cy_ADC_GetInterruptStatus -****************************************************************************//** -* -* Returns the interrupt status of the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \return -* The interrupt status. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_GetInterruptStatus -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_ADC_GetInterruptStatus(MXS28ADCCOMP_Type const * base) -{ - return (base->INTR & MXS28ADCCOMP_INTR_INTERRUPT_CIC_Msk); -} - - -/******************************************************************************* -* Function Name: Cy_ADC_ClearInterrupt -****************************************************************************//** -* -* Clears the interrupt status. -* -* \param base -* The pointer to the hardware ADC block. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_ClearInterrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_ADC_ClearInterrupt(MXS28ADCCOMP_Type * base, uint32_t interrupt) -{ - base->INTR = MXS28ADCCOMP_INTR_INTERRUPT_CIC_Msk; -} - - -/******************************************************************************* -* Function Name: Cy_ADC_SetInterrupt -****************************************************************************//** -* -* Sets the interrupt for the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_SetInterruptMask -* -*******************************************************************************/ -__STATIC_INLINE void Cy_ADC_SetInterrupt(MXS28ADCCOMP_Type * base, uint32_t interrupt) -{ - base->INTR_SET = MXS28ADCCOMP_INTR_INTERRUPT_CIC_Msk; -} - - -/******************************************************************************* -* Function Name: Cy_ADC_GetInterruptMask -****************************************************************************//** -* -* Returns the interrupt mask value of the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \return -* The interrupt mask value. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_SetInterruptMask -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_ADC_GetInterruptMask(MXS28ADCCOMP_Type const * base) -{ - return (base->INTR_MASK & MXS28ADCCOMP_INTR_INTERRUPT_CIC_Msk); -} - - -/******************************************************************************* -* Function Name: Cy_ADC_SetInterruptMask -****************************************************************************//** -* -* Sets an interrupt mask value for the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_SetInterruptMask -* -*******************************************************************************/ -__STATIC_INLINE void Cy_ADC_SetInterruptMask(MXS28ADCCOMP_Type * base, uint32_t interrupt) -{ - uint32_t interruptState = Cy_SysLib_EnterCriticalSection(); - base->INTR_MASK = (base->INTR_MASK & ~CY_ADC_CIC) | (interrupt & CY_ADC_CIC); - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_ADC_GetInterruptStatusMasked -****************************************************************************//** -* -* Returns the logical AND of the corresponding INTR and INTR_MASK fields -* in a single-load operation. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \return -* The masked interrupt status. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_ClearInterrupt -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_ADC_GetInterruptStatusMasked(MXS28ADCCOMP_Type const * base) -{ - return (base->INTR_MASKED & MXS28ADCCOMP_INTR_INTERRUPT_CIC_Msk); -} - - - -__STATIC_INLINE void Cy_ADC_SetTrigger(MXS28ADCCOMP_Type * base, uint32_t trigger) -{ - base->TRIGGER_SET = trigger & MXS28ADCCOMP_TRIGGER_SET_TR_CIC_Msk; -} - -__STATIC_INLINE void Cy_ADC_ClearTrigger(MXS28ADCCOMP_Type * base, uint32_t trigger) -{ - base->TRIGGER_CLR = trigger & MXS28ADCCOMP_TRIGGER_CLR_TR_CIC_Msk; -} - - - - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_ADCCOMP */ - -#endif /* (CY_ADC_H) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_comp.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_comp.h deleted file mode 100644 index 2afec5b83b..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_comp.h +++ /dev/null @@ -1,216 +0,0 @@ -#if !defined (CY_COMP_H) -#define CY_COMP_H - -#include "cy_device_headers.h" - -#if defined (CY_IP_MXS28ADCCOMP) - -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - - -/** -* \addtogroup group_comp_macros_interrupt_masks Interrupt Masks -* \{ -*/ - -/** Bit 0: Comparator 1 interrupt mask. */ -#define CY_COMP_1 (MXS28ADCCOMP_INTR_INTERRUPT_LPCOMP1_Msk) -/** Bit 1: Comparator 2 interrupt mask. */ -#define CY_COMP_2 (MXS28ADCCOMP_INTR_INTERRUPT_LPCOMP2_Msk) -/** Bits 1 and 2: Combined mask for both comparators. */ -#define CY_COMP_BOTH (CY_COMP_1 | CY_COMP_2) - -/** \} group_comp_macros_interrupt_masks */ - -/**< COMP PDL ID */ -#define CY_COMP_ID CY_PDL_DRV_ID(0x47u) - - - - - -/** The COMP error codes. */ -typedef enum -{ - CY_COMP_SUCCESS = 0x00U, /**< Successful */ - CY_COMP_BAD_PARAM = CY_COMP_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */ - CY_COMP_UNKNOWN = CY_COMP_ID | CY_PDL_STATUS_ERROR | 0xFFU, /**< Unknown failure */ -} cy_en_comp_status_t; - - -typedef enum -{ - CY_COMP_IN_N_GPIO04 = 0x00U, /**< GPIO0 for COMP2 and GPIO4 for COMP1 */ - CY_COMP_IN_N_GPIO15 = 0x01U /**< GPIO1 for COMP2 and GPIO5 for COMP1 */ -} cy_en_comp_in_n_t; - - -typedef enum -{ - CY_COMP_IN_P_GPIO26 = 0x00U, /**< GPIO2 for COMP2 and GPIO6 for COMP1 */ - CY_COMP_IN_P_GPIO37 = 0x01U, /**< GPIO3 for COMP2 and GPIO7 for COMP1 */ - CY_COMP_IN_P_MIC = 0x02U /**< MIC for both COMP2 and COMP1 */ -} cy_en_comp_in_p_t; - - -typedef struct -{ - uint32_t chanMsk; /**< Channel mask */ - uint32_t hyst; - bool hyst_x2; - bool ntd_en; - cy_en_comp_in_n_t inN; - cy_en_comp_in_p_t inP; -} cy_stc_comp_config_t; - - -cy_en_comp_status_t Cy_COMP_Init(MXS28ADCCOMP_Type* base, cy_stc_comp_config_t const * config); -void Cy_COMP_DeInit(MXS28ADCCOMP_Type* base, uint32_t chanMsk); - - -/******************************************************************************* -* Function Name: Cy_COMP_GetInterruptStatus -****************************************************************************//** -* -* Returns the interrupt status of the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \return -* The interrupt status, see \ref group_comp_macros_interrupt_masks. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_COMP_GetInterruptStatus -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_COMP_GetInterruptStatus(MXS28ADCCOMP_Type const * base) -{ - return (base->INTR & CY_COMP_BOTH); -} - - -/******************************************************************************* -* Function Name: Cy_ADC_ClearInterrupt -****************************************************************************//** -* -* Clears the interrupt status. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_ClearInterrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_COMP_ClearInterrupt(MXS28ADCCOMP_Type * base, uint32_t interrupt) -{ - base->INTR = interrupt & CY_COMP_BOTH; -} - - -/******************************************************************************* -* Function Name: Cy_COMP_SetInterrupt -****************************************************************************//** -* -* Sets the interrupt for the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \param interrupt -* The interrupt mask. See \ref group_comp_macros_interrupt_masks. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_COMP_SetInterruptMask -* -*******************************************************************************/ -__STATIC_INLINE void Cy_COMP_SetInterrupt(MXS28ADCCOMP_Type * base, uint32_t interrupt) -{ - base->INTR_SET = interrupt & CY_COMP_BOTH; -} - - -/******************************************************************************* -* Function Name: Cy_COMP_GetInterruptMask -****************************************************************************//** -* -* Returns the interrupt mask value of the specified channel. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \return -* The interrupt mask value. See \ref group_comp_macros_interrupt_masks. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_COMP_SetInterruptMask -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_COMP_GetInterruptMask(MXS28ADCCOMP_Type const * base) -{ - return (base->INTR_MASK & CY_COMP_BOTH); -} - - -/******************************************************************************* -* Function Name: Cy_COMP_SetInterruptMask -****************************************************************************//** -* -* Sets an interrupt mask value for the specified comparator. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \param interrupt -* The interrupt mask, see \ref group_comp_macros_interrupt_masks. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_COMP_SetInterruptMask -* -*******************************************************************************/ -__STATIC_INLINE void Cy_COMP_SetInterruptMask(MXS28ADCCOMP_Type * base, uint32_t interrupt) -{ - uint32_t interruptState = Cy_SysLib_EnterCriticalSection(); - base->INTR_MASK = (base->INTR_MASK & ~CY_COMP_BOTH) | (interrupt & CY_COMP_BOTH); - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_COMP_GetInterruptStatusMasked -****************************************************************************//** -* -* Returns the logical AND of the corresponding INTR and INTR_MASK fields -* in a single-load operation. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \return -* The masked interrupt status. See \ref group_comp_macros_interrupt_masks. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_COMP_ClearInterrupt -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_COMP_GetInterruptStatusMasked(MXS28ADCCOMP_Type const * base) -{ - return (base->INTR_MASKED & CY_COMP_BOTH); -} - - - - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_ADCCOMP */ - -#endif /* (CY_COMP_H) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_cryptolite.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_cryptolite.h deleted file mode 100644 index eeb674e0a1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_cryptolite.h +++ /dev/null @@ -1,349 +0,0 @@ -/***************************************************************************//** -* \file cy_cryptolite.h -* \version 1.0.0 -* -* \brief -* This file provides common constants and parameters -* for the Cryptolite driver. -* -******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ -/** -* \addtogroup group_cryptolite -* \{ -* The Cryptolite driver provides a public API to perform SHA256 hash -* calculation, using a cryptolite hardware IP block to accelerate operation. -* -* The functions and other declarations used in this driver are in cy_cryptolite.h. -* You can also include cy_pdl.h to get access to all functions and declarations in the PDL. -* -* The Cryptolite driver supports only SHA256. -* -* \section group_cryptolite_configuration_considerations Configuration Considerations -* -* Firmware sets up a cryptographic operation by passing in the required data as -* parameters in the function call. -* -* Cryptolite SHA256 function require a context. A context is a data -* structure that the driver uses for its operations. Firmware declares a -* context (allocates memory) but does not write or read the values in that -* context. In effect, the context is a scratch pad you provide to the driver. -* The driver uses the context to store and manipulate data during cryptographic -* operations. The Cryptolite driver header file declare all the required structures -* for context. -* -* \section group_cryptolite_definitions Definitions -* -* -* -* -* -* -* -* -* -* -* -* -*
TermDefinition
Secure Hash Algorithm (SHA)A cryptographic hash function. -* This function takes a message of an arbitrary length and reduces it to a -* fixed-length residue or message digest after performing a series of -* mathematically defined operations that practically guarantee that any -* change in the message will change the hash value. It is used for message -* authentication by transmitting a message with a hash value appended to it -* and recalculating the message hash value using the same algorithm at the -* recipient's end. If the hashes differ, then the message is corrupted. -* For more information see [Secure Hash standard description] -* (https://csrc.nist.gov/csrc/media/publications/fips/180/2/archive/2002-08-01/documents/fips180-2.pdf). -*
-* -* \defgroup group_cryptolite_macros Macros -* \defgroup group_cryptolite_functions Functions -* \defgroup group_cryptolite_data_structures Data Structures -* \defgroup group_cryptolite_enums Enumerated Types -*/ - -#if !defined (CY_CRYPTOLITE_H) -#define CY_CRYPTOLITE_H - -#include "cy_device.h" - -#if defined (CY_IP_MXCRYPTOLITE) - -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#include -#include -#include "cy_sysint.h" -#include "cy_cryptolite_hw.h" - -/** \cond INTERNAL */ -/** Block size for the SHA256(in bytes) */ -#define CY_CRYPTOLITE_SHA256_BLOCK_SIZE (64u) -/** HASH size for the SHA256(in bytes) */ -#define CY_CRYPTOLITE_SHA256_HASH_SIZE (32u) -/** PAD size for the SHA256(in bytes) */ -#define CY_CRYPTOLITE_SHA256_PAD_SIZE (56uL) -/** \endcond */ - -/** -* \addtogroup group_cryptolite_macros -* \{ -*/ -/** Driver major version */ -#define CY_CRYPTOLITE_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_CRYPTOLITE_DRV_VERSION_MINOR 0 - -/** Cryptolite Driver PDL ID */ -#define CY_CRYPTOLITE_ID CY_PDL_DRV_ID(0x0Cu) -/** \} group_cryptolite_macros */ - -/** -* \addtogroup group_cryptolite_enums -* \{ -*/ - -/** Errors of the Cryptolite block */ -typedef enum -{ - /** Operation completed successfully. */ - CY_CRYPTOLITE_SUCCESS = 0x00u, - - /** The Crypto operation parameters are incorrect. */ - CY_CRYPTOLITE_BAD_PARAMS = CY_CRYPTOLITE_ID | CY_PDL_STATUS_ERROR | 0x01u, - - /** The Crypto HW is busy. */ - CY_CRYPTOLITE_HW_BUSY = CY_CRYPTOLITE_ID | CY_PDL_STATUS_ERROR | 0x02u, - - /** The Crypto AHB bus error. */ - CY_CRYPTOLITE_BUS_ERROR = CY_CRYPTOLITE_ID | CY_PDL_STATUS_ERROR | 0x03u - -} cy_en_cryptolite_status_t; - -/** \} group_cryptolite_enums */ - -/** -* \addtogroup group_cryptolite_data_structures -* \{ -*/ - -/** \cond INTERNAL */ -/** The cryptolite SHA256 IP descriptor structure. -* All fields for the structure are internal. Firmware never reads or -* writes these values. -*/ -typedef struct sha_struct_t { - uint32_t data0; - uint32_t data1; - uint32_t data2; -} cy_stc_cryptolite_sha_descr_t; -/** \endcond */ - -/** The structure for storing the SHA256 context. -* All fields for the context structure are internal. Firmware never reads or -* writes these values. Firmware allocates the structure and provides the -* address of the structure to the driver in the function calls. Firmware must -* ensure that the defined instance of this structure remains in scope -* while the drive is in use. -*/ -typedef struct -{ - /** \cond INTERNAL */ - uint32_t msgblock[CY_CRYPTOLITE_SHA256_BLOCK_SIZE / 4u]; - uint32_t hash[CY_CRYPTOLITE_SHA256_HASH_SIZE / 4u]; - uint32_t message_schedule[CY_CRYPTOLITE_SHA256_BLOCK_SIZE]; - uint8_t *message; - uint32_t messageSize; - uint32_t msgIdx; - /** Operation data descriptors */ - cy_stc_cryptolite_sha_descr_t message_schedule_struct; - cy_stc_cryptolite_sha_descr_t message_process_struct; - /** \endcond */ -} cy_stc_cryptolite_context_sha_t; - - -/** \} group_cryptolite_data_structures */ - -/** -* \addtogroup group_cryptolite_functions -* \{ -*/ -/******************************************************************************* -* Function Name: Cy_Cryptolite_Sha256_Init -****************************************************************************//** -* -* The function to initialize the SHA256 operation. -* -* \param base -* The pointer to the Cryptolite instance. -* -* \param cfContext -* The pointer to the \ref cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* \return -* \ref cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Init(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext); - -/******************************************************************************* -* Function Name: Cy_Cryptolite_Sha256_Start -****************************************************************************//** -* -* Initializes the initial Hash vector. -* -* \param base -* The pointer to the CRYPTOLITE instance. -* -* \param cfContext -* The pointer to the \ref cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* \return -* \ref cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Start(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext); - -/******************************************************************************* -* Function Name: Cy_Cryptolite_Sha256_Update -****************************************************************************//** -* -* Performs the SHA256 calculation on one message. -* -* \param base -* The pointer to the CRYPTOLITE instance. -* -* \param cfContext -* The pointer to the \ref cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* \param message -* The pointer to the message whose Hash is being computed. -* -* \param messageSize -* The size of the message whose Hash is being computed. -* -* \return -* \ref cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Update(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext, - uint8_t const *message, - uint32_t messageSize); - -/******************************************************************************* -* Function Name: Cy_Cryptolite_Sha256_Finish -****************************************************************************//** -* -* Completes the SHA256 calculation. -* -* \param base -* The pointer to the CRYPTOLITE instance. -* -* \param cfContext -* The pointer to the \ref cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* \param digest -* The pointer to the calculated Hash digest. -* -* \return -* \ref cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Finish(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext, - uint8_t *digest); - -/******************************************************************************* -* Function Name: Cy_Cryptolite_Sha256_Free -****************************************************************************//** -* -* Clears the used memory and context data. -* -* \param base -* The pointer to the CRYPTOLITE instance. -* -* \param cfContext -* The pointer to the \ref cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* \return -* \ref cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Free(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext); - -/******************************************************************************* -* Function Name: Cy_Cryptolite_Sha256_Run -****************************************************************************//** -* -* This function performs the SHA256 Hash function. -* Provide the required parameters and the pointer -* to the context structure when making this function call. -* It is independent of the previous Crypto state because it already contains -* preparation, calculation, and finalization steps. -* -* \param base -* The pointer to the CRYPTOLITE instance. -* -* \param message -* The pointer to a message whose hash value is being computed. -* -* \param messageSize -* The size of a message in bytes. -* -* \param digest -* The pointer to the hash digest. -* -* \param cfContext -* The pointer to the \ref cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* \return -* \ref cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Run(CRYPTO_Type *base, - uint8_t const *message, - uint32_t messageSize, - uint8_t *digest, - cy_stc_cryptolite_context_sha_t *cfContext); - -/** \} group_cryptolite_functions */ -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXCRYPTOLITE */ - -#endif /* #if !defined (CY_CRYPTOLITE_H) */ -/** \} group_cryptolite */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_cryptolite_hw.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_cryptolite_hw.h deleted file mode 100644 index 79779222e8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_cryptolite_hw.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************//** -* \file cy_cryptolite_hw.h -* \version 1.0.0 -* -* \brief -* This file provides common constants and macros -* for the Cryptolite driver. -* -******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ -#if !defined (CY_CRYPTOLITE_HW_H) -#define CY_CRYPTOLITE_HW_H - -#include "cy_device.h" - -#if defined (CY_IP_MXCRYPTOLITE) - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "ip/cyip_crypto.h" - -#define REG_CRYPTOLITE_CTL(base) (((CRYPTO_Type*)(base))->CTL) -#define REG_CRYPTOLITE_STATUS(base) (((CRYPTO_Type*)(base))->STATUS) -#define REG_CRYPTOLITE_SHA_DESCR(base) (((CRYPTO_Type*)(base))->SHA_DESCR) -#define REG_CRYPTOLITE_SHA_INTR_ERROR(base) (((CRYPTO_Type*)(base))->INTR_ERROR) -#define REG_CRYPTOLITE_SHA_INTR_ERROR_SET(base) (((CRYPTO_Type*)(base))->INTR_ERROR_SET) -#define REG_CRYPTOLITE_SHA_INTR_ERROR_MASK(base) (((CRYPTO_Type*)(base))->INTR_ERROR_MASK) -#define REG_CRYPTOLITE_SHA_INTR_ERROR_MASKED(base) (((CRYPTO_Type*)(base))->INTR_ERROR_MASKED) - -#define CY_CRYPTOLITE_MSG_SCH_CTLWD ((uint32_t)(0 << 28)) -#define CY_CRYPTOLITE_PROCESS_CTLWD ((uint32_t)(1 << 28)) -/*bus error interrupt mask*/ -#define CY_CRYPTOLITE_INTR_BUS_ERROR_MASK ((uint32_t)CRYPTO_INTR_ERROR_BUS_ERROR_Msk) - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXCRYPTOLITE */ - -#endif /* #if !defined (CY_CRYPTOLITE_HW_H) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ephy.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ephy.h deleted file mode 100644 index 96c5511b50..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ephy.h +++ /dev/null @@ -1,358 +0,0 @@ -/***************************************************************************//** -* \file cy_ephy.h -* \version 1.0 -* -* Provides an API declaration of the Ethernet Generic PHY driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_ephy -* \{ -* The EPHY driver provides an API for PHY management abstraction layer -* -* The functions and other declarations used in this driver are in cy_ephy.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* \section group_ephy_more_information More Information -* -* Refer to the technical reference manual (TRM) and the device datasheet. -* -* \section group_ephy_MISRA MISRA-C Compliance -* The EPHY driver does not have any specific deviation -* -* \section group_ephy_Changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_ephy_macros Macros -* \defgroup group_ephy_functions Functions -* \defgroup group_ephy_enums Enumerated Types -* \defgroup group_ephy_data_structures Data Structures -*/ - -#if !defined (CY_EPHY_H) -#define CY_EPHY_H - -#include "cy_device.h" - -#if defined (CY_IP_MXETH) - -#include -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** \addtogroup group_ephy_macros -* \{ -*/ - -/** Driver major version */ -#define CY_EPHY_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_EPHY_DRV_VERSION_MINOR 0 - -/** EPHY driver ID */ -#define CY_EPHY_ID CY_PDL_DRV_ID(0x70U) - -/** \} group_ephy_macros */ - -/*************************************** -* Constants -***************************************/ - -/** \cond INTERNAL */ - -#define MIN_PHY_ADDRESS 0 -#define MAX_PHY_ADDRESS 31 - -/** Naming and numbering of basic PHY registers. */ -#define PHYREG_00_BMCR (0x00UL) /**< Basic Mode Control Register. */ -#define PHYREG_01_BMSR (0x01UL) /**< Basic Mode Status Register. */ -#define PHYREG_02_PHYSID1 (0x02UL) /**< PHYS ID 1 */ -#define PHYREG_03_PHYSID2 (0x03UL) /**< PHYS ID 2 */ -#define PHYREG_04_ADVERTISE (0x04UL) /**< Advertisement control reg */ - -/** Bit fields for 'PHYREG_00_BMCR' the 'Basic Mode Control Register'. */ -#define PHYBMCR_FULL_DUPLEX_Msk (0x0100UL) /**< Full duplex. */ -#define PHYBMCR_FULL_DUPLEX_Pos (8UL) -#define PHYBMCR_AN_RESTART_Msk (0x0200UL) /**< Auto negotiation restart. */ -#define PHYBMCR_AN_RESTART_Pos (9UL) -#define PHYBMCR_ISOLATE_Msk (0x0400UL) /**< 1 = Isolates 0 = Normal operation. */ -#define PHYBMCR_ISOLATE_Pos (10UL) -#define PHYBMCR_AN_ENABLE_Msk (0x1000UL) /**< Enable auto negotiation. */ -#define PHYBMCR_AN_ENABLE_Pos (12UL) -#define PHYBMCR_SPEED_100_Msk (0x2000UL) /**< Set Network speed. 1:100Mbps 0:10Mbps */ -#define PHYBMCR_SPEED_100_Pos (13UL) -#define PHYBMCR_RESET_Msk (0x8000UL) /**< Reset the PHY. */ -#define PHYBMCR_RESET_Pos (15UL) - -/** Bit fields for 'BMSR', 'Basic Mode Status Register' */ -#define PHYBMSR_LINK_STATUS_Msk (0x0004UL) /**< Link Status */ -#define PHYBMSR_LINK_STATUS_Pos (2UL) -#define PHYBMSR_AN_COMPLETE_Msk (0x0020UL) /**< Auto-Negotiation process completed */ -#define PHYBMSR_AN_COMPLETE_Pos (5UL) -#define PHYBMSR_10BASE_T_HD_Msk (0x0800UL) /**< 10BASE-T Half Duplex Capable */ -#define PHYBMSR_10BASE_T_HD_Pos (11UL) -#define PHYBMSR_10BASE_T_FD_Msk (0x1000UL) /**< 10BASE-T Full Duplex Capable */ -#define PHYBMSR_10BASE_T_FD_Pos (12UL) -#define PHYBMSR_100BASE_TX_HD_Msk (0x2000UL) /**< 100BASE-TX Half Duplex Capable */ -#define PHYBMSR_100BASE_TX_HD_Pos (13UL) -#define PHYBMSR_100BASE_TX_FD_Msk (0x4000UL) /**< 100BASE-TX Full Duplex Capable */ -#define PHYBMSR_100BASE_TX_FD_Pos (14UL) -#define PHYBMSR_100BASE_T4_Msk (0x8000UL) /**< 100BASE-T4 Capable */ -#define PHYBMSR_100BASE_T4_Pos (15UL) /**< 100BASE-T4 Capable */ - -/** PHYREG_02_PHYSID1 */ -#define PHYID1_OUI_Msk (0xFFFFUL) /**< OUI: 6-21st bits */ -#define PHYID1_OUI_Pos (0UL) - -/** PHYREG_03_PHYSID2 */ -#define PHYID2_REV_NUM_Msk (0x000FUL) /**< Revision Number */ -#define PHYID2_REV_NUM_Pos (0UL) -#define PHYID2_MODEL_NUM_Msk (0x03F0UL) /**< Model Number */ -#define PHYID2_MODEL_NUM_Pos (4FUL) -#define PHYID2_OUI_LSB_Msk (0xFC00UL) /**< OUI_LSB: Assign to 0-5th bits of OUI */ -#define PHYID2_OUI_LSB_Pos (10UL) - -#define PHYID_ID1_Msk (0xFFFF0000UL) /**< ID1 */ -#define PHYID_ID1_Pos (16UL) -#define PHYID_ID2_Msk (0xFFFFUL) /**< ID2 */ -#define PHYID_ID2_Pos (0UL) - - -/** Description of all capabilities that can be advertised to the peer */ -#define PHYANAR_CSMA_Msk (0x0001FUL) /**< Only selector supported. */ -#define PHYANAR_CSMA_Pos (0UL) -#define PHYANAR_10BASE_T_Msk (0x0020UL) /**< Try for 10mbps half-duplex. */ -#define PHYANAR_10BASE_T_Pos (5UL) -#define PHYANAR_10BASE_T_FD_Msk (0x0040UL) /**< Try for 10mbps full-duplex. */ -#define PHYANAR_10BASE_T_FD_Pos (6UL) -#define PHYANAR_100BASE_TX_Msk (0x0080UL) /**< Try for 100mbps half-duplex. */ -#define PHYANAR_100BASE_TX_Pos (7UL) -#define PHYANAR_100BASE_TX_FD_Msk (0x0100UL) /**< Try for 100mbps full-duplex. */ -#define PHYANAR_100BASE_TX_FD_Pos (8UL) -#define PHYANAR_ALL_Msk ( PHYANAR_10BASE_T_Msk | PHYANAR_10BASE_T_FD_Msk | PHYANAR_100BASE_TX_Msk | PHYANAR_100BASE_TX_FD_Msk ) - - - -/****************************************************************************** -* Global Enumerations definitions -******************************************************************************/ - -/* PHY state machine states */ -typedef enum { - CY_EPHY_DOWN, /**< PHY device and driver are not ready for anything */ - CY_EPHY_READY, /** < PHY is ready to send and receive packets, but the controller is not */ - CY_EPHY_UP, /**< The PHY and attached device are ready to do work */ - CY_EPHY_AN, /**< The PHY is currently negotiating the link state. Link is therefore down for now */ - CY_EPHY_RUNNING, /**< PHY is currently up, running, and possibly sending and/or receiving packets */ -} cy_en_ephy_state_t; - -/** \endcond */ - -/** -* \addtogroup group_ephy_enums -* \{ -*/ - -/** EPHY Driver error codes */ -typedef enum -{ - CY_EPHY_SUCCESS = 0x00U, /**< Returned successful */ - CY_EPHY_ERROR = CY_EPHY_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */ -} cy_en_ephy_status_t; - -/** PHY Duplex Mode */ -typedef enum -{ - CY_EPHY_DUPLEX_HALF, /**< half duplex */ - CY_EPHY_DUPLEX_FULL, /**< full duplex */ - CY_EPHY_DUPLEX_AUTO /**< both half/full duplex */ -} cy_en_ephy_duplex_t; - -/** PHY Speed */ -typedef enum -{ - CY_EPHY_SPEED_10, /**< 10Mbps */ - CY_EPHY_SPEED_100, /**< 100Mbps */ - CY_EPHY_SPEED_AUTO /**< both 10/100 Mbps */ -} cy_en_ephy_speed_t; - -/** \} group_ephy_enums */ - -/****************************************************************************** -* Global Data Structure definitions -******************************************************************************/ - -/** -* \addtogroup group_ephy_data_structures -* \{ -*/ - -/** PHY read handle to application */ -typedef void (*phy_read_handle)(uint32_t phyId, uint32_t regAddress, uint32_t *value); - -/** PHY write handle to application */ -typedef void (*phy_write_handle)(uint32_t phyId, uint32_t regAddress, uint32_t value); - -/** This is the private data structure of EPHY. This has be instantiated by application */ -typedef struct cy_stc_ephy -{ - phy_read_handle fnPhyRead; /**< read handle */ - phy_write_handle fnPhyWrite; /**< write handle */ - uint32_t phyId; /**< phy ID */ - cy_en_ephy_state_t state; /**< PHY state */ - uint32_t bmcr; /**< store the BMCR value while PHY configuration */ - uint32_t anar; /**< store the ANAR value while PHY configuration */ -} cy_stc_ephy_t; - -/** EPHY configuration */ -typedef struct cy_stc_ephy_config -{ - uint32_t speed; /**< speed */ - uint32_t duplex; /**< suplex mode */ -} cy_stc_ephy_config_t; - -/** \} group_ephy_data_structures */ - - -/****************************************************************************** -* Global functions * -******************************************************************************/ - -/** -* \addtogroup group_ephy_functions -* \{ -*/ - -/******************************************************************************* -* Function Name: Cy_EPHY_Init -****************************************************************************//** -* -* This function initializes the private structure and assign a PHY-read, -* PHY-write function handle to its private data structure. -* -* \param phy pointer to PHY private data structure. -* \param fnRead pointer to read function implemented in application -* \param fnWrite pointer to write function implemented in application -* -* \return -* initialization status -* -*******************************************************************************/ -cy_en_ephy_status_t Cy_EPHY_Init(cy_stc_ephy_t *phy, phy_read_handle fnRead, phy_write_handle fnWrite); - -/******************************************************************************* -* Function Name: Cy_EPHY_Discover -****************************************************************************//** -* -* Discovers connected PHY at address zero. Reads ID1 and ID2 register to form -* PHY ID. PHY ID is stored in config structure. -* -* \param phy pointer to PHY private data structure -* -* \return -* discover status -* -*******************************************************************************/ -cy_en_ephy_status_t Cy_EPHY_Discover(cy_stc_ephy_t *phy); - -/******************************************************************************* -* Function Name: Cy_EPHY_Configure -****************************************************************************//** -* -* Configures PHY with user provided speed and duplex mode -* -* \param phy pointer to PHY private data structure -* \param config pointer to PHY configuration structure -* -* \return -* configuration status -* -*******************************************************************************/ -cy_en_ephy_status_t Cy_EPHY_Configure(cy_stc_ephy_t *phy, cy_stc_ephy_config_t *config); - -/******************************************************************************* -* Function Name: Cy_EPHY_GetLinkStatus -****************************************************************************//** -* -* Get current link status of PHY and update phy state in private data structure. -* We need to read the status register twice, keeping the second value. -* -* \param phy pointer to PHY private data structure -* -* \return -* link status of PHY (0=down, 1=up) -* -*******************************************************************************/ -uint32_t Cy_EPHY_GetLinkStatus(cy_stc_ephy_t *phy); - -/******************************************************************************* -* Function Name: Cy_EPHY_StartAutoNegotiation -****************************************************************************//** -* -* Start auto negotiation by enabling 12th bit of BMCR -* -* \param phy pointer to PHY private data structure -* -* \return -* status of starting auto-negotiation feature -* -*******************************************************************************/ -cy_en_ephy_status_t Cy_EPHY_StartAutoNegotiation(cy_stc_ephy_t *phy); - -/******************************************************************************* -* Function Name: Cy_EPHY_Reset -****************************************************************************//** -* Soft reset PHY by enabling 15th bit of BMCR register -* -* \param phy pointer to PHY private data structure -* -* \return -* status of reset -* -*******************************************************************************/ -cy_en_ephy_status_t Cy_EPHY_Reset(cy_stc_ephy_t *phy); - -/** \} group_ephy_functions */ - - - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXETH */ - -#endif /* CY_EPHY_H */ - -/** \} group_ephy */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ethif.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ethif.h deleted file mode 100644 index 3b9f83a9a1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ethif.h +++ /dev/null @@ -1,514 +0,0 @@ -/***************************************************************************//** -* \file cy_ethif.h -* \version 1.0 -* -* Provides an API declaration of the Ethernet Interface driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_ethif -* \{ -* The ETHIF driver is wrapper around Cadence's EMAC core driver. This is a -* network interface driver to Cadence core EMAC driver. It provides APIs to -* communicate with Ethernet IP. The PHY driver also uses this driver to -* communicate with PHY chip (via application). This driver has internal buffer -* management, handling callbacks from Cadence EMAC during transport, etc. -* -* The functions and other declarations used in this driver are in cy_ethif.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* \section group_ethif_more_information More Information -* -* Refer to the technical reference manual (TRM) and the device datasheet. -* -* \section group_ethif_MISRA MISRA-C Compliance -* The Ethernet driver has no specific deviations -* -* \section group_ethif_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_ethif_macros Macros -* \defgroup group_ethif_functions Functions -* \defgroup group_ethif_data_structures Data Structures -* \defgroup group_ethif_enums Enumerated Types -*/ - -#if !defined (CY_ETHIF_H) -#define CY_ETHIF_H - -#include "cy_device.h" - -#if defined (CY_IP_MXETH) - -#include -#include "cy_syslib.h" -#include "cdn_errno.h" -#include "cedi.h" -#include "emac_regs_macro.h" -#include "edd_int.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** \addtogroup group_ethif_macros -* \{ -*/ - -/** Driver major version */ -#define CY_ETHIF_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_ETHIF_DRV_VERSION_MINOR 0 - -/** Eth driver ID */ -#define CY_ETHIF_ID CY_PDL_DRV_ID(0x51U) - -/** \} group_ethif_macros */ - -/*************************************** -* Constants -***************************************/ - -/** \cond INTERNAL */ - -/*############################################################################*/ -/** Ethernet configurations constants */ -#define CY_ETH_STANDARD_BD (0) // Standard Buffer Descriptor Mode -#define CY_ETH_EXTENDED_BD (1) // Extended Buffer Descriptor Mode -#define CY_ETH_TX_FSFM (0) // Full Store and Forward Mode [FSFM] for Tx -#define CY_ETH_TX_PSFM (1) // Partial Store and Forward Mode [PSFM] for Tx -#define CY_ETH_RX_FSFM (0) // Full Store and Forward Mode for Rx -#define CY_ETH_RX_PSFM (1) // Partial Store and Forward Mode for Rx - -/** Ethernet channel */ -#define CY_ETH_DEFINE_NUM_IP (1) // Number of Ethernet channels intended to use, maximum 2 -#define CY_ETH_DEFINE_NUM_RXQS (2) // Number of queues intended to use, maximum 2 -#define CY_ETH_DEFINE_NUM_TXQS (2) // Number of queues intended to use, maximum 2 - -/** Ethernet Operation Mode */ -#define CY_ETH_DEFINE_TX_OP_MODE CY_ETH_TX_FSFM // FSFM OR PSFM -#define CY_ETH_DEFINE_RX_OP_MODE CY_ETH_RX_FSFM // FSFM OR PSFM -#define CY_ETH_DEFINE_TX_WATERMARK (50) // Watermark level for Tx -#define CY_ETH_DEFINE_RX_WATERMARK (50) // Watermark level for Rx - -/** Buffer Descriptor mode */ -#define CY_ETH_DEFINE_BD CY_ETH_EXTENDED_BD // standard or extended - -/** Memory Allocation defines */ // Frame Buffers are allocated based on number of buffer descriptors -#define CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE (2) // Total number of Buffer Descriptors allocated for each transmit queue -#define CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE (4) // Total number of Buffer Descriptors allocated for each receive queue -/*############################################################################*/ - -#define CY_ETH_TX_PBUF_SIZE (1) // 1: Use full configured addressable space -#define CY_ETH_RX_PBUF_SIZE (3) // 3: Use full configured addressable space - -#define CY_ETH0_ADDR_REG_BASE (ETH0_BASE) // Register area for ETH0 - -#define CY_ETH0_GEMGXL_ADDR_REGBASE (ETH0_BASE + 0x00001000) // Register area for GEMGXL - -/** Driver constants */ -#define CY_ETH_SIZE_MIN_FRAME (64) -#define CY_ETH_SIZE_MAX_FRAME (1536) -#define CY_ETH_SIZE_BUF_TXQ_RXQ (1536) - -#if CY_ETH_DEFINE_BD == CY_ETH_EXTENDED_BD -#define CY_ETH_BD_SIZE (16) // Bytes -#else -#define CY_ETH_BD_SIZE (8) // Bytes -#endif - -#define CY_ETH_DISABLE_0 (0) -#define CY_ETH_ENABLE_1 (1) -#define CY_ETH_MDIO_BUSY_0 (0) -#define CY_ETH_MDIO_IDLE_1 (1) -#define CY_ETH_QS0_0 (0) -#define CY_ETH_QS1_1 (1) -#define CY_ETH_QS2_2 (2) -#define CY_ETH_QS3_3 (3) -#define CY_ETH_NOT_INITIALIZE_0 (0) -#define CY_ETH_INITIALIZE_1 (1) -#define CY_ETHIF_BUFFER_CLEARED_0 (0) - -#define CY_ETH_TOTAL_TX_BUF (CY_ETH_DEFINE_NUM_IP * CY_ETH_DEFINE_NUM_TXQS * CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE) -#define CY_ETH_TOTAL_RX_BUF (CY_ETH_DEFINE_NUM_IP * CY_ETH_DEFINE_NUM_RXQS * CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE * 2) // *2 is to replace the already provided buffer to BDs - -#define CY_ETHIF_NO_BUFFER_AVAILABLE (255) -#define CY_ETHIF_BUFFER_AVAILABLE (254) - -#define CY_ETHIF_MDIO_READ_FAILED (2) -#define CY_ETHIF_PHY_FLAG (0) // defines clause 22 - -#define CY_ETHIF_TX_STATUS_CLEAR (0x000001FF) - -#define CY_EHTIF_EMPTYVALUE (0xDEADBEEF) - -#define CY_ETHIF_PAUSE_P0 (0) -#define CY_ETHIF_PAUSE_P1 (1) -#define CY_ETHIF_PAUSE_P2 (2) -#define CY_ETHIF_PAUSE_P3 (3) -#define CY_ETHIF_PAUSE_P4 (4) -#define CY_ETHIF_PAUSE_P5 (5) -#define CY_ETHIF_PAUSE_P6 (6) -#define CY_ETHIF_PAUSE_P7 (7) - -/** \endcond */ - -/*************************************** -* Enumerations -***************************************/ - -/** -* \addtogroup group_ethif_enums -* \{ -*/ - -/** - ***************************************************************************** - ** \brief Eth driver error codes. - ** - *****************************************************************************/ -typedef enum -{ - CY_ETHIF_SUCCESS = 0, /**< Returned successful */ - CY_ETHIF_BAD_PARAM, /**< Bad parameter was passed */ - CY_ETHIF_MEMORY_NOT_ENOUGH, /**< Assigned memory for BDs not enough */ - CY_ETHIF_LINK_DOWN, /**< Link between nodes is not up */ - CY_ETHIF_LINK_UP, /**< Link between nodes is up */ - CY_ETHIF_BUFFER_NOT_AVAILABLE, /**< No local buffer available to send the frame */ -} cy_en_ethif_status_t; - -/** - ***************************************************************************** - ** \brief Eth driver buffer status. - ** - *****************************************************************************/ -typedef enum -{ - CY_ETHIF_BUFFER_UNINIT = 0, /**< Buffer Uninitialized */ - CY_ETHIF_BUFFER_FREE, /**< Buffer free and cleared with CY_EHTIF_EMPTYVALUE */ - CY_ETHIF_BUFFER_OCCUPIED, /**< Buffer has been allocated to BD or in case of Tx loaded with the source data */ - CY_ETHIF_BUFFER_RELEASED, /**< Buffer has been used and can be written with CY_EHTIF_EMPTYVALUE */ -} cy_en_ethif_buffer_status_t; - -/** - ***************************************************************************** - ** \brief EMAC Drive Modes. - ** - *****************************************************************************/ -typedef enum -{ - CY_ETHIF_CTL_MII_10 = 0, /**< CTL.ETH_MODE 2'd0 | Network_config[0](speed) 0 | Network_config[10](gigabit_mode_enable) 0 | PHY mode MII - 10Mbps */ - CY_ETHIF_CTL_MII_100 = 1, /**< CTL.ETH_MODE 2'd0 | Network_config[0](speed) 1 | Network_config[10](gigabit_mode_enable) 0 | PHY mode MII - 100Mbps */ - CY_ETHIF_CTL_GMII_1000 = 2, /**< CTL.ETH_MODE 2'd1 | Network_config[0](speed) 0 | Network_config[10](gigabit_mode_enable) 1 | PHY mode GMII - 1000Mbps */ - CY_ETHIF_CTL_RGMII_10 = 3, /**< CTL.ETH_MODE 2'd2 | Network_config[0](speed) 0 | Network_config[10](gigabit_mode_enable) 0 | PHY mode RGMII - 10Mbps (4bits/Cycle) */ - CY_ETHIF_CTL_RGMII_100 = 4, /**< CTL.ETH_MODE 2'd2 | Network_config[0](speed) 1 | Network_config[10](gigabit_mode_enable) 0 | PHY mode RGMII - 100Mbps (4bits/Cycle) */ - CY_ETHIF_CTL_RGMII_1000 = 5, /**< CTL.ETH_MODE 2'd2 | Network_config[0](speed) 0 | Network_config[10](gigabit_mode_enable) 1 | PHY mode RGMII - 1000Mbps (8bits/Cycle) */ - CY_ETHIF_CTL_RMII_10 = 6, /**< CTL.ETH_MODE 2'd3 | Network_config[0](speed) 0 | Network_config[10](gigabit_mode_enable) 0 | PHY mode RMII - 10Mbps */ - CY_ETHIF_CTL_RMII_100 = 7, /**< CTL.ETH_MODE 2'd3 | Network_config[0](speed) 1 | Network_config[10](gigabit_mode_enable) 0 | PHY mode RMII - 100Mbps */ -} cy_en_ethif_speed_sel_t; - -/** - ***************************************************************************** - ** \brief Reference Clock for RMII/RGMII. - ** - *****************************************************************************/ -typedef enum -{ - CY_ETHIF_EXTERNAL_HSIO = 0, /**< Clock coming from HSIO */ - CY_ETHIF_INTERNAL_PLL, /**< Clock referenced from Internal PLL source */ -} cy_en_ethif_clock_ref; - -/** Filter Type */ -typedef enum -{ - CY_ETH_FILTER_TYPE_DESTINATION = 0, /**< filter on destination address */ - CY_ETH_FILTER_TYPE_SOURCE = 1, /**< filter on source address */ -} cy_en_ethif_filter_type_t; - -/** number of filters supported */ -typedef enum -{ - CY_ETH_FILTER_NUM_1 = 1, /**< filter 1 */ - CY_ETH_FILTER_NUM_2 = 2, /**< filter 2 */ - CY_ETH_FILTER_NUM_3 = 3, /**< filter 3 */ - CY_ETH_FILTER_NUM_4 = 4, /**< filter 4 */ - CY_ETH_FILTER_NUM_INV, /**< Invalid Filter */ -} cy_en_ethif_filter_num_t; - -/** \} group_ethif_enums */ - - -/*************************************** -* Configuration Structures -***************************************/ -/** -* \addtogroup group_ethif_data_structures -* \{ -*/ - -/** - ***************************************************************************** - ** \brief Wrapper Configuration - *****************************************************************************/ -typedef struct -{ - cy_en_ethif_speed_sel_t stcInterfaceSel; /**< Interface selection for ENET */ - cy_en_ethif_clock_ref bRefClockSource; /**< Reference clock selection */ - uint8_t u8RefClkDiv; /**< Actual division would be u8RefClkDiv + 1 */ -} cy_stc_ethif_wrapper_config_t; - -/** - ***************************************************************************** - ** \brief Queue status - *****************************************************************************/ -typedef struct -{ - bool bTxQueueDisable[CY_ETH_QS2_2+1]; /**< Tx Queue0-2 || 0: Queue Enabled, 1: Queue Disabled */ - bool bRxQueueDisable[CY_ETH_QS2_2+1]; /**< Rx Queue0-2 || 0: Queue Enabled, 1: Queue Disabled */ -} cy_stc_ethif_queue_disablestatus_t; - -/** - ***************************************************************************** - ** \brief Buffer status - *****************************************************************************/ -typedef struct -{ - CEDI_BuffAddr cy_ethif_bufaddr; /**< Buffer address as per requirement by Cadence driver */ - cy_en_ethif_buffer_status_t enBufStatus; /**< Buffer status */ -} cy_stc_ethif_bufstatus_t; - -/** - ***************************************************************************** - ** \brief Time Stamp Unit Init - *****************************************************************************/ -typedef struct -{ - CEDI_1588TimerVal * pstcTimerValue; /**< TSU Timer value */ - CEDI_TimerIncrement * pstcTimerIncValue; /**< TSU Timer increment value */ - bool bOneStepTxSyncEnable; /**< One step sync enable */ - CEDI_TxTsMode enTxDescStoreTimeStamp; /**< Store Time stamp value in Tx descriptor */ - CEDI_RxTsMode enRxDescStoreTimeStamp; /**< Store Time stamp value in Rx descriptor */ - bool bStoreNSinRxDesc; /**< Store NanoSecond field of TSU in Rx Descriptor */ -} cy_stc_ethif_tsu_config_t; - -/** - ***************************************************************************** - ** \brief Frame transmission complete callback function (cy_ethif_tx_msg_func_ptr_t). - ** - ** Signals a successful completed transmission. - *****************************************************************************/ - typedef void (*cy_ethif_tx_msg_cb_t)(uint8_t u8QueueIndex); - - /** - ***************************************************************************** - ** \brief Frame transmission Error callback function (cy_ethif_tx_error_func_ptr_t). - ** - ** Signals a transmission error. - *****************************************************************************/ - typedef void (*cy_ethif_tx_error_cb_t)(uint8_t u8QueueIndex); - - /** - ***************************************************************************** - ** \brief Frame received callback function (cy_ethif_rx_frame_func_ptr_t). - ** - ** Signals a successful reception of frame. - *****************************************************************************/ - typedef void (*cy_ethif_rx_frame_cb_t)(uint8_t * u8RxBuffer, uint32_t u32Length); - - /** - ***************************************************************************** - ** \brief TSU Second counter increment callback function (cy_ethif_rx_frame_func_ptr_t). - ** - ** Signals a One second increment in the TSU. - *****************************************************************************/ - typedef void (*cy_ethif_tsu_inc_cb_t)(); - -/** - ***************************************************************************** - ** \brief Ethernet MAC call back handlers - *****************************************************************************/ - typedef struct - { - cy_ethif_tx_msg_cb_t txcompletecb; /**< Transmit complete */ - cy_ethif_tx_error_cb_t txerrorcb; /**< Tx Error */ - cy_ethif_rx_frame_cb_t rxframecb; /**< Frame Received */ - cy_ethif_tsu_inc_cb_t tsuSecondInccb; /**< TSU timer Second counter incremented */ - } cy_stc_ethif_cb_t; - -/** - ***************************************************************************** - ** \brief Ethernet MAC detailed configurations - *****************************************************************************/ -typedef struct -{ - bool bintrEnable; /**< interrupts/events to enable on start */ - CEDI_DmaDatBLen dmaDataBurstLen; /**< fixed burst length for DMA data transfers */ - /**< bit4:0 amba_burst_length */ - /**< 1xxxx: attempt use burst up to 16 (CEDI_DMA_DBUR_LEN_16) */ - /**< 01xxx: attempt use burst up to 8 (CEDI_DMA_DBUR_LEN_8) */ - /**< 001xx: attempt use burst up to 4 (CEDI_DMA_DBUR_LEN_4) */ - /**< 0001x: always use single burst */ - /**< 00001: always use single burst (CEDI_AMBD_BURST_LEN_1) */ - /**< 00000: best AXI burst up to 256 beats */ - uint8_t u8dmaCfgFlags; /**< DMA config register bits 24, 25 & 26. */ - /**< OR the following bit-flags to set corresponding bits - */ - /**< CEDI_CFG_DMA_DISC_RXP, */ - /**< CEDI_CFG_DMA_FRCE_RX_BRST, */ - /**< CEDI_CFG_DMA_FRCE_TX_BRST */ - CEDI_MdcClkDiv mdcPclkDiv; /**< divisor to generate MDC from pclk */ - /**< CEDI_MDC_DIV_BY_8 = 0 */ - /**< CEDI_MDC_DIV_BY_16 = 1 */ - /**< CEDI_MDC_DIV_BY_32 = 2 */ - /**< CEDI_MDC_DIV_BY_48 = 3 */ - /**< CEDI_MDC_DIV_BY_64 = 4 */ - /**< CEDI_MDC_DIV_BY_96 = 5 */ - /**< CEDI_MDC_DIV_BY_128 = 6 */ - /**< CEDI_MDC_DIV_BY_224 = 7 */ - uint8_t u8rxLenErrDisc; /**< enable discard of frames with length field error */ - uint8_t u8disCopyPause; /**< disable copying Rx pause frames to memory */ - uint8_t u8chkSumOffEn; /**< enable checksum offload operation - OR bit-flags - * to enable in Tx and/or Rx: - * CEDI_CFG_CHK_OFF_TX, CEDI_CFG_CHK_OFF_RX */ - uint8_t u8rx1536ByteEn; /**< enable Rx of frames up to 1536 bytes */ - uint8_t u8rxJumboFrEn; /**< enable Rx of jumbo frames */ - uint8_t u8enRxBadPreamble; /**< enable Rx frames with non-standard preamble */ - uint8_t u8ignoreIpgRxEr; /**< ignore IPG rx_er (NetCfg b30) */ - uint8_t u8storeUdpTcpOffset; /**< u8storeUdpTcpOffset */ - uint8_t u8aw2wMaxPipeline; /**< Maximum number of outstanding AXI write requests, - * that can be issued by DMA via the AW channel. - * Must not be = 0 if using AXI as this would disable writes - */ - uint8_t u8ar2rMaxPipeline; /**< Maximum number of outstanding AXI read requests, - * that can be issued by DMA via the AR channel. - * Must not be = 0 if using AXI as this would disable reads - */ - uint8_t u8pfcMultiQuantum; /**< enable pfc multiple quantum (8 different priorities) */ - cy_stc_ethif_wrapper_config_t * pstcWrapperConfig; /**< Configuration for Wrapper */ - cy_stc_ethif_tsu_config_t * pstcTSUConfig; /**< Configuration for TSU */ - bool btxq0enable; /**< Tx Q0 Enable */ - bool btxq1enable; /**< Tx Q1 Enable */ - bool btxq2enable; /**< Tx Q2 Enable */ - bool brxq0enable; /**< Rx Q0 Enable */ - bool brxq1enable; /**< Rx Q1 Enable */ - bool brxq2enable; /**< Rx Q2 Enable */ - -} cy_stc_ethif_config_t; - -/** - ****************************************************************************** - ** \brief Interrupt configuration for Ethernet MAC - ******************************************************************************/ -typedef struct -{ - bool btsu_time_match; /**< Time stamp unit time match event */ - bool bwol_rx; /**< Wake on LAN event received */ - bool blpi_ch_rx; /**< LPI indication status bit change received */ /* TODO: LPI, wait for conclusion? */ - bool btsu_sec_inc; /**< TSU seconds register increment */ - bool bptp_tx_pdly_rsp; /**< PTP pdelay_resp frame transmitted */ - bool bptp_tx_pdly_req ; /**< PTP pdelay_req frame transmitted */ - bool bptp_rx_pdly_rsp; /**< PTP pdelay_resp frame received */ - bool bptp_rx_pdly_req; /**< PTP pdelay_req frame received */ - bool bptp_tx_sync; /**< PTP sync frame transmitted */ - bool bptp_tx_dly_req; /**< PTP delay_req frame transmitted */ - bool bptp_rx_sync; /**< PTP sync frame received */ - bool bptp_rx_dly_req; /**< PTP delay_req frame received */ - // bool bpcs_lp_page_rx; /** PCS auto-negotiation link partner page received */ - // bool bpcs_an_complete; /** PCS auto-negotiation has completed */ - bool bext_intr; /**< External input interrupt detected */ - bool bpause_frame_tx; /**< Pause frame transmitted */ - bool bpause_time_zero; /**< Pause time reaches zero or zeroq pause frame received */ - bool bpause_nz_qu_rx; /**< Pause frame with non-zero quantum received */ - bool bhresp_not_ok; /**< DMA hresp not OK */ - bool brx_overrun; /**< Rx overrun error */ - bool bpcs_link_change_det; /**< Link status change detected by PCS */ /* TODO: PCS, wait for conclusion */ - bool btx_complete; /**< Frame has been transmitted successfully */ - bool btx_fr_corrupt; /**< Tx frame corruption */ - bool btx_retry_ex_late_coll; /**< Retry limit exceeded or late collision */ - bool btx_underrun; /**< Tx underrun */ - bool btx_used_read; /**< Used bit set has been read in Tx descriptor list */ - bool brx_used_read; /**< Used bit set has been read in Rx descriptor list */ - bool brx_complete; /**< Frame received successfully and stored */ - bool bman_frame; /**< Management Frame Sent */ -} cy_stc_ethif_interruptconfig_t; - - -/** - ****************************************************************************** - ** \brief filter configuration for Ethernet MAC - ******************************************************************************/ - -typedef struct -{ - cy_en_ethif_filter_type_t typeFilter; /**< typeFilter */ - CEDI_MacAddress filterAddr; /**< filterAddr */ - uint8_t ignoreBytes; /**< e.g. ignoreBytes = 0x01 implies first byte received should not be compared. - * e.g. ignoreBytes = 0x03 implies first and second byte received should not be compared. */ -} cy_stc_ethif_filter_config_t; - -/** \} group_ethif_data_structures */ - - -/** \} group_ethif_data_structures */ - -/*************************************** -* Function Prototypes -***************************************/ -/** -* \addtogroup group_ethif_functions -* \{ -*/ - -cy_en_ethif_status_t Cy_ETHIF_Init(cy_stc_ethif_config_t *pstcEthIfConfig, cy_stc_ethif_interruptconfig_t *pstcInterruptList); -void Cy_ETHIF_RegisterCallbacks(cy_stc_ethif_cb_t *cbFuncsList); -void Cy_ETHIF_DecodeEvent(void); -uint8_t Cy_ETHIF_ClearReleasedBuf(bool bClearAll, bool bTransmitBuf); -cy_en_ethif_status_t Cy_ETHIF_TransmitFrame(uint8_t * pu8TxBuffer, uint16_t u16Length, uint8_t u8QueueIndex, bool bEndBuffer); -cy_en_ethif_status_t Cy_ETHIF_Get1588TimerValue(CEDI_1588TimerVal* stcRetTmrValue); -cy_en_ethif_status_t Cy_ETHIF_Set1588TimerValue(CEDI_1588TimerVal * pstcTmrValue); -cy_en_ethif_status_t Cy_ETHIF_TxPauseFrame(bool bZeroTQ); -cy_en_ethif_status_t Cy_ETHIF_ConfigPause(uint16_t u16PauseQuanta); -cy_en_ethif_status_t Cy_ETHIF_PhyRegWrite(uint8_t u8RegNo, uint16_t u16Data, uint8_t u8PHYAddr); -uint32_t Cy_ETHIF_PhyRegRead(uint8_t u8RegNo, uint8_t u8PHYAddr); -cy_en_ethif_status_t Cy_ETHIF_SetFilterAddress(cy_en_ethif_filter_num_t filterNo, const cy_stc_ethif_filter_config_t* config); -void Cy_ETHIF_SetCopyAllFrames(bool toBeEnabled); -void Cy_ETHIF_SetNoBroadCast(bool rejectBC); - -/** \} group_ethif_functions */ - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXETH */ - -#endif /* CY_ETHIF_H */ - -/** \} group_eth */ - -/* [] END OF FILE */ \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_i3c.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_i3c.h deleted file mode 100644 index a8781e0af2..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_i3c.h +++ /dev/null @@ -1,1827 +0,0 @@ -/***************************************************************************//** -* \file cy_i3c.h -* \version 1.00 -* -* Provides I3C API declarations for the I3C Controller. -* -******************************************************************************** -* \copyright -* Copyright 2019-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_cy_i3c -* \{ -* Driver API for I3C Bus Peripheral -* -* I3C - The Improved Inter-Integrated Circuit (I3C) bus is a MIPI industry-standard. -* -* The functions and other declarations used in this part of the driver are in -* cy_i3c.h. You can also include cy_pdl.h to get access to all functions and declarations -* in the PDL. -* -* The I3C peripheral driver provides an API to implement I3C in Slave, Main-Master, -* or Secondary-Master roles based on the DW I3C hardware block. -* This I3C bus is capable of supporting I3C as well as I2C slave devices as defined -* in the specification. -* I2C slaves are supported with Fast-mode, and Fast-mode Plus with external 50ns -* spike filter as per I3C specification. -* -* Features: -* * An industry-standard I3C bus interface -* * Supports slave, main master, and secondary master operation -* * SCL frequency up to 12.5MHz (SDR data rate 12.5Mbps, HDR-DDR data rate at 25Mbps) -* * In master mode, number of addressable slave devices is 11 -* * Works in active power mode only -* * Does not support I3C HDR-TSP/TSR modes -* * Does not support I3C CDR (clock data recovery) -* * Does not support I3C address arbitration optimizations -* * Does not support I3C IBI with data -* * Does not support I3C time stamping -* * Does not support vendor specific CCCs -* * Does not support I2C slave role -* -******************************************************************************** -* \section group_cy_i3c_configuration Configuration Considerations -******************************************************************************** -* The I3C driver configuration can be divided to number of sequential -* steps listed below: -* * \ref group_i3c_config -* * \ref group_i3c_pins -* * \ref group_i3c_clock -* * \ref group_i3c_data_rate -* * \ref group_i3c_intr -* * \ref group_i3c_enable -* -******************************************************************************** -* \subsection group_i3c_config Configure i3c -******************************************************************************** -* To set up the I3C driver, provide the configuration parameters in the -* \ref cy_stc_i3c_config_t structure. Provide i3cMode to the select -* operation mode slave, master or secondary master-slave. -* To initialize the driver, call \ref Cy_I3C_Init function providing a -* pointer to the populated \ref cy_stc_i3c_config_t -* structure and the allocated \ref cy_stc_i3c_context_t structure. -* -* For I3C slave setup read and write buffer before enabling its -* operation using \ref Cy_I3C_SlaveConfigReadBuf and \ref -* Cy_I3C_SlaveConfigWriteBuf appropriately. Note that the master reads -* data from the slave read buffer and writes data into the slave write buffer. -* -******************************************************************************** -* \subsection group_i3c_pins Assign and Configure Pins -******************************************************************************** -* Only dedicated pins can be used for I3C operation. The HSIOM -* register must be configured to connect dedicated I3C pins to the -* block. Also the open-drain enable pin for I3C must be configured in open-drain -* with internal pull up enabled -* (this pin configuration implies usage of external pull-up resistors) -* -******************************************************************************** -* \subsection group_i3c_clock Assign Clock Divider -******************************************************************************** -* A clock source must be connected to the block to oversample input and -* output signals, in this document this clock will be referred as clk_i3c. -* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk -* driver API to do this. -* -******************************************************************************** -* \subsection group_i3c_data_rate Configure Data Rate -******************************************************************************** -* To get I3C slave operation with the desired data rate, the clk_i3c must be -* fast enough to provide sufficient oversampling. Use the -* \ref group_sysclk driver API to do this. -* -* To get I3C master operation with the desired data rate, the source clock -* frequency and SCL low and high phase duration must be configured. Use the -* \ref group_sysclk driver API to configure source clock frequency. Then call -* \ref Cy_I3C_SetDataRate to set the SCL low, high phase duration -* This function sets SCL low and high phase settings based on -* source clock frequency. -* -******************************************************************************** -* \subsection group_i3c_intr Configure Interrupt -******************************************************************************** -* The interrupt is mandatory for I3C operation. -* The driver provides three interrupt functions: \ref Cy_I3C_Interrupt, -* \ref Cy_I3C_SlaveInterrupt, and \ref Cy_I3C_MasterInterrupt. One of -* these functions must be called in the interrupt handler for the selected -* instance. Call \ref Cy_I3C_SlaveInterrupt when I3C is configured to -* operate as a slave, \ref Cy_I3C_MasterInterrupt when I3C is configured -* to operate as a master and \ref Cy_I3C_Interrupt when I3C is configured -* to operate as master and slave. Using the slave- or master-specific interrupt -* function allows reducing the flash consumed by the I3C driver. Also this -* interrupt must be enabled in the NVIC otherwise it will not work. -* \note -* The I3C driver documentation refers to the \ref Cy_I3C_Interrupt function -* when interrupt processing is mandatory for the operation. This is done to -* simplify the readability of the driver's documentation. The application should -* call the slave- or master-specific interrupt functions \ref Cy_I3C_SlaveInterrupt -* or \ref Cy_I3C_MasterInterrupt, when appropriate. -* -******************************************************************************** -* \subsection group_i3c_enable Enable I3C -******************************************************************************** -* Finally, enable the I3C operation by calling \ref Cy_I3C_Enable. Then I3C -* slave starts respond to the assigned address and I3C master ready to execute -* transfers. -* -******************************************************************************** -* \section group_i3c_use_cases Common Use Cases -******************************************************************************** -* \subsection group_i3c_master_mode Master Operation -******************************************************************************** -* Call \ref Cy_I3C_MasterRead or \ref Cy_I3C_MasterWrite to -* communicate with the slave. These functions do not block and only start a -* transaction. After a transaction starts, the \ref Cy_I3C_Interrupt -* handles further data transaction until its completion (successfully or -* with error occurring). To monitor the transaction, -* use \ref Cy_I3C_GetBusStatus or register callback function using -* \ref Cy_I3C_RegisterEventCallback to be notified about -* \ref group_i3c_macros_callback_events. -* -******************************************************************************** -* \subsection group_i3c_slave Slave Operation -******************************************************************************** -* Slave operation requires the \ref Cy_I3C_Interrupt be -* called inside the interrupt handler. The read and write buffers must -* be provided for the slave to enable communication with the master. Use -* \ref Cy_I3C_SlaveConfigReadBuf and \ref Cy_I3C_SlaveConfigWriteBuf -* for this purpose. Note that after transaction completion the buffer must be -* configured again. Otherwise, the same buffer is used starting from the point -* where the master stopped a previous transaction. -* For example: The read buffer is configured to be 10 bytes and the master reads -* 8 bytes. If the read buffer is not configured again, the next master read -* will start from the 9th byte. -* To monitor the transaction status, use \ref Cy_I3C_GetBusStatus or -* use \ref Cy_I3C_RegisterEventCallback to register a callback function -* to be notified about \ref group_i3c_macros_callback_events. -* -******************************************************************************** -* \section group_i3c_lp Low Power Support -******************************************************************************** -* The I3C driver provides callback functions to handle power mode transition. -* The callback \ref Cy_I3C_DeepSleepCallback must be called -* during execution of \ref Cy_SysPm_CpuEnterDeepSleep \ref Cy_I3C_HibernateCallback -* must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. To trigger the -* callback execution, the callback must be registered before calling the -* power mode transition function. Refer to \ref group_syspm driver for more -* information about power mode transitions and callback registration. -* -* \defgroup group_i3c_macros Macros -* \defgroup group_i3c_enums Enumerated Types -* \defgroup group_i3c_data_structures Data Structures -* \defgroup group_i3c_functions Functions -* \{ -* \defgroup group_i3c_general_functions General -* \defgroup group_i3c_slave_functions Slave -* \defgroup group_i3c_master_functions Master -* \defgroup group_i3c_secondary_master_functions Secondary Master -* \defgroup group_i3c_interrupt_functions Interrupt -* \defgroup group_i3c_low_power_functions Low Power Callbacks -* \} -*/ - -#if !defined (CY_I3C_H) -#define CY_I3C_H - -#include "cy_device_headers.h" -#include "cy_device.h" - -#if defined (CY_IP_MXI3C) - -#include "cy_syspm.h" -#include "cy_i3c_ccc.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/****************************************************************************** - * Constants * - ******************************************************************************/ - -/** -* \addtogroup group_i3c_macros -* \{ -*/ - -/** Driver major version */ -#define CY_I3C_DRV_VERSION_MAJOR (1) //What should these be? - -/** Driver minor version */ -#define CY_I3C_DRV_VERSION_MINOR (0) //What should these be?? - -/** I3C driver identifier */ -#define CY_I3C_ID CY_PDL_DRV_ID(0x2AU) //TBD - What should be here? - -/** -* \addtogroup group_i3c_macros_common_macros Common Macros -* \{ -*/ - -/** Max device address value */ -#define CY_I3C_MAX_ADDR CY_I3C_GENMASK(6, 0) - -/** Max number of slave devices addressable in master mode */ -#define CY_I3C_MAX_DEVS (11) - -/** I3C Broadcast Address */ -#define CY_I3C_BROADCAST_ADDR (0x7E) - -/** \} group_i3c_macros_common_macros */ - -/** -* \defgroup group_i3c_macros_intr_macros Interrupt Status -* \{ -*/ - -/** -* The number of empty locations in the transmit buffer is greater than or -* equal to the specified threshold value. -*/ -#define CY_I3C_INTR_TX_BUFFER_THLD_STS I3C_CORE_INTR_STATUS_TX_THLD_STS_Msk - -/** -* The number of elements in the receive buffer is greater than or -* equal to the specified threshold value. -*/ -#define CY_I3C_INTR_RX_BUFFER_THLD_STS I3C_CORE_INTR_STATUS_RX_THLD_STS_Msk - -/** -* The number of elements in the IBI buffer is greater than or -* equal to the specified threshold value. -*/ -#define CY_I3C_INTR_IBI_BUFFER_THLD_STS I3C_CORE_INTR_STATUS_IBI_THLD_STS_Msk - -/** -* The number of empty locations in the command queue is greater than or -* equal to the specified threshold value. -*/ -#define CY_I3C_INTR_CMD_QUEUE_READY_STS I3C_CORE_INTR_STATUS_CMD_QUEUE_READY_STS_Msk - -/** -* The number of elements in the response queue is greater than or -* equal to the specified threshold value. -*/ -#define CY_I3C_INTR_RESP_READY_STS I3C_CORE_INTR_STATUS_RESP_READY_STS_Msk - -/** -* The transfer is aborted. -*/ -#define CY_I3C_INTR_TRANSFER_ABORT_STS I3C_CORE_INTR_STATUS_TRANSFER_ABORT_STS_Msk - -/** -* The CCC registers are updated by the I3C Master through CCC commands. -*/ -#define CY_I3C_INTR_CCC_UPDATED_STS I3C_CORE_INTR_STATUS_CCC_UPDATED_STS_Msk - -/** -* The dynamic address of the device is assigned through SETDASA or ENTDAA CCC -*/ -#define CY_I3C_INTR_DYN_ADDR_ASSGN_STS I3C_CORE_INTR_STATUS_DYN_ADDR_ASSGN_STS_Msk - -/** -* Error occured in the transfer. -*/ -#define CY_I3C_INTR_TRANSFER_ERR_STS I3C_CORE_INTR_STATUS_TRANSFER_ERR_STS_Msk - -/** -* DEFSLV CCC is received. -*/ -#define CY_I3C_INTR_DEFSLV_STS I3C_CORE_INTR_STATUS_DEFSLV_STS_Msk - -/** -* The read request is received from the current master; command queue is empty. -*/ -#define CY_I3C_INTR_READ_REQ_RECV_STS I3C_CORE_INTR_STATUS_READ_REQ_RECV_STS_Msk - -/** -* The IBI request initiated via SIR request register is addressed and status is updated. -*/ -#define CY_I3C_INTR_IBI_UPDATED_STS I3C_CORE_INTR_STATUS_IBI_UPDATED_STS_Msk - -/** -* The role of the controller is changed. -*/ -#define CY_I3C_INTR_BUSOWNER_UPDATED_STS I3C_CORE_INTR_STATUS_BUSOWNER_UPDATED_STS_Msk - -/** -* Provides the list of allowed sources for slave mode. -*/ -#define CY_I3C_SLV_INTR_Msk (CY_I3C_INTR_CCC_UPDATED_STS | CY_I3C_INTR_DYN_ADDR_ASSGN_STS | \ - CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_READ_REQ_RECV_STS ) - -/** \} group_i3c_macros_intr_macros */ - -/** -* \defgroup group_i3c_macros_master_status I3C Master Status -* Macros to check current I3C master status returned by -* \ref Cy_I3C_GetBusStatus function. Each I3C master status is encoded -* in a separate bit, therefore multiple bits may be set to indicate the -* current status. -* \{ -*/ - -/** -* The master is busy executing operation started by \ref Cy_I3C_SendCCCCmd or -* \ref Cy_I3C_MasterRead or \ref Cy_I3C_MasterWrite or \ref Cy_I3C_MasterStartEntDaa -* \ref Cy_I3C_MasterSendHdrCmds. -*/ -#define CY_I3C_MASTER_BUSY (0x00010000UL) - -/** -* The master has currently performed a broadcast CCC write transfer -*/ -#define CY_I3C_MASTER_BROADCAST_CCC_WR_XFER (0x00000001UL) - -/** -* The master has currently performed a directed CCC write transfer -*/ -#define CY_I3C_MASTER_DIRECTED_CCC_WR_XFER (0x00000002UL) - -/** -* The master has currently performed a broadcast CCC read transfer -*/ -#define CY_I3C_MASTER_DIRECTED_CCC_RD_XFER (0x00000004UL) - -/** -* The master has currently performed DAA -*/ -#define CY_I3C_MASTER_ENTDAA_XFER (0x00000008UL) - -/** -* The master has currently performed a privete SDR write to an I3C Slave -*/ -#define CY_I3C_MASTER_I3C_SDR_WR_XFER (0x00000010UL) - -/** -* The master has currently performed a privete SDR read from an I3C Slave -*/ -#define CY_I3C_MASTER_I3C_SDR_RD_XFER (0x00000020UL) - -/** -* The master has currently performed a privete SDR read to an I2C Slave -*/ -#define CY_I3C_MASTER_I2C_SDR_WR_XFER (0x00000040UL) - -/** -* The master has currently performed a privete SDR read from an I2C Slave -*/ -#define CY_I3C_MASTER_I2C_SDR_RD_XFER (0x00000080UL) - -/** -* The master has currently performed a private HDR write in DDR mode -*/ -#define CY_I3C_MASTER_HDR_DDR_WR_XFER (0x00000100UL) - -/** -* The master has currently performed a private HDR read in DDR mode -*/ -#define CY_I3C_MASTER_HDR_DDR_RD_XFER (0x00000200UL) - -/** -* The master has currently responded to a IBI request -*/ -#define CY_I3C_MASTER_IBI_XFER (0x00000400UL) - -/** -* The master is in HALT state due to error in the transfer -*/ -#define CY_I3C_MASTER_HALT_STATE (0x00000800UL) //This is the BUS_ERR - Ask - -/** -* The transaction was aborted -*/ -#define CY_I3C_MASTER_XFER_ABORTED (0X00001000UL) - -/** \} group_i3c_macros_master_status */ - -/** -* \defgroup group_i3c_macros_slave_status I3C Slave Status -* Macros to check current I3C slave status returned by -* \ref Cy_I3C_GetBusStatus function. Each I3C slave status is encoded -* in a separate bit, therefore multiple bits may be set to indicate the -* current status. -* \{ -*/ - -/** -* The master has finished reading data from the slave -*/ -#define CY_I3C_SLAVE_RD_CMPLT (0x00002000UL) - -/** -* The master has finished writing data into the slave -*/ -#define CY_I3C_SLAVE_WR_CMPLT (0x00004000UL) - -/** There is a read transaction in progress */ -#define CY_I3C_SLAVE_RD_BUSY (0x00008000UL) - -/** There is a write transaction in progress */ -#define CY_I3C_SLAVE_WR_BUSY (0x00010000UL) - -/** \} group_i3c_macros_slave_status */ - -/** -* \defgroup group_i3c_macros_callback_events I3C Callback Events -* \{ -* Macros to check I3C events passed by \ref cy_cb_i3c_handle_events_t callback. -* Each event is encoded in a separate bit, and therefore it is possible to -* notify about multiple events. -*/ - -/** The master write started by \ref Cy_I3C_MasterWrite is complete */ -#define CY_I3C_MASTER_WR_CMPLT_EVENT (0x00000001UL) - -/** The master read started by \ref Cy_I3C_MasterRead is complete */ -#define CY_I3C_MASTER_RD_CMPLT_EVENT (0x00000002UL) - -/** CY_I3C_MASTER_WR_EARLY_TERMINATION_EVENT */ -#define CY_I3C_MASTER_WR_EARLY_TERMINATION_EVENT (0x00000004UL) - -/** -* Indicates the I3C hardware has detected an error. -*/ - -/** CY_I3C_CRC_ERROR_EVENT */ -#define CY_I3C_CRC_ERROR_EVENT (0x00000008UL) -/** CY_I3C_PARITY_ERROR_EVENT */ -#define CY_I3C_PARITY_ERROR_EVENT (0x00000010UL) -/** CY_I3C_FRAME_ERROR_EVENT */ -#define CY_I3C_FRAME_ERROR_EVENT (0x00000020UL) -/** CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT */ -#define CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT (0x00000040UL) -/** CY_I3C_ADDR_NACK_ERROR_EVENT */ -#define CY_I3C_ADDR_NACK_ERROR_EVENT (0x00000080UL) -/** CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT */ -#define CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT (0x00000100UL) -/** CY_I3C_XFER_ABORTED_ERROR_EVENT */ -#define CY_I3C_XFER_ABORTED_ERROR_EVENT (0x00000200UL) -/** CY_I3C_I2C_SLV_WDATA_NACK_ERROR_EVENT */ -#define CY_I3C_I2C_SLV_WDATA_NACK_ERROR_EVENT (0x00000400UL) -/** CY_I3C_MASTER_EARLY_TERMINATION_EVENT */ -#define CY_I3C_MASTER_EARLY_TERMINATION_EVENT (0x00000800UL) -/** CY_I3C_MASTER_ERROR_M0_EVENT */ -#define CY_I3C_MASTER_ERROR_M0_EVENT (0X00001000UL) - -/** CY_I3C_MASTER_ERR_EVENT */ -#define CY_I3C_MASTER_ERR_EVENT (CY_I3C_CRC_ERROR_EVENT| CY_I3C_PARITY_ERROR_EVENT| CY_I3C_FRAME_ERROR_EVENT| \ - CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT| CY_I3C_ADDR_NACK_ERROR_EVENT| CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT| \ - CY_I3C_XFER_ABORTED_ERROR_EVENT| CY_I3C_I2C_SLV_WDATA_NACK_ERROR_EVENT| CY_I3C_MASTER_ERROR_M0 ) - -/** CY_I3C_SLAVE_ERR_EVENT */ -#define CY_I3C_SLAVE_ERR_EVENT (CY_I3C_CRC_ERROR_EVENT| CY_I3C_PARITY_ERROR_EVENT| CY_I3C_FRAME_ERROR_EVENT| \ - CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT | CY_I3C_MASTER_EARLY_TERMINATION_EVENT) - -/** The slave device is assigned a dynamic address through SETDASA or ENTDAA CCC from the master */ -#define CY_I3C_SLAVE_ASSIGNED_DYN_ADDR_EVENT (0X00002000UL) - -/** -* The master has read all data out of the configured Read buffer. -* This event can be used to configure the next Read buffer. If the buffer -* remains empty, the CY_I3C_DEFAULT_TX bytes are returned to the master. -*/ - -/** CY_I3C_SLAVE_RD_BUF_EMPTY_EVENT */ -#define CY_I3C_SLAVE_RD_BUF_EMPTY_EVENT (0x00004000UL) - -/** CY_I3C_SLAVE_MAX_RD_LEN_UPDT_EVENT */ -#define CY_I3C_SLAVE_MAX_RD_LEN_UPDT_EVENT (0X00008000UL) - -/** CY_I3C_SLAVE_MAX_WR_LEN_UPDT_EVENT */ -#define CY_I3C_SLAVE_MAX_WR_LEN_UPDT_EVENT (0X00010000UL) - -/** -* Indicates the master completed reading from the slave (set by the master NAK -* or Stop) -*/ -#define CY_I3C_SLAVE_RD_CMPLT_EVENT (0x00020000UL) - -/** -* Indicates the master completed writing to the slave (set by the master Stop -* or Restart) -*/ -#define CY_I3C_SLAVE_WR_CMPLT_EVENT (0x00040000UL) - -/** -* One of the CCC register is updated by I3C Master through CCC commands -*/ -#define CY_I3C_SLAVE_CCC_REG_UPDATED_EVENT (0x00080000UL) - -/** -* There is no valid command in the command queue -*/ -#define CY_I3C_SLAVE_NO_VALID_CMD_IN_CMDQ_EVENT (0x00100000UL) - -/** -* The data in Tx FIFO is not equal to the data length size of the command -* or the TX_START_THLD value or the Response queue is full -*/ -#define CY_I3C_SLAVE_DATA_NOT_READY_EVENT (0x00200000UL) - -/** -* DEFSLVS CCC is received. -*/ -#define CY_I3C_DEFSLV_EVENT (0x00400000UL) - -/** -* Role of the controller changed from Master to Slave or vice-versa -*/ -#define CY_I3C_CONTROLLER_ROLE_UPDATED_EVENT (0x00800000UL) - - -/** \} group_i3c_macros_callback_events */ - -/** \cond INTERNAL */ - -/* COMMAND_QUEUE_PORT Register */ -#define I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_Pos 0UL -#define I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_Msk 0x7UL -/* Transfer Command Structure */ -#define I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD 0x0UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TID_Pos 3UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TID_Msk 0x78UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CMD_Pos 7UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CMD_Msk 0x7F80UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CP_Pos 15UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CP_Msk 0x8000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX_Pos 16UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX_Msk 0x1F0000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED_Pos 21UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED_Msk 0xE00000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Pos 26UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk 0x4000000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Pos 27UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk 0x8000000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_RnW_Pos 28UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_RnW_Msk 0x10000000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Pos 30UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk 0x40000000UL -/* Transfer Argument Command Structure */ -#define I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG 0x01 -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH_Pos 16UL -#define I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH_Msk 0xFFFF0000UL -/* Short Data Argument Structure */ -#define I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG 0x02UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB_Pos 3UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB_Msk 0x38UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0_Pos 8UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0_Msk 0xFF00UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_1_Pos 16UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_1_Msk 0xFF0000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_2_Pos 23UL -#define I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_2_Msk 0xFF000000UL -/* To select the valid data bytes of the Short Data Argument */ -#define CY_I3C_BYTE_STROBE1 1UL -#define CY_I3C_BYTE_STROBE2 3UL -#define CY_I3C_BYTE_STROBE3 7UL -/* Address Assignment Command Structure */ -#define I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_ADDR_ASSGN_CMD 0x03UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_TID_Pos 0x3UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_TID_Msk 0x78UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_CMD_Pos 7UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_CMD_Msk 0x7F80UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_INDX_Pos 16UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_INDX_Msk 0x1F0000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_COUNT_Pos 21UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_COUNT_Msk 0x3E00000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_ROC_Pos 26UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_ROC_Msk 0x4000000UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_TOC_Pos 30UL -#define I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_TOC_Msk 0x40000000UL - -/* RESPONSE_QUEUE_PORT Register */ -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Pos 0UL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk 0xFFFFUL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_CCCT_Pos 16UL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_CCCT_Msk 0xFF0000UL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_TID_Pos 24UL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_TID_Msk 0xF000000UL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS_Pos 28UL -#define I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS_Msk 0xF0000000UL - -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_DATA_LENGTH_Pos 0UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk 0xFFFFUL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_CCC_HDR_HEADER_Pos 16UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_CCC_HDR_HEADER_Msk 0xFF0000UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_TID_Pos 24UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_TID_Msk 0x7000000UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_RX_RSP_Pos 27UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_RX_RSP_Msk 0x8000000UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_ERR_STS_Pos 28UL -#define I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_ERR_STS_Msk 0xF0000000UL - -/* BCR Register */ -#define CY_I3C_CORE_BCR_DEVICE_ROLE_Msk (0xC0) -#define CY_I3C_CORE_BCR_I3C_SLAVE (0 << 6) -#define CY_I3C_CORE_BCR_I3C_MASTER (1 << 6) -#define CY_I3C_CORE_BCR_HDR_CAP_Msk (0x20) -#define CY_I3C_CORE_BCR_BRIDGE_Msk (0x10) -#define CY_I3C_CORE_BCR_OFFLINE_CAP_Msk (0x08) -#define CY_I3C_CORE_BCR_IBI_PAYLOAD_Msk (0x04) -#define CY_I3C_CORE_BCR_IBI_REQ_CAP_Msk (0x02) -#define CY_I3C_CORE_BCR_MAX_DATA_SPEED_LIM_Msk (0x01) - -/* LVR register */ -#define CY_I3C_LVR_LEGACY_I2C_INDEX_MASK (0xE0) -#define CY_I3C_LVR_I2C_MODE_INDICATOR (0x10) - -/* IBI Identifiers */ -#define CY_I3C_HOT_JOIN_ADDR (0x02) -#define CY_I3C_IBI_QUEUE_IBI_ADDR(x) ((x) >> 1) -#define CY_I3C_IBI_TYPE_HOT_JOIN(x) (CY_I3C_IBI_QUEUE_IBI_ADDR((x)) == CY_I3C_HOT_JOIN_ADDR && !((x) & CY_I3C_BIT(0))) -#define CY_I3C_IBI_TYPE_MASTERSHIP_REQUEST(x) (CY_I3C_IBI_QUEUE_IBI_ADDR((x)) != CY_I3C_HOT_JOIN_ADDR && !((x) & CY_I3C_BIT(0))) -#define CY_I3C_IBI_TYPE_SIR_REQUEST(x) (CY_I3C_IBI_QUEUE_IBI_ADDR((x)) != CY_I3C_HOT_JOIN_ADDR && ((x) & CY_I3C_BIT(0))) -#define CY_I3C_IBI_SIR_REQ_ID(x) ((((x) & CY_I3C_GENMASK(6, 5)) >> 5) + ((x) & CY_I3C_GENMASK(4, 0))) - -/* Interrupt Mask */ -#define CY_I3C_INTR_MASK ( I3C_CORE_INTR_STATUS_EN_TX_THLD_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_RX_THLD_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_IBI_THLD_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_CMD_QUEUE_READY_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_RESP_READY_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_TRANSFER_ABORT_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_CCC_UPDATED_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_DYN_ADDR_ASSGN_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_TRANSFER_ERR_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_DEFSLV_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_READ_REQ_RECV_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_IBI_UPDATED_STS_EN_Msk | \ - I3C_CORE_INTR_STATUS_EN_BUSOWNER_UPDATED_STS_EN_Msk ) - -/* I3C states */ -#define CY_I3C_IDLE (0x10000000UL) -#define CY_I3C_IDLE_MASK (0x10000000UL) - -/* Master states */ -#define CY_I3C_MASTER_ACTIVE (0X00100000UL) -#define CY_I3C_MASTER_RX (0x00100001UL) -#define CY_I3C_MASTER_TX (0x00100002UL) - -/* Slave states */ -#define CY_I3C_SLAVE_ACTIVE (0x00001000UL) -#define CY_I3C_SLAVE_RX (0x00001001UL) -#define CY_I3C_SLAVE_TX (0x00001002UL) - -/* FIFO size */ -#define CY_FIFO_SIZE (256UL) - -#define CY_I3C_FIFO_SIZE CY_FIFO_SIZE -#define CY_I3C_HALF_FIFO_SIZE (CY_FIFO_SIZE / 2UL) - -#define CY_I3C_DEFAULT_RETURN (0xFFUL) - -/* Convert the timeout in milliseconds to microseconds */ -#define CY_I3C_CONVERT_TIMEOUT_TO_US(timeoutMs) ((timeoutMs) * 1000UL) - -/* I3C data rates */ -#define CY_I3C_SDR_DATA_RATE (12500000U) -#define CY_I3C_SDR1_DATA_RATE (8000000U) -#define CY_I3C_SDR2_DATA_RATE (6000000U) -#define CY_I3C_SDR3_DATA_RATE (4000000U) -#define CY_I3C_SDR4_DATA_RATE (2000000U) -#define CY_I3C_HDRDDR_DATA_RATE (25000000U) -#define CY_I3C_BUS_I2C_FM_TLOW_MIN_NS (1300) -#define CY_I3C_BUS_I2C_FMP_TLOW_MIN_NS (500) -#define CY_I3C_BUS_THIGH_MAX_NS (41) -#define CY_I3C_SCL_I3C_TIMING_CNT_MIN (5) - - -/* I2C data rates max (Hz): standard, fast and fast plus modes */ -#define CY_I3C_I2C_FM_DATA_RATE (400000U) -#define CY_I3C_I2C_FMP_DATA_RATE (1000000U) - -#define CY_I3C_IS_MODE_VALID(mode) ( (CY_I3C_SLAVE == (mode)) || \ - (CY_I3C_MASTER == (mode)) || \ - (CY_I3C_SECONDARY_MASTER == (mode)) ) -#define CY_I3C_IS_BUS_MODE_VALID(mode) ( (CY_I3C_BUS_PURE == (mode)) || \ - (CY_I3C_BUS_MIXED_FAST == (mode)) || \ - (CY_I3C_BUS_MIXED_SLOW == (mode)) ) -#define CY_I3C_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) ) - -#define CY_I3C_IS_SDR_DATA_RATE_VALID(dataRateHz) ( ((dataRateHz) > 0UL) && \ - ((dataRateHz) <= CY_I3C_SDR_DATA_RATE) ) - -#define CY_I3C_IS_HDR_DATA_RATE_VALID(dataRateHz) ( ((dataRateHz) > 0UL) && \ - ((dataRateHz) <= CY_I3C_HDRDDR_DATA_RATE) ) - -#define CY_I3C_IS_TIMEOUT_VALID(timeoutMs) ( (timeoutMs) <= (0xFFFFFFFFUL / 1000UL) ) - -#define CY_IS_I3C_ADDR_VALID(addr) ( (0U == ((addr) & 0x80U)) ) - -#define CY_IS_I3C_BUFFER_VALID(buffer, size) ( (NULL != (buffer)) && ((size) > 0UL) ) - -#define CY_I3C_IS_BUFFER_SIZE_VALID(size) ( ((size) > 0UL) && \ - ((size) <= CY_I3C_FIFO_SIZE) ) - - -/* Default Values */ - -#define I3C_CORE_QUEUE_THLD_CTRL_DEF_VAL (_VAL2FLD(I3C_CORE_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD, 1UL) | \ - _VAL2FLD(I3C_CORE_QUEUE_THLD_CTRL_RESP_BUF_THLD, 1UL) | \ - _VAL2FLD(I3C_CORE_QUEUE_THLD_CTRL_IBI_STATUS_THLD, 1UL)) - -#define I3C_CORE_DATA_BUFFER_THLD_CTRL_DEF_VAL (_VAL2FLD(I3C_CORE_DATA_BUFFER_THLD_CTRL_TX_EMPTY_BUF_THLD, 1UL) | \ - _VAL2FLD(I3C_CORE_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD, 1UL) | \ - _VAL2FLD(I3C_CORE_DATA_BUFFER_THLD_CTRL_TX_START_THLD, 1UL) | \ - _VAL2FLD(I3C_CORE_DATA_BUFFER_THLD_CTRL_RX_START_THLD, 1UL)) - -/** \endcond */ - -/** \} group_i3c_macros */ - -/******************************************************************************* -* Enumerated Types -*******************************************************************************/ - -/** -* \addtogroup group_i3c_enums -* \{ -*/ - -/** I3C status codes */ -typedef enum -{ - /** Operation completed successfully */ - CY_I3C_SUCCESS = 0U, - - /** One or more of input parameters are invalid */ - CY_I3C_BAD_PARAM = (CY_I3C_ID| CY_PDL_STATUS_ERROR | 1U), - - /** - * The master is not ready to start a new transaction. - * Either the master is still processing a previous transaction or in the - * master-slave mode, the slave operation is in progress. - */ - CY_I3C_MASTER_NOT_READY = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 2U), - - /** - * The master failed to attach the slave device to the bus - * as there already exists maximum number of devices on the bus. - */ - CY_I3C_MASTER_MAX_DEVS_PRESENT = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 3U), - - /** - * The master rejected to attach an I2C device without 50ns Spike filter. - */ - CY_I3C_MASTER_BAD_I2C_DEVICE = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 4U), - - /** - * Unsupported CCC command - */ - CY_I3C_MASTER_CCC_NOT_SUPPORTED =(CY_I3C_ID | CY_PDL_STATUS_ERROR | 5U), - - /** - * SDR Master Error Code M0 for Illegally formatted CCC Response - */ - CY_I3C_MASTER_ERROR_M0 = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 6U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * CRC Error - */ - CY_I3C_MASTER_CRC_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 7U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * Parity Error - */ - CY_I3C_MASTER_PARITY_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 8U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * Frame Error - */ - CY_I3C_MASTER_FRAME_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 9U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * Broadcast Address NACK Error - */ - CY_I3C_MASTER_BROADCAST_ADDR_NACK_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 10U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * Address NACK Error - Slave NACKs for the dynamic address assignment during - * ENTDAA process. - */ - CY_I3C_MASTER_ADDR_NACK_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 11U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * TX/RX Buffer Overflow Error - Only for HDR Transfers - */ - CY_I3C_MASTER_BUFFER_OVERFLOW_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 12U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * Transfer Aborted Error - */ - CY_I3C_MASTER_XFER_ABORTED_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 13U ), - - /** - * Error Type of the proccessed command received in Response Data Structure: - * I2C Slave Write Data NACK Error - */ - CY_I3C_MASTER_I2C_SLV_WDATA_NACK_ERROR = ( CY_I3C_ID | CY_PDL_STATUS_ERROR | 14U ), - - /** The master NACKed the IBI */ - CY_I3C_MASTER_IBI_NACK = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 15U), - - /** The master ACKed the Mastership Request IBI */ - CY_I3C_MASTER_MR_IBI_ACK = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 16U), - - /** The master ACKed the Slave Interrupt Request IBI */ - CY_I3C_MASTER_SIR_IBI_ACK = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 17U), - - /** The master ACKed the Hot-join IBI */ - CY_I3C_MASTER_HOTJOIN_IBI_ACK = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 18U), - - /** Free address unavailable */ - CY_I3C_MASTER_FREE_ADDR_UNAVIAL = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 19U), - - /** The device is not HDR capable */ - CY_I3C_NOT_HDR_CAP = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 20U), - - /** The buffer size is greater than the FIFO size */ - CY_I3C_BAD_BUFFER_SIZE = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 21U), - - /** The secondary master responded with incorrect address to GETACCMST CCC */ - CY_I3C_ADDR_MISMATCH = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 22U), - - /** The device is not yet assigned a dynamic address */ - CY_I3C_ADDR_INVALID = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 23U), - - /** In Slave mode of operation, the Master has disabled SIR through DISEC */ - CY_I3C_SIR_DISABLED = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 24U), - - /** In Slave mode of operation, the Master has disabled MR through DISEC */ - CY_I3C_MR_DISABLED = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 25U), - - /** The Slave device failed to issue IBI */ - CY_I3C_IBI_NOT_ATTEMPTED = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 26U), - - /** There are no secondary master devices on the bus */ - CY_I3C_NO_SECONDARY_MASTER_DEVICES = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 27U), - - /** The slave device requested generation of hot-join event generation */ //tbd - provide more clarity in the comment - CY_I3C_BAD_EVENT_REQ = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 28U), - - /** The device is not a secondary master */ - CY_I3C_NOT_SECONDARY_MASTER = (CY_I3C_ID | CY_PDL_STATUS_ERROR | 29U), - -} cy_en_i3c_status_t; - -/** I3C Operation Modes */ -typedef enum -{ - CY_I3C_SLAVE = 1U, /**< Configures I3C for Slave operation */ - CY_I3C_MASTER = 2U, /**< Configures I3C for Main Master operation */ - CY_I3C_SECONDARY_MASTER = 3U, /**< Configures I3C for Secondory Master-Slave operation */ -} cy_en_i3c_mode_t; - -/** I3C Bus Modes */ -typedef enum -{ - CY_I3C_BUS_PURE, /**< Only I3C devices are connected to the bus. No limitation expected */ - CY_I3C_BUS_MIXED_FAST, /**< I2C devices with 50ns spike filter are present on the bus. - High SCL pulse has to stay below 50ns when transmitting I3C frames */ - CY_I3C_BUS_MIXED_SLOW, /**< I2C devices without 50ns spike filter are present on the bus */ -} cy_en_i3c_bus_mode_t; - -/** I3C Address Slot Statuses */ -typedef enum -{ - CY_I3C_ADDR_SLOT_FREE, /**< Address is free */ - CY_I3C_ADDR_SLOT_RSVD, /**< Address is reserved */ - CY_I3C_ADDR_SLOT_I2C_DEV, /**< Address is assigned to an I2C device */ - CY_I3C_ADDR_SLOT_I3C_DEV, /**< Address is assigned to an I3C device */ - CY_I3C_ADDR_SLOT_STATUS_MASK = 3, /**< Address slot mask */ -}cy_en_i3c_addr_slot_status_t; - -/** I3C IBI Types */ -typedef enum -{ - CY_I3C_IBI_HOTJOIN, /**< IBI Hot join Request */ - CY_I3C_IBI_SIR, /**< IBI Slave Interrupt Request */ - CY_I3C_IBI_MASTER_REQ, /**< IBI Master ownership Request */ -} cy_en_i3c_ibi_type_t; - -/** I3C Transaction IDs for HDR and SDR commands */ -typedef enum -{ - CY_I3C_MASTER_SDR_WRITE_TID = 1, /**< TID for SDR Write Transfer */ - CY_I3C_MASTER_SDR_READ_TID = 2, /**< TID for SDR Read Transfer */ - CY_I3C_MASTER_HDR_WRITE_TID = 3, /**< TID for HDR Write Transfer */ - CY_I3C_MASTER_HDR_READ_TID = 4, /**< TID for HDR Read Transfer */ -}cy_en_i3c_tid_t; - -/** I3C Mode, SDR and HDR transfer speeds */ -typedef enum -{ - CY_I3C_SDR0 = 0, /**< I3C mode transfer speed - SDR0*/ - CY_I3C_SDR1 = 1, /**< I3C mode transfer speed - SDR1*/ - CY_I3C_SDR2 = 2, /**< I3C mode transfer speed - SDR2*/ - CY_I3C_SDR3 = 3, /**< I3C mode transfer speed - SDR3*/ - CY_I3C_SDR4 = 4, /**< I3C mode transfer speed - SDR4*/ - CY_I3C_HDR_DDR = 6, /**< I3C mode transfer speed - HDR-DDR */ -}cy_en_i3c_data_speed_t; - -/** I2C Mode, SDR transfer speeds */ -typedef enum -{ - CY_I3C_FMP_I2C = 0, /**< I2C mode transfer speed - Fast Mode Plus */ - CY_I3C_FM_I2C = 1, /**< I2C mode transfer speed - Fast Mode */ -}cy_en_i2c_data_speed_t; -/** \} group_i3c_enums */ - -/******************************************************************************* -* Type Definitions -*******************************************************************************/ - -/** -* \addtogroup group_i3c_data_structures -* \{ -*/ - -/** -* I3C device IBI structure. -* Defines an IBI event. -*/ -typedef struct cy_stc_i3c_ibi -{ - /** IBI event type */ - cy_en_i3c_ibi_type_t event; - - /** Address of the device requesting IBI */ - uint8_t slaveAddress; - - /** IBI Status. Indicates the master response for the received IBI */ - uint32_t status; -}cy_stc_i3c_ibi_t; - -/** -* Provides the typedef for the callback function called in the -* \ref Cy_I3C_Interrupt to notify the user about occurrences of -* \ref group_i3c_macros_callback_events. -*/ -typedef void (* cy_cb_i3c_handle_events_t)(uint32_t event); - -/** -* Provides the typedef for the callback function called in the -* \ref Cy_I3C_Interrupt to notify the user about occurrences of -* \ref group_i3c_macros_callback_events. -*/ -typedef void (* cy_cb_i3c_handle_ibi_t)(cy_stc_i3c_ibi_t *event); - -/** -* I2C device structure. -* Defines an I2C device. -* It is mandatory to provide I2C device static address and lvr information. -*/ -typedef struct cy_stc_i2c_device -{ - /** Static address of the I2C device */ - uint8_t staticAddress; - - /** Legacy Virtual Register */ - uint8_t lvr; -} cy_stc_i2c_device_t; - -/** -* I3C device structure. -* Defines an I3C device. -* StaticAddress of the I3C device if provided will be used by the controller -* to initiate the dynamic address assignment procedure through SETDASA. -* Desired I3C dynamic address to be used can be provided, but if set to zero, -* available free address will be assigned to the device by the controller. -*/ -typedef struct cy_stc_i3c_device -{ - /** 48 bit provisional ID of I3C device */ - uint64_t provisonalID; - - /** Device Charactaristic Register of I3C device */ - uint8_t dcr; - - /** Bus Charactaristic Register of I3C device */ - uint8_t bcr; - - /** Static address of the I3C device if used */ - uint8_t staticAddress; - - /** - * Desired dynamic address for I3C device. - * If set to zero, available free address will be assigned by I3C controller. - */ - uint8_t dynamicAddress; - - /** Max private SDR read length in bytes */ - uint16_t mrl; - - /** Max private SDR write length in bytes */ - uint16_t mwl; - - /** Max read speed information */ - uint8_t maxReadDs; - - /** Max write speed information */ - uint8_t maxWriteDs; - - /** Max read turn-around time in micro -seconds */ - uint8_t maxReadTurnaround[3]; - - /** Supported HDR modes */ - uint8_t HDRCap; - - /** - * Support for HDR Mode. - * true: HDR modes supported. HDRCap member for the device is valid. - * false: HDR modes are not supported. - */ - bool hdrSupport; - - /** - * Max data speed limitation. - * true: Limitation on max data speed. maxReadDs, maxWriteDs, maxReadTurnaround members for the device are valid - * false: No limitation on max data speed - */ - bool speedLimit; -}cy_stc_i3c_device_t; - -/** A local list of devices on the bus */ -typedef struct cy_stc_i3c_master_devlist -{ - /** Identifies the device type */ - bool i2c; - - /** I2C/I3C device descriptor */ - union - { - cy_stc_i3c_device_t i3cDevice; - cy_stc_i2c_device_t i2cDevice; - }; -}cy_stc_i3c_master_devlist_t; - -/** Device Charactersitic Table structure */ -typedef struct cy_stc_i3c_dev_char -{ - uint32_t LSBProvisionalID; /**< The LSB 32-bit value of provisional ID */ - uint32_t MSBProvisionalID; /**< The MSB 16-bit value of provisional ID */ - uint32_t DCR_BCR; /**< DCR [7:0] and BCR [15:8] of the I3C device */ - uint32_t dynamicAddress; /**< Dynamic address [7:0] of the I3C device */ -}cy_stc_i3c_dev_char_t; - -/** 64-bit CCC structure */ -typedef struct cy_stc_i3c_ccc -{ - uint32_t cmdHigh; /**< cmdHigh */ - uint32_t cmdLow; /**< cmdLow */ -}cy_stc_i3c_ccc_t; - -/** I3C bus configuration structure */ -typedef struct cy_stc_i3c_config -{ - /** Specifies the mode of I3C controller operation */ - cy_en_i3c_mode_t i3cMode; - - /** Specifies the mode of I3C bus operation */ - cy_en_i3c_bus_mode_t i3cBusMode; - - /** Use the SDMA for Rx/Tx */ - bool useDma; - - /** The frequency of the clock connected to the I3C block in Hz. */ - uint32_t i3cClockHz; - - /** The desired I3C data Rate in Hz. */ - uint32_t i3cSclRate; - - /** SDR only or SDR and HDR capable - true: SDR and HDR - false: SDR only - */ - bool hdrCapable; - - /** - * Max data speed limitation. - * true: Limitation on max data speed. maxReadDs, maxWriteDs, maxReadTurnaround members for the device are valid - * false: No limitation on max data speed - */ - bool speedLimit; - - /** The device characteristic value of the I3C Device */ - uint8_t dcr; - - /** The Provisional ID of the Device */ - uint64_t pid; - - /** Below members are only applicable for the Slave mode */ - - /** The static address of the I3C Slave Device, if present */ - uint8_t staticAddress; - - /** Enable/Disable Hot-join */ - bool hotjoinEnable; - -} cy_stc_i3c_config_t; - -/** I3C CCC command payload structure */ -typedef struct cy_stc_i3c_ccc_payload -{ - /** Payload length */ - uint16_t len; - - /** Payload data */ - void *data; -} cy_stc_i3c_ccc_payload_t; - -/** I3C CCC command structure */ -typedef struct cy_stc_i3c_ccc_cmd -{ - /** CCC command id */ - uint8_t cmd; - - /** CCC command payload or NULL */ - cy_stc_i3c_ccc_payload_t *data; - - /** Destination address */ - uint8_t address; -}cy_stc_i3c_ccc_cmd_t; - -/** I3C Master information */ -typedef struct cy_stc_i3c_master -{ - /** two bits per address to depict the status of the addresses - 8*4*8 */ - unsigned long addrslotsStatusArray[((CY_I3C_MAX_ADDR + 1) * 2) / CY_I3C_BITS_PER_LONG]; - - /** immediate last address, from the address list, assigned as dynamic address to the slave device */ - int8_t lastAddress; - - /** index of the free position wrt the Device Address Table */ - uint32_t freePos; - - /** the number of devices on the bus */ - uint32_t devCount; - - /** Count of i2c devices on the bus */ - uint32_t i2cDeviceCount; - - /** Number of dynamically addressed devices */ - uint32_t dynAddrDevCount; -}cy_stc_i3c_master_t; - -/** I3C HDR command Structure */ -typedef struct cy_stc_i3c_hdr_cmd -{ - /** - * Command opcode. Bit 7 encodes the direction of the data transfer, if - * set this is a read, otherwise this is a write. - */ - uint8_t code; - - /** Number of data words (a word is 16bits wide) to transfer */ - uint32_t ndatawords; - - /** Input/Output buffer */ - union - { - uint16_t *in; - const uint16_t *out; - }data; -}cy_stc_i3c_hdr_cmd_t; - - -/** -* I3C context structure. -* All fields for the context structure are internal. Firmware never reads or -* writes these values. Firmware allocates the structure and provides the -* address of the structure to the driver in function calls. Firmware must -* ensure that the defined instance of this structure remains in scope -* while the drive is in use. -*/ -typedef struct cy_stc_i3c_context -{ - /** \cond INTERNAL */ - - volatile uint32_t state; /**< The driver state */ - cy_en_i3c_mode_t i3cMode; /** Specifies the mode of i3c controller operation */ - cy_en_i3c_bus_mode_t i3cBusMode; /** Specifies the mode of i3c bus operation */ - - uint32_t i3cSclRate; - uint32_t i3cClockHz; - - volatile uint32_t masterStatus; /**< The master status */ - - uint8_t *masterBuffer; /**< The pointer to the master buffer (either for a transmit or a receive operation) */ - uint32_t masterBufferSize; /**< The current master buffer size */ - volatile uint32_t masterBufferIdx; /**< The current location in the master buffer */ - volatile uint8_t destDeviceAddr; /**< The destination device address in the transfers */ - - volatile uint32_t slaveStatus; /**< The slave status */ - volatile bool slaveRdBufEmpty; /**< Tracks slave Read buffer empty event */ - - uint8_t *slaveTxBuffer; /**< The pointer to the slave transmit buffer (a master reads from it) */ - uint32_t slaveTxBufferSize; /**< The current slave transmit buffer size */ - volatile uint32_t slaveTxBufferIdx; /**< The current location in the slave buffer */ - volatile uint32_t slaveTxBufferCnt; /**< The number of transferred bytes */ - - uint8_t *slaveRxBuffer; /**< The pointer to the slave receive buffer (a master writes into it) */ - uint32_t slaveRxBufferSize; /**< The current slave receive buffer size */ - volatile uint32_t slaveRxBufferIdx; /**< The current location in the slave buffer */ - volatile uint32_t slaveRxBufferCnt; - - cy_stc_i3c_master_t i3cMaster; /**< I3C Master bus details */ - - cy_stc_i3c_master_devlist_t devList[CY_I3C_MAX_DEVS]; /**< The list of devices on the bus */ - - cy_stc_i3c_hdr_cmd_t *hdrCmd; /** provisonalID = ((uint64_t)(ptr->LSBProvisionalID)); - i3cDevice->provisonalID |= ((uint64_t)(ptr->MSBProvisionalID) << 32UL); - i3cDevice->dcr = I3C_CORE_DEV_CHAR_TABLE1_LOC3_DCR_Msk & (ptr->DCR_BCR); - i3cDevice->bcr = _FLD2VAL(I3C_CORE_DEV_CHAR_TABLE1_LOC3_BCR, (ptr->DCR_BCR)); - i3cDevice->dynamicAddress = ptr->dynamicAddress; -} - -/******************************************************************************* -* Function Name: Cy_I3C_UpdateI3CDevInList -****************************************************************************//** -* -* Adds the I3C device to the list of devices \ref cy_stc_i3c_master_devlist_t -* present on the bus. -* -* \param i3cDevice -* The pointer to the I3C device description structure \ref cy_stc_i3c_device_t. -* -* \param pos -* The position of the device in the list \ref cy_stc_i3c_master_devlist_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_I3C_UpdateI3CDevInList(cy_stc_i3c_device_t *i3cDevice, uint8_t pos, cy_stc_i3c_context_t *context) -{ - context->devList[pos].i2c = false; - context->devList[pos].i3cDevice = *i3cDevice; -} - -/******************************************************************************* -* Function Name: Cy_I3C_UpdateI2CDevInList -****************************************************************************//** -* -* Adds the I2C device to the list of devices \ref cy_stc_i3c_master_devlist_t -* present on the bus. -* -* \param i2cDevice -* The pointer to the I2C device description structure \ref cy_stc_i2c_device_t. -* -* \param pos -* The position of the device in the list \ref cy_stc_i3c_master_devlist_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_I3C_UpdateI2CDevInList(cy_stc_i2c_device_t *i2cDevice, uint8_t pos, cy_stc_i3c_context_t *context) -{ - context->devList[pos].i2c = true; - context->devList[pos].i2cDevice = *i2cDevice; -} - -/******************************************************************************* -* Function Name: Cy_I3C_ReadRxFIFO -****************************************************************************//** -* -* Reads a data element directly out of the RX FIFO. -* This function does not check whether the RX FIFO has data before reading it. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* Data from RX FIFO. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_I3C_ReadRxFIFO(I3C_CORE_Type *base) -{ - return (I3C_CORE_TX_RX_DATA_PORT(base)); -} - -/******************************************************************************* -* Function Name: Cy_I3C_WriteTxFIFO -****************************************************************************//** -* -* Writes data directly into the TX FIFO. -* This function does not check whether the TX FIFO is not full before writing -* into it. -* -* \param base -* The pointer to the I3C instance. -* -* \param data -* Data to write to the TX FIFO. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_I3C_WriteTxFIFO(I3C_CORE_Type *base, uint32_t data) -{ - I3C_CORE_TX_RX_DATA_PORT(base) = data; -} - -/******************************************************************************* -* Function Name: Cy_I3C_GetFreeEntriesInTxFifo -****************************************************************************//** -* -* Provides the number of empty locations in the TX FIFO. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* Transmit buffer empty level value. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_I3C_GetFreeEntriesInTxFifo(I3C_CORE_Type *base) -{ - return _FLD2VAL(I3C_CORE_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC, I3C_CORE_DATA_BUFFER_STATUS_LEVEL(base)); -} - -/******************************************************************************* -* Function Name: Cy_I3C_GetFreeEntriesInRxFifo -****************************************************************************//** -* -* Provides the number of empty locations in the RX FIFO. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* Receive buffer empty level value. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_I3C_GetFreeEntriesInRxFifo(I3C_CORE_Type *base) -{ - return ((CY_I3C_FIFO_SIZE/4) - _FLD2VAL(I3C_CORE_DATA_BUFFER_STATUS_LEVEL_RX_BUF_BLR, I3C_CORE_DATA_BUFFER_STATUS_LEVEL(base))); -} - -/******************************************************************************* -* Function Name: Cy_I3C_SetRxFifoLevel -****************************************************************************//** -* -* Sets the RX FIFO level. When there are more data elements in the RX FIFO than -* this level, the RX FIFO level interrupt is triggered. -* -* \param base -* The pointer to the I3C instance. -* -* \param level -* When there are more data elements in the FIFO than this level, the RX level -* interrupt is triggered. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_I3C_SetRxFifoLevel(I3C_CORE_Type *base, uint32_t level) -{ - CY_REG32_CLR_SET(I3C_CORE_DATA_BUFFER_THLD_CTRL(base), I3C_CORE_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD, level); -} - -/******************************************************************************* -* Function Name: Cy_SCB_GetRxFifoLevel -****************************************************************************//** -* -* Returns the RX FIFO level. When there are more words in the RX FIFO than the -* threshold level, the RX FIFO level interrupt is triggered. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* RX FIFO level. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_I3C_GetRxFifoLevel(CySCB_Type const *base) -{ - return _FLD2VAL(I3C_CORE_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD, I3C_CORE_DATA_BUFFER_THLD_CTRL(base)); -} - -/******************************************************************************* -* Function Name: Cy_I3C_SetTxEmptyThldLevel -****************************************************************************//** -* -* Sets the TX FIFO level. When the number of empty locations in the TX FIFO is -* greater than this level, the TX FIFO level interrupt is triggered. -* -* \param base -* The pointer to the I3C instance. -* -* \param level -* When there are more empty locations in the TX FIFO than this level, -* the TX level interrupt is triggered. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_I3C_SetTxEmptyThldLevel(CySCB_Type const *base, uint32_t level) -{ - CY_REG32_CLR_SET(I3C_CORE_DATA_BUFFER_THLD_CTRL(base), I3C_CORE_DATA_BUFFER_THLD_CTRL_TX_EMPTY_BUF_THLD, level); -} - -/** \} group_i3c_general_functions */ - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXI3C */ - -#endif /* (CY_I3C_H) */ - -/** \} group_i3c */ - -/* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_i3c_ccc.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_i3c_ccc.h deleted file mode 100644 index fee4ca59f3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_i3c_ccc.h +++ /dev/null @@ -1,271 +0,0 @@ -/***************************************************************************//** -* \file cy_i3c_ccc.h -* \version 1.00 -* -* Provides API declarations for the I3C Controller. -* -******************************************************************************** -* \copyright -* Copyright 2019-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include -#include - -#if defined (CY_IP_MXI3C) - -#if !defined (CY_I3C_CCC_H) -#define CY_I3C_CCC_H - -#if defined(__cplusplus) -extern "C" { -#endif - - -/******************************************************************************* -* API Constants -*******************************************************************************/ - -/** -* \addtogroup group_i3c_macros_common_macros Common Macros -* \{ -*/ - -/** Bits per long */ -#define CY_I3C_BITS_PER_LONG (32) - -/** - * Create a contiguous bitmask starting at bit position l and ending at position h. For example - * CY_I3C_GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000FFFFE00000. - */ -#define CY_I3C_GENMASK(h, l) (((~(0UL)) - ((1UL) << (l)) + 1) & (~(0UL) >> (CY_I3C_BITS_PER_LONG - 1 - (h)))) - -/** Create a bitmask at bit position @n */ -#define CY_I3C_BIT(n) ((1UL) << n) - -/** Divide and round up */ -#define CY_I3C_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) - -/** Swap the bytes of a 16-bit word */ -#define CY_I3C_SWAP16(x) ((uint16_t)((((uint16_t)(x) & (uint16_t)0x00FFU) << 8) | (((uint16_t)(x) & (uint16_t)0xFF00U) >> 8) )) - -/** Dircet CCC Mask */ -#define CY_I3C_CCC_DIRECT 0x80UL - -/**Create Broadcast/Direct CCC Id */ -#define CY_I3C_CCC_ID(id, broadcast) ((id) | ((broadcast) ? 0 : CY_I3C_CCC_DIRECT)) - -/** Enable SLave Events Command: valid in both broadcast and unicast modes */ -#define CY_I3C_CCC_ENEC(broadcast) CY_I3C_CCC_ID(0x0, broadcast) - -/** Disable SLave Events Command: valid in both broadcast and unicast modes */ -#define CY_I3C_CCC_DISEC(broadcast) CY_I3C_CCC_ID(0x1, broadcast) - -/** Enter Activity State 0-3 Command: valid in both broadcast and unicast modes */ -#define CY_I3C_CCC_ENTAS(as, broadcast) CY_I3C_CCC_ID(0x2 + (as), broadcast) - -/** Reset Dynamic Address Assignment Command: valid in both broadcast and unicast modes */ -#define CY_I3C_CCC_RSTDAA(broadcast) CY_I3C_CCC_ID(0x6, broadcast) - -/** Set Maaximum Write Length Command: valid in both broadcast and unicast modes */ -#define CY_I3C_CCC_SETMWL(broadcast) CY_I3C_CCC_ID(0x9, broadcast) - -/**Set Maximum Read Length Command: valid in both broadcast and unicast modes */ -#define CY_I3C_CCC_SETMRL(broadcast) CY_I3C_CCC_ID(0xA, broadcast) - -/** Enter Dynamic Address Assignment Command: Broadcast-only command */ -#define CY_I3C_CCC_ENTDAA CY_I3C_CCC_ID(0x7, true) - -/** Define List of Slaves Command: Broadcast-only command */ -#define CY_I3C_CCC_DEFSLVS CY_I3C_CCC_ID(0x8, true) - -/** Enter HDR Mode Command: Broadcast-only command */ -#define CY_I3C_CCC_ENTHDR(x) CY_I3C_CCC_ID(0x20 + (x), true) - -/** Set Dynamic Address from Static Address Command: Unicast-only command */ -#define CY_I3C_CCC_SETDASA CY_I3C_CCC_ID(0x7, false) - -/** Set New Dynamic Address Command: Unicast-only command */ -#define CY_I3C_CCC_SETNEWDA CY_I3C_CCC_ID(0x8, false) - -/** Get Maximum Write Length Command: Unicast-only command */ -#define CY_I3C_CCC_GETMWL CY_I3C_CCC_ID(0xB, false) - -/** Get Maximum Read Length Command: Unicast-only command */ -#define CY_I3C_CCC_GETMRL CY_I3C_CCC_ID(0xC, false) - -/** Get Provisioned ID(PID) Command: Unicast-only command */ -#define CY_I3C_CCC_GETPID CY_I3C_CCC_ID(0xD, false) - -/** Get Bus Characteristic Register(BCR) Command: Unicast-only command */ -#define CY_I3C_CCC_GETBCR CY_I3C_CCC_ID(0xE, false) - -/** Get Device Characteristic Register(DCR) Command: Unicast-only command */ -#define CY_I3C_CCC_GETDCR CY_I3C_CCC_ID(0xF, false) - -/** Get Device Status Command: Unicast-only command */ -#define CY_I3C_CCC_GETSTATUS CY_I3C_CCC_ID(0x10, false) - -/** Get Accept Mastership Command: Unicast-only command */ -#define CY_I3C_CCC_GETACCMST CY_I3C_CCC_ID(0x11, false) - -/** Get Maximum Data Speed Command: Unicast-only command */ -#define CY_I3C_CCC_GETMXDS CY_I3C_CCC_ID(0x14, false) - -/** Get HDR Capability Command: Unicast-only command */ -#define CY_I3C_CCC_GETHDRCAP CY_I3C_CCC_ID(0x15, false) - -/** Slave Interrupt Request Event \ref cy_stc_i3c_ccc_events_t */ -#define CY_I3C_CCC_EVENT_SIR CY_I3C_BIT(0) - -/** Mastership Request Event \ref cy_stc_i3c_ccc_events_t */ -#define CY_I3C_CCC_EVENT_MR CY_I3C_BIT(1) - -/**Hot-join Event \ref cy_stc_i3c_ccc_events_t */ -#define CY_I3C_CCC_EVENT_HJ CY_I3C_BIT(3) - -/** HDR Read Command Code */ -#define CY_I3C_HDR_IS_READ_CMD CY_I3C_BIT(7) - -/** -* \addtogroup group_i3c_macros_common_macros_getstatus_ccc_fields GetStatus CCC Fields -* \{ -*/ - -/** -* Contains the interrupt number of any pending interrupt, -* or 0 if no interrupts are pending -*/ -#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & CY_I3C_GENMASK(3, 0)) - -/** Indicates the Slave has detected a protocol error */ -#define I3C_CCC_STATUS_PROTOCOL_ERROR CY_I3C_BIT(5) - -/** Indicates the Slave Device's current activity mode */ -#define I3C_CCC_STATUS_ACTIVITY_MODE(status) (((status) & CY_I3C_GENMASK(7, 6)) >> 6) - -/** \} group_i3c_macros_common_macros_getstatus_ccc_fields */ - -/** \} group_i3c_macros_common_macros */ - -/******************************************************************************* -* Type Definitions -*******************************************************************************/ - -/** -* \addtogroup group_i3c_data_structures -* \{ -*/ - -/** ENEC/DISEC CCC payload structure */ -typedef struct cy_stc_i3c_ccc_events -{ - uint8_t events; /**< bitmask of CY_I3C_CCC_EVENT_xxx events */ -}cy_stc_i3c_ccc_events_t; - -/** SETMWL/GETMWL CCC payload structure */ -typedef struct cy_stc_i3c_ccc_mrwl -{ - uint16_t len; /**< maximum write length in bytes */ -}cy_stc_i3c_ccc_mrwl_t; - -/** SETMRL/GETMRL CCC payload structure */ -typedef struct cy_stc_i3c_ccc_mrl -{ - uint16_t readLen; /**< maximum read length in bytes */ -}cy_stc_i3c_ccc_mrl_t; - -/** I3C/I2C device descriptor used for DEFSLVS */ -typedef struct cy_stc_i3c_ccc_dev_desc -{ - uint8_t dynAddress; /**< dynamic address assigned to the I3C slave or 0 if the entry is describing an I2C Slave */ - union { - uint8_t dcr; /**< DCR value (not applicable to entries describing I2C devices) */ - uint8_t lvr; /**< LVR value (not applicable to entries describing I3C devices) */ - }; - uint8_t bcr; /**< BCR value or 0 if this entry is describing an I2C slave */ - uint8_t staticAddress; /**< static address or 0 if the device does not have a static address */ -}cy_stc_i3c_ccc_dev_desc_t; - -/** DEFSLVS CCC payload structure */ -typedef struct cy_stc_i3c_ccc_defslvs -{ - uint8_t count; /**< number of dev descriptors */ - cy_stc_i3c_ccc_dev_desc_t master; /**< descriptor describing the current master */ - cy_stc_i3c_ccc_dev_desc_t *slaves; /**< array of descriptors describing slaves controlled by the current master */ -}cy_stc_i3c_ccc_defslvs_t ; - -/** SETNEWDA and SETDASA CCCs payload structure */ -typedef struct cy_stc_i3c_ccc_setda -{ - uint8_t address; /**< dynamic address to assign to an I3C device */ -}cy_stc_i3c_ccc_setda_t; - -/** GETPID CCC payload structure */ -typedef struct cy_stc_i3c_ccc_getpid -{ - uint8_t pid[6]; /**< 48 bits PID in big endian */ -}cy_stc_i3c_ccc_getpid_t; - -/** GETBCR CCC payload structure */ -typedef struct cy_stc_i3c_ccc_getbcr -{ - uint8_t bcr; /**< BCR (Bus Characteristic Register) value */ -}cy_stc_i3c_ccc_getbcr_t; - -/** GETDCR CCC payload structure */ -typedef struct cy_stc_i3c_ccc_getdcr -{ - uint8_t dcr; /**< DCR (Device Characteristic Register) value */ -}cy_stc_i3c_ccc_getdcr_t; - -/** GETSTATUS CCC payload structure */ -typedef struct cy_stc_i3c_ccc_getstatus -{ - uint16_t status; /**< status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more information */ -}cy_stc_i3c_ccc_getstatus_t; - -/** GETACCMST CCC payload structure */ -typedef struct cy_stc_i3c_ccc_getaccmst -{ - uint8_t newmaster; /**< address of the master taking bus ownership */ -}cy_stc_i3c_ccc_getaccmst_t; - -/** GETMXDS CCC payload structure */ -typedef struct cy_stc_i3c_ccc_getmxds -{ - uint8_t maxwr; /**< write limitations */ - uint8_t maxrd; /**< read limitations */ - uint8_t maxrdturn[3]; /**< maximum read turn-around expressed micro-seconds and little-endian formatted */ -}cy_stc_i3c_ccc_getmxds_t; - -/** GETHDRCAP CCC payload structure */ -typedef struct cy_stc_i3c_ccc_gethdrcap -{ - uint8_t modes; /**< bitmap of supported HDR modes */ -}cy_stc_i3c_ccc_gethdrcap_t; -/** \} group_i3c_data_structures */ - -#if defined(__cplusplus) -} -#endif - -#endif /* (CY_I3C_CCC_H) */ - -#endif /* CY_IP_MXI3C */ -/* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ipc_bt.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ipc_bt.h deleted file mode 100644 index f20999c986..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ipc_bt.h +++ /dev/null @@ -1,692 +0,0 @@ -/***************************************************************************//** -* \file cy_ipc_bt.h -* \version 1.0 -* -* \brief -* Provides an API declaration for the BT IPC driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#ifndef CY_IPC_BT_H -#define CY_IPC_BT_H - -/******************************************************************************/ -/* Include files */ -/******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXIPC) - -#include "cy_ipc_drv.h" -#include "cy_syslib.h" -#include "cy_sysint.h" - -/** -* \addtogroup group_ipc_bt IPC bluetooth sub-system layer (IPC_BTSS) -* \{ -* The BT IPC functions provide a method to transfer Host Controller Interface (HCI) -* and Hight Priority Controller (HPC) messages between the MCU and BT SS. -* -* Include cy_ipc_bt.h. Alternatively include cy_pdl.h -* to get access to all functions and declarations in the PDL. -* -* The data needs to be provided in an array along with the payload type indicator. -* Depending on the payload length, the message gets formatted in to short or long -* message. If the payload length is less than 7 bytes, then it is considered as a short -* message. Short messages are packed and sent using IPC channel DATA0 and DATA1 -* registers. Any payload length greater than 7 bytes will be sent using the buffers in -* the shared memory. -* -* It supports callback function for notification on receiving the HCI messages from the BT SS -* HCI notification callback function is registered during the initialization of the driver. -* It also supports multiple callback registration for notification on receiving the -* HPC messages. -* -* \defgroup group_ipc_bt_macros Macros -* Macro definitions are used in the driver -* -* \defgroup group_ipc_bt_functions Functions -* Functions are used in the driver -* -* \defgroup group_ipc_bt_data_structures Data Structures -* Data structures are used in the driver -* -* \defgroup group_ipc_bt_enums Enumerated Types -* Enumerations are used in the driver -* \} -* -*/ - -/** -* \addtogroup group_ipc_bt_macros -* \{ -*/ - -/** Software PDL driver ID for IPC BT functions */ -#define CY_BT_IPC_ID CY_PDL_DRV_ID(0x22u) - -/** Return prefix for BT IPC driver function status codes */ -#define CY_BT_IPC_ID_INFO (uint32_t)( CY_BT_IPC_ID | CY_PDL_STATUS_INFO ) - -/** Return prefix for BT IPC driver function warning return values */ -#define CY_BT_IPC_ID_WARNING (uint32_t)( CY_BT_IPC_ID | CY_PDL_STATUS_WARNING) - -/** Return prefix for BT IPC driver function error return values */ -#define CY_BT_IPC_ID_ERROR (uint32_t)( CY_BT_IPC_ID | CY_PDL_STATUS_ERROR) - -/** Maximum HPC callback supported */ -#define MAX_BT_IPC_HPC_CB 5 - -/** Maximum number of buffers in the pool */ -#define MAX_BUF_COUNT 10 - -/** \} group_ipc_bt_macros */ - - -/** Maximum length of short message */ -#define MAX_SHORT_MESG_LENGTH 7 - -/** Buffer descriptor length in init message */ -#define BUFFER_DESCRIPTION_LEN 7 - -/** size of cy_stc_ipc_msg_subheader_t structure */ -#define SUB_HEADER_SIZE 4 - -/** -* \addtogroup group_ipc_bt_enums -* \{ -*/ -/** -* This is a list of ENUMs used for function return status. -*/ -typedef enum -{ - CY_BT_IPC_DRV_SUCCESS =(uint32_t)(0x00u), /**< BT IPC API return for no error */ - CY_BT_IPC_DRV_ERROR =(uint32_t)(CY_BT_IPC_ID_ERROR | 1ul), /**< BT IPC API return for general error */ - CY_BT_IPC_DRV_ERROR_BAD_HANDLE =(uint32_t)(CY_BT_IPC_ID_ERROR | 2ul), /**< BT IPC API return for bad handle */ - CY_BT_IPC_DRV_ERROR_CH_BUSY =(uint32_t)(CY_BT_IPC_ID_ERROR | 3ul), /**< BT IPC API return for channel busy */ - CY_BT_IPC_DRV_ERROR_LOCK_REL =(uint32_t)(CY_BT_IPC_ID_ERROR | 4ul), /**< BT IPCAPI return for channel release error */ - CY_BT_IPC_DRV_ERROR_LOCK_ACQUIRE =(uint32_t)(CY_BT_IPC_ID_ERROR | 5ul), /**< BT IPC API return for channel release error */ - CY_BT_IPC_DRV_ERROR_BUF_GET =(uint32_t)(CY_BT_IPC_ID_ERROR | 6ul), /**< BT IPC API return for get buffer error */ - CY_BT_IPC_DRV_ERROR_BUF_FULL =(uint32_t)(CY_BT_IPC_ID_ERROR | 7ul), /**< BT IPC API return for buffer pool full error */ - CY_BT_IPC_DRV_ERROR_PARAM =(uint32_t)(CY_BT_IPC_ID_ERROR | 8ul), /**< BT IPC API return for bad parameter error */ -} cy_en_btipcdrv_status_t; - -/** -* This is a list of ENUMs used for buffer types. -*/ -typedef enum -{ - CY_BT_IPC_CTRL_BUF = (0x00u), /**< Control buffer type */ - CY_BT_IPC_HCI_BREDR_BUF = (0x01u), /**< BREDR buffer type */ - CY_BT_IPC_HCI_BLE_BUF = (0x02u), /**< BLE buffer type */ - CY_BT_IPC_HCI_ISOC_BUF = (0x03u), /**< ISOC buffer type */ - CY_BT_IPC_HCI_INVALID_BUF = (0xFFu), /**< Invalid buffer type */ -} cy_en_btipc_buftype_t; - -/** -* This is a list of ENUMs used for HCI packet type. -*/ -typedef enum -{ - CY_BT_IPC_HCI_IGNORE = (0x00u), /**< HCI payload type ignore */ - CY_BT_IPC_HCI_CMD = (0x01u), /**< HCI payload type command */ - CY_BT_IPC_HCI_ACL = (0x02u), /**< HCI payload type ACL */ - CY_BT_IPC_HCI_SCO = (0x03u), /**< HCI payload type SCO */ - CY_BT_IPC_HCI_EVT = (0x04u), /**< HCI payload type Event */ - CY_BT_IPC_HCI_ISO = (0x05u), /**< HCI payload type ISO */ - CY_BT_IPC_HCI_DIAG = (0x07u), /**< HCI payload type Diagnostics */ - CY_BT_IPC_HCI_MPAF = (0x0Au), /**< HCI payload type MPAF */ - CY_BT_IPC_HCI_SLIPH5 = (0xC0u), /**< HCI payload type SLIPH5 */ - CY_BT_IPC_HCI_LONG = (0xFFu), /**< HCI payload type long message */ -} cy_en_btipc_hcipti_t; - -/** -* This is a list of ENUMs used for HPC packet type. -*/ -typedef enum -{ - CY_BT_IPC_HPC_BUF_FREE = (0x00u), /**< HPC payload type free buffer */ - CY_BT_IPC_HPC_BUF_CHSIZE = (0x01u), /**< HPC payload type change buffer size */ - CY_BT_IPC_HPC_BUF_ALLOC = (0x02u), /**< HPC payload type allocate buffer */ - CY_BT_IPC_HPC_BUF_REQTRNG = (0x03u), /**< HPC payload type request TRNG */ - CY_BT_IPC_HPC_BUF_AVAIL = (0x04u), /**< HPC payload type buffer available */ - CY_BT_IPC_HPC_LONG = (0xFFu), /**< HPC payload type long message */ -} cy_en_btipc_hpcpti_t; - -/** -* This is a list of ENUMs used for bt boot type. -*/ -typedef enum -{ - CY_BT_IPC_COLD_BOOT = (0x00u), /**< BT cold boot */ - CY_BT_IPC_SW_RST = (0x01u), /**< BT software reset boot */ - CY_BT_IPC_ERR_RST = (0x02u), /**< BT error reset */ -} cy_en_btipc_boottype_t; - -/** \} group_ipc_bt_enums */ - -/* - * This section defines the system level constants required to define - * callback arrays for the Cypress pipe and the user pipe. These defines - * are used for both the max callback count and maximum clients. -*/ - -/** Typedef for bt ipc callback function pointer */ -typedef void (* cy_ipc_bt_callback_ptr_t)(uint32_t * msgPtr); - -/** Typedef for bt ipc channel release callback function pointer */ -typedef void (* cy_ipc_bt_relcallback_ptr_t)(void); - -/** Typedef for bt ipc irq function pointer */ -typedef void (* cy_ipc_bt_irq_handler_t)(void); - -/** -* \addtogroup group_ipc_bt_data_structures -* \{ -*/ - -/** -* This is the definition of an allocation msg strcuture. -*/ -typedef struct cy_stc_ipc_msg_alloc_t -{ - uint8_t pti; /**< Payload type indicator */ - uint8_t bufType; /**< Buffer type indicator */ - uint16_t bufSize; /**< Buffer size */ - uint8_t *bufAddr; /**< Pointer to the buffer */ -} cy_stc_ipc_msg_alloc_t; - -/** -* This is the definition of a long message strcuture. -*/ -typedef struct cy_stc_ipc_msg_buff_t -{ - uint8_t pti; /**< Payload type indicator */ - uint8_t actualPti; /**< Actual PTI for the long messages */ - uint16_t bufSize; /**< Buffer size */ - uint8_t *bufAddr; /**< Pointer to the buffer */ -} cy_stc_ipc_msg_buff_t; - -/** -* This is the definition of a short msg strcuture. -*/ -typedef struct cy_stc_ipc_msg_short_t -{ - uint8_t pti; /**< Payload type indicator */ - uint8_t db0; /**< Payload byte 0 for short message */ - uint8_t db1; /**< Payload byte 1 for short message */ - uint8_t db2; /**< Payload byte 2 for short message */ - uint8_t db3; /**< Payload byte 3 for short message */ - uint8_t db4; /**< Payload byte 4 for short message */ - uint8_t db5; /**< Payload byte 5 for short message */ - uint8_t db6; /**< Payload byte 6 for short message */ -} cy_stc_ipc_msg_short_t; - -/** \} group_ipc_bt_data_structures */ - -/** -* This is the definition of an init msg strcuture. -*/ -typedef __PACKED_STRUCT cy_stc_ipc_msg_init_t -{ - uint8_t msgId; /**< Message ID for HPC message */ - uint8_t bootType; /**< BT boot type indicator */ - uint8_t payLoadLen; /**< Payload length in bytes */ -} cy_stc_ipc_msg_init_t; - -/** -* This is the definition of an sub header msg strcuture. -*/ -typedef __PACKED_STRUCT cy_stc_ipc_msg_subheader_t -{ - uint8_t msgId; /**< Message ID for HPC message */ - uint8_t dummy; /**< Dummy byte to be igonored */ - uint16_t payLoadLen; /**< Payload length in bytes */ -} cy_stc_ipc_msg_subheader_t; - -/** -* This is the definition of buffer descriptor strcuture. -*/ -typedef __PACKED_STRUCT cy_stc_ipc_bt_buf_t -{ - cy_en_btipc_buftype_t bufType; /**< Buffer type indicator */ - uint16_t bufLen; /**< Buffer length */ - uint8_t *bufPtr; /**< Pointer to the buffer */ -} cy_stc_ipc_bt_buf_t; - -/* Following are the the HCI packet header typedefs */ -/** -* This is the definition of CMD header strcuture. -*/ -typedef __PACKED_STRUCT BTHCI_CMD_HDR_t -{ - uint16_t opcode; - uint8_t params_len; -} BTHCI_CMD_HDR_t; - -/** -* This is the definition of event header strcuture. -*/ -typedef __PACKED_STRUCT BTHCI_EVENT_HDR_t -{ - uint8_t code; - uint8_t params_len; -} BTHCI_EVENT_HDR_t; - -/** -* This is the definition of ACL header strcuture. -*/ -typedef __PACKED_STRUCT BTHCI_ACL_HDR_t -{ - uint16_t conn_handle_and_flags; - uint16_t data_len; -} BTHCI_ACL_HDR_t; - -/** -* This is the definition of ISO header strcuture. -*/ -typedef __PACKED_STRUCT BTHCI_ISO_HDR_t -{ - uint16_t conn_handle_and_flags; - uint16_t data_len; -} BTHCI_ISO_HDR_t; - -/** -* This is the definition of SCO header strcuture. -*/ -typedef __PACKED_STRUCT BTHCI_SCO_HDR_t -{ - __PACKED_UNION - { - uint16_t audioChannel; - uint16_t connectionHandle; - } u; - uint8_t data_len; -} BTHCI_SCO_HDR_t; - -/** Typedef for internal ipc callback function pointer */ -typedef void (* cy_ipc_bt_int_cb_ptr_t)(void *btIpcContext, uint32_t * msgPtr); - - -/** -* \addtogroup group_ipc_bt_data_structures -* \{ -*/ - -/** -* This is the definition of BT IPC context strcuture. -*/ -typedef struct cy_stc_ipc_bt_context_t -{ - uint32_t ulChannelHCI; /**< HCI Channel used to send to BLE */ - uint32_t dlChannelHCI; /**< HCI Channel used to receive from BLE */ - - uint32_t ulChannelHPC; /**< HPC Channel used to send to BLE */ - uint32_t dlChannelHPC; /**< HPC Channel used to receive from BLE */ - - uint32_t intStuctureSelf; /**< Interrupt struture for the MCU */ - uint32_t intStucturePeer; /**< Interrupt struture for the BLE */ - - uint32_t intPeerMask; /**< Interrupt mask for the peer */ - - uint32_t dlNotifyMask; /**< Down link notify mask */ - uint32_t ulReleaseMask; /**< Up link release mask */ - - cy_stc_sysint_t ipcIntConfig; /**< IPC Interrupt configuration structure */ - - cy_ipc_bt_irq_handler_t irqHandlerPtr; /**< This handler will be removed later once similations are done */ - - cy_ipc_bt_int_cb_ptr_t internal_hpc_notify_cb; /**< This callback will be removed later once similations are done */ - - cy_ipc_bt_callback_ptr_t dlNotifyCallbackPtr; /**< Callback function called when the DL mesg is recevieved */ - - cy_ipc_bt_relcallback_ptr_t ulReleaseCallbackPtr; /**< Callback function called when the UL channel is released */ - - cy_ipc_bt_callback_ptr_t hpcNotifyCallbackPtr[MAX_BT_IPC_HPC_CB]; /**< Array of callback pointers registered for control channel notification */ - - cy_stc_ipc_bt_buf_t buffPool[MAX_BUF_COUNT]; /**< Storage for pool of buffers sent by BLE for communication */ -} cy_stc_ipc_bt_context_t; - -/** -* This is the definition of BT IPC configuration strcuture. -*/ -typedef struct cy_stc_ipc_bt_config_t -{ - uint32_t ulChannelHCI; /**< HCI Channel used to send to BLE */ - uint32_t dlChannelHCI; /**< HCI Channel used to receive from BLE */ - - uint32_t ulChannelHPC; /**< HPC Channel used to send to BLE */ - uint32_t dlChannelHPC; /**< HPC Channel used to receive from BLE */ - - uint32_t intStuctureSelf; /**< Interrupt struture for the MCU */ - uint32_t intStucturePeer; /**< Interrupt struture for the BLE */ - - cy_stc_sysint_t ipcIntConfig; /**< IPC Interrupt configuration structure */ - - cy_ipc_bt_irq_handler_t irqHandlerPtr; /**< This handler will be removed later once similations are done */ - - cy_ipc_bt_int_cb_ptr_t internal_hpc_notify_cb; /**< This callback will be removed later once similations are done */ - - cy_ipc_bt_callback_ptr_t dlNotifyCallbackPtr; /**< Callback function called when the DL mesg is recevieved */ - cy_ipc_bt_relcallback_ptr_t ulReleaseCallbackPtr; /**< Callback function called when the UL channel is released */ -} cy_stc_ipc_bt_config_t; - -/** \} group_ipc_bt_data_structures */ - -/** -* \addtogroup group_ipc_bt_functions -* \{ -*/ -/******************************************************************************* -* Function Name: Cy_BTIPC_Init -****************************************************************************//** -* -* This function initializes the bluetooth IPC. The IPC channels used for HCI and HPC packet exchange -* between MCU and BT SS are initialized. -* -* \note In general, this function is during application initializaation. -* -* \param btIpcConfig -* This is the pointer to the bt ipc configuration structure. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure. -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR: BT IPC API return for general error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_Init(cy_stc_ipc_bt_context_t *btIpcContext, cy_stc_ipc_bt_config_t * btIpcConfig); - -/******************************************************************************* -* Function Name: Cy_BTIPC_Deinit -****************************************************************************//** -* -* This function de-initializes the bluetooth IPC. All the registered callbacks are deleted. -* -* \note In general, this function is called when the application does not need BT IPC service -* anymore. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure. -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_Deinit(cy_stc_ipc_bt_context_t *btIpcContext); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HCI_getPTI -****************************************************************************//** -* -* This function gets the payload type indicator and the legth of the HCI packet received -* from BTSS. This function can be called to find out the type of HCI packet and allocate -* buffer of approriate size to copy the packet data. -* -* \note In general, this function is called before reading the packet to allocate memory -* of required size. -* -* \param pti -* This is the pointer to payload type indicator which is returned by the function. -* -* \param p_length -* This is the pointer to the length of the payload filled by the function. -* -* \param msgPtr -* This is the pointer to buffer which contains the IPC data recevied in DATA0 and DATA1 -* registers. -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_getPTI (cy_en_btipc_hcipti_t *pti, uint32_t *p_length, uint32_t *msgPtr); - -/******************************************************************************* -* Function Name: Cy_BTIPC_GetBuffer -****************************************************************************//** -* -* This function gets the free buffer form the pool of shared memory buffers. -* between MCU and BT SS are initialized. -* -* \param bufPtr -* This is the pointer to the pointer whic will be filled by the function with -* the addressbt of the buffer. -* -* \param bufType -* This is the buffer type that is being requested. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure. -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_BUF_GET: BT IPC API return for get buffer error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_GetBuffer (cy_stc_ipc_bt_context_t *btIpcContext, void **bufPtr, cy_en_btipc_buftype_t bufType); - -/******************************************************************************* -* Function Name: Cy_BTIPC_PutBuffer -****************************************************************************//** -* -* This function puts the free buffer back to the buffer pool -* -* \param bufDecriptor -* This is the pointer to the buffer descriptor. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure. -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_BUF_FULL: BT IPC API return for buffer pool full error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_PutBuffer(cy_stc_ipc_bt_context_t *btIpcContext, cy_stc_ipc_bt_buf_t *bufDecriptor); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HCI_Write -****************************************************************************//** -* -* This function sends the HCI packet form the BT stack to the BTSS. -* -* \param pti -* This is the HCI payload type indicator. -* -* \param data -* This is the pointer to the buffer holding the HCI payload. -* -* \param length -* This is the length of the HCI payload in number of bytes. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_LOCK_ACQUIRE: BT IPC API return for buffer pool full error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_Write(cy_stc_ipc_bt_context_t *btIpcContext, cy_en_btipc_hcipti_t pti, void *data, size_t length); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HPC_Write -****************************************************************************//** -* -* This function sends the HPC packet form the MCU to the BTSS. -* -* \param data -* This is the pointer to the buffer holding the HPC payload. -* -* \param length -* This is the length of the HPC payload in number of bytes. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_LOCK_ACQUIRE: BT IPC API return for buffer pool full error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_Write(cy_stc_ipc_bt_context_t *btIpcContext, void *data, size_t length); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HCI_Read -****************************************************************************//** -* -* This function reads the HCI packet received by MCU from BTSS. -* -* \param pti -* This is the HCI payload type indicator. -* -* \param data -* This is the pointer to the buffer for receiving the HCI payload. -* -* \param pLength -* This is the pointer to the size of the payload received in number of bytes -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_LOCK_ACQUIRE: BT IPC API return for buffer pool full error -* CY_BT_IPC_DRV_ERROR_LOCK_REL: BT IPCAPI return for channel release error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_Read (cy_stc_ipc_bt_context_t *btIpcContext, cy_en_btipc_hcipti_t pti, void *data, size_t* pLength); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HCI_RelChannel -****************************************************************************//** -* -* This function releases the HCI channel after handling the notification from the -* BT SS -* -* \param buf -* This is the pointer to the buffer received from BT SS in DATA0 and DATA1 channel -* registers. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_LOCK_REL: BT IPCAPI return for channel release error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_RelChannel(cy_stc_ipc_bt_context_t *btIpcContext, void * buf); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HPC_RelChannel -****************************************************************************//** -* -* This function releases the HPC channel after handling the notification from the -* BT SS -* -* \param buf -* This is the pointer to the buffer received from BT SS in DATA0 and DATA1 channel -* registers. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR_LOCK_REL: BT IPCAPI return for channel release error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_RelChannel(cy_stc_ipc_bt_context_t *btIpcContext, void * buf); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HPC_RegisterCb -****************************************************************************//** -* -* This function registers the callback for HPC message nofitications from BT SS -* -* \param hpcNotifyCallbackPtr -* This is the pointer to the function to be called for HPC notifications. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR: BT IPC API return for general error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_RegisterCb(cy_stc_ipc_bt_context_t *btIpcContext, cy_ipc_bt_callback_ptr_t hpcNotifyCallbackPtr); - -/******************************************************************************* -* Function Name: Cy_BTIPC_HPC_UnregisterCb -****************************************************************************//** -* -* This function un-registers the callback function registered for HPC message -* nofitications from BT SS -* -* \param hpcNotifyCallbackPtr -* This is the pointer to the function to be un-registered. -* -* \param btIpcContext -* This is the pointer to the bt ipc context structure -* -* \return -* CY_BT_IPC_DRV_SUCCESS: BT IPC API return for no error -* CY_BT_IPC_DRV_ERROR_BAD_HANDLE: BT IPC API return for bad handle -* CY_BT_IPC_DRV_ERROR: BT IPC API return for general error -* -*******************************************************************************/ -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_UnregisterCb(cy_stc_ipc_bt_context_t *btIpcContext, cy_ipc_bt_callback_ptr_t hpcNotifyCallbackPtr); - -/** \} group_ipc_bt_functions */ - -void Cy_BTIPC_IRQ_Handler(cy_stc_ipc_bt_context_t *btIpcContext); - -/* This function prototype will be removed once the simulations are done */ -void Cy_BTIPC_HPC_Notify(void *btIpcContext, uint32_t * msgPtr); - - -/** \} group_ipc_bt */ - -#ifdef __cplusplus -} -#endif - -#endif /* CY_IP_MXIPC */ - -#endif /* !defined (CY_IPC_BT_H) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_keyscan.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_keyscan.h deleted file mode 100644 index c4a51da2cc..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_keyscan.h +++ /dev/null @@ -1,528 +0,0 @@ -/***************************************************************************//** -* \file cy_keyscan.h -* \version 1.0 -* -* \brief -* Provides an API declaration of the KEYSCAN driver -* -******************************************************************************** -* \copyright -* Copyright 2020-2021, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -/** -* \addtogroup group_keyscan -* \{ -* MXKEYSCAN is a DEEPSLEEP peripheral IP that performs autonomous key-matrix scan and system notification. -* Key processing detects both press and un-press actions, -* includes micro and macro de-bouncing filters and ghost key detection. -* -* Configurable key-matrix size supports up to 20x8 keys. -* Up to 20 columns are driven as the output and up to 8 rows are processed as the input. -* Key actions are stored in the FIFO with interrupt notification available based on the FIFO threshold. -* -* The Scan matrix support up to 8X20 matrix, maximum of 160 keys. -* Any key press will be translated into an index corresponding column and corresponding row. -* Before any key is pressed, the Key Matrix Scan Logic is disabled. -* Once a key press is detected by the Key Detection Logic, it will enable the gate for clock to drive the key Matrix Scan Logic for GPIO scanning. -* GPIO scanning is done one column at a time by driving each column "low" and reading from the row GPIO pins to find out which input is low. -* After the Key Scan Logic had scanned through the matrix for a specific number for debounce times configured by firmware though the configuration register, -* keycode representing the pressed key is pushed into the key FIFO for firmware to read and an interrupt to CPU will be generated. -* There are two types of debounce mechanisms build into this scan matrix block. -* The micro-debounce logic will provide a small debounce period to debounce the break type of mechanical vibration. -* The macro debounce logic will scan through the matrix for a number of times for qualify a key as being pressed. -* -* Features: -* * Ability to turn off its clock if no keys pressed. -* * Sequential scanning of up to 160 keys in a 8X20 matrix -* * Programmable number of columns from 1 to 20. -* * Programmable number of rows from 1 to 8. -* * 20-byte key-code buffer. -* * 128-kHz clock allow scanning of full 160 key matrix in about 1.2ms. -* * Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs. -* * Hardware debouncing and noice/glitch filtering. -* -* This driver provides the user an easy method for accessing KeyScan registers and provides some simple functionality for reading key index from keyscan FIFO. -* -* \section group_keyscan_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_keyscan_cmd_macro KeyScan command type definition -* \defgroup group_keyscan_intr_mask_macro KeyScan ALL interrupt mask definition -* \defgroup group_keyscan_functions Functions -* \defgroup group_keyscan_data_structures Data Structures -* \defgroup group_keyscan_enums Enumerated Types -*/ - - -#if !defined(CY_KEYSCAN_H) -#define CY_KEYSCAN_H -#include "cy_device.h" -#if defined (CY_IP_MXKEYSCAN) -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - ***************************************************************************** - ** \defgroup KeyScanGroup (KEYSCAN) - ** - ** \brief This section describes the interface for the KEYSCAN. - ** - *****************************************************************************/ -/** @{ */ - - -/*****************************************************************************/ -/* Global pre-processor symbols/macros ('#define') */ -/*****************************************************************************/ -/** Driver major version */ -#define CY_KEYSCAN_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_KEYSCAN_DRV_VERSION_MINOR 0 - -/** KEYSCAN driver ID */ -#define CY_KEYSCAN_ID CY_PDL_DRV_ID(0x51u) -/** -* \addtogroup group_keyscan_enums -* \{ -*/ -/** KEYSCAN API status definition */ -typedef enum -{ - CY_KEYSCAN_SUCCESS = 0x00u, /**< Returned successful */ - CY_KEYSCAN_BAD_PARAM = CY_KEYSCAN_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ - CY_KEYSCAN_BUSY = CY_KEYSCAN_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Change settings while tx/rx on-going */ - CY_KEYSCAN_QUEUE_OVERFLOW = CY_KEYSCAN_ID | CY_PDL_STATUS_ERROR | 0x03u, /**< QUEUE Over flow condition */ - CY_KEYSCAN_QUEUE_EMPTY = CY_KEYSCAN_ID | CY_PDL_STATUS_ERROR | 0x04u, /**< QUEUE Empty condition */ - CY_KEYSCAN_EVENT_NONE = CY_KEYSCAN_ID | CY_PDL_STATUS_ERROR | 0x05u, /**< Event None */ -} cy_en_ks_status_t; - -/** - ***************************************************************************** - ** \brief Keycode enumerations - ** - *****************************************************************************/ -typedef enum { - KEYSCAN_KEYCODE_GHOST = 0xf5, /*!< Ghost key keycode */ - KEYSCAN_KEYCODE_NONE = 0xfd, /*!< Keycode value if no key is pressed.*/ - KEYSCAN_KEYCODE_END_OF_SCAN_CYCLE = 0xfe, /*!< Event returned to indicate the end of a scan cycle.*/ - KEYSCAN_KEYCODE_ROLLOVER = 0xff, /*!< Rollover event generated by the keyscan driver in case of an error (ghost or overflow) */ -}cy_en_ks_keycode_t; - - -/** \} group_keyscan_enums */ -/*****************************************************************************/ -/* Global variable declarations ('extern', definition in C source) */ -/*****************************************************************************/ -/** -* \addtogroup group_keyscan_cmd_macro KeyScan command type definition -* \{ -* Specifies the mask value for interrupt status/mask -*/ -/** Mia keyevent HW FIFO size. */ -#define MIA_KEY_EVENT_FIFO_SIZE (20u) -/** keyscan FW FIFO size. This FIFO is implemented with KeyscanQueue. */ -#define KEYSCAN_FW_FIFO_SIZE (2u*MIA_KEY_EVENT_FIFO_SIZE + 6u) - -/** keyscan CTL register KeyScan enable Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_KS_EN_DEFAULT 0U -/** keyscan CTL register ghost enable Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_GHOST_EN_DEFAULT 1U -/** keyscan CTL register keyscan int enable Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_KS_INT_EN_DEFAULT 1U -/** keyscan CTL register keyscan reset enable Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN_DEFAULT 0U -/** keyscan CTL register Idle duration between column scans Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_RC_EXT_DEFAULT 3U -/** keyscan CTL register No of Rows Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_RCTC_ROW_DEFAULT 7U -/** keyscan CTL register No of Columns Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_RCTC_COLUMN_DEFAULT 19U -/** keyscan CTL register used to pull the columns high after each column scan to alleviate slow rise-time due to a large key matrix capacitance. - ** Default value definition. */ -#define MXKEYSCAN_KEYSCAN_CTL_PULL_HIGH_DEFAULT 1U -/** keyscan CTL register Default Value. */ -#define MXKEYSCAN_KEYSCAN_CTL_KSI_DRV_HIGH_DEFAULT 1U -/** keyscan CTL register keyscan clock will stay on when set; otherwise, the clock will be gated off by when no activity is detected. - ** Default value definition */ -#define MXKEYSCAN_KEYSCAN_CTL_KYSCLK_STAYON_DEFAULT 1U -/** keyscan CTL register All Default values. */ -#define KEYSCAN_CTL_DEFAULT (_VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KS_EN, MXKEYSCAN_KEYSCAN_CTL_KS_EN_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_GHOST_EN, MXKEYSCAN_KEYSCAN_CTL_GHOST_EN_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KS_INT_EN, MXKEYSCAN_KEYSCAN_CTL_KS_INT_EN_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN, MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_RC_EXT, MXKEYSCAN_KEYSCAN_CTL_RC_EXT_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_RCTC_ROW, MXKEYSCAN_KEYSCAN_CTL_RCTC_ROW_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_RCTC_COLUMN, MXKEYSCAN_KEYSCAN_CTL_RCTC_COLUMN_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_PULL_HIGH, MXKEYSCAN_KEYSCAN_CTL_PULL_HIGH_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KSI_DRV_HIGH, MXKEYSCAN_KEYSCAN_CTL_KSI_DRV_HIGH_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KYSCLK_STAYON, MXKEYSCAN_KEYSCAN_CTL_KYSCLK_STAYON_DEFAULT)) -/** \} group_keyscan_cmd_macro */ - -/** -* \addtogroup group_keyscan_intr_mask_macro KeyScan ALL interrupt mask definition -* \{ -* Specifies the mask value for interrupt status/mask -*/ -/** keyscan Interrupt KEY EDGE value definition. */ -#define MXKEYSCAN_INTR_KEY_EDGE_DONE (MXKEYSCAN_INTR_KEY_EDGE_Msk) -/** keyscan Interrupt FIFO THRESHOLD value definition. */ -#define MXKEYSCAN_INTR_FIFO_THRESH_DONE (MXKEYSCAN_INTR_FIFO_THRESH_Msk) -/** keyscan ALL Interrupt value definition. */ -#define MXKEYSCAN_INTR_ALL (MXKEYSCAN_INTR_KEY_EDGE_Msk |\ - MXKEYSCAN_INTR_FIFO_THRESH_Msk) - -/** \} group_keyscan_intr_mask_macro */ - -/** -* \addtogroup group_keyscan_data_structures -* \{ -*/ -/** keyscan callback function definition. - ** Application has to register for callback for receiving the key press events. -*/ -typedef void (* cy_cb_keyscan_handle_events_t)(void); -/** - ***************************************************************************** - ** \brief keyscan configuration - ** This settings are per KEYSCAN instance. - *****************************************************************************/ -typedef struct cy_stc_ks_config_t -{ - uint8_t macroDownDebCnt; /**< macro down debounce count */ - - uint8_t macroUpDebCnt; /**< macro Up debounce count */ - - uint8_t microDebCnt; /**< macro debounce count */ - - uint8_t noofRows; /**< set the number of rows of the key matrx */ - - uint8_t noofColumns; /**< set the number of columns of the key matrx */ - - bool ghostEnable; /**< Enable ghost detection. */ - - bool hostWakeupEnable; /**< enables the keyscan block to wake the MCU module if key is detected. */ - - bool clkStayOn; /**< The keyscan clock will stay on when set; otherwise, the clock will be gated off by when no activity is detected*/ -}cy_stc_ks_config_t ; - -/** - ***************************************************************************** - ** \brief keyscan key event - *****************************************************************************/ -typedef struct cy_stc_key_event -{ - - uint8_t keyCode; /**< Key code. This is the location in the keyscan matrix that is pressed/released. - May be implemented as ((row * numCols) + col) or ((col * numRows) + row. */ - - uint8_t upDownFlag; /**< Up/down flag */ - - uint8_t scanCycleFlag; /**< Should be toggled for every scan cycle in which a new event is queued. - Use of this flag is optional. If used, it allows the consumer to determine whether - an event is detected in the same scan cycle as the previous event or a different one. - Note that this flag does not indicate any separation in time. */ -}cy_stc_key_event; - - -/** - ***************************************************************************** - ** \brief KEYSCAN Context configuration - ** This settings are per keyscan context. - *****************************************************************************/ -typedef struct cy_stc_keyscan_context_t -{ - cy_stc_key_event bufStart[KEYSCAN_FW_FIFO_SIZE]; /**< Location where the queue starts. Provided during initialization. */ - - uint8_t elementSize; /**< Maximum size of elements. Provided during initialization. */ - - uint8_t maxNumElements; /**< Maximum number of elements that can be placed in the queue. Provided during initialization. */ - - uint8_t curNumElements; /**< Number of elements currently in the queue */ - - uint8_t readIndex; /**< Read index into the queue. */ - - uint8_t writeIndex; /**< Write index into the queue. */ - - uint8_t savedWriteIndexForRollBack; /**< Saved write index for rollback. */ - - uint8_t savedNumElements; /**< Saved number of elements for rollback. */ - - uint8_t keysPressedCount; /**< Number of key down events that are not yet matched by key up events, - which gives the number of keys currently being pressed */ - - bool keyscan_pollingKeyscanHw; /**< Whether HW polling is done from Keyscan */ - - cy_cb_keyscan_handle_events_t cbEvents; /**< callback function */ -}cy_stc_keyscan_context_t; - -/** \} group_keyscan_data_structures */ - - -/** -* \addtogroup group_keyscan_functions -* \{ -*/ -/*****************************************************************************/ -/* Global function prototypes ('extern', definition in C source) */ -/*****************************************************************************/ - -/** - ***************************************************************************** - ** \brief Registers for callback - ** Application has to register for callback for receiving the key press events. - ** In the interrupt handler data from HW Fifo is copied to fw fifo and - ** application is notied to get the data using this callback function. - ** - ** \param [in] cbEvents Pointer to the callback function. - ** - ** \param [in] context Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Register_Callback(cy_cb_keyscan_handle_events_t cbEvents, cy_stc_keyscan_context_t* context); - -/** - ***************************************************************************** - ** \brief Register Context with the driver - ** This Function registers for the event callback and firmware queue buffer. - ** - ** \pre The Application must configure corresponding keyscan pins - ** according to requirements and settings of keyscan instance. - ** - ** \param [in] base Pointer to KeyScan instance register area - ** \param [in] config KeyScan module configuration. See #cy_stc_ks_config_t. - ** \param [in] context Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Init(MXKEYSCAN_Type* base, cy_stc_ks_config_t* config, cy_stc_keyscan_context_t *context ); - -/** - ***************************************************************************** - ** \brief Reset Keyscan. - ** Reset's the Keyscan HW - ** Clear FW FIFO after a HW reset. - ** Restores the control data and enables scans if they were enabled before this function was called. - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** \param context [in] Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Reset(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context); - -/** - ***************************************************************************** - ** \brief Enable Keyscan. - ** Enables the keyscan hardware. - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param context [in] Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Enable(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context); - -/** - ***************************************************************************** - ** \brief Disable keyscan - ** Reset's the Keyscan hardware and disables the keyscan hardware. - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param context [in] Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Disable(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context); - -/** - ***************************************************************************** - ** \brief Events pending - ** Return whether any events are in the FW fifo or not. - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param context [in] Pointer to the context. - ** \param eventsPending [out] Pointer to the eventsPending, True if events pending and otherwise False. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_EventsPending(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context, bool *eventsPending); - -/** - ***************************************************************************** - ** \brief Get next event from FW FIFO. - ** Applications have to call \ref Cy_Keyscan_Interrupt_handler from keyscan interrupt handler. - ** After successfully reading from HW FIFO and writing to SW FIFO applications - ** will be notified through the registered callback. - ** Applications to read from the sw fifo has to call this function in a loop till - ** the return value is CY_KEYSCAN_EVENT_NONE - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param context [in] Pointer to the context. - ** \param event [out] Pointer to the next event. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetNextEvent(MXKEYSCAN_Type* base, cy_stc_key_event *event, cy_stc_keyscan_context_t *context); - -/** - ***************************************************************************** - ** \brief Setup interrupt source to be accepted. - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param mask [in] The mask with the OR of the interrupt source to be accepted. - ** See \ref group_keyscan_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_SetInterruptMask(MXKEYSCAN_Type* base, uint32_t mask); - -/** - ***************************************************************************** - ** \brief Return interupt mask setting. - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param mask [out] The mask with the OR of the interrupt source which is masked. - ** See \ref group_keyscan_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetInterruptMask(MXKEYSCAN_Type* base, uint32_t *mask); - -/** - ***************************************************************************** - ** \brief Return interupt masked status. - ** - ** \param base [in] Pointer to KeyScan instance register area. - ** \param status [out] The mask with the OR of the interrupt source which occurs. - ** See \ref group_keyscan_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetInterruptMaskedStatus(MXKEYSCAN_Type* base, uint32_t *status); - -/** - ***************************************************************************** - ** \brief Return interupt raw status. - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** \param status [out] The mask with the OR of the interrupt source which occurs. - ** See \ref group_keyscan_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetInterruptStatus(MXKEYSCAN_Type* base, uint32_t *status); - -/** - ***************************************************************************** - ** \brief Clear interupt status. - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** \param mask [in] The mask with the OR of the interrupt source to be cleared. - ** See \ref group_keyscan_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_ClearInterrupt(MXKEYSCAN_Type* base, uint32_t mask); - -/** - ***************************************************************************** - ** \brief Handler for keyscan interrupts. - ** Applications have to call this function from keyscan interrupt handler. - ** After successfully reading from HW FIFO and writing to SW FIFO this function - ** will notify application to read from the sw fifo. - ** Application has to call Cy_Keyscan_getNextEvent() in a loop till - ** the return value is CY_KEYSCAN_EVENT_NONE - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** \param context [in] Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Interrupt_handler(MXKEYSCAN_Type *base, cy_stc_keyscan_context_t *context); - -/** - ***************************************************************************** - ** \brief Flush events from HW queue. - ** Flush the Fw FIFO also and it is equallent to no key press events. - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** \param context [in] Pointer to the context. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_FlushHwEvents(MXKEYSCAN_Type *base, cy_stc_keyscan_context_t *context); - -/** - ***************************************************************************** - ** \brief Enables Ghost detection - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_EnableGhostDetection(MXKEYSCAN_Type *base); - -/** - ***************************************************************************** - ** \brief Disables Ghost detection - ** - ** \param base [in] Pointer to Keyscan instance register area. - ** - ** \retval Refer \ref cy_en_ks_status_t - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_DisableGhostDetection(MXKEYSCAN_Type *base); - -/** \} group_keyscan_functions */ -/** @} */ - - - - -#ifdef __cplusplus -} -#endif -#endif /*(CY_IP_MXKEYSCAN) */ -#endif /* __CY_KEYSCAN_H__ */ - -/** \} group_keyscan */ -/*****************************************************************************/ -/* EOF (not truncated) */ -/*****************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_lin.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_lin.h deleted file mode 100644 index 906bacf9da..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_lin.h +++ /dev/null @@ -1,645 +0,0 @@ -/***************************************************************************//** -* \file cy_lin.h -* \version 1.0 -* -* \brief -* Provides an API declaration of the LIN driver -* -******************************************************************************** -* \copyright -* Copyright 2020-2021, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -/** -* \addtogroup group_lin -* \{ -* The LIN driver provides a function API to manage Local Interconnect Network. -* -* The functions and other declarations used in this driver are in cy_lin.h. -* You can include cy_pdl.h to get access to all functions -* and declarations in the PDL. -* -* The Local Interconnect Network (LIN) bus was developed to create a standard for low-cost, low-end multiplexed communication. The use of a standard * bus protocol promotes the interoperability of network nodes. -* The LIN bus is a sub-bus system based on a serial communications protocol. The bus is a single master / multiple slave bus that uses a single wire * to transmit data. -* A LIN cluster exchanges messages with a pre-defined message frame format. The master node initiates a message exchange. Both the master node and * the slave nodes can transmit (TX) and receive (RX). -* The LIN protocol is half-duplex: a LIN node is either transmitting or receiving, but it cannot transmit and receive at the same time. Messages are * exchanged when the LIN cluster is in operational mode. -* A LIN cluster also exchanges wake-up signals. Both the master node and the slave nodes can initiate a wake-up. Wake-up signals are exchanged when * the LIN cluster is in sleep mode. -* The LIN bus can have a length of 10's of meters and has a bit-rate in the range of 1 kbps to 20 kbps. Most bus timing is expressed in bit periods * (e.g. a 20 kbps LIN bus has a 50 us bit period). -* The LIN bus uses single wire communication using a "lin" line with an operating Voltage of 12 V. Most master and slave nodes use discrete * transceiver devices. -* -* Features: -* * Single LIN hardware unit supporting multiple LIN channels. -* * Unified interrupt model. -* * Per LIN channel: -* * * Master and slave functionality. -* * * Master node autonomous header transmission. Master node autonomous response transmission and reception. -* * * Slave node autonomous header reception. Slave node autonomous response transmission and reception. -* * * Message buffer for PID, data and checksum fields. -* * * Break detection during message reception. -* * * Classic and enhanced checksum. -* * * Wakeup signaling. -* * * Timeout detection. -* * * Error detection. -* -* The LIN bus is an industry standard. -* -* \section group_lin_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_lin_cmd_macro LIN command type definition -* \defgroup group_lin_intr_mask_macro LIN ALL error mask definition -* \defgroup group_lin_functions Functions -* \defgroup group_lin_data_structures Data Structures -* \defgroup group_lin_enums Enumerated Types -*/ - - -#if !defined(CY_LIN_H) -#define CY_LIN_H -#include "cy_device.h" -#if defined (CY_IP_MXLIN) -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - ***************************************************************************** - ** \defgroup LinGroup Local Interconnect Network (LIN) - ** - ** \brief This section describes the interface for the Local Interconnect Network. - ** - *****************************************************************************/ -/** @{ */ - - -/*****************************************************************************/ -/* Global pre-processor symbols/macros ('#define') */ -/*****************************************************************************/ -/** Driver major version */ -#define CY_LIN_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_LIN_DRV_VERSION_MINOR 0 - -/** LIN driver ID */ -#define CY_LIN_ID CY_PDL_DRV_ID(0x37u) - -/** Maximum ID */ -#define LIN_ID_MAX (0x3Fu) -/** Maximum data length */ -#define LIN_DATA_LENGTH_MAX (8u) -/** Minimum data length */ -#define LIN_DATA_LENGTH_MIN (1u) -/** Maximum time out length */ -#define LIN_TIMEOUT_LENGTH_MAX (255u) -/** Minimum wakeup peroid value = 250usec*/ -#define LIN_WAKEUP_PERIOD_MIN (250u) -/** Maximum break_wakeup period bit length */ -#define LIN_BREAK_WAKEUP_LENGTH_BITS_MAX (31u) -/** LIN Master minimum break filed detection length */ -#define LIN_MASTER_BREAK_FILED_LENGTH_MIN (13u) -/** \} LinGroup */ - -/** -* \addtogroup group_lin_enums -* \{ -*/ -/** LIN API status definition */ -typedef enum -{ - CY_LIN_SUCCESS = 0x00u, /**< Returned successful */ - CY_LIN_BAD_PARAM = CY_LIN_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ - CY_LIN_BUSY = CY_LIN_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Change settings while tx/rx on-going */ - CY_LIN_FRAME_NOT_RECEIVED = CY_LIN_ID | CY_PDL_STATUS_ERROR | 0x03u, /**< No frame received */ -} cy_en_lin_status_t; -/** \} group_lin_enums */ - -/** -* \addtogroup group_lin_cmd_macro LIN command type definition -* \{ -* Specifies the parameter values passed to LIN command API -*/ -/** LIN Command TX Header */ -#define LIN_CMD_TX_HEADER (LIN_CH_CMD_TX_HEADER_Msk) -/** LIN Command TX Response */ -#define LIN_CMD_TX_RESPONSE (LIN_CH_CMD_TX_RESPONSE_Msk) -/** LIN Command RX Response */ -#define LIN_CMD_RX_RESPONSE (LIN_CH_CMD_RX_RESPONSE_Msk) -/** LIN Command TX Header and TX Response */ -#define LIN_CMD_TX_HEADER_TX_RESPONSE (LIN_CH_CMD_TX_HEADER_Msk | LIN_CH_CMD_TX_RESPONSE_Msk) -/** LIN Command TX Header and RX Response */ -#define LIN_CMD_TX_HEADER_RX_RESPONSE (LIN_CH_CMD_TX_HEADER_Msk | LIN_CH_CMD_RX_RESPONSE_Msk) -/** LIN Command RX Header and RX Response */ -#define LIN_CMD_RX_HEADER_RX_RESPONSE (LIN_CH_CMD_RX_HEADER_Msk | LIN_CH_CMD_RX_RESPONSE_Msk) -/** LIN Command TX Wake up */ -#define LIN_CMD_TX_WAKEUP (LIN_CH_CMD_TX_WAKEUP_Msk) -/** \} group_lin_cmd_macro */ - -/** -* \addtogroup group_lin_intr_mask_macro LIN ALL error mask definition -* \{ -* Specifies the mask value for interrupt status/mask -*/ -/** Mask for TX Header DONE */ -#define LIN_INTR_TX_HEADER_DONE (LIN_CH_INTR_TX_HEADER_DONE_Msk) -/** Mask for TX Response DONE */ -#define LIN_INTR_TX_RESPONSE_DONE (LIN_CH_INTR_TX_RESPONSE_DONE_Msk) -/** Mask for TX Wake up DONE */ -#define LIN_INTR_TX_WAKEUP_DONE (LIN_CH_INTR_TX_WAKEUP_DONE_Msk) -/** Mask for RX Header DONE */ -#define LIN_INTR_RX_HEADER_DONE (LIN_CH_INTR_RX_HEADER_DONE_Msk) -/** Mask for RX Respinse DONE */ -#define LIN_INTR_RX_RESPONSE_DONE (LIN_CH_INTR_RX_RESPONSE_DONE_Msk) -/** Mask for RX Wake up DONE */ -#define LIN_INTR_RX_WAKEUP_DONE (LIN_CH_INTR_RX_WAKEUP_DONE_Msk) -/** Mask for RX Header Sync DONE */ -#define LIN_INTR_RX_HEADER_SYNC_DONE (LIN_CH_INTR_RX_HEADER_SYNC_DONE_Msk) -/** Mask for RX Noise Detect */ -#define LIN_INTR_RX_NOISE_DETECT (LIN_CH_INTR_RX_NOISE_DETECT_Msk) -/** Mask for timeout */ -#define LIN_INTR_TIMEOUT (LIN_CH_INTR_TIMEOUT_Msk) -/** Mask for TX Header Bit error */ -#define LIN_INTR_TX_HEADER_BIT_ERROR (LIN_CH_INTR_TX_HEADER_BIT_ERROR_Msk) -/** Mask for TX Response Bit error */ -#define LIN_INTR_TX_RESPONSE_BIT_ERROR (LIN_CH_INTR_TX_RESPONSE_BIT_ERROR_Msk) -/** Mask for RX Header frame error */ -#define LIN_INTR_RX_HEADER_FRAME_ERROR (LIN_CH_INTR_RX_HEADER_FRAME_ERROR_Msk) -/** Mask for Rx header sync error */ -#define LIN_INTR_RX_HEADER_SYNC_ERROR (LIN_CH_INTR_RX_HEADER_SYNC_ERROR_Msk) -/** Mask for Rx header parity error */ -#define LIN_INTR_RX_HEADER_PARITY_ERROR (LIN_CH_INTR_RX_HEADER_PARITY_ERROR_Msk) -/** Mask for Rx Respinse frame error */ -#define LIN_INTR_RX_RESPONSE_FRAME_ERROR (LIN_CH_INTR_RX_RESPONSE_FRAME_ERROR_Msk) -/** Mask for Rx response checksum error */ -#define LIN_INTR_RX_RESPONSE_CHECKSUM_ERROR (LIN_CH_INTR_RX_RESPONSE_CHECKSUM_ERROR_Msk) -/** Mask for all slave errors */ -#define LIN_INTR_ALL_ERROR_MASK_SLAVE (LIN_CH_INTR_RX_NOISE_DETECT_Msk |\ - LIN_CH_INTR_TIMEOUT_Msk |\ - LIN_CH_INTR_TX_RESPONSE_BIT_ERROR_Msk |\ - LIN_CH_INTR_RX_HEADER_FRAME_ERROR_Msk |\ - LIN_CH_INTR_RX_HEADER_SYNC_ERROR_Msk |\ - LIN_CH_INTR_RX_HEADER_PARITY_ERROR_Msk |\ - LIN_CH_INTR_RX_RESPONSE_FRAME_ERROR_Msk |\ - LIN_CH_INTR_RX_RESPONSE_CHECKSUM_ERROR_Msk) -/** Mask for all master errors */ -#define LIN_INTR_ALL_ERROR_MASK_MASTER (LIN_INTR_ALL_ERROR_MASK_SLAVE | LIN_CH_INTR_TX_HEADER_BIT_ERROR_Msk) - - -/** \} group_lin_intr_mask_macro */ - -/** -* \addtogroup group_lin_enums -* \{ -*/ -/*****************************************************************************/ -/* Global type definitions ('typedef') */ -/*****************************************************************************/ -/** - ***************************************************************************** - ** \brief LIN break delimiter length - ** - ** This configuration is effective only when corresponding channel = master mode. - *****************************************************************************/ -typedef enum cy_en_lin_break_delimiter_length{ - LIN_BREAK_DILIMITER_LENGTH_1BITS = 0, /*!< 1-bit length */ - LIN_BREAK_DILIMITER_LENGTH_2BITS = 1, /*!< 2-bit length */ - LIN_BREAK_DILIMITER_LENGTH_3BITS = 2, /*!< 3-bit length */ - LIN_BREAK_DILIMITER_LENGTH_4BITS = 3 /*!< 4-bit length */ -}cy_en_lin_break_delimiter_length_t; - -/** - ***************************************************************************** - ** \brief Stop bit selection. - ** - *****************************************************************************/ -typedef enum cy_en_lin_stopbit -{ - LIN_ONE_STOP_BIT = 1, /*!< 1 stop bit */ - LIN_TWO_STOP_BIT = 3 /*!< 2 stop bits */ -} cy_en_lin_stopbit_t; - -/** - ***************************************************************************** - ** \brief Checksum type selection. - ** - *****************************************************************************/ -typedef enum cy_en_lin_checksum_type -{ - LIN_CHECKSUM_TYPE_NORMAL = 0, /*!< Normal (classic) checksum */ - LIN_CHECKSUM_TYPE_EXTENDED = 1 /*!< Extended (enhanced) checksum */ -}cy_en_lin_checksum_type_t; - -/** - ***************************************************************************** - ** \brief timeout type selection. - ** - *****************************************************************************/ -typedef enum cy_en_lin_timeout_sel_type -{ - LIN_TIMEOUT_NONE = 0, /*!< No timeout */ - LIN_TIMEOUT_FROM_BREAK_TO_CHECKSUM = 1, /*!< Frame mode: from the start of break field to checksum field STOP bits */ - LIN_TIMEOUT_FROM_BREAK_TO_PID = 2, /*!< Frame header mode: detects timeout from the start of break field to PID field STOP bits */ - LIN_TIMEOUT_FROM_RESPONSE_TO_CHECKSUM = 3 /*!< Frame response mode: detects timeout from the first data field START bit to checksum field STOP bits. */ -}cy_en_lin_timeout_sel_type_t; -/** \} group_lin_enums */ - -/** -* \addtogroup group_lin_data_structures -* \{ -*/ - -/** - ***************************************************************************** - ** \brief LIN configuration - ** This settings are per LIN instance. - *****************************************************************************/ -typedef struct cy_stc_lin_config -{ - - bool masterMode; /**< If TRUE, corresponding channel = master mode, If FALSE, slave mode. */ - - bool linTransceiverAutoEnable; /**< If TRUE, corresponding LIN channel transceiver is enabled automatically, - If FALSE, firmware has to handle the transceiver enable signal manually */ - - uint8_t breakFieldLength; /**< Break field length. */ - - cy_en_lin_break_delimiter_length_t breakDelimiterLength; /**< Break delimiter length. See #cy_en_lin_break_delimiter_length_t */ - - cy_en_lin_stopbit_t stopBit; /**< Stop bit length. See #cy_en_lin_stopbit_t. */ - - bool filterEnable; /**< If TRUE, lin_rx_in filter operates. - Median 3 operates on the last three "lin_rx_in" values. - The sequences '000', '001', '010' and '100' result in a filtered value '0'. - The sequences '111', '110', '101' and '011' result in a filtered value '1'. - */ -}cy_stc_lin_config_t; - -/** \} group_lin_data_structures */ - -/*****************************************************************************/ -/* Global variable declarations ('extern', definition in C source) */ -/*****************************************************************************/ -/** -* \addtogroup group_lin_intr_mask_macro LIN ALL error mask definition -* \{ -* Specifies the mask value for interrupt status/mask -*/ - -/** Mask for Stop Bits */ -#define LIN_CH_CTL0_STOP_BITS_DEFAULT LIN_ONE_STOP_BIT -/** Mask for Auto Enable */ -#define LIN_CH_CTL0_AUTO_EN_DEFAULT 0U -/** Mask for break delimiter length */ -#define LIN_CH_CTL0_BREAK_DELIMITER_LENGTH_DEFAULT 1U -/** Mask for break wake up length */ -#define LIN_CH_CTL0_BREAK_WAKEUP_LENGTH_DEFAULT 12U -/** Mask for mode */ -#define LIN_CH_CTL0_MODE_DEFAULT 0U -/** Mask for error ignore */ -#define LIN_CH_CTL0_BIT_ERROR_IGNORE_DEFAULT 0U -/** Mask for parity */ -#define LIN_CH_CTL0_PARITY_DEFAULT 0U -/** Mask for parity enable */ -#define LIN_CH_CTL0_PARITY_EN_DEFAULT 0U -/** Mask for filter enable */ -#define LIN_CH_CTL0_FILTER_EN_DEFAULT 1U -/** Mask for enabled */ -#define LIN_CH_CTL0_ENABLED_DEFAULT 0U -/** Mask for default */ -#define LIN_CH_CTL0_DEFAULT (_VAL2FLD(LIN_CH_CTL0_STOP_BITS, LIN_CH_CTL0_STOP_BITS_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_AUTO_EN, LIN_CH_CTL0_AUTO_EN_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_BREAK_DELIMITER_LENGTH, LIN_CH_CTL0_BREAK_DELIMITER_LENGTH_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_BREAK_WAKEUP_LENGTH, LIN_CH_CTL0_BREAK_WAKEUP_LENGTH_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_MODE, LIN_CH_CTL0_MODE_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_BIT_ERROR_IGNORE, LIN_CH_CTL0_BIT_ERROR_IGNORE_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_PARITY, LIN_CH_CTL0_PARITY_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_PARITY_EN, LIN_CH_CTL0_PARITY_EN_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_FILTER_EN, LIN_CH_CTL0_FILTER_EN_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_ENABLED, LIN_CH_CTL0_ENABLED_DEFAULT)) -/** \} group_lin_intr_mask_macro */ - -/** -* \addtogroup group_lin_functions -* \{ -*/ - -/*****************************************************************************/ -/* Global function prototypes ('extern', definition in C source) */ -/*****************************************************************************/ -/** - ***************************************************************************** - ** \brief DeInitialisation of a LIN module. - ** This Function deinitialises the selected LIN channel. - ** - ** \param [in] base Pointer to LIN instance channel register - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_DeInit( LIN_CH_Type* base ); - -/** - ***************************************************************************** - ** \brief Initialisation of a LIN module. - ** This Function initialises the LIN according the Options setup in the - ** passed Config Struct. Several Checkings are done before that and an error - ** is returned if invalid Modes are requested. - ** - ** \pre The Application must configure corresponding LIN pins (SIN, SOT) - ** according to requirements and settings of LIN instance. - ** And must set baudrate using SysClk. LIN I/F has internal fixed - ** oversampling value (16). Therefore LIN clock / 16 is actual - ** baudrate. - ** - ** \param [in] base Pointer to LIN instance register area - ** \param [in] pstcConfig LIN module configuration. See #cy_stc_lin_config_t. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_Init( LIN_CH_Type* base, const cy_stc_lin_config_t *pstcConfig); - -/** - ***************************************************************************** - ** \brief Read response data. - ** - ** \pre Must be run after RX_RESPONSE_DONE. - ** - ** \note This function return last received data set. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param data [out] Pointer to received data. - ** Must have enough space for current Rx data. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_ReadData( LIN_CH_Type* base, uint8_t *data); - -/** - ***************************************************************************** - ** \brief Write response data. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param data [in] Pointer to response data. - ** \param dataLength [in] Data length in bytes. - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_WriteData( LIN_CH_Type* base, const uint8_t *data, uint8_t dataLength ); - -/** - ***************************************************************************** - ** \brief Enable LIN channel. - ** - ** \param base [in] Pointer to LIN instance register area. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_Enable(LIN_CH_Type* base); - -/** - ***************************************************************************** - ** \brief Disable LIN channel. - ** Disabling LIN channel causes clearing none retained registers. - ** e.g) CMD register, INTR register, STATUS regiser. - ** This behavior can be uses re-initialization after error, - ** abort RX operation. - ** - ** \param base [in] Pointer to LIN instance register area. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_Disable(LIN_CH_Type* base); - -/** - ***************************************************************************** - ** \brief Setup LIN break/wakeup field length. - ** Normaly this I/F is used for detection of the wakeup pulse. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param length [in] Bit length of the break/wakeup field. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetBreakWakeupFieldLength(LIN_CH_Type* base, uint8_t length); - -/** - ***************************************************************************** - ** \brief Setup LIN response field data length - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param length [in] Data length in byte - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetDataLength(LIN_CH_Type* base, uint8_t length); - -/** - ***************************************************************************** - ** \brief Setup LIN checksum type setting - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param type [in] Checksum type. Refer \ref cy_en_lin_checksum_type_t - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetChecksumType(LIN_CH_Type* base, cy_en_lin_checksum_type_t type); - -/** - ***************************************************************************** - ** \brief Setup LIN operation command - ** - ** \note As a normal usage, following comobinations are used. - ** - Master - ** Header TX only : LIN_CMD_TX_HEADER - ** Header TX & TX response : LIN_CMD_TX_HEADER_TX_RESPONSE - ** Header TX & RX response : LIN_CMD_TX_HEADER_RX_RESPONSE - ** - Slave - ** Header RX : LIN_CMD_RX_HEADER_RX_RESPONSE - ** TX response : LIN_CMD_TX_RESPONSE - ** RX response : Already set when header RX - ** As a typical usage, RX response is always set at header RX phase. - ** - Wakeup frame : LIN_CMD_TX_WAKEUP - ** Instead of above macro, you can use raw definition LIN_CH_CMD_*_Msk defined in IO header file. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param command [in] Required operation command. Refer \ref group_lin_cmd_macro - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetCmd(LIN_CH_Type* base, uint32_t command); - -/** - ***************************************************************************** - ** \brief Setup LIN header for master tx header operation - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param id [in] ID value - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetHeader(LIN_CH_Type* base, uint8_t id); - -/** - ***************************************************************************** - ** \brief Return received LIN header - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param id [out] Received ID value. - ** \param parity [out] Received parity value. - ** Note that parity check is always done by HW automatically. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetHeader(LIN_CH_Type* base, uint8_t *id, uint8_t *parity); - -/** - ***************************************************************************** - ** \brief Setup interrupt source to be accepted. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param mask [in] The mask with the OR of the interrupt source to be accepted. - ** See \ref group_lin_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetInterruptMask(LIN_CH_Type* base, uint32_t mask); - -/** - ***************************************************************************** - ** \brief Return interupt mask setting. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param mask [out] The mask with the OR of the interrupt source which is masked. - ** See \ref group_lin_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetInterruptMask(LIN_CH_Type* base, uint32_t *mask); - -/** - ***************************************************************************** - ** \brief Return interupt masked status. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param status [out] The mask with the OR of the interrupt source which occurs. - ** See \ref group_lin_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetInterruptMaskedStatus(LIN_CH_Type* base, uint32_t *status); - -/** - ***************************************************************************** - ** \brief Return interupt raw status. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param status [out] The mask with the OR of the interrupt source which occurs. - ** See \ref group_lin_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetInterruptStatus(LIN_CH_Type* base, uint32_t *status); - -/** - ***************************************************************************** - ** \brief Clear interupt status. - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param mask [in] The mask with the OR of the interrupt source to be cleared. - ** See \ref group_lin_intr_mask_macro for the set of constants. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_ClearInterrupt(LIN_CH_Type* base, uint32_t mask); - -/** - ***************************************************************************** - ** \brief Return LIN module status - ** - ** \param base [in] Pointer to LIN instance register area. - ** \param status [out] LIN module status. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetStatus(LIN_CH_Type* base, uint32_t *status); - -/** - ***************************************************************************** - ** \brief Enables LIN channel 'en' out - ** - ** If linTransceiverAutoEnable in cy_stc_lin_config_t config strucuture is set to true - ** then tranceiver is set automatically and user need not call this funcition, - ** else user has to call Cy_Status_EnOut_Enable() before sending a message and call - ** Cy_Status_EnOut_Disable() after sending the message. - ** - ** \param base [in] Pointer to LIN instance register area. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Status_EnOut_Enable(LIN_CH_Type* base); - -/** - ***************************************************************************** - ** \brief Disables LIN channel 'en' out - ** - ** If linTransceiverAutoEnable in cy_stc_lin_config_t config strucuture is set to true - ** then tranceiver is set automatically and user need not call this funcition, - ** else user has to call Cy_Status_EnOut_Enable() before sending a message and call - ** Cy_Status_EnOut_Disable() after sending the message. - ** - ** \param base [in] Pointer to LIN instance register area. - ** - ** \retval Refer \ref cy_en_lin_status_t - ** - *****************************************************************************/ -cy_en_lin_status_t Cy_Status_EnOut_Disable(LIN_CH_Type* base); - -/** \} group_lin_functions */ -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif /*(CY_IP_MXLIN) */ -#endif /* __CY_LIN_H__ */ - -/** \} group_lin */ - -/*****************************************************************************/ -/* EOF (not truncated) */ -/*****************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mpc.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mpc.h deleted file mode 100644 index 3aba6fdd6f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mpc.h +++ /dev/null @@ -1,202 +0,0 @@ -/***************************************************************************//** -* \file cy_mpc.h -* \version 1.0 -* -* \brief -* The header file of the MPC driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_mpc -* \{ -* MPC is the Memory Protection Controller which helps in configuring the memory as secure or non-secure. -* -* The functions and other declarations used in this driver are in cy_mpc.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* You can use this driver to configre memory regions as secure/non-secure. -* -* \section group_mpc_more_information More Information -* -* For more information on the MPC , refer to -* the technical reference manual (TRM). -* -* \section group_mpc_MISRA MISRA-C Compliance -* The mpc driver does not have any specific deviations. -* -* \section group_mpc_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_mpc_macros Macros -* \defgroup group_mpc_functions Functions -* \defgroup group_mpc_data_structures Data Structures -* \defgroup group_mpc_enums Enumerated Types -*/ -/** \} group_mpc */ - - -#if !defined (CY_MPC_H) -#define CY_MPC_H - -#include -#include -#include -#include "cy_syslib.h" -#include "cy_device_headers.h" -#include "cy_device.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_mpc_macros -* \{ -*/ -/** The MPC driver identifier */ -/** MPC driver ID */ -#define CY_MPC_ID (CY_PDL_DRV_ID(0x60U)) - -/** Driver major version */ -#define CY_MPC_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_MPC_DRV_VERSION_MINOR 0 -/** \} group_mpc_macros */ - -/** -* Prot Driver error codes -*/ - -/** -* \addtogroup group_mpc_enums -* \{ -*/ -/** MPC API return status */ -typedef enum -{ - CY_MPC_SUCCESS = 0x00U, /**< Returned successful */ - CY_MPC_BAD_PARAM = CY_MPC_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */ - CY_MPC_INVALID_STATE = CY_MPC_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< The operation is not setup */ - CY_MPC_FAILURE = CY_MPC_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< The resource is locked */ - CY_MPC_UNAVAILABLE = CY_MPC_ID | CY_PDL_STATUS_ERROR | 0x04U /**< The resource is unavailable */ -} cy_en_mpc_status_t; - -/** Access permission */ -typedef enum -{ - CY_MPC_ACCESS_DISABLED = 0x00U, /**< Read and Write disabled */ - CY_MPC_ACCESS_R = 0x01U, /**< Read enabled */ - CY_MPC_ACCESS_W = 0x02U, /**< Write enabled */ - CY_MPC_ACCESS_RW = 0x03U /**< Read and Write enabled */ -}cy_en_mpc_access_attr_t; - -/** Security permission */ -typedef enum -{ - CY_MPC_SECURE = 0x0U, /**< Secure */ - CY_MPC_NON_SECURE = 0x1U /**< Non-secure */ -}cy_en_mpc_sec_attr_t; - -/** MPC block size */ -typedef enum -{ - CY_MPC_SIZE_32B = 0U, /**< 32 bytes */ - CY_MPC_SIZE_64B = 1U, /**< 64 bytes */ - CY_MPC_SIZE_128B = 2U, /**< 128 bytes */ - CY_MPC_SIZE_256B = 3U, /**< 256 bytes */ - CY_MPC_SIZE_512B = 4U, /**< 512 bytes */ - CY_MPC_SIZE_1KB = 5U, /**< 1 Kilobyte */ - CY_MPC_SIZE_2KB = 6U, /**< 2 Kilobytes */ - CY_MPC_SIZE_4KB = 7U, /**< 4 Kilobytes */ - CY_MPC_SIZE_8KB = 8U, /**< 8 Kilobytes */ - CY_MPC_SIZE_16KB = 9U, /**< 16 Kilobytes */ - CY_MPC_SIZE_32KB = 10U, /**< 32 Kilobytes */ - CY_MPC_SIZE_64KB = 11U, /**< 64 Kilobytes */ - CY_MPC_SIZE_128KB = 12U, /**< 128 Kilobytes */ - CY_MPC_SIZE_256KB = 13U, /**< 256 Kilobytes */ - CY_MPC_SIZE_512KB = 14U, /**< 512 Kilobytes */ - CY_MPC_SIZE_1MB = 15U /**< 1 Megabyte */ -}cy_en_mpc_size_t; - -/** MPC protection context */ -typedef enum -{ - CY_MPC_PC_0 = 0U, /**< PC 0 */ - CY_MPC_PC_1 = 1U, /**< PC 1 */ - CY_MPC_PC_2 = 2U /**< PC 2 */ -}cy_en_mpc_prot_context_t; - -/** \} group_mpc_enums */ - -/** -* \addtogroup group_mpc_data_structures -* \{ -*/ -/** The OTP Control configuration structure. */ -/** Configuration structure for ROT MPC Struct initialization */ -typedef struct -{ - uint32_t startAddress; /**< Sarting memory address */ - uint32_t size; /**< Size of the memory */ - cy_en_mpc_size_t regionSize; /**< Size of the memory region */ - cy_en_mpc_prot_context_t pc; /**< Protection Context */ - cy_en_mpc_sec_attr_t secure; /**< Security permissions for the region */ - cy_en_mpc_access_attr_t access; /**< Access permissions for the region */ -} cy_stc_mpc_rot_cfg_t; - -/** Configuration structure for MPC Struct initialization */ -typedef struct -{ - uint32_t startAddress; /**< Sarting memory address */ - uint32_t size; /**< Size of the memory */ - cy_en_mpc_size_t regionSize; /**< Size of the memory region */ - cy_en_mpc_sec_attr_t secure; /**< Security permissions for the region */ -} cy_stc_mpc_cfg_t; - -/** \} group_mpc_data_structures */ - - -/** -* \addtogroup group_mpc_functions -* \{ -*/ - -cy_en_mpc_status_t Cy_Mpc_ConfigRotMpcStruct(RAMC_MPC_Type* base, const cy_stc_mpc_rot_cfg_t* rotConfig); -cy_en_mpc_status_t Cy_Mpc_ConfigMpcStruct(RAMC_MPC_Type* base, const cy_stc_mpc_cfg_t* config); -void Cy_Mpc_Lock(RAMC_MPC_Type* base); - -/** \} group_mpc_functions */ - -#if defined(__cplusplus) -} -#endif - -#endif /* #if !defined (CY_MPC_H) */ - -/* [] END OF FILE */ \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxconnbridge.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxconnbridge.h deleted file mode 100644 index 0961e14920..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxconnbridge.h +++ /dev/null @@ -1,528 +0,0 @@ -/***************************************************************************//** -* \file cy_mxconnbridge.h -* \version 1.0 -* -* This file provides an API declaration of the MXCONNBRIDGE driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_connbridge -* \{ -* MXCONNBRIDGE IP acts as a bridging interface between the MCU Subsystem and -* WLAN Subsystem. The IP handles signal routing between the two subsystems, and -* also handles AHB based register access from MCUSS side to access WLAN -* subsystem resources. The high level functionalities supported by the IP -* include: -* 1) Enables AHB access to the Global Coexistence Interface (GCI) block on the -* WLAN side through an internal bridge. -* 2) Provides interrupt generation, masking capability from the GCI block to -* the MCUSS -* 3) Enables AHB register access to control RF switch control IO's, and -* read/write WLAN GPIOs -* 4) Enables configuration of the WLAN reset logic, WLAN SDIO signal -* multiplexing. -* -* \section group_connbridge_more_information More Information -* For more information on the Connbridge peripheral, refer to the technical reference manual (TRM). -* -* \section group_connbridge_MISRA MISRA-C Compliance -* The Connbridge driver does not have any specific deviations. -* -* \section group_connbridge_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_connbridge_functions Functions -*/ - -#if !defined (CY_MXCONNBRIDGE_H) -#define CY_MXCONNBRIDGE_H - -#include "cy_device.h" - -#if defined (CY_IP_MXCONNBRIDGE) - -#include -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** \addtogroup group_connbridge_macros -* \{ -*/ - -/** Driver major version */ -#define CY_CONNBRIDGE_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_CONNBRIDGE_DRV_VERSION_MINOR 0 - -/** Connbridge driver ID */ -#define CY_CONNBRIDGE_ID CY_PDL_DRV_ID(0x49U) - -/** \} group_connbridge_macros */ - -/*************************************** -* Constants -***************************************/ - -/** \cond INTERNAL */ - -/* Parameter validation constants */ -#define CY_MXCONNBRIDGE_INTRS_MAX (4UL) /**< Number of interrupt lines */ -#define CY_MXCONNBRIDGE_RFCTL_MAX (32UL) /**< Number of RF controls */ -#define CY_MXCONNBRIDGE_GPIO_PIN_MAX (8UL) /**< Number of GPIO IN pins */ - - -/* connbridge Mask */ -#define CY_MXCONNBRIDGE_INTR_STATUS_MASK (0x01UL) /**< Single interrupt line mask for interrupt status in INTR register */ -#define CY_MXCONNBRIDGE_INTR_EN_MASK (0x01UL) /**< Single interrupt line mask for interrupt in INTR register */ -#define CY_MXCONNBRIDGE_RFCTL_EN_MASK (0x01UL) /**< RF control enable mask for RF_SWITCH_CTRL register */ -#define CY_MXCONNBRIDGE_GPIO_PIN_MASK (0x01UL) /**< GPIO IN/OUT bit mask for GPIO_IN and GPIO_OUT register */ -#define CY_MXCONNBRIDGE_WLAN_RESET_STATUS_MASK (0x01UL) -#define CY_MXCONNBRIDGE_WLAN_RESET_MUX_MASK (0x01UL) -#define CY_MXCONNBRIDGE_WLAN_SDIO_MUX_MASK (0x01UL) - -/* Offsets */ -#define CY_MXCONNBRIDGE_WLAN_RESET_STATUS_OFFSET (0UL) /**< Offset for HSIOM */ -#define CY_MXCONNBRIDGE_WLAN_RESET_MUX_OFFSET (1UL) /**< Offset for HSIOM */ -#define CY_MXCONNBRIDGE_WLAN_SDIO_MUX_OFFSET (2UL) /**< Offset for HSIOM */ - - -/* Parameter validation macros */ -#define CY_MXCONNBRIDGE_IS_INTRNUM_VALID(intrNum) (CY_MXCONNBRIDGE_INTRS_MAX > (intrNum)) -#define CY_MXCONNBRIDGE_IS_RFCTLNUM_VALID(rfNum) (CY_MXCONNBRIDGE_RFCTL_MAX > (rfNum)) -#define CY_MXCONNBRIDGE_IS_VALUE_VALID(outVal) (1UL >= (outVal)) -#define CY_MXCONNBRIDGE_IS_GPIO_PIN_VALID(pinNum) (CY_MXCONNBRIDGE_GPIO_PIN_MAX > (pinNum)) - -/** \endcond */ - -/** -* \addtogroup group_connbridge_functions -* \{ -*/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_Enable(MXCONNBRIDGE_Type *base); -__STATIC_INLINE void Cy_MXCONNBRIDGE_Disable(MXCONNBRIDGE_Type *base); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetInterruptStatusMasked(MXCONNBRIDGE_Type *base, uint32_t intrNum); -__STATIC_INLINE void Cy_MXCONNBRIDGE_SetInterruptMask(MXCONNBRIDGE_Type* base, uint32_t intrNum, uint32_t value); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetInterruptMask(MXCONNBRIDGE_Type* base, uint32_t intrNum); -__STATIC_INLINE void Cy_MXCONNBRIDGE_SetRfSwitchControl(MXCONNBRIDGE_Type *base, uint32_t rfNum, uint32_t value); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetRfSwitchControl(MXCONNBRIDGE_Type* base, uint32_t rfNum); -__STATIC_INLINE void Cy_MXCONNBRIDGE_WriteGpioInPin(MXCONNBRIDGE_Type *base, uint32_t pinNum, uint32_t value); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetGpioInPin(MXCONNBRIDGE_Type* base, uint32_t pinNum); -__STATIC_INLINE void Cy_MXCONNBRIDGE_WriteGpioOutPin(MXCONNBRIDGE_Type *base, uint32_t pinNum, uint32_t value); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetGpioOutPin(MXCONNBRIDGE_Type* base, uint32_t pinNum); -__STATIC_INLINE void Cy_MXCONNBRIDGE_DEVWAKEEnable(MXCONNBRIDGE_Type *base); -__STATIC_INLINE void Cy_MXCONNBRIDGE_DEVWAKEDisable(MXCONNBRIDGE_Type *base); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_WLANResetStatus(MXCONNBRIDGE_Type *base); -void Cy_MXCONNBRIDGE_WLANResetMux(MXCONNBRIDGE_Type *base, uint32_t value); -void Cy_MXCONNBRIDGE_SetWLANSDIOMux(MXCONNBRIDGE_Type *base, uint32_t value); -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetWLANSDIOMux(MXCONNBRIDGE_Type *base); - - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_Enable -****************************************************************************//** -* -* Enables the mxconnbridge ip -* -* \param base -* The pointer to a MXCONNBRIDGE instance. -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_Enable(MXCONNBRIDGE_Type *base) -{ - MXCONNBRIDGE_CTL(base) = (unsigned int)(1<<31); -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_Disable -****************************************************************************//** -* -* Disables the mxconnbridge ip -* -* \param base -* The pointer to a MXCONNBRIDGE instance. -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_Disable(MXCONNBRIDGE_Type *base) -{ - MXCONNBRIDGE_CTL(base) = 0UL; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_GetInterruptStatusMasked -****************************************************************************//** -* -* Returns the interrupt status for incoming signal interrupt_0, interrupt_1, -* interrupt_2 and interrupt_3 after HW masking -* -* \param base -* The pointer to a MXCONNBRIDGE instance. -* -* \param intrNum -* Interrupt number (incoming signal) -* -* \return -* 0 = interrupt condition not detected -* 1 = interrupt condition detected -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetInterruptStatusMasked(MXCONNBRIDGE_Type *base, uint32_t intrNum) -{ - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_INTRNUM_VALID(intrNum)); - return (MXCONNBRIDGE_INTR_STATUS(base) >> intrNum) & CY_MXCONNBRIDGE_INTR_STATUS_MASK; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_SetInterruptMask -****************************************************************************//** -* -* Configures the interrupt line to be forwarded to the CPU NVIC. -* -* \param base -* Pointer to the mxconnbridge register base address -* -* \param intrNum -* Incoming intrrupt line number. -* -* \param value -* 0 = interrupt not forwarded to CPU interrupt controller -* 1 = interrupt masked and forwarded to CPU interrupt controller -* -* \note -* This function modifies a register in a read-modify-write operation. It is -* not thread safe as the resource is shared among multiple interrupt lines. -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_SetInterruptMask(MXCONNBRIDGE_Type* base, uint32_t intrNum, uint32_t value) -{ - uint32_t tempReg; - - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_INTRNUM_VALID(intrNum)); - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_VALUE_VALID(value)); - - tempReg= MXCONNBRIDGE_INTR_MASK(base) & ~(CY_MXCONNBRIDGE_INTR_EN_MASK << intrNum); - MXCONNBRIDGE_INTR_MASK(base) = tempReg | ((value & CY_MXCONNBRIDGE_INTR_EN_MASK) << intrNum); -} - - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_GetInterruptMask -****************************************************************************//** -* -* Returns the state of the interrupt mask of interrupt line. -* -* This mask is used to determine whether the line is configured to be forwarded -* to the CPU NVIC. -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param intrNum -* Position of the line bit-field within the mask register. -* -* \return -* 0 = interrupt not forwarded to CPU interrupt controller -* 1 = interrupt masked and forwarded to CPU interrupt controller -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetInterruptMask(MXCONNBRIDGE_Type* base, uint32_t intrNum) -{ - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_INTRNUM_VALID(intrNum)); - - return (MXCONNBRIDGE_INTR_MASK(base) >> intrNum) & CY_MXCONNBRIDGE_INTR_EN_MASK; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_SetRfSwitchControl -****************************************************************************//** -* -* Configure to enable/disable RF SWITCH CONTROL -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param rfNum -* Position of the line bit-field within the rf switch ctrl register. -* -* \param value -* 0 = dissable rf switch control -* 1 = enable rf switch control -* -* \note -* This function modifies a register in a read-modify-write operation. It is -* not thread safe as the resource is shared among multiple rf switch ctrl. -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_SetRfSwitchControl(MXCONNBRIDGE_Type *base, uint32_t rfNum, uint32_t value) -{ - uint32_t tempReg; - - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_RFCTLNUM_VALID(rfNum)); - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_VALUE_VALID(value)); - - tempReg= MXCONNBRIDGE_RF_SWITCH_CTRL(base) & ~(CY_MXCONNBRIDGE_RFCTL_EN_MASK << rfNum); - MXCONNBRIDGE_RF_SWITCH_CTRL(base) = tempReg | ((value & CY_MXCONNBRIDGE_RFCTL_EN_MASK) << rfNum); -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_GetRfSwitchControl -****************************************************************************//** -* -* Returns the state of the RF switch ctrl. -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param rfNum -* Position of the line bit-field within the rf switch ctrl register. -* -* \return -* 0 = RF switch ctrl enabled -* 1 = RF switch ctrl disabled -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetRfSwitchControl(MXCONNBRIDGE_Type* base, uint32_t rfNum) -{ - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_RFCTLNUM_VALID(rfNum)); - - return (MXCONNBRIDGE_RF_SWITCH_CTRL(base) >> rfNum) & CY_MXCONNBRIDGE_RFCTL_EN_MASK; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_WriteGpioInPin -****************************************************************************//** -* -* Configure to write to a GPIO-IN pin -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param pinNum -* GPIO pin number -* -* \param value -* Logic level to drive out on the pin -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_WriteGpioInPin(MXCONNBRIDGE_Type *base, uint32_t pinNum, uint32_t value) -{ - uint32_t tempReg; - - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_GPIO_PIN_VALID(pinNum)); - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_VALUE_VALID(value)); - - tempReg= MXCONNBRIDGE_GPIO_IN(base) & ~(CY_MXCONNBRIDGE_GPIO_PIN_MASK << pinNum); - MXCONNBRIDGE_GPIO_IN(base) = tempReg | ((value & CY_MXCONNBRIDGE_GPIO_PIN_MASK) << pinNum); -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_GetGpioInPin -****************************************************************************//** -* -* Reads the current logic level on the input buffer of the pin. -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param pinNum -* Position of the pin bit-field within the GPIO_IN register. -* -* \return -* Logic level present on the pin -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetGpioInPin(MXCONNBRIDGE_Type* base, uint32_t pinNum) -{ - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_GPIO_PIN_VALID(pinNum)); - - return (MXCONNBRIDGE_GPIO_IN(base) >> pinNum) & CY_MXCONNBRIDGE_GPIO_PIN_MASK; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_WriteGpioOutPin -****************************************************************************//** -* -* Configure to write to a GPIO-OUT pin -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param pinNum -* GPIO-OUT pin number -* -* \param value -* Logic level to drive out on the pin -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_WriteGpioOutPin(MXCONNBRIDGE_Type *base, uint32_t pinNum, uint32_t value) -{ - uint32_t tempReg; - - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_GPIO_PIN_VALID(pinNum)); - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_VALUE_VALID(value)); - - tempReg= MXCONNBRIDGE_GPIO_OUT(base) & ~(CY_MXCONNBRIDGE_GPIO_PIN_MASK << pinNum); - MXCONNBRIDGE_GPIO_OUT(base) = tempReg | ((value & CY_MXCONNBRIDGE_GPIO_PIN_MASK) << pinNum); -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_GetGpioOutPin -****************************************************************************//** -* -* Reads the current logic level on the input buffer of the pin. -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param pinNum -* Position of the pin bit-field within the GPIO_OUT register. -* -* \return -* Logic level present on the pin -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetGpioOutPin(MXCONNBRIDGE_Type* base, uint32_t pinNum) -{ - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_GPIO_PIN_VALID(pinNum)); - - return (MXCONNBRIDGE_GPIO_OUT(base) >> pinNum) & CY_MXCONNBRIDGE_GPIO_PIN_MASK; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_DEVWAKEEnable -****************************************************************************//** -* -* Configure to enable dev-wake signal from mcuss to wlan -* -* \param base -* Pointer to the mxconnbridge base address -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_DEVWAKEEnable(MXCONNBRIDGE_Type *base) -{ - MXCONNBRIDGE_DEV_WAKE(base) = 1UL; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_DEVWAKEDisable -****************************************************************************//** -* -* Configure to clear the dev-wake signal from mcuss to wlan -* -* \param base -* Pointer to the mxconnbridge base address -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXCONNBRIDGE_DEVWAKEDisable(MXCONNBRIDGE_Type *base) -{ - MXCONNBRIDGE_DEV_WAKE(base) = 0UL; -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_WLANResetStatus -****************************************************************************//** -* -* Get the status of WLAN RESET signal -* -* \param base -* Pointer to the mxconnbridge base address -* -* \return -* Logic level present on the signal -* 0 = WLAN is in reset -* 1 = WLAN is out of reset -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_WLANResetStatus(MXCONNBRIDGE_Type *base) -{ - return _FLD2VAL(MXCONNBRIDGE_SDIO_RESET_CTL_WLAN_RESET_N_CTL, MXCONNBRIDGE_AP_WLAN_CTL(base)); -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_GetWLANSDIOMux -****************************************************************************//** -* -* Reads the current logic level of WLAN_SDIO bit. -* -* \param base -* Pointer to the mxconnbridge base address -* -* \return -* returns sdio mode -* -* \funcusage -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXCONNBRIDGE_GetWLANSDIOMux(MXCONNBRIDGE_Type *base) -{ - return _FLD2VAL(MXCONNBRIDGE_SDIO_RESET_CTL_WLAN_SDIO_MUX,MXCONNBRIDGE_AP_WLAN_CTL(base)); -} - -/** \} group_connbridge_functions */ - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXCONNBRIDGE */ - -#endif /* CY_MXCONNBRIDGE_H */ - -/** \} group_connbridge */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxotpc.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxotpc.h deleted file mode 100644 index 2cfafcf924..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxotpc.h +++ /dev/null @@ -1,537 +0,0 @@ -/***************************************************************************//** -* \file cy_mxotpc.h -* \version 1.0 -* -* Provides the API declarations of the MXOTPC driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_mxotpc -* \{ -* MXOTPC is the OTP Controller which helps in read/write of OTP memory. -* -* The functions and other declarations used in this driver are in cy_mxotpc.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* You can use this driver to read/write OTP memory locations. -* -* \section group_mxotpc_more_information More Information -* -* For more information on the MXOTPC , refer to -* the technical reference manual (TRM). -* -* \section group_mxotpc_MISRA MISRA-C Compliance -* The mxotpc driver does not have any specific deviations. -* -* \section group_mxotpc_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_mxotpc_macros Macros -* \defgroup group_mxotpc_functions Functions -* \defgroup group_mxotpc_data_structures Data Structures -* \defgroup group_mxotpc_enums Enumerated Types -*/ - -#ifndef CY_MXOTPC_H -#define CY_MXOTPC_H - -#include "cy_device.h" - -#if defined (CY_IP_MXS28OTPC) - -#include -#include -#include "cy_syslib.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* \addtogroup group_mxotpc_macros -* \{ -*/ -/** The MXOTPC driver identifier */ -#define CY_MXOTPC_ID CY_PDL_DRV_ID(0x36U) -/** CY_MXOTPC_MAX_OTP_ROW */ -#define CY_MXOTPC_MAX_OTP_ROW 512 -/** CY_START_STATUS_CHECK_TIMEOUT */ -#define CY_START_STATUS_CHECK_TIMEOUT 1000 - -/** \} group_mxotpc_macros */ - - -/** \cond PARAM_CHECK_MACROS */ -/** Parameter check macros */ - -#define CY_MXOTPC_IS_DIRECT_CMD_VALID(cmd) ((CY_MXOTPC_READ_CMD == (cmd)) || \ - (CY_MXOTPC_PROG_CMD == (cmd)) || \ - (CY_MXOTPC_PROG_ECC_CMD == (cmd))) -/** \endcond */ - - -/** -* \addtogroup group_mxotpc_data_structures -* \{ -*/ -/** The OTP Control configuration structure. */ -typedef struct -{ - bool fuseDisable; /**< Latching of memory repair bits is disabled and forced to 0. */ - bool eccDblErrClear; /**< When this field is set, ECC_DBL_ERR field of reg OTP_ECC_STATUS is cleared. */ - bool forceOtpClkEn; /**< Force enable the OTP Clocks. */ - bool fuseReload; /**< 1 - memory repair bits reload every time mxotpc is reset. 0- Memory repair bits reload only on deep sleep reset. */ - bool disCpuAccess; /**< disables any command execution through CPU interface. */ - bool forcePowerDis; /**< disable OTP power and force it into reset. */ -} cy_mxotpc_ctl_config_t; - -/** The OTP Command structure. */ -typedef struct -{ - uint8_t colAddr; /**< Column address of the OTP bit to be read only. Not considered for programming.*/ - uint16_t rowAddr; /**< Row address of OTP bit to be accessed.*/ - uint8_t cmd; /**< OTP Controller command to access OTP. */ -} cy_mxotpc_cmd_t; - - -/** \} group_mxotpc_data_structures */ - -/******************************************************************************* -* Enumerated Types -*******************************************************************************/ - -/** -* \addtogroup group_mxotpc_enums -* \{ -*/ - -/** MXOTPC API return status */ -typedef enum -{ - CY_MXOTPC_SUCCESS = 0x00UL, /**Success */ - CY_MXOTPC_BAD_PARAM = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x01UL, /** Invalid function input parameter */ - CY_MXOTPC_TIMEOUT = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x02UL, /** Timeout occurred */ - CY_MXOTPC_INVALID = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x03UL, /** invalid state */ - CY_MXOTPC_READ_ERROR = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x04UL, /** Read Error */ - CY_MXOTPC_WRITE_ERROR = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x05UL, /** Write Error */ - CY_MXOTPC_WRITE_PROG_ERROR = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x06UL, /** OTP Programming Error */ - CY_MXOTPC_WRITE_ECC_ERROR = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x07UL, /** OTP ECC Programming Error */ - CY_MXOTPC_READ_ECC_ERROR = CY_MXOTPC_ID | CY_PDL_STATUS_ERROR | 0x08UL, /** Read ECC Error */ -} cy_mxotpc_status_t; - -/** MXOTPC Commands */ -typedef enum -{ - CY_MXOTPC_READ_CMD, /** 0x00, READ */ - CY_MXOTPC_READBURST_CMD, /** 0x01, READBURST */ - CY_MXOTPC_OTP_PROGENABLE_CMD, /** 0x02, OTP_PROGENABLE */ - CY_MXOTPC_OTP_PROGDISABLE_CMD, /** 0x03, OTP_PROGDISABLE */ - CY_MXOTPC_PRESCREEN_CMD, /** 0x04, PRESCREEN */ - CY_MXOTPC_PRESCREEN_RP_CMD, /** 0x05, PRESCREEN_RP */ - CY_MXOTPC_FLUSH_CMD, /** 0x06, FLUSH */ - CY_MXOTPC_NOP_CMD, /** 0x07, NOP */ - CY_MXOTPC_PROG_ECC_CMD, /** 0x08, PROG_ECC */ - CY_MXOTPC_PROG_ECC_WREAD_CMD, /** 0x09, PROG_ECC_WREAD */ - CY_MXOTPC_PROG_CMD, /** 0x0a, PROG */ - CY_MXOTPC_PROGRAM_RP_CMD, /** 0x0b, PROGRAM_RP */ - CY_MXOTPC_PROGRAM_OVST_CMD, /** 0x0c, PROGRAM_OVST */ - CY_MXOTPC_RELOAD_CMD, /** 0x0d, RELOAD */ - CY_MXOTPC_ERASE_CMD, /** 0x0e, ERASE */ - CY_MXOTPC_LOAD_RF_CMD, /** 0x0f, LOAD_RF */ - CY_MXOTPC_CTRL_WR_CMD, /** 0x10, CTRL_WR */ - CY_MXOTPC_CTRL_RD_CMD, /** 0x11, CTRL_RD */ - CY_MXOTPC_READ_HP_CMD, /** 0x12, READ_HP */ - CY_MXOTPC_READ_OVST_CMD, /** 0x13, READ_OVST */ - CY_MXOTPC_READ_VERIFY_Y0_CMD, /** 0x14, READ_VERIFY_Y0 */ - CY_MXOTPC_READ_VERIFY_Y1_CMD, /** 0x15, READ_VERIFY_Y1 */ - CY_MXOTPC_READ_FORCE0_CMD, /** 0x16, READ_FORCE0 */ - CY_MXOTPC_READ_FORCE1_CMD, /** 0x17, READ_FORCE1 */ - CY_MXOTPC_BURNIN_CMD, /** 0x18, BURNIN */ - CY_MXOTPC_PROGRAM_LOCK_CMD, /** 0x19, PROGRAM_LOCK */ - CY_MXOTPC_PROGRAM_TESTCOL_CMD, /** 0x1a, PROGRAM_TESTCOL */ - CY_MXOTPC_READ_TESTCOL_CMD, /** 0x1b, READ_TESTCOL */ - CY_MXOTPC_READ_FOUT_CMD = 0x1e, /** 0x1e, READ_FOUT */ - CY_MXOTPC_SET_RESET_CMD = 0x1f, /** 0x1f, SET_RESET */ -} cy_mxotpc_cmd_types_t; - -/** \} group_mxotpc_enums */ - - -/** -* \addtogroup group_mxotpc_functions -* \{ -*/ - -cy_mxotpc_status_t Cy_MXOTPC_Init(cy_mxotpc_ctl_config_t const *mxotpcConfig); -cy_mxotpc_status_t Cy_MXOTPC_DeInit(void); -cy_mxotpc_status_t Cy_MXOTPC_WriteRowReadBack(uint32_t otpRowNum, uint32_t otpWriteData, uint32_t *otpReadBackData, bool enable_ecc); -cy_mxotpc_status_t Cy_MXOTPC_WriteRow(uint32_t otpRowNum, uint32_t otpWriteData, bool enable_ecc); -cy_mxotpc_status_t Cy_MXOTPC_WriteBitReadBack(uint32_t otpRowNum, uint32_t bitNum, uint32_t *otpReadBackData); -cy_mxotpc_status_t Cy_MXOTPC_WriteBit(uint32_t otpRowNum, uint32_t bitNum); -cy_mxotpc_status_t Cy_MXOTPC_WriteEcc(uint32_t otpRowNum); -cy_mxotpc_status_t Cy_MXOTPC_ReadRow(uint32_t otpRowNum, uint32_t *otpReadData); -cy_mxotpc_status_t Cy_MXOTPC_ReadBootRow( uint32_t *otpReadData); -cy_mxotpc_status_t Cy_MXOTPC_ReadBit(uint32_t otpRowNum, uint32_t bitNum, uint32_t *otpReadBit); -cy_mxotpc_status_t Cy_MXOTPC_DirectWriteRow(uint32_t otpRowNum, uint32_t otpWriteData, uint32_t *otpReadBackData, bool otpProgEccEnable); -cy_mxotpc_status_t Cy_MXOTPC_IndirectReadBit(uint32_t otpRowNum, uint32_t bitNum, uint32_t *otpReadBit); -cy_mxotpc_status_t Cy_MXOTPC_WriteProgramSequence(void); -cy_mxotpc_status_t Cy_MXOTPC_WriteRowArray(uint32_t otpRowNum, uint32_t *otpSrcPointer, uint32_t size, bool enable_ecc); -cy_mxotpc_status_t Cy_MXOTPC_ReadRowArray(uint32_t otpRowNum, uint32_t *otpDstPointer, uint32_t size); -__STATIC_INLINE void Cy_MXOTPC_IpEnable(void); -__STATIC_INLINE void Cy_MXOTPC_IpDisable(void); -__STATIC_INLINE cy_mxotpc_status_t Cy_MXOTPC_OtpCtlConfig(cy_mxotpc_ctl_config_t const *otpConfig); -__STATIC_INLINE cy_mxotpc_status_t Cy_MXOTPC_OtpCmd(cy_mxotpc_cmd_t *otpCmd); -__STATIC_INLINE void Cy_MXOTPC_OtpStartCmd(void); -__STATIC_INLINE void Cy_MXOTPC_OtpCpuProgCmd(cy_mxotpc_cmd_types_t otpCmd); -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetStatus(uint32_t mask); -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetStartStatus(void); -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetReadBitStatus(void); -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetEccStatus(uint32_t mask); -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetFoutEccStatus(uint32_t mask); -__STATIC_INLINE void Cy_MXOTPC_OtpSetProgData(uint32_t otpData); -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpIndirectReadBit(void); -__STATIC_INLINE cy_mxotpc_status_t Cy_MXOTPC_OtpCheckStartStatus(uint32_t timeOut); -__STATIC_INLINE void Cy_MXOTPC_OtpProgEnable(bool enable); - -/** \} group_mxotpc_functions */ - -/** -* \addtogroup group_mxotpc_functions -* \{ -*/ - -/******************************************************************************* -* Function Name: Cy_MXOTPC_IpEnable -****************************************************************************//** -* -* Enables the MXOTPC IP. -* -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_IpEnable(void) -{ - MXOTPC_CTL |= MXOTPC_CTL_ENABLED_Msk; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_IpDisable -****************************************************************************//** -* -* Disables the MXOTPC IP. -* -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_IpDisable(void) -{ - MXOTPC_CTL &= ~MXOTPC_CTL_ENABLED_Msk; -} - -/******************************************************************************* -* Function Name: Cy_MxOTPC_OtpCtlConfig -****************************************************************************//** -* -* Configures MXOTPC through OTP_CTL register. -* -* \param otpConfig -* This structure contains the data that needs to be filled in OTP_CTL register. -* -* \return cy_mxotpc_status_t -* -*******************************************************************************/ -__STATIC_INLINE cy_mxotpc_status_t Cy_MXOTPC_OtpCtlConfig(cy_mxotpc_ctl_config_t const *otpConfig) -{ - cy_mxotpc_status_t ret = CY_MXOTPC_BAD_PARAM; - if(otpConfig != NULL) - { - - MXOTPC_OTP_CTL = _VAL2FLD(MXOTPC_OTP_CTL_FUSE_DISABLE, otpConfig->fuseDisable) | - _VAL2FLD(MXOTPC_OTP_CTL_ECC_DBL_ERR_CLR, otpConfig->eccDblErrClear) | - _VAL2FLD(MXOTPC_OTP_CTL_FORCE_OTP_CLK_EN, otpConfig->forceOtpClkEn) | - _VAL2FLD(MXOTPC_OTP_CTL_FUSE_RELOAD_PER_PU, otpConfig->fuseReload) | - _VAL2FLD(MXOTPC_OTP_CTL_DISCPUACCESS, otpConfig->disCpuAccess) | - _VAL2FLD(MXOTPC_OTP_CTL_FORCE_OTP_PWR_DIS, otpConfig->forcePowerDis); - - ret = CY_MXOTPC_SUCCESS; - } - return ret; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpProgEnable -****************************************************************************//** -* -* Enable/Disable the OTP CPU Program control -* -* \param enable -* Contians value to enable or disable the OTPPROG_EN bit of OTP_CTL -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_OtpProgEnable(bool enable) -{ - if(enable) - MXOTPC_OTP_CTL |= MXOTPC_OTP_CTL_OTPPROG_EN_Msk; - else - MXOTPC_OTP_CTL &= ~MXOTPC_OTP_CTL_OTPPROG_EN_Msk; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpCmd -****************************************************************************//** -* -* Writed the OTP_CMD register with row/column addresses and command type along -* with the START bit set. -* -* \param otpCmd -* Contains command which consists of Column/Row address and CMD to be sent to -* OTP Controller. -* -* \return cy_mxotpc_status_t -* -*******************************************************************************/ -__STATIC_INLINE cy_mxotpc_status_t Cy_MXOTPC_OtpCmd(cy_mxotpc_cmd_t *otpCmd) -{ - cy_mxotpc_status_t ret = CY_MXOTPC_BAD_PARAM; - - if(otpCmd != NULL) - { - - MXOTPC_OTP_CMD = _VAL2FLD(MXOTPC_OTP_CMD_COLADDR, otpCmd->colAddr) | - _VAL2FLD(MXOTPC_OTP_CMD_ROWADDR, otpCmd->rowAddr) | - _VAL2FLD(MXOTPC_OTP_CMD_CMD, otpCmd->cmd) | - MXOTPC_OTP_CMD_RD_ERR_Msk | - MXOTPC_OTP_CMD_START_Msk; - - ret = CY_MXOTPC_SUCCESS; - } - return ret; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpStartCmd -****************************************************************************//** -* -* Starts programming the command , which was filled by Cy_MXOTPC_OtpCmd -* Note: Call Cy_MXOTPC_OtpCmd, before calling this function. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_OtpStartCmd(void) -{ - MXOTPC_OTP_CMD |= MXOTPC_OTP_CMD_START_Msk; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpCpuProgCmd -****************************************************************************//** -* -* Used with Direct access , Programs the CPU_PROG_CMD register with the command. -* -* \param otpCmd -* Contains command which consists of Column/Row address and CMD to be sent to -* OTP Controller -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_OtpCpuProgCmd(cy_mxotpc_cmd_types_t otpCmd) -{ - CY_ASSERT_L2(CY_MXOTPC_IS_DIRECT_CMD_VALID((cy_mxotpc_cmd_types_t)otpCmd)); - - MXOTPC_CPU_PROG_CMD = _VAL2FLD(MXOTPC_CPU_PROG_CMD_PROG_CMD, otpCmd); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpGetStatus -****************************************************************************//** -* -* Get the status of a parameter from OTP_STATUS Register. -* -* \param mask -* Contains the mask value of parameter whose status needs to be obtained -* -* \return -* Non-zero if status bit(s) are set, Zero if status bit(s) are not set -* Note: LOCK status is 8 bits, so return value can be used to figure out which -* lock bit is set. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetStatus(uint32_t mask) -{ - return (MXOTPC_OTP_STATUS & mask); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpGetStatus -****************************************************************************//** -* -* Get the status of start command done by OTP_CTL.START bit. -* -* \return -* 1 if START bit is set, 0 if START bit is not set -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetStartStatus(void) -{ - return ((MXOTPC_OTP_CMD & MXOTPC_OTP_CMD_START_Msk) ? 1 : 0); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpGetReadBitStatus -****************************************************************************//** -* -* Get the read status from OTP_CMD.RD_ERR bit. -* -* \return -* 1 if RD_ERR bit is set, 0 if RD_ERR bit is not set -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetReadBitStatus(void) -{ - return ((MXOTPC_OTP_CMD & MXOTPC_OTP_CMD_RD_ERR_Msk) ? 1 : 0); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpGetEccStatus -****************************************************************************//** -* -* Get the read status from ECC_STATUS Register. -* -* \param mask -* Contains the mask value of parameter whose status needs to be obtained -* -* \return -* Non-zero if status bit(s) are set, Zero if status bit(s) are not set -* Note: LOCK status is 8 bits, so return value can be used to figure out which -* lock bit is set. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetEccStatus(uint32_t mask) -{ - return (MXOTPC_ECC_STATUS & mask); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpGetFoutEccStatus -****************************************************************************//** -* -* Get the read status from FOUT_ECC_STATUS Register. -* -* \param mask -* Contains the mask value of parameter whose status needs to be obtained -* -* \return -* 1 if status bit is set, 0 if status bit is not set -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpGetFoutEccStatus(uint32_t mask) -{ - return ((MXOTPC_FOUT_ECC_STATUS & mask) ? 1 : 0); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpProgCtrl -****************************************************************************//** -* -* Writes in to OTP_PROGDATA Register. -* -* \param otpData -* Contians value to be written in to OTP_PROGDATA Register. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_OtpSetProgData(uint32_t otpData) -{ - MXOTPC_OTP_PROGDATA = otpData; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpIndirectReadBit -****************************************************************************//** -* -* Get the read bit from OTP_CMD.READVAL -* -* Note: This API should be called after Cy_MXOTPC_OtpCmd & Cy_MXOTPC_OtpStartCmd. -* -* \return -* 1 if status bit is set, 0 if status bit is not set -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_MXOTPC_OtpIndirectReadBit(void) -{ - return ((MXOTPC_OTP_CMD & MXOTPC_OTP_CMD_READVAL_Msk) ? 1 : 0); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_OtpCheckStartStatus -****************************************************************************//** -* -* Checks the status of OTP_CMD.START bit for timeOut milliseconds. -* -* \return -* CY_MXOTPC_SUCCESS if START bit is 0 within timeOut milliseconds -* CY_MXOTPC_TIMEOUT if START bit is 1 within timeOut milliseconds -* -*******************************************************************************/ -__STATIC_INLINE cy_mxotpc_status_t Cy_MXOTPC_OtpCheckStartStatus(uint32_t timeOut) -{ - while(timeOut) - { - if(!Cy_MXOTPC_OtpGetStartStatus()) - return CY_MXOTPC_SUCCESS; - Cy_SysLib_Delay(1); - timeOut--; - } - - return CY_MXOTPC_TIMEOUT; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_LockCCRegion -****************************************************************************//** -* -* Configure CC312_RGN_LOCK_CTL register -* -* \param mask -* Contians mask value to enable a particular lock region on CC312_RGN_LOCK_CTL register. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_MXOTPC_LockCCRegion(uint32_t mask) -{ - MXOTPC_CC312_RGN_LOCK_CTL |= mask; -} - -/** \} group_mxotpc_functions */ - -#ifdef __cplusplus -} -#endif - -#endif /* CY_IP_MXS28OTPC */ - -#endif /* CY_MXOTPC_H */ - -/** \} group_mxotpc */ - -/* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxsdiodev.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxsdiodev.h deleted file mode 100644 index 9cb636493f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_mxsdiodev.h +++ /dev/null @@ -1,683 +0,0 @@ -/***************************************************************************//** -* \file cy_mxsdiodev.h -* \version 1.0 -* -* This file provides an API declaration of the MXSDIODEV driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_sdio_dev -* \{ -* **MXSDIODEV**: The SDIO 3.0 Device (mxsdiodev) is a IP core that has been -* previously integrated in many of Cypress's WLAN Chip tapeouts. The IP is designed to mate -* with standards compliant to SDIO Host. SDIO Device has in built DMA for external host communication. -* -* - Supports SDIO version 3.0 including the new UHS-I modes -* - DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). -* - HS: High-speed up to 50 MHz (3.3V signaling). -* - SDR12: SDR up to 25 MHz (1.8V signaling). -* - SDR25: SDR up to 50 MHz (1.8V signaling). -* - SDR50: SDR up to 100 MHz (1.8V signaling). -* - Backwards compatible with SDIO 2.0 Hosts -* - The following three functions are supported: -* - Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B) -* - Function 1 Backplane Function to access the internal SoC address space (max. BlockSize/ByteCount = 64B) -* - Function 2 WLAN Function for efficient WLAN packet transfer through DMA (max. BlockSize/ByteCount = 512B) -* - AHB Lite DMA capable Master -* - AHB Lite Slave for MMIO programming -* -* Host software uses Function 2 to Read and Write framed data from/to the sdio device. -* -* \section group_sdio_dev_more_information More Information -* For more information on the SDIO Device, refer to the technical reference manual (TRM). -* -* \section group_sdio_dev_MISRA MISRA-C Compliance -* The SDIO Device driver does not have any specific deviations. -* -* \section group_sdio_dev_Changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_sdio_dev_macros_general_purpose General Purpose Macros -* \defgroup group_sdio_dev_macros Macros -* \defgroup group_sdio_dev_functions Functions -* \defgroup group_sdio_dev_interrupt_functions Interrupt -* \defgroup group_sdio_dev_data_structures Data Structures -* \defgroup group_sdio_dev_enums Enumerated Types -*/ -#if !defined (CY_MXSDIODEV_H) -#define CY_MXSDIODEV_H - -#include "cy_device.h" - -#if defined (CY_IP_MXSDIODEV) - -#include -#include "cy_syslib.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_sdio_dev_macros_general_purpose -* \{ -*/ - -/** Driver major version */ -#define CY_SDIO_DEV_DRV_VERSION_MAJOR 1 - -/** Driver minor version */ -#define CY_SDIO_DEV_DRV_VERSION_MINOR 0 - -/** DMA Channel */ -#define MXSDIODEV_DMA_CHANNEL 0 - -/****************************************************************************** -* API Constants -******************************************************************************/ - -/** SDIO Device ID */ -#define CY_SDIO_DEV_ID (CY_PDL_DRV_ID(0x51U)) - -/** Manufacturer ID Size in tuples (2 bytes)*/ -#define CY_SDIO_DEV_MANFID_SIZE (3) - -/** Frame tag length */ -#define CY_SDIO_DEV_FRAMETAG_LEN (4) - -/* rx header flags */ -/** CRC error detected */ -#define RXF_CRC 0x0001 -/** write frame out of sync */ -#define RXF_WOOS 0x0002 -/** write frame terminated */ -#define RXF_WF_TERM 0x0004 -/** write frame aborted */ -#define RXF_ABORT 0x0008 -/** bad frame */ -#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) - -/** -* \defgroup group_sdio_dev_macros_callback_events SDIO Device Callback Events -* \{ -* Macros to check SDIO events passed by \ref cy_cb_sdio_dev_handle_events_t callback. -* Each event is encoded in a separate bit, and therefore it is possible to -* notify about multiple events. -*/ - -/** -* Indicates the slave read packet from master -*/ -#define CY_SDIO_DEV_RECEIVE_CMPLT_EVENT (0x00000010UL) - -/** -* Indicates the slave transmitted packet -*/ -#define CY_SDIO_DEV_TRANSMIT_CMPLT_EVENT (0x00000020UL) - -/** -* Indicates the receive packet error -*/ -#define CY_SDIO_DEV_RECEIVE_PKT_ERROR (0x00000030UL) - -/** \} group_sdio_dev_macros_callback_events */ - -/** \cond INTERNAL */ - -#define CY_SDIO_DEV_RETRY_TIME (1000UL) /* The number loops to make the timeout in msec. */ -#define CY_SDIO_DEV_TIMEOUT_MS (3U) /* The Command complete timeout. */ - -/* Interrupt Status */ -#define I_ERRORS (MXSDIO_INTSTATUS_DESCERR_Msk | \ - MXSDIO_INTSTATUS_RCVDESCUF_Msk | \ - MXSDIO_INTSTATUS_RCVFIFOOF_Msk | \ - MXSDIO_INTSTATUS_XMTFIFOUF_Msk) /** DMA Errors */ - -/* Default Interrupt mask */ -#define DEF_INTMASK (I_ERRORS | \ - MXSDIO_INTSTATUS_TOSBMAIL_Msk | \ - MXSDIO_INTSTATUS_RCVINT_Msk | \ - MXSDIO_INTSTATUS_XMTINT_Msk | \ - MXSDIO_INTSTATUS_RDOUTOFSYNC_Msk) - -#define DEF_SDIO_INTMASK (DEF_INTMASK | \ - MXSDIO_INTSTATUS_SRESET_Msk | \ - MXSDIO_INTSTATUS_IOE2CHANGE_Msk) - -/* tohostmailbox bits corresponding to intstatus bits */ -#define HMB_INT_ACK (1 << 0) /* To Host Mailbox Dev Interrupt ACK */ -#define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ -#define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ -#define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ - -/* Descriptor control flags 1 */ -#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ -#define D64_CTRL1_NOTPCIE ((uint32)1 << 18) /* buirst size control */ -#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */ -#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */ -#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */ -#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */ - -/* Descriptor control flags 2 */ -#define D64_CTRL2_BC_USABLE_MASK 0x00003fff /* buffer byte count. real data len must <= 16KB */ -#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ -#define D64_CTRL2_AE 0x00030000 /* address extension bits */ -#define D64_CTRL2_AE_SHIFT 16 -#define D64_CTRL2_PARITY 0x00040000 /* parity bit */ - -/** \endcond */ - -/** \endcond */ - -/** \} group_sdio_dev_macros_general_purpose */ - -/** -* \addtogroup group_sdio_dev_enums -* \{ -*/ - -/****************************************************************************** - * Enumerations - *****************************************************************************/ - -/** SDIO Device error codes. */ -typedef enum -{ - CY_SDIO_DEV_SUCCESS = 0U, /**< Successful. */ - CY_SDIO_DEV_ERROR = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 1U, /**< Non-specific error code. */ - CY_SDIO_DEV_ERROR_INVALID_PARAMETER = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 2U, /**< The provided parameter is not valid. */ - CY_SDIO_DEV_ERROR_OPERATION_IN_PROGRESS = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 3U, /**< A conflicting or requested operation is still in progress. */ - CY_SDIO_DEV_ERROR_UNINITIALIZED = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 4U, /**< The module (or part of it) was not initialized properly. */ - CY_SDIO_DEV_ERROR_TIMEOUT = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 5U, /**< A Time Out error occurred */ - CY_SDIO_DEV_OPERATION_INPROGRESS = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 6U, /**< The indicator for operation in progress. */ - CY_SDIO_DEV_ERROR_UNUSABLE_CARD = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 7U, /**< The card is unusable. */ - CY_SDIO_DEV_ERROR_DISCONNECTED = CY_SDIO_DEV_ID | CY_PDL_STATUS_ERROR | 8U /**< The card is disconnected. */ -} cy_en_sdio_dev_status_t; - -/** DMA transmit state. */ -typedef enum -{ - CY_SDIO_DEV_XS_DISABLED, /**< disabled */ - CY_SDIO_DEV_XS_ACTIVE, /**< active */ - CY_SDIO_DEV_XS_IDLE, /**< idle wait */ - CY_SDIO_DEV_XS_STOPPED, /**< stopped */ - CY_SDIO_DEV_XS_SUSP /**< suspend pending */ -} cy_en_sdio_dev_transmit_state_t; - -/** DMA receive state. */ -typedef enum -{ - CY_SDIO_DEV_RS_DISABLED, /**< disabled */ - CY_SDIO_DEV_RS_ACTIVE, /**< active */ - CY_SDIO_DEV_RS_IDLE, /**< idle wait */ - CY_SDIO_DEV_RS_STOPPED, /**< stopped */ - CY_SDIO_DEV_RS_SUSP /**< suspend pending */ -} cy_en_sdio_dev_receive_state_t; - -/** SDIO Device Manufacturer ID configuration. */ -typedef enum -{ - CY_SDIO_DEV_USE_DEFAULT_MANF_ID = 0U, /**< Use default manufacturer ID from CIS area. */ - CY_SDIO_DEV_USER_PROVIDED_MANF_ID = 1U, /**< Use user provided manufacture ID from config structure. */ -} cy_en_sdio_dev_manf_id_config_t; - -/** SDIO Device VERSION */ -typedef enum -{ - CY_SDIO_DEV_VERSION_3_0 = 0U, /**< Use SDIO Version 3.0. */ - CY_SDIO_DEV_VERSION_2_0 = 1U, /**< Use SDIO Version 2.0. */ -} cy_en_sdio_dev_ver_config_t; - -/** SDIO Device Block Size */ -typedef enum -{ - CY_SDIO_DEV_BLK_SIZE_512 = 0U, /**< Use F2 Block Size as 512 bytes. */ - CY_SDIO_DEV_BLK_SIZE_256 = 1U, /**< Use F2 Block Size as 256 bytes. */ - CY_SDIO_DEV_BLK_SIZE_128 = 2U, /**< Use F2 Block Size as 128 bytes. */ - CY_SDIO_DEV_BLK_SIZE_64 = 3U, /**< Use F2 Block Size as 64 bytes. */ -} cy_en_sdio_dev_blk_size_config_t; - -/** SDIO Device Max Speed */ -typedef enum -{ - CY_SDIO_DEV_SDR12 = 0U, /**< SDR12 - Max Clock Frequency 25 Mhz. */ - CY_SDIO_DEV_SDR25 = 1U, /**< SDR25 - Max Clock Frequency 50 Mhz. */ - CY_SDIO_DEV_SDR50 = 2U, /**< SDR50 - Max Clock Frequency 100 Mhz. */ - CY_SDIO_DEV_SDR104 = 3U, /**< SDR104 - Max Clock Frequency 208 Mhz. */ - CY_SDIO_DEV_DDR50 = 4U, /**< DDR50 - Max Clock Frequency 50 Mhz. */ -} cy_en_sdio_dev_max_speed_config_t; - -/** \} group_sdio_dev_enums */ - -/** -* \addtogroup group_sdio_dev_data_structures -* \{ -*/ - -/** -* Provides the typedef for the callback function called in the -* \ref Cy_SDIO_DEV_Interrupt to notify the user about occurrences of -* \ref group_sdio_dev_macros_callback_events. -*/ -typedef void (* cy_cb_sdio_dev_handle_events_t)(uint32_t event); - -/** \} group_sdio_dev_data_structures */ - -/****************************************************************************** - * Structures - *****************************************************************************/ - -/** SDIO Device configuration structure. */ -typedef struct -{ - cy_en_sdio_dev_ver_config_t version; /**< SDIO protocol version supported. */ - cy_en_sdio_dev_manf_id_config_t use_default_manfid; /**< SDIO Device manufacturer ID configuration. If this field is set to - CY_SDIO_DEV_USER_PROVIDED_MANF_ID, SDIO Device uses user provided - manufaturer ID using manfid field. Otherwise, default manufacturer ID. */ - uint32_t manfid[CY_SDIO_DEV_MANFID_SIZE]; /**< 6 bytes or 3 tuples of user provided manufacturer ID. This will be used - only when use_default_manfid is set to CY_SDIO_DEV_USER_PROVIDED_MANF_ID */ - cy_en_sdio_dev_blk_size_config_t blk_size; /**< This field specifies the block size user for function 2 data transferes. - Minimum value is CY_SDIO_DEV_BLK_SIZE_64 and Maximum value CY_SDIO_DEV_BLK_SIZE_512. */ - cy_en_sdio_dev_max_speed_config_t max_speed_config; /**< This field specifies maximum speed configuration allowed for this SDIO device. - Minimum value is CY_SDIO_DEV_SDR12 and Maximum value CY_SDIO_DEV_DDR50. */ -} cy_stc_sdio_dev_config_t; - -/** \cond INTERNAL */ - -/** Context structure. */ -typedef struct -{ - cy_en_sdio_dev_max_speed_config_t current_speed_config; /**< Max speed configuration set */ - cy_en_sdio_dev_blk_size_config_t current_blk_size; /**< Minimum value is 1 and Maximum value for F2 supported is 512. */ - cy_cb_sdio_dev_handle_events_t cbEvents; - uint8_t *rx_buffer; - uint32_t max_rx_buf_len; - uint8_t *tx_buffer; - uint32_t tx_buf_len; -} cy_stc_sdio_dev_context_t; - -/** - * DMA Descriptor - * Descriptors are only read by the hardware, never written back. - */ -typedef volatile struct { - uint32_t ctrl1; /**< misc control bits */ - uint32_t ctrl2; /**< buffer count and address extension */ - uint32_t addrlow; /**< memory address of the date buffer, bits 31:0 */ - uint32_t addrhigh; /**< memory address of the date buffer, bits 63:32 */ -} cy_stc_sdio_dev_dma_descr_t; - -/* Receive Frame Status Header */ -typedef volatile struct { - uint16 len; - uint16 flags; -} cy_stc_sdio_dev_rx_header_t; - -/** \endcond */ - - -/** -* \addtogroup group_sdio_dev_functions -* \{ -*/ - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Init -****************************************************************************//** -* -* This API will initialise MXSDIO IP with the configuration parameters -* -* \param base -* The pointer to a MXSDIODEV instance. -* -* \param *config -* The pointer to the MXSDIO device configuration structure. -* -* \param context -* The pointer to the context structure \ref cy_stc_sdio_dev_context_t allocated -* by the user. The structure is used during the SDIO device operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* If using only the SDIO device functions which do not require context, pass NULL -* as the pointer to the context. -* -* \return \ref cy_en_sdio_dev_status_t -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Init(MXSDIO_Type *base, cy_stc_sdio_dev_config_t const *config, cy_stc_sdio_dev_context_t *context); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_DeInit -****************************************************************************//** -* -* Restores the MXSDIO block registers back to default. -* -* \param *base -* The pointer to a MXSDIODEV instance. -* -*******************************************************************************/ -void Cy_SDIO_DEV_DeInit(MXSDIO_Type *base); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Enable -****************************************************************************//** -* -* This API will enable MXSDIODEV IP and allow TX and RX operations -* -* \param base -* The pointer to a MXSDIODEV instance. -* -* \funcusage -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Enable(MXSDIO_Type *base); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Disable -****************************************************************************//** -* -* Disables the MXSDIODEV IP from its operation. -* -* \param base -* The pointer to a MXSDIODEV instance. -* -* \funcusage -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Disable(MXSDIO_Type *base); - -/******************************************************************************* -* Function Name: Cy_SD_Host_GetSdStatus -****************************************************************************//** -* -* Returns the SDIO status from the MXSDIO block. -* -* \param *base -* The pointer to a MXSDIODEV instance. -* -* \param *sdStatus -* The pointer to store the status of MXSDIO Function 2 -* -* \return \ref cy_en_sd_host_status_t -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_GetStatus(MXSDIO_Type const *base, bool *sdStatus); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_ConfigReadBuf -****************************************************************************//** -* -* Returns the SDIO status from the MXSDIO block. -* -* \param *base -* The pointer to a MXSDIODEV instance. -* -* \param *buffer -* *buffer -* -* \param *context -* *context -* -* \param size -* size -* -* \return \ref cy_en_sd_host_status_t -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_ConfigReadBuf(MXSDIO_Type const *base, uint8_t *buffer, uint32_t size, cy_stc_sdio_dev_context_t *context); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Interrupt -****************************************************************************//** -* -* The Interrupt Service Routine for the MXSDIO. The interrupt code will be -* responsible for the DMA operations on DMA interrupts during ongoing transfers. -* The user must place a call to this interrupt function in the interrupt -* routine corresponding to the interrupt attached to the MXSDIO. If the -* user does not do this, will break: the functionality of all the API functions in -* the MXSDIO driver that use MXSDIO interrupts to affect transfers. -* -* \param base -* The pointer to a MXSDIODEV instance. -* -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* MXSDIODEV block. -* -*******************************************************************************/ -void Cy_SDIO_DEV_Interrupt(MXSDIO_Type *base, cy_stc_sdio_dev_context_t *context); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_RegisterEventCallback -****************************************************************************//** -* -* Registers a callback function that notifies that -* \ref group_sdio_dev_macros_callback_events occurred in the -* \ref Cy_SDIO_DEV_Interrupt. -* -* \param base -* The pointer to the MXSDIO instance. -* -* \param callback -* The pointer to a callback function. -* See \ref cy_cb_sdio_dev_handle_events_t for the function prototype. -* -* \param context -* The pointer to context structure \ref cy_stc_sdio_dev_context_t allocated by -* the user. The structure is used while the SDIO Device operation for internal -* configuration and data retention. The user should not modify anything in -* this structure. -* -* \note -* To remove the callback, pass NULL as the pointer to the callback function. -* -*******************************************************************************/ -void Cy_SDIO_DEV_RegisterEventCallback(MXSDIO_Type const *base, cy_cb_sdio_dev_handle_events_t callback, cy_stc_sdio_dev_context_t *context); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Transmit_Buffer -****************************************************************************//** -* -* This function is used to transmit data over SDIO interface. This -* function uses the internal DMA to implement the transmit functionality. The -* function sets up an interrupt to trigger the Transmit completion event and at the -* end of the transmission, the callback \ref cy_cb_sdio_dev_handle_events_t is executed. -* -* \param base -* Holds the base address of the SMIF block registers. -* -* \param buffer -* The pointer to the data to be transferred. First 4 bytes of the buffer -* should be reserved for frame header and actual buffer to be transferredIf -* should start from fifth byte. If this pointer is a NULL, then the -* function returns CY_SDIO_DEV_ERROR. -* -* \param size -* The size of buffer. Must be > 0 and not greater than 65527. -* -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* MXSDIO_Type block. -* -* \return A status of a transmission. -* - \ref CY_SDIO_DEV_SUCCESS -* - \ref CY_SDIO_DEV_ERROR -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Transmit_Buffer(MXSDIO_Type const *base, uint8_t *buffer, uint16_t size, cy_stc_sdio_dev_context_t *context); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Transmit_Buffer -****************************************************************************//** -* -* This function is used to transmit data over SDIO interface. This -* function uses the internal DMA to implement the transmit functionality. The -* function blocks until the buffer gets transmitted and return to caller. -* -* \param base -* Holds the base address of the SMIF block registers. -* -* \param buffer -* The pointer to the data to be transferred. First 4 bytes of the buffer -* should be reserved for frame header and actual buffer to be transferredIf -* should start from fifth byte. If this pointer is a NULL, then the -* function returns CY_SDIO_DEV_ERROR. -* -* \param buf_len buf_len -* -* \return A status of a transmission. -* - \ref CY_SDIO_DEV_SUCCESS -* - \ref CY_SDIO_DEV_ERROR -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Transmit_Buffer_Blocking(MXSDIO_Type const *base, uint8_t *buffer, uint16_t buf_len); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Receive_Buffer -****************************************************************************//** -* -* This function is used to receive data over SDIO interface. This -* function uses the internal DMA to implement the receive functionality. The -* function sets up an interrupt to trigger the receive completion event and at the -* end of the reception, the callback \ref cy_cb_sdio_dev_handle_events_t is executed. -* -* \param base -* Holds the base address of the SMIF block registers. -* -* \param context -* Passes a configuration structure that contains the transfer parameters of the -* MXSDIO_Type block. -* -* \return A status of a transmission. -* - \ref CY_SDIO_DEV_SUCCESS -* - \ref CY_SDIO_DEV_ERROR -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Receive_Buffer(MXSDIO_Type const *base, cy_stc_sdio_dev_context_t *context); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_Receive_Buffer_Blocking -****************************************************************************//** -* -* This function is used to receive data over SDIO interface. This -* function uses the internal DMA to implement the receive functionality. The -* function blocks until the buffer received and return to caller. -* -* \param base -* Holds the base address of the SMIF block registers. -* -* \param buffer -* The pointer to the data received. If this pointer is a NULL, then the -* function returns CY_SDIO_DEV_ERROR. -* -* \param buf_len -* buf_len -* -* \return A status of a transmission. -* - \ref CY_SDIO_DEV_SUCCESS -* - \ref CY_SDIO_DEV_ERROR -* -*******************************************************************************/ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Receive_Buffer_Blocking(MXSDIO_Type const *base, char **buffer, uint32_t *buf_len); - -/** \} group_sdio_dev_functions */ - -/** -* \addtogroup group_sdio_dev_interrupt_functions -* \{ -*/ -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_GetInterruptStatus -****************************************************************************//** -* -* This function gets the interrupt status information from interrupt status register -* -* \param base -* Holds the base address of the MXSDIO block registers. -* -* \return Returns the interrupt status. -* -*******************************************************************************/ -uint32_t Cy_SDIO_DEV_GetInterruptStatus(MXSDIO_Type const *base); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_ClearInterrupt -****************************************************************************//** -* -* Clears the selected MXSDIO interrupt status. -* -* \param *base -* Holds the base address of the MXSDIO block registers. -* -* \param status -* The bitmask of statuses to clear. -* -*******************************************************************************/ -void Cy_SDIO_DEV_ClearInterruptStatus(MXSDIO_Type const *base, uint32_t status); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_GetInterruptMask -****************************************************************************//** -* -* Returns which interrupts are masked to cause an interrupt. -* -* \param *base -* Holds the base address of the MXSDIO block registers. -* -* \return uint32_t -* The Bit field of which interrupts are masked to cause an interrupt. -* -*******************************************************************************/ -uint32_t Cy_SDIO_DEV_GetInterruptMask(MXSDIO_Type const *base); - -/******************************************************************************* -* Function Name: Cy_SDIO_DEV_SetInterruptMask -****************************************************************************//** -* -* Setting a bit in this register allows the enabled status to cause an interrupt. -* -* \param *base -* Holds the base address of the MXSDIO block registers. -* -* \param interrupt -* The Bit field of which interrupts can cause an interrupt. -* -*******************************************************************************/ -void Cy_SDIO_DEV_SetInterruptMask(MXSDIO_Type const *base, uint32_t interrupt); - -/** \} group_sdio_dev_interrupt_functions */ - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_MXSDIODEV_H */ - -#endif /* CY_IP_MXSDIODEV */ -/** \} group_sdio_dev */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_pd_ppu.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_pd_ppu.h deleted file mode 100644 index 5572ae6a9e..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_pd_ppu.h +++ /dev/null @@ -1,97 +0,0 @@ -/***************************************************************************//** -* \file cy_pd_ppu.h -* \version 1.0 -* -* This file provides the header for ARM PPU Platform PD specific driver -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_pd_ppu -* \{ -* PD PPU driver is a platform dependant driver on top of ARM PPU Driver -* -* The functions and other declarations used in this driver are in cy_pd_ppu.h. -* -* You can use this driver to implement the platform dependant code to -* control power domainusing PPU -* -* \section group_pd_ppu_more_information More Information -* -* For more information on the PD PPU , refer to -* the technical reference manual (TRM). -* -* \section group_pd_ppu_MISRA MISRA-C Compliance -* The PD PPU driver does not have any specific deviations. -* -* \section group_pd_ppu_changelog Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_pd_ppu_macros Macros -* \defgroup group_pd_ppu_functions Functions -* \defgroup group_pd_ppu_data_structures Data Structures -* \defgroup group_pd_ppu_enums Enumerated Types -*/ -/** \} group_pd_ppu */ - -#ifndef CY_PD_PPU_H -#define CY_PD_PPU_H - -#include -#include "ppu_v1.h" -#include "cy_pdl.h" - - -/******************************************************************************* -* Enumerated Types -*******************************************************************************/ - -/** -* \addtogroup group_pd_ppu_enums -* \{ -*/ -/** Defines general-purpose function return values */ -typedef enum -{ - CY_PD_PPU_SUCCESS = 0x00UL, /**< Command completed with no errors */ - CY_PD_PPU_BAD_PARAM = 0x01UL, /**< Invalid function input parameter */ - CY_PD_PPU_TIMEOUT = 0x02UL, /**< Timeout occurred */ - CY_PD_PPU_INVALID_STATE = 0x03UL, /**< Clock is in an invalid state */ - CY_PD_PPU_ERROR = 0x04UL /**< Error */ -} cy_pd_ppu_status_t; -/** \} group_pd_ppu_enums */ - -/** -* \addtogroup group_pd_ppu_functions -* \{ -*/ -cy_pd_ppu_status_t cy_pd_ppu_init(struct ppu_v1_reg *ppu); -cy_pd_ppu_status_t cy_pd_ppu_get_power_mode(struct ppu_v1_reg *ppu, uint32_t *mode); -cy_pd_ppu_status_t cy_pd_ppu_set_power_mode(struct ppu_v1_reg *ppu, uint32_t mode); -cy_pd_ppu_status_t cy_pd_ppu_reset(struct ppu_v1_reg *ppu); -/** \} group_pd_ppu_functions */ - -#endif /* CY_PD_PPU_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_pdm_pcm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_pdm_pcm_v2.h deleted file mode 100644 index 2f89d80637..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_pdm_pcm_v2.h +++ /dev/null @@ -1,1001 +0,0 @@ -/***************************************************************************//** -* \file cy_pdm_pcm_v2.h -* \version 1.0 -* -* The header file of the PDM_PCM driver. -* -******************************************************************************** -* \copyright -* Copyright 2019-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_pdm_pcm_v2 -* \{ -* -* The pulse-density modulation to pulse-code modulation (PDM-PCM) driver provides an -* API to manage PDM-PCM conversion. A PDM-PCM converter is used -* to convert 1-bit digital audio streaming data to PCM data. -* -* The functions and other declarations used in this driver are in cy_pdm_pcm.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* Features: -* - Supports up to 8 PDM receivers -* - Supports Stereo/Mono dual mode PDM (pulse-density-modulated) to PCM (pulse-code-modulated) conversion -* - Half rate sampling to reduce system power consumption -* - CIC filter, FIR filter, DC block filter signal processing path -* - Programmable interface clock -* - Programmable FIR filter coefficients -* - Programmable CIC and FIR filter decimation -* - Programmable DC blocking coefficient -* - Programmable PCM word size (8, 10, 12, 14, 16, 18, 20, 24, 32 bits) -* - Programmable sampling delay, to cope with different master-slavemaster roundtrip delays -* - 64 entry RX FIFO with interrupt and trigger support -* - Debug/freeze trigger support -* - Receiver activate trigger support -* - Test mode support, the IP includes a programmable PDM pattern generator -* - Area efficient datapath implementation, with SRAMs, FIR filter, DC blocking filter logic shared by all receivers -* - "Does this IP block affect overall chip performance?" YES (The PDM interfaces are chip external interfaces) -* - Is this block critical to Chip Integration? NO -* - Is the block intended for use in a single product?" NO -* -* Pulse-density modulation, or PDM, represents -* an analog signal with a binary signal. In a PDM signal, specific amplitude values -* are not encoded into codewords of pulses of different weight as they would be -* in pulse-code modulation (PCM); rather, the relative density of the pulses corresponds -* to the analog signal's amplitude. The output of a 1-bit DAC is the same -* as the PDM encoding of the signal. -* -* Pulse-code modulation (PCM) is the method used to digitally represent sampled analog signals. -* It is the standard form of digital audio in computers, compact discs, digital telephony, -* and other digital audio applications. In a PCM stream, the amplitude of the analog signal -* is sampled regularly at uniform intervals, and each sample is quantized -* to the nearest value within a range of digital steps. -* -* \section group_pdm_pcm_configuration_considerations_v2 Configuration Considerations -* -* To set up a PDM-PCM, provide the configuration parameters in the -* \ref cy_stc_pdm_pcm_config_v2_t structure. -* -* For example, set dataStreamingEnable to true, configure rxFifoTriggerLevel, -* dmaTriggerEnable (depending on whether DMA is going to be used), -* provide clock settings (clkDiv, mclkDiv and ckoDiv), set sincDecRate -* to the appropriate decimation rate, wordLen, and wordBitExtension. -* No other parameters are necessary for this example. -* -* To initialize the PDM-PCM channels, call \ref Cy_PDM_PCM_Channel_Init function, providing the -* filled \ref cy_stc_pdm_pcm_channel_config_t structure -* To initialize the PDM-PCM block, call the \ref Cy_PDM_PCM_Init function, providing the -* filled \ref cy_stc_pdm_pcm_config_v2_t structure. -* -* If you use a DMA, the DMA channel should be previously configured. PDM-PCM interrupts -* (if applicable) can be enabled by calling \ref Cy_PDM_PCM_SetInterruptMask. -* -* For example, if the trigger interrupt is used during operation, the ISR -* should call the \ref Cy_PDM_PCM_ReadFifo as many times as required for your -* FIFO payload. Then call \ref Cy_PDM_PCM_Channel_ClearInterrupt with appropriate parameters. -* -* If a DMA is used and the DMA channel is properly configured, no CPU activity -* (or application code) is needed for PDM-PCM operation. -* -* \section group_pdm_pcm_more_information_v2 More Information -* See: the PDM-PCM chapter of the device technical reference manual (TRM); -* the PDM_PCM_PDL Component datasheet; -* -* \section group_pdm_pcm_MISRA_v2 MISRA-C Compliance -* The PDM-PCM driver has the following specific deviations: -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
-* -* \section group_pdm_pcm_changelog_v2 Changelog -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* -* \defgroup group_pdm_pcm_macros_v2 Macros -* \defgroup group_pdm_pcm_functions_v2 Functions -* \defgroup group_pdm_pcm_data_structures_v2 Data Structures -* \defgroup group_pdm_pcm_enums_v2 Enumerated Types -* -*/ - -#if !defined (CY_PDM_PCM_V2_H__) -#define CY_PDM_PCM_V2_H__ - -/******************************************************************************/ -/* Include files */ -/******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXPDM) - -#include "cy_syslib.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -/****************************************************************************** - * Global definitions - ******************************************************************************/ - -/* Macros */ -/** -* \addtogroup group_pdm_pcm_macros_v2 -* \{ -*/ - -/** The driver major version */ -#define CY_PDM_PCM_DRV_VERSION_MAJOR 1 - -/** The driver minor version */ -#define CY_PDM_PCM_DRV_VERSION_MINOR 0 - -/** The PDM-PCM driver identifier */ -#define CY_PDM_PCM_ID CY_PDL_DRV_ID(0x26u) - -/** -* \defgroup group_pdm_pcm_macros_interrupt_masks_v2 Interrupt Masks -* \{ -*/ - -/** More entries in the RX FIFO than specified by Trigger Level. */ -#define CY_PDM_PCM_INTR_RX_TRIGGER (PDM_CH_INTR_RX_FIFO_TRIGGER_Msk) -/** Attempt to write to a full RX FIFO. */ -#define CY_PDM_PCM_INTR_RX_OVERFLOW (PDM_CH_INTR_RX_FIFO_OVERFLOW_Msk) -/** Attempt to read from an empty RX FIFO. */ -#define CY_PDM_PCM_INTR_RX_UNDERFLOW (PDM_CH_INTR_RX_FIFO_UNDERFLOW_Msk) -/** CIC filter PCM samples are produced at a faster rate than the FIR filter can process them */ -#define CY_PDM_PCM_INTR_RX_FIR_OVERFLOW (PDM_CH_INTR_RX_FIR_OVERFLOW_Msk) -/** when PDM samples are generated too fast */ -#define CY_PDM_PCM_INTR_RX_IF_OVERFLOW (PDM_CH_INTR_RX_IF_OVERFLOW_Msk) - -/** \} group_pdm_pcm_macros_interrupt_masks_v2 */ - -/** \} group_pdm_pcm_macros_v2 */ - -/** -* \addtogroup group_pdm_pcm_enums_v2 -* \{ -*/ - -/** PDM Word Length. */ -typedef enum -{ - CY_PDM_PCM_WSIZE_8_BIT = 0U, /**< Word length: 8 bit. */ - CY_PDM_PCM_WSIZE_10_BIT = 1U, /**< Word length: 10 bit. */ - CY_PDM_PCM_WSIZE_12_BIT = 2U, /**< Word length: 12 bit. */ - CY_PDM_PCM_WSIZE_14_BIT = 3U, /**< Word length: 14 bit. */ - CY_PDM_PCM_WSIZE_16_BIT = 4U, /**< Word length: 16 bit. */ - CY_PDM_PCM_WSIZE_18_BIT = 5U, /**< Word length: 18 bit. */ - CY_PDM_PCM_WSIZE_20_BIT = 6U, /**< Word length: 20 bit. */ - CY_PDM_PCM_WSIZE_24_BIT = 7U, /**< Word length: 24 bit. */ - CY_PDM_PCM_WSIZE_32_BIT = 8U /**< Word length: 32 bit. */ -} cy_en_pdm_pcm_word_size_t; - -/** cy_en_pdm_pcm_clock_sel_t. */ -typedef enum -{ - CY_PDM_PCM_SEL_SRSS_CLOCK = 0U, /* Interface clock is selected as clk_if_srss[0]. */ - CY_PDM_PCM_SEL_PDM_DATA0 = 1U, /* Interface clock is selected as pdm_data[0]. */ - CY_PDM_PCM_SEL_PDM_DATA1 = 2U, /* Interface clock is selected as pdm_data[1]. */ - CY_PDM_PCM_SEL_OFF = 3U /* Interface clock clk_if is off. */ -} cy_en_pdm_pcm_clock_sel_t; - -/** PDM Halve Rate Sampling. */ -typedef enum -{ - CY_PDM_PCM_RATE_FULL = 0U, /**< Channel full. */ - CY_PDM_PCM_RATE_HALVE = 1U /**< Channel halve. */ -} cy_en_pdm_pcm_halve_rate_sel_t; - -/** CIC DECIM CODE. */ -typedef enum -{ - CY_PDM_PCM_CHAN_CIC_DECIM_2 = 0U, /**< CIC Filter PCM Frequency is 1/2 * PDM Frequency. */ - CY_PDM_PCM_CHAN_CIC_DECIM_4 = 1U, /**< CIC Filter PCM Frequency is 1/4 * PDM Frequency. */ - CY_PDM_PCM_CHAN_CIC_DECIM_8 = 2U, /**< CIC Filter PCM Frequency is 1/8 * PDM Frequency. */ - CY_PDM_PCM_CHAN_CIC_DECIM_16 = 3U, /**< CIC Filter PCM Frequency is 1/16 * PDM Frequency. */ - CY_PDM_PCM_CHAN_CIC_DECIM_32 = 4U /**< CIC Filter PCM Frequency is 1/32 * PDM Frequency. */ -} cy_en_pdm_pcm_ch_cic_decimcode_t; - -/** FIR0 DECIM CODE. */ -typedef enum -{ - CY_PDM_PCM_CHAN_FIR0_DECIM_1 = 0U, /**< FIR0 Filter PCM Frequency is 1/1 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR0_DECIM_2 = 1U, /**< FIR0 Filter PCM Frequency is 1/2 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR0_DECIM_3 = 2U, /**< FIR0 Filter PCM Frequency is 1/3 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR0_DECIM_4 = 3U, /**< FIR0 Filter PCM Frequency is 1/4 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR0_DECIM_5 = 4U /**< FIR0 Filter PCM Frequency is 1/5 * PCM Frequency. */ -} cy_en_pdm_pcm_ch_fir0_decimcode_t; - -/** FIR1 DECIM CODE. */ -typedef enum -{ - CY_PDM_PCM_CHAN_FIR1_DECIM_1 = 0U, /**< FIR1 Filter PCM Frequency is 1/1 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR1_DECIM_2 = 1U, /**< FIR1 Filter PCM Frequency is 1/2 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR1_DECIM_3 = 2U, /**< FIR1 Filter PCM Frequency is 1/3 * PCM Frequency. */ - CY_PDM_PCM_CHAN_FIR1_DECIM_4 = 3U, /**< FIR1 Filter PCM Frequency is 1/4 * PCM Frequency. */ -} cy_en_pdm_pcm_ch_fir1_decimcode_t; - -/** DC Block CODE. */ -typedef enum -{ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_1 = 0U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-0)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_2 = 1U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-1)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_4 = 2U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-2)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_8 = 3U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-3)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_16 = 4U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-4)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_32 = 5U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-5)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_64 = 6U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-6)). */ - CY_PDM_PCM_CHAN_DCBLOCK_CODE_128 = 7U, /**< DCBLOCK Filter alpha = 1 - (1/2^(12-7)). */ -} cy_en_pdm_pcm_ch_dcblock_coef_t; - -/** \cond INTERNAL */ -/** PDM Output Mode. */ -typedef enum -{ - CY_PDM_PCM_OUT_CHAN_LEFT = 1U, /**< Channel mono left. */ - CY_PDM_PCM_OUT_CHAN_RIGHT = 2U, /**< Channel mono right. */ - CY_PDM_PCM_OUT_STEREO = 3U /**< Channel stereo. */ -} cy_en_pdm_pcm_out_t; -/** \endcond */ - -/** \cond INTERNAL */ -/** The PDM-PCM status codes. */ -typedef enum -{ - CY_PDM_PCM_SUCCESS = 0x00UL, /**< Success status code */ - CY_PDM_PCM_BAD_PARAM = CY_PDM_PCM_ID | CY_PDL_STATUS_ERROR |0x01UL /**< Bad parameter status code */ -} cy_en_pdm_pcm_status_t; -/** \endcond */ - -/** \} group_pdm_pcm_enums_v2 */ - - -/** -* \addtogroup group_pdm_pcm_data_structures_v2 -* \{ -*/ - -/****************************************************************************** - * Global type definitions - ******************************************************************************/ - - /** PDM-PCM Test Mode configuration */ - typedef struct - { - uint8_t drive_delay_hi; /**< Interface drive delay on the low phase of the PDM interface clock. - This field specifies when a PDM value is driven expressed in clk_if clock cycles. - DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: - "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. - "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. - ... - "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm. */ - uint8_t drive_delay_lo; /**< Interface drive delay on the low phase of the PDM interface clock. - This field specifies when a PDM value is driven expressed in clk_if clock cycles. - DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: - "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. - "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. - ... - "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm. */ - uint8_t mode_hi; /**< Pattern generator mode on the low phase of the PDM interface clock. - This field specifies the type of pattern driven by the generator: - "0": constant 0's - "1": constant 1's - "2": alternating 0's and 1's (clock pattern) - "3": sine wave */ - uint8_t mode_lo; /**< Pattern generator mode on the low phase of the PDM interface clock. - This field specifies the type of pattern driven by the generator: - "0": constant 0's - "1": constant 1's - "2": alternating 0's and 1's (clock pattern) - "3": sine wave */ - uint8_t audio_freq_div; /**< Frequency division factor (legal range [3, 13]) to obtain audio frequency - from the PDM clock frequency. This field determines the frequency of the sine wave - generated by the pattern generator when MODE=3. The formula is below: - Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV) */ - bool enable; /**< enable. */ - - - }cy_stc_test_config_t; - - /** PDM-PCM fir coeff_data structure */ - typedef struct - { - - int16_t coeff_data0; /**< The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients - (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7. - The FIR filter coefficients have no default values: - the coefficients MUST be programmed BEFORE the filter is enabled. */ - int16_t coeff_data1; /**< coeff_data1. */ - }cy_stc_pdm_pcm_fir_coeff_t; - - /** PDM-PCM Channel initialization configuration */ - typedef struct - { - uint8_t sampledelay; /**< Interface sample delay. This field specifies when a PDM value is captured, - expressed in clk_if clock cycles.SAMPLE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV].*/ - - cy_en_pdm_pcm_word_size_t wordSize; /**< see #cy_en_pdm_pcm_word_size_t */ - bool signExtension; /**< Word extension type: - - 0: extension by zero - - 1: extension by sign bits */ - - uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words), - range: 0 - 63 */ - - bool fir0_enable; /**< FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation): - '0': Disabled. The middle FIR filter coefficient (16th coefficient, or tap 15 in [0:29] range) is "1" and - all other FIR filter coefficients are "0"; i.e. the FIR filter is a pass through filter and the filter gain is "1". - fir0_pcm[44:0] = cic_pcm[25:0] (with sign extension)'1': Enabled. - This filter is disabled by default, and typically only used for sample frequencies (Fs) of 8 and 16 kHz. */ - - - cy_en_pdm_pcm_ch_cic_decimcode_t cic_decim_code; /**< CIC filter decimation. The CIC filter PCM frequency is a fraction of the PDM frequency: - "0": CIC filter PCM frequency is 1/2 * PDM frequency. CIC PCM values are in the range [-0x10, 0x10]. - "1": CIC filter PCM frequency is 1/4 * PDM frequency. CIC PCM values are in the range [-0x200, 0x200]. - "2": CIC filter PCM frequency is 1/8 * PDM frequency. CIC PCM values are in the range [-0x4000, 0x4000]. - "3": CIC filter PCM frequency is 1/16 * PDM frequency. CIC PCM values are in the range [-0x8:0000, 0x8:0000]. - "4": CIC filter PCM frequency is 1/32 * PDM frequency. CIC PCM values are in the range [-0x100:0000, 0x100:0000]. - "5"-"7": Illegal values. */ - - cy_en_pdm_pcm_ch_fir0_decimcode_t fir0_decim_code;/**< FIR filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency: - "0": FIR 0 filter PCM frequency is 1 * CIC filter PCM frequency. - "1": FIR 0 filter PCM frequency is 1/2 * CIC filter PCM frequency. - "2": FIR 0 filter PCM frequency is 1/3 * CIC filter PCM frequency. - "3": FIR 0 filter PCM frequency is 1/4 * CIC filter PCM frequency. - "4": FIR 0 filter PCM frequency is 1/5 * CIC filter PCM frequency. */ - - uint8_t fir0_scale; /**< FIR 0 filter PCM scaling. FIR 0 filter PCM values (fir0_pcm[44:0]) are scaled (right shifted, rounded and clipped) - to 26-bit signed PCM values (fir0_scaled_pcm[25:0]). These 26-bit PCM values are input to the FIR 1 filter. - SCALE specifies the right shift amount (and performs a rounding) */ - - cy_en_pdm_pcm_ch_fir1_decimcode_t fir1_decim_code;/**< FIR filter decimation. The FIR filter PCM frequency is a fraction of the FIR0 filter PCM frequency: - "0": FIR 0 filter PCM frequency is 1 * FIR0 filter PCM frequency. - "1": FIR 0 filter PCM frequency is 1/2 * FIR0 filter PCM frequency. - "2": FIR 0 filter PCM frequency is 1/3 * FIR0 filter PCM frequency. - "3": FIR 0 filter PCM frequency is 1/4 * FIR0 filter PCM frequency. */ - - uint8_t fir1_scale; /**< FIR 1 filter PCM scaling. FIR 1 filter PCM values (fir1_pcm[43:0]) are scaled (right shifted, rounded and clipped) - to 26-bit signed PCM values (fir1_scaled_pcm[23:0]). These 24-bit PCM values are input to the DC blocker. - SCALE specifies the right shift amount (and performs a rounding) */ - - uint8_t dc_block_code; /**< DC blocker coefficient. The DC blocker is defined as: - "0": alpha = 1 - (1/2^(12-0)) = 0.999755859. - "1": alpha = 1 - (1/2^(12-1)) = 0.999511719. - "2": alpha = 1 - (1/2^(12-2)) = 0.999023438. - "3": alpha = 1 - (1/2^(12-3)) = 0.998046875. - "4": alpha = 1 - (1/2^(12-4)) = 0.99609375. - "5": alpha = 1 - (1/2^(12-5)) = 0.9921875. - "6": alpha = 1 - (1/2^(12-6)) = 0.984375. - "7": alpha = 1 - (1/2^(12-7)) = 0.96875. */ - } cy_stc_pdm_pcm_channel_config_t; - - -/** PDM-PCM initialization configuration */ -typedef struct -{ - uint8_t clkDiv; /**< PDM Clock Divider - This configures a frequency of PDM CLK. The configured frequency - is used to operate PDM core. I.e. the frequency is input to - MCLKQ_CLOCK_DIV register. */ - cy_en_pdm_pcm_clock_sel_t clksel; /**< Interface clock clk_if selection - "0": SRSS clock clk_if_srss. - "1": IOSS data input signal "pdm_data[0]". - "2": IOSS data input signal "pdm_data[1]". - "3": Clock clk_if is off.*/ - cy_en_pdm_pcm_halve_rate_sel_t halverate; /**< Halve rate sampling: - '0': Full rate sampling. The PDM interface clock pdm_clk is as specified by CLOCK_DIV[]. - Each captured PDM value is provided once to the CIC filter. - '1': Halve rate sampling. The PDM interface clock clk_pdm is as specified by CLOCK_DIV[] divided by two (halve the frequency). - Each PDM value is captured twice and provided twice to the CIC filter; i.e. the PDM value is repeated. */ - uint8_t route; /**< Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver. - Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. - The 1-bit field DATA_SEL[j] specification is as follows: - '0': PDM receiver j uses data input signal "pdm_data[j]". - '1': PDM receiver j uses data input signal "pdm_data[j ^ 1]" (the lower bit of the index is inverted). */ - - - uint8_t fir0_coeff_user_value; /**< FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation): - '0': Disabled. The middle FIR filter coefficient (16th coefficient, or tap 15 in [0:29] range) is "1" and - all other FIR filter coefficients are "0"; i.e. the FIR filter is a pass through filter and the filter gain is "1". - fir0_pcm[44:0] = cic_pcm[25:0] (with sign extension)'1': Enabled. - This filter is disabled by default, and typically only used for sample frequencies (Fs) of 8 and 16 kHz. */ - - uint8_t fir1_coeff_user_value; /**< FIR 1 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation): - '0': Disabled. The middle FIR filter coefficient (28th coefficient, or tap 27 in [0:54] range) is "1" - and all other FIR filter coefficients are "0"; i.e. the FIR filter is a pass through filter - and the filter gain is "1". fir1_pcm[43:0] = fir0_scaled_pcm[25:0] (with sign extension)'1': Enabled. - Disabling of the filter functionality is provided for debug purposes. */ - - cy_stc_pdm_pcm_fir_coeff_t fir0_coeff[8]; /**< The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients - (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7. - The FIR filter coefficients have no default values: - the coefficients MUST be programmed BEFORE the filter is enabled. - By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies.*/ - - cy_stc_pdm_pcm_fir_coeff_t fir1_coeff[14]; /**< The (symmetric) 55-taps finite impulse response (FIR) filter - with 14-bit signed coefficients (in the range [-8192, 8191]) - are specified by FIR1_COEFF0, ..., FIR1_COEFF13. - The (default) FIR filter has built in droop correction. - The filter gain (sum of the coefficients) is 13921 and the default - coefficients (as specified by FIR1_COEFFx.DATA0/1[13:0]) are: - -2, 21, 26, -17, -41, 25, 68, -33, - -107, 41, 160, -48, -230, 54, 325, -56, - -453, 51, 631, -31, -894, -21, 1326, 172, - -2191, -770, 4859, 8191, 4859, -770, -2191, 172, - 1326, -21, -894, -31, 631, 51, -453, -56, - 325, 54, -230, -48, 160, 41, -107, -33, - 68, 25, -41, -17, 26, 21, -2. */ -} cy_stc_pdm_pcm_config_v2_t; - -/** \cond INTERNAL */ -typedef cy_stc_pdm_pcm_config_v2_t cy_stc_pdm_pcm_config_t; -/** \endcond */ - -/** \} group_pdm_pcm_data_structures_v2 */ - - -/** \cond INTERNAL */ -/****************************************************************************** - * Local definitions -*******************************************************************************/ -/** Define bit mask for all available interrupt sources */ -#define CY_PDM_PCM_INTR_MASK (CY_PDM_PCM_INTR_RX_TRIGGER | \ - CY_PDM_PCM_INTR_RX_FIR_OVERFLOW | \ - CY_PDM_PCM_INTR_RX_OVERFLOW | \ - CY_PDM_PCM_INTR_RX_IF_OVERFLOW | \ - CY_PDM_PCM_INTR_RX_UNDERFLOW) - -/* Non-zero default values */ -#define CY_PDM_PCM_CH_IF_CTL_DEFAULT (0x3U) - -#define CY_PDM_PCM_CLK_DIV_MAX 255 - -#define CY_PDM_PCM_CH_CIC_DECIM_CODE_DEFAULT (0x4U) -#define CY_PDM_PCM_CH_FIR0_DECIM_CODE_DEFAULT (0x0U) -#define CY_PDM_PCM_CH_FIR0_SCALE_DEFAULT (0x0U) -#define CY_PDM_PCM_CH_FIR1_DECIM_CODE_DEFAULT (0x1U) -#define CY_PDM_PCM_CH_FIR1_SCALE_DEFAULT (0x0FU) -#define CY_PDM_PCM_CH_FIR1_ENABLE_DEFAULT (0x1U) -#define CY_PDM_PCM_CH_DCBLOCK_CODE_DEFAULT (0x1U) -#define CY_PDM_PCM_CH_DCBLOCK_ENABLE_DEFAULT (0x1U) - -#define PDM_TEST_CTL_DRIVE_DELAY_HI_DEFAULT (0x00U) -#define PDM_TEST_CTL_DRIVE_DELAY_LO_DEFAULT (0x04U) -#define PDM_TEST_CTL_MODE_HI_DEFAULT (0x3U) -#define PDM_TEST_CTL_MODE_LO_DEFAULT (0x3U) -#define PDM_TEST_CTL_AUDIO_FREQ_DIV_DEFAULT (0x7U) -#define PDM_TEST_CTL_CH_ENABLED_DEFAULT (0x0U) - -#define PDM_CLOCK_CTL_CLOCK_DIV_DEFAULT (0x07U) -#define PDM_CLOCK_CTL_CLOCK_SEL_DEFAULT (0x3U) -#define PDM_CLOCK_CTL_HALVE_DEFAULT (0x0U) - - -#define CY_PDM_PCM_ENABLE (0x1U) -#define CY_PDM_PCM_DISABLE (0x0U) - - - -#define CY_PDM_PCM_CH_CTL_WORDSIZE_DEFAULT (0x0U) -#define CY_PDM_PCM_CH_CTL_WORDSIGN_EXT_DEFAULT (0x100U) -#define CY_PDM_PCM_CH_CTL_CH_ENABLE_DEFAULT (0x00000000U) - -#define CY_PDM_PCM_TEST_CTL_DEFAULT (_VAL2FLD(PDM_TEST_CTL_DRIVE_DELAY_HI, PDM_TEST_CTL_DRIVE_DELAY_HI_DEFAULT) | \ - _VAL2FLD(PDM_TEST_CTL_DRIVE_DELAY_LO, PDM_TEST_CTL_DRIVE_DELAY_LO_DEFAULT) | \ - _VAL2FLD(PDM_TEST_CTL_MODE_HI, PDM_TEST_CTL_MODE_HI_DEFAULT) | \ - _VAL2FLD(PDM_TEST_CTL_MODE_LO, PDM_TEST_CTL_MODE_LO_DEFAULT) | \ - _VAL2FLD(PDM_TEST_CTL_AUDIO_FREQ_DIV, PDM_TEST_CTL_AUDIO_FREQ_DIV_DEFAULT) | \ - _VAL2FLD(PDM_TEST_CTL_CH_ENABLED, PDM_TEST_CTL_CH_ENABLED_DEFAULT)) - -#define CY_PDM_PCM_CLK_CTL_DEFAULT (_VAL2FLD(PDM_CLOCK_CTL_CLOCK_DIV, PDM_CLOCK_CTL_CLOCK_DIV_DEFAULT) | \ - _VAL2FLD(PDM_CLOCK_CTL_CLOCK_SEL, PDM_CLOCK_CTL_CLOCK_SEL_DEFAULT) | \ - _VAL2FLD(PDM_CLOCK_CTL_HALVE, PDM_CLOCK_CTL_HALVE_DEFAULT)) - -#define CY_PDM_PCM_CH_CTL_DEFAULT (_VAL2FLD(PDM_CH_CTL_WORD_SIZE, CY_PDM_PCM_CH_CTL_WORDSIZE_DEFAULT) | \ - _VAL2FLD(PDM_CH_CTL_WORD_SIGN_EXTEND, CY_PDM_PCM_CH_CTL_WORDSIGN_EXT_DEFAULT) | \ - _VAL2FLD(PDM_CH_CTL_ENABLED, CY_PDM_PCM_CH_CTL_CH_ENABLE_DEFAULT)) - -#define CY_PDM_PCM_CH_FIR1_DEFAULT (_VAL2FLD(PDM_CH_FIR1_CTL_DECIM2, CY_PDM_PCM_CH_FIR1_DECIM_CODE_DEFAULT) | \ - _VAL2FLD(PDM_CH_FIR1_CTL_SCALE, CY_PDM_PCM_CH_FIR1_SCALE_DEFAULT) | \ - _VAL2FLD(PDM_CH_FIR1_CTL_ENABLED, CY_PDM_PCM_CH_FIR1_ENABLE_DEFAULT)) - -#define CY_PDM_PCM_CH_DCBLOCK_DEFAULT (_VAL2FLD(PDM_CH_DC_BLOCK_CTL_CODE, CY_PDM_PCM_CH_DCBLOCK_CODE_DEFAULT) | \ - _VAL2FLD(PDM_CH_DC_BLOCK_CTL_ENABLED, CY_PDM_PCM_CH_DCBLOCK_ENABLE_DEFAULT)) - - - -/* Macros for conditions used by CY_ASSERT calls */ - -#define CY_PDM_PCM_IS_CLK_DIV_VALID(clkDiv) (((clkDiv) >= 1U) && ((clkDiv) <= CY_PDM_PCM_CLK_DIV_MAX)) - -#define CY_PDM_PCM_IS_CLK_SEL_VALID(clksel) (((clksel) == CY_PDM_PCM_SEL_SRSS_CLOCK) || \ - ((clksel) == CY_PDM_PCM_SEL_PDM_DATA0) || \ - ((clksel) == CY_PDM_PCM_SEL_PDM_DATA1) || \ - ((clksel) == CY_PDM_PCM_SEL_OFF)) - -#define CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(halverate) (((halverate) == CY_PDM_PCM_RATE_FULL) || \ - ((halverate) == CY_PDM_PCM_RATE_HALVE)) - -#define CY_PDM_PCM_IS_ROUTE_VALID(route) ((route) <= 126) - -#define CY_PDM_PCM_IS_CH_SET_VALID(chanselect) (((chanselect) >= 1U) && ((chanselect) <= 255)) - -#define CY_PDM_PCM_IS_SAMPLE_DELAY_VALID(sampledelay) ((sampledelay) <= 255) - -#define CY_PDM_PCM_IS_WORD_SIZE_VALID(wordSize) (((wordSize) == CY_PDM_PCM_WSIZE_8_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_10_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_12_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_14_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_16_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_18_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_20_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_24_BIT) || \ - ((wordSize) == CY_PDM_PCM_WSIZE_32_BIT)) - -#define CY_PDM_PCM_IS_SCALE_VALID(scale) ((scale) <= 31) - -#define CY_PDM_PCM_IS_ENABLE_VALID(enable) ((enable == 0)||(enable == 1)) - -#define CY_PDM_PCM_IS_SIGNEXTENSION_VALID(signExtension) ((signExtension == 0)||(signExtension == 1)) - -#define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_INTR_MASK))) -#define CY_PDM_PCM_IS_TRIG_LEVEL(trigLevel) ((trigLevel) <= 63) - -/** \endcond */ - -/** -* \addtogroup group_pdm_pcm_functions_v2 -* \{ -*/ - -cy_en_pdm_pcm_status_t Cy_PDM_PCM_Channel_Init(PDM_Type * base, cy_stc_pdm_pcm_channel_config_t const * chan_config, uint8_t channel_num); -void Cy_PDM_PCM_Channel_DeInit(PDM_Type * base, uint8_t channel_num); - -cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config); - void Cy_PDM_PCM_DeInit(PDM_Type * base); - -cy_en_pdm_pcm_status_t Cy_PDM_PCM_test_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config, cy_stc_test_config_t const * test_config); - -__STATIC_INLINE void Cy_PDM_PCM_Activate_Channel(PDM_Type * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_DeActivate_Channel(PDM_Type * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_SetRateSampling(PDM_Type * base, cy_en_pdm_pcm_halve_rate_sel_t rate); - -__STATIC_INLINE void Cy_PDM_PCM_Channel_Enable(PDM_Type * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_Channel_Disable(PDM_Type * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_Cic_DecimCode(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_cic_decimcode_t decimcode); -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_Fir0(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_fir0_decimcode_t decimcode,uint32_t scale); -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_Fir1(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_fir1_decimcode_t decimcode,uint32_t scale); -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_DCblock(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_dcblock_coef_t coef); -__STATIC_INLINE void Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base, uint32_t channel_num, uint32_t interrupt); -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptMask(PDM_Type const * base, uint32_t channel_num); -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatusMasked(PDM_Type const * base, uint32_t channel_num); -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatus(PDM_Type const * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base, uint32_t channel_num, uint32_t interrupt); -__STATIC_INLINE void Cy_PDM_PCM_Channel_SetInterrupt(PDM_Type * base, uint32_t channel_num, uint32_t interrupt); -__STATIC_INLINE uint8_t Cy_PDM_PCM_Channel_GetNumInFifo(PDM_Type const * base, uint32_t channel_num); -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifo(PDM_Type const * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_Channel_FreezeFifo(PDM_Type * base, uint32_t channel_num); -__STATIC_INLINE void Cy_PDM_PCM_Channel_UnfreezeFifo(PDM_Type * base, uint32_t channel_num); -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifoSilent(PDM_Type const * base, uint32_t channel_num); - - -/** \} group_pdm_pcm_functions_v2 */ - -/** -* \addtogroup group_pdm_pcm_functions_v2 -* \{ -*/ - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Enable -***************************************************************************//** -* -* Enables the PDM-PCM data conversion. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num channel_num -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_Enable(PDM_Type * base, uint32_t channel_num) -{ - PDM_PCM_CH_CTL(base,channel_num) |= PDM_CH_CTL_ENABLED_Msk; - -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Disable -***************************************************************************//** -* -* Disables the PDM-PCM data conversion. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num channel_num -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_Disable(PDM_Type * base, uint32_t channel_num) -{ - PDM_PCM_CH_CTL(base,channel_num) &= (uint32_t) ~PDM_CH_CTL_ENABLED_Msk; - -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Activate_Channel -***************************************************************************//** -* -* Activates the PDM-PCM channel. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num to be activated -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Activate_Channel(PDM_Type * base, uint32_t channel_num) -{ - PDM_PCM_CTL_SET(base) = (1 << channel_num); -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_DeActivate_Channel -***************************************************************************//** -* -* DeActivates the PDM-PCM channel. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num to be deactivated -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_DeActivate_Channel(PDM_Type * base, uint32_t channel_num) -{ - PDM_PCM_CTL_CLR(base) = (1 << channel_num); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_GetCurrentState -***************************************************************************//** -* -* Returns the current PDM-PCM state (running/stopped). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \return The current state (CMD register). -* -******************************************************************************/ -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetCurrentState(PDM_Type const * base, uint32_t channel_num) -{ - return (PDM_PCM_CH_CTL(base,channel_num)); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_SetRateSampling -***************************************************************************//** -* -* Sets Halve rate Sampling rate. -* -* \param base The pointer to the PDM-PCM instance address. -* \param rate Halve rate sampling enabled or disabled. -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_SetRateSampling(PDM_Type * base, cy_en_pdm_pcm_halve_rate_sel_t rate) -{ - CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(rate)); - PDM_PCM_CLOCK_CTL(base) &= ~PDM_CLOCK_CTL_HALVE_Msk; - PDM_PCM_CLOCK_CTL(base) |= _VAL2FLD(PDM_CLOCK_CTL_HALVE, rate); -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_SetCicDecimCode -***************************************************************************//** -* -* Sets PDM-PCM CIC Filter Decim code. -* -* \param base The pointer to the PDM-PCM instance address -* \param channel_num -* \param decimcode \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_Cic_DecimCode(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_cic_decimcode_t decimcode) -{ - PDM_PCM_CH_CIC_CTL(base, channel_num) = decimcode; -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_Set_Fir0 -***************************************************************************//** -* -* Sets PDM-PCM FIR0 Filter Decim code, Scale and enabling the filter. -* The FIR filter coefficients have no default values: -* the coefficients MUST be programmed BEFORE the filter is enabled. -* By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies. -* For other frequencies it is a pass through. -* -* \param base The pointer to the PDM-PCM instance address -* \param channel_num -* \param decimcode \ref group_pdm_pcm_macros_interrupt_masks_v2. -* \param scale scale -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_Fir0(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_fir0_decimcode_t decimcode,uint32_t scale) -{ - CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(scale)); - PDM_PCM_CH_FIR0_CTL(base, channel_num) |= _VAL2FLD(PDM_CH_FIR0_CTL_DECIM3, decimcode) | - _VAL2FLD(PDM_CH_FIR0_CTL_SCALE, scale); -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_Set_Fir1 -***************************************************************************//** -* -* Sets PDM-PCM FIR1 Filter Decim code, Scale and enabling the filter. -* -* \param base The pointer to the PDM-PCM instance address -* \param channel_num -* \param decimcode \ref group_pdm_pcm_macros_interrupt_masks_v2. -* \param scale scale -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_Fir1(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_fir1_decimcode_t decimcode,uint32_t scale) -{ - CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(scale)); - PDM_PCM_CH_FIR0_CTL(base, channel_num) |= _VAL2FLD(PDM_CH_FIR1_CTL_DECIM2, decimcode) | - _VAL2FLD(PDM_CH_FIR1_CTL_SCALE, scale); -} - - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_Set_DCblock -***************************************************************************//** -* -* Sets PDM-PCM FIR1 Filter Decim code, Scale and enabling the filter. -* -* \param base The pointer to the PDM-PCM instance address -* \param channel_num -* \param coef coef -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_Set_DCblock(PDM_Type * base, uint32_t channel_num, cy_en_pdm_pcm_ch_dcblock_coef_t coef) -{ - PDM_PCM_CH_DC_BLOCK_CTL(base, channel_num) |= _VAL2FLD(PDM_CH_DC_BLOCK_CTL_CODE, coef); -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_SetInterruptMask -***************************************************************************//** -* -* Sets one or more PDM-PCM interrupt factor bits (sets the INTR_MASK register). -* -* \param base The pointer to the PDM-PCM instance address -* \param channel_num -* \param interrupt Interrupt bit mask -* \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base, uint32_t channel_num, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); - PDM_PCM_INTR_RX_MASK(base, channel_num) = interrupt; -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_GetInterruptMask -***************************************************************************//** -* -* Returns the PDM-PCM interrupt mask (a content of the INTR_MASK register). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \return The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -******************************************************************************/ -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptMask(PDM_Type const * base, uint32_t channel_num) -{ - return (PDM_PCM_INTR_RX_MASK(base, channel_num)); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_GetInterruptStatusMasked -***************************************************************************//** -* -* Reports the status of enabled (masked) PDM-PCM interrupt sources. -* (an INTR_MASKED register). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \return The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -*****************************************************************************/ -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatusMasked(PDM_Type const * base, uint32_t channel_num) -{ - return (PDM_PCM_INTR_RX_MASKED(base, channel_num)); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_GetInterruptStatus -***************************************************************************//** -* -* Reports the status of PDM-PCM interrupt sources (an INTR register). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \return The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -******************************************************************************/ -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatus(PDM_Type const * base, uint32_t channel_num) -{ - return (PDM_PCM_INTR_RX(base, channel_num)); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_ClearInterrupt -***************************************************************************//** -* -* Clears one or more PDM-PCM interrupt statuses (sets an INTR register's bits). -* -* \param base The pointer to the PDM-PCM instance address -* \param channel_num -* \param interrupt -* The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base, uint32_t channel_num, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); - PDM_PCM_INTR_RX(base, channel_num) = interrupt; - (void) PDM_PCM_INTR_RX(base, channel_num); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_SetInterrupt -***************************************************************************//** -* -* Sets one or more interrupt source statuses (sets an INTR_SET register). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \param interrupt -* The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2. -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_SetInterrupt(PDM_Type * base, uint32_t channel_num, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); - PDM_PCM_INTR_RX_SET(base, channel_num) = interrupt; -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_GetNumInFifo -***************************************************************************//** -* -* Reports the current number of used words in the output data FIFO. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \return The current number of used FIFO words (range is 0 - 254). -* -******************************************************************************/ -__STATIC_INLINE uint8_t Cy_PDM_PCM_Channel_GetNumInFifo(PDM_Type const * base, uint32_t channel_num) -{ - return (uint8_t) (_FLD2VAL(PDM_CH_RX_FIFO_STATUS_USED, PDM_PCM_RX_FIFO_STATUS(base, channel_num))); -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_ReadFifo -***************************************************************************//** -* -* Reads ("pops") one word from the output data FIFO. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* \return The data word. -* -******************************************************************************/ -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifo(PDM_Type const * base, uint32_t channel_num) -{ - return (PDM_PCM_RX_FIFO_RD(base, channel_num)); -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_FreezeFifo -***************************************************************************//** -* -* Freezes the RX FIFO (Debug purpose). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_FreezeFifo(PDM_Type * base, uint32_t channel_num) -{ - PDM_PCM_RX_FIFO_CTL(base, channel_num) |= PDM_CH_RX_FIFO_CTL_FREEZE_Msk; -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_UnfreezeFifo -***************************************************************************//** -* -* Unfreezes the RX FIFO (Debug purpose). -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num -* -******************************************************************************/ -__STATIC_INLINE void Cy_PDM_PCM_Channel_UnfreezeFifo(PDM_Type * base, uint32_t channel_num) -{ - PDM_PCM_RX_FIFO_CTL(base, channel_num) &= (uint32_t) ~PDM_CH_RX_FIFO_CTL_FREEZE_Msk; -} - - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_ReadFifoSilent -***************************************************************************//** -* -* Reads the RX FIFO silent (without touching the FIFO function). -* -* \param base Pointer to PDM-PCM instance address. -* \param channel_num -* \return FIFO value. -* -******************************************************************************/ -__STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifoSilent(PDM_Type const * base, uint32_t channel_num) -{ - return (PDM_PCM_RX_FIFO_RD_SILENT(base, channel_num)); -} - -/** \} group_pdm_pcm_functions_v2 */ - -#ifdef __cplusplus -} -#endif /* of __cplusplus */ - -#endif /* CY_IP_MXPDM */ - -#endif /* CY_PDM_PCM_V2_H__ */ - -/** \} group_pdm_pcm_v2 */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ppu_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ppu_v1.h deleted file mode 100644 index b91693f4da..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_ppu_v1.h +++ /dev/null @@ -1,258 +0,0 @@ -/***************************************************************************//** -* \file cy_ppu_v1.h -* \version 1.0 -* -* This file provides the header for ARM PPU Player specific driver -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - - -#ifndef CY_PPU_V1_H -#define CY_PPU_V1_H - -//#include -//#include -#include -//#include //TBD -//#include //TBD -#include "ppu_v1.h" - -/*! - * \addtogroup GroupModules Modules - * @{ - */ - -/*! - * \defgroup GroupModulePPUv1 PPUv1 Driver - * @{ - */ - -/*! - * \brief Indexes of the interfaces exposed by the module. - */ -enum cy_ppu_v1_api_idx { - /*! Power domain driver API */ - CY_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER, - /*! interrupt Service Routine driver API */ - CY_PPU_V1_API_IDX_ISR, - /*! System boot API */ - CY_PPU_V1_API_IDX_BOOT, - /*! Number of exposed interfaces */ - CY_PPU_V1_API_IDX_COUNT, -}; - -/*! - * \brief Types of power domain. - */ -enum cy_pd_type { - /*! Processor. */ - CY_PD_TYPE_CPUSS, - /*! Processor cluster. */ - CY_PD_TYPE_CLUSTER, - /*! Generic device. */ - CY_PD_TYPE_DEVICE, - /*! Debug device. */ - CY_PD_TYPE_DEVICE_DEBUG, - /*! System. */ - CY_PD_TYPE_SYSTEM, - /*! Number of power domain types. */ - CY_PD_TYPE_COUNT -}; - - -/** -* \addtogroup group_sysclk_returns -* \{ -*/ -/** Defines general-purpose function return values */ -typedef enum -{ - CY_PPU_SUCCESS = 0x00UL, /**< Command completed with no errors */ - CY_PPU_BAD_PARAM = 0x01UL, /**< Invalid function input parameter */ - CY_PPU_TIMEOUT = 0x02UL, /**< Timeout occurred */ - CY_PPU_INVALID_STATE = 0x03UL /**< Clock is in an invalid state */ -} cy_en_ppu_status_t; -/** \} group_sysclk_returns */ - -/*! - * \brief Identifiers of the power domain states. The other states are defined - * by the platform code for more flexibility. The power states defined by - * the platform must be ordered from the shallowest to the deepest state. - */ -enum cy_pd_state { - /*! \c OFF power state */ - CY_PD_STATE_OFF, - - /*! \c ON power state */ - CY_PD_STATE_ON, - - /*! \c SLEEP power state */ - CY_PD_STATE_SLEEP, - - /*! Number of power states */ - CY_PD_STATE_COUNT -}; - -/*! - * \brief Masks for the power domain states. - */ -enum cy_pd_state_mask { - CY_PD_STATE_OFF_MASK = 1 << CY_PD_STATE_OFF, - CY_PD_STATE_ON_MASK = 1 << CY_PD_STATE_ON, - CY_PD_STATE_SLEEP_MASK = 1 << CY_PD_STATE_SLEEP, -}; - -/*! - * \brief Types of system shutdown - */ -enum cy_pd_system_shutdown { - /*! System shutdown */ - CY_PD_SYSTEM_SHUTDOWN, - - /*! System cold reset */ - CY_PD_SYSTEM_COLD_RESET, - - /*! System warm reset */ - CY_PD_SYSTEM_WARM_RESET, - - /*! Sub-system reset */ - CY_PD_SYSTEM_SUB_SYSTEM_RESET, - - /*! Forced system shutdown */ - CY_PD_SYSTEM_FORCED_SHUTDOWN, - - /*! Number of shutdown types */ - CY_PD_SYSTEM_COUNT, -}; - - -/*! - * \brief Power domain PPU descriptor. - */ -struct cy_ppu_v1 { - /*! Base address of the PPU registers */ - uintptr_t reg_base; - - /*! PPU's IRQ number */ - unsigned int irq; -}; - -/*! - * \brief PPU_V1 module configuration - */ -struct cy_ppu_v1_config ; - -/*! - * \brief Configuration data of a power domain of the PPU_V1 driver module. - */ -struct cy_ppu_v1_pd_config { - /*! Power domain type */ - enum cy_pd_type pd_type; - - /*! PPU descriptor */ - struct cy_ppu_v1 ppu; - - /*! - * In the case of a core power domain, identifier of the cluster power - * domain it belongs to. If the power domain is not a core power domain, - * the value of this field is undefined. - */ - //fwk_id_t cluster_id; //TBD - - /*! - * Flag indicating if this domain should be powered on during element - * init. This flag is only supported for device and system PPUs and should - * not be set for any other type. - */ - bool default_power_on; - - /*! - * \brief Identifier of an entity wishing to be notified when the PPU - * transitions out of the OFF state. - * - * \note This field may be set to \ref FWK_ID_NONE, in which case no - * observer will be set. - */ - //fwk_id_t observer_id; //TBD - - /*! - * \brief Identifier of the power state observer API implemented by - * \ref observer_id. - */ - //fwk_id_t observer_api; //TBD - - /*! - * \brief Parameter passed to - * \ref mod_ppu_v1_power_state_observer_api::post_ppu_on(). - */ - void *post_ppu_on_param; -}; - -/*! - * \brief PPU_V1 Power State Observer API. - * - * \details This API should be implemented by any modules that should be - * notified when a PPU changes state. - */ -struct cy_ppu_v1_power_state_observer_api { - /*! - * \brief Called after a PPU has turned on. - * - * \param param Generic configurable parameter. - */ - void (*post_ppu_on)(void *param); -}; - -/*! - * \brief PPU_V1 module ISR API - */ -struct ppu_v1_isr_api { - /*! - * \brief Handle a power domain PPU interrupt - * - * \param pd_id Identifier of the power domain - */ - void (*ppu_interrupt_handler)(struct ppu_v1_reg *ppu); //TBD -}; - -/*! - * \brief PPU_V1 module boot API - */ -struct ppu_v1_boot_api { - /*! - * \brief Power on a specified power domain - * - * \param pd_id Identifier of the power domain - * - * \retval FWK_SUCCESS Operation successful. - * \return One of the standard framework error codes. - */ - int (*power_mode_on)(struct ppu_v1_reg *ppu); //TBD -}; - -/*! - * @} - */ - -/*! - * @} - */ - -#endif /* CY_PPU_V1_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_tdm.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_tdm.h deleted file mode 100644 index 432928464f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/cy_tdm.h +++ /dev/null @@ -1,1200 +0,0 @@ -/***************************************************************************//** -* \file cy_tdm.h -* \version 1.0 -* -* \brief -* The header file of the Audio TDM driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_tdm -* \{ -* Configures audio TDM/I2S. -* -* The functions and other declarations used in this driver are in cy_tdm.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* -* Features: -* * Supports I2S mode and TDM mode. -* * Master and slave functionality. -* * Full-duplex transmitter and receiver operation. -* * Support for up to 32 channels. -* * Programmable channel size (up to 32 bits) -* * Programmable channel delay of 0 or 1 bit. -* * Delayed sampling support. -* * Programmable PCM sample formatting (8, 10, 12, 14, 16, 18, 20, 24, 32 bits). -* * Programmable synchronization pulse type. -* * Left-aligned and right-aligned sample formatting. -* * 128 entry TX FIFO with interrupt and trigger support. -* * 128 entry RX FIFO with interrupt and trigger support. -* -* \section group_tdm_configuration Configuration Considerations -* -* To set up a TDM driver, iInitializes the TDM Transmitter module in accordance with a configuration structure. -* -* * Each TDM/I2S (TX, RX) pair consists of a TDM/I2S transmitter and a TDM/I2S receiver. -* * The transmitter and receiver can function simultaneously and have dedicated clock control. -* * The transmitter and receiver have dedicated MMIO registers and a dedicated FIFO. -* * The transmitter and receiver have a dedicated FIFO interrupt and FIFO trigger. -* * The transmitter trigger is activated when a programmable number of PCM data slots is available in the TX FIFO. -* * The receiver trigger is activated when a programmable number of PCM data words is received into the RX FIFO. -* -* -* \section group_tdm_more_information More Information. -* See: the TDM chapter of the device technical reference manual (TRM); -* the TDM Component datasheet; -* -* -* \section group_tdm_MISRA MISRA-C Compliance -* The TDM driver has the following specific deviations: -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
10.3RA composite expression of the "essentially unsigned" type is being -* cast to a different type category.The value got from the bitfield physically cannot exceed the enumeration -* that describes this bitfield. So, the code is safe by design.
11.4AA cast should not be performed between a pointer to object type and -* a different pointer to object type.
20.3RThe validity of values passed to library functions shall be checked.This violation is not caused by code changes, i.e. is not a regression.
-* -* \section group_tdm_changelog Changelog -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
1.0Initial version
-* - -* \defgroup group_tdm_i2s_macros_intrerrupt_masks Interrupt Masks -* \defgroup group_tdm_data_structures Data Structures -* \defgroup group_tdm_enums Enumerated Types -* \defgroup group_tdm_macros Macros -* \defgroup group_tdm_functions Functions - -*/ - -#if !defined (CY_TDM_H) -#define CY_TDM_H - -#include "cy_device.h" - -#if defined (CY_IP_MXTDM) - -#include "cy_syslib.h" -#include -#include -#include - -#if defined(__cplusplus) -extern "C" { -#endif - -/****************************************************************************** - * Macro definitions * - ******************************************************************************/ - -/** -* \addtogroup group_tdm_macros -* \{ -*/ - -/** The driver major version */ -#define CY_I2S_DRV_VERSION_MAJOR 1 - -/** The driver minor version */ -#define CY_I2S_DRV_VERSION_MINOR 0 - -/** The TDM driver identifier */ -#define CY_TDM_ID (CY_PDL_DRV_ID(0x50U)) - -/** \} group_tdm_macros */ - -/** -* \addtogroup group_tdm_i2s_macros_intrerrupt_masks -* \{ -*/ - -/** Bit 0: Less entries in the TX FIFO than specified by Trigger Level. */ -#define CY_TDM_INTR_TX_FIFO_TRIGGER (TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_TRIGGER_Msk) -/** Bit 1: Attempt to write to a full TX FIFO. */ -#define CY_TDM_INTR_TX_FIFO_OVERFLOW (TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_OVERFLOW_Msk) -/** Bit 2: Attempt to read from an empty TX FIFO. */ -#define CY_TDM_INTR_TX_FIFO_UNDERFLOW (TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_UNDERFLOW_Msk) -/** Bit 8: Interface frequency is higher than PCM sample frequency. */ -#define CY_TDM_INTR_TX_IF_UNDERFLOW (TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_IF_UNDERFLOW_Msk) - -/** Bit 0: Less entries in the RX FIFO than specified by Trigger Level. */ -#define CY_TDM_INTR_RX_FIFO_TRIGGER (TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_TRIGGER_Msk) -/** Bit 1: Attempt to write to a full RX FIFO. */ -#define CY_TDM_INTR_RX_FIFO_OVERFLOW (TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_OVERFLOW_Msk) -/** Bit 2: Attempt to read from an empty RX FIFO. */ -#define CY_TDM_INTR_RX_FIFO_UNDERFLOW (TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_UNDERFLOW_Msk) -/** Bit 8: Interface frequency is higher than PCM sample frequency. */ -#define CY_TDM_INTR_RX_IF_UNDERFLOW (TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_IF_OVERFLOW_Msk) - -/** \} group_tdm_i2s_macros_intrerrupt_masks */ - - -/** -* \addtogroup group_tdm_enums -* \{ -*/ - -/** cy_en_tdm_ws_t */ -typedef enum -{ - CY_TDM_SIZE_8 = 0U, /**< PCM word size:8bit. */ - CY_TDM_SIZE_10 = 1U, /**< PCM word size:10bit. */ - CY_TDM_SIZE_12 = 2U, /**< PCM word size:12bit. */ - CY_TDM_SIZE_14 = 3U, /**< PCM word size:14bit. */ - CY_TDM_SIZE_16 = 4U, /**< PCM word size:16bit. */ - CY_TDM_SIZE_18 = 5U, /**< PCM word size:18bit. */ - CY_TDM_SIZE_20 = 6U, /**< PCM word size:20bit. */ - CY_TDM_SIZE_24 = 7U, /**< PCM word size:24bit. */ - CY_TDM_SIZE_32 = 8U /**< PCM word size:32bit. */ -} cy_en_tdm_ws_t; - -/** cy_en_tdm_format_t */ -typedef enum -{ - CY_TDM_LEFT_DELATED = 0, /**< Format is left aligned and delayed. */ - CY_TDM_LEFT = 1, /**< Format is left aligned. */ - CY_TDM_RIGHT_DELATED = 2, /**< Format is right aligned and delayed. */ - CY_TDM_RIGHT = 3 /**< Format is right aligned. */ -} cy_en_tdm_format_t; - -/** cy_en_tdm_device_cfg_t */ -typedef enum -{ - CY_TDM_DEVICE_SLAVE = 0U, /**< Device is configured as slave. */ - CY_TDM_DEVICE_MASTER = 1U /**< Device is configured as master. */ -} cy_en_tdm_device_cfg_t; - -/** cy_en_tdm_word_extend_cfg_t */ -typedef enum -{ - CY_ZERO_EXTEND = 0U, /**< Zero extended. */ - CY_SIGN_EXTEND = 1U /**< sign extended. */ -} cy_en_tdm_word_extend_cfg_t; - -/** cy_en_tdm_clock_sel_t */ -typedef enum -{ - CY_TDM_SEL_SRSS_CLK0 = 0U, /**< Interface clock is selected as clk_if_srss[0]. */ - CY_TDM_SEL_SRSS_CLK1 = 1U, /**< Interface clock is selected as clk_if_srss[1]. */ - CY_TDM_SEL_SRSS_CLK2 = 2U, /**< Interface clock is selected as clk_if_srss[2]. */ - CY_TDM_SEL_SRSS_CLK3 = 3U, /**< Interface clock is selected as clk_if_srss[3]. */ - CY_TDM_SEL_TX_MCLK_IN = 4U /**< Interface clock is selected as tdm_tx_mclk_in. */ -} cy_en_tdm_clock_sel_t; - -/** cy_en_tdm_sckpolarity_t */ -typedef enum -{ - CY_TDM_CLK = 0U, /**< TDM Clock is used as is. */ - CY_TDM_CLK_INVERTED = 1U /**< TDM Clock is inverted. */ -} cy_en_tdm_sckpolarity_t; - -/** cy_en_tdm_fsyncpolarity_t*/ -typedef enum -{ - CY_TDM_SIGN = 0U, /**< TDM Sign is used as is. */ - CY_TDM_SIGN_INVERTED = 1U /**< TDM Sign is inverted. */ -} cy_en_tdm_fsyncpolarity_t; - -/** cy_en_tdm_fsyncformat_t */ -typedef enum -{ - CY_TDM_BIT_PERIOD = 0U, /**< TDM Channel synchronizarion is duration of a bit period. */ - CY_TDM_CH_PERIOD = 1U /**< TDM Channel synchronizarion is duration of a channel period. */ -} cy_en_tdm_fsyncformat_t; - -/** -* TDM status definitions. -*/ -typedef enum -{ - CY_TDM_SUCCESS = 0x00UL, /**< Successful. */ - CY_TDM_BAD_PARAM = CY_TDM_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */ -} cy_en_tdm_status_t; - -/** cy_en_tdm_source_status_t */ -typedef enum -{ - CY_TDM_OK = 0x00UL, /**< Successful. */ - CY_TDM_BAD = 0x01UL /**< Not Good */ -} cy_en_tdm_source_status_t; - -/** \} group_tdm_enums */ - -/** -* \addtogroup group_tdm_data_structures -* \{ -*/ -/** TDM Initialization configuration. */ -typedef struct -{ - bool enable; /**< Enable TDM TX : true: "Enable" false: "Disable" */ - cy_en_tdm_device_cfg_t masterMode; /**< see #cy_en_tdm_device_cfg_t */ - cy_en_tdm_ws_t wordSize; /**< TX word length. Channel size must be greater or equal to the word size.*/ - cy_en_tdm_format_t format; /**< TX data format, see: #cy_en_tdm_format_t. */ - uint16_t clkDiv; /**< CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50% duty cycle clock. - * Only for Master Mode */ - cy_en_tdm_clock_sel_t clkSel; /**< Interface clock "clk_if" selection, see#cy_en_tdm_clock_sel_t. */ - cy_en_tdm_sckpolarity_t sckPolarity; /**< TX clock polarity, 0 for as is and 1 for inverted. */ - cy_en_tdm_fsyncpolarity_t fsyncPolarity; /**< Channel synchronization polarity:'false':used "as is". 'true': inverted. */ - cy_en_tdm_fsyncformat_t fsyncFormat; /**< Channel synchronization pulse format: - * '1': Duration of a single bit period.'0': Duration of the first channel.*/ - uint8_t channelNUM; /**< Number of channels in the frame: - * "0": Undefined/illegal."1": 2 channels."2": 3 channels...."31":32 channels - * Note: the field value chould be less than CH_NR (the number of support channels). - * Note: the TX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels. */ - uint8_t channelSize; /**< Channel size:"0": 1 bit."1": 2 bits..."31": 32 bits. - * Note: channel size must be greater or equal to the word size. */ - uint8_t fifoTriggerLevel; /**< Trigger level. When the TX FIFO has less entries than the number of this field, - * a transmitter trigger event is generated. */ - uint32_t chEN; /**< Channel enable. */ - uint32_t signalInput; /**< Controls routing to the TX slave signalling inputs (FSYNC/SCK): - '0': TX slave signaling indipendent from RX signaling: - '1': TX slave signalling inputs driven by RX Slave: - '2': TX slave signalling inputs driven by RX Master: */ - bool i2sMode; /**< IF set to 1 the IP is configured for I2S mode else for TDM mode */ -}cy_stc_tdm_config_tx_t; - -/** cy_stc_tdm_config_rx_t */ -typedef struct -{ - bool enable; /**< Enable TDM RX : true: "Enable" false: "Disable" */ - cy_en_tdm_device_cfg_t masterMode; /**< see#cy_en_tdm_device_cfg_t */ - cy_en_tdm_ws_t wordSize; /**< RX word length. Channel size must be greater or equal to the word size.*/ - cy_en_tdm_word_extend_cfg_t signExtend; /**< Word extension */ - cy_en_tdm_format_t format; /**< RX data format, see: #cy_en_tdm_format_t. */ - uint16_t clkDiv; /**< CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50% duty cycle clock. - * Only for Master Mode */ - cy_en_tdm_clock_sel_t clkSel; /**< Interface clock "clk_if" selection, see#cy_en_tdm_clock_sel_t. */ - cy_en_tdm_sckpolarity_t sckPolarity; /**< RX clock polarity, 0 for as is and 1 for inverted. */ - cy_en_tdm_fsyncpolarity_t fsyncPolarity; /**< Channel synchronization polarity:'false':used "as is". 'true': inverted. */ - bool lateSample; /**< Interface late sample sample delay. - * Slave configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_in - * "true" : Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_in" (half a cycle delay). - * Master configuratio: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_out". - * "ture" : Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_out" (half a cycle delay). */ - /**< RISING = 0 FALLING = 1 */ - cy_en_tdm_fsyncformat_t fsyncFormat; /**< Channel synchronization pulse format: - * 'false': Duration of a single bit period.'true': Duration of the first channel.*/ - uint8_t channelNUM; /**< Number of channels in the frame: - * "0": Undefined/illegal."1": 2 channels."2": 3 channels...."31":32 channels - * Note: the field value chould be less than CH_NR (the number of support channels). - * Note: the TX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels. */ - uint8_t channelSize; /**< Channel size:"0": 1 bit."1": 2 bits. ..."31": 32 bits. - * Note: channel size must be greater or equal to the word size. */ - uint32_t chEN; /**< Channel enable. */ - - uint8_t fifoTriggerLevel; /**< Trigger level. When the RX FIFO has less entries than the number of this field, - * a transmitter trigger event is generated. */ - uint32_t signalInput; /**< Controls routing to the RX slave signalling inputs (FSYNC/SCK): - '0': RX slave signaling indipendent from TX signaling: - '1': RX slave signalling inputs driven by TX Slave: - '2': RX slave signalling inputs driven by TX Master: */ - bool i2sMode; /**< IF set to 1 the IP is configured for I2S mode else for TDM mode */ -} cy_stc_tdm_config_rx_t; - -/** cy_stc_tdm_config_t */ -typedef struct -{ - cy_stc_tdm_config_tx_t tx_config; /**< TDM Initialization configuration for TX. */ - cy_stc_tdm_config_rx_t rx_config; /**< TDM Initialization configuration for RX. */ -}cy_stc_tdm_config_t; - -/** \} group_tdm_data_structures */ - -/** -* \addtogroup group_tdm_macros -* \{ -*/ -/** \cond INTERNAL */ -/*******************************************************************************/ -/* Local definitions */ -/********************************************************************************/ - -#define CY_TDM_INTR_TX_MASK (CY_TDM_INTR_TX_FIFO_TRIGGER |\ - CY_TDM_INTR_TX_FIFO_OVERFLOW |\ - CY_TDM_INTR_TX_FIFO_UNDERFLOW |\ - CY_TDM_INTR_TX_IF_UNDERFLOW) - - -#define CY_TDM_INTR_RX_MASK (CY_TDM_INTR_RX_FIFO_TRIGGER |\ - CY_TDM_INTR_RX_FIFO_OVERFLOW |\ - CY_TDM_INTR_RX_FIFO_UNDERFLOW |\ - CY_TDM_INTR_RX_IF_UNDERFLOW) - - -/* Non-zero default values for TX_CTL register */ -#define CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS_DEFAULT (0x1U) /**< Default mode is selected as master */ - -#define CY_TDM_TX_CTL_DEFAULT (_VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS, CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS_DEFAULT)) - -/* Non-zero default values for TX_IF_CTL register */ -#define CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV_DEFAULT (0x7U) /**< Default clock is clk_if/(CLOCK_DIV+1) */ -#define CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL_DEFAULT (0x7U) /**< Default clock is selected as clk_if_srss[0], later it will be off */ -#define CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_SIZE_DEFAULT (0x1FU) /**< Default channel size is 32 bits */ - -#define CY_TDM_TX_IF_CTL_DEFAULT (_VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV, CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV_DEFAULT) | \ - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL, CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL_DEFAULT) | \ - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_SIZE, CY_TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_SIZE_DEFAULT)) - -/* Non-zero default values for RX_CTL register */ -#define CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIGN_EXTEND_DEFAULT (0x1U) /**< Default rx data word with sign extension */ - -#define CY_TDM_RX_CTL_DEFAULT (_VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIGN_EXTEND, CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIGN_EXTEND_DEFAULT)) - - -/* Non-zero default values for RX_IF_CTL register */ -#define CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV_DEFAULT (0x7U) /**< Default clock is clk_if/(CLOCK_DIV+1) */ -#define CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL_DEFAULT (0x7U) /**< Default clock is selected as clk_if_srss[0], later it will be off */ -#define CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_SIZE_DEFAULT (0x1FU) /**< Default channel size is 32 bits */ - -#define CY_TDM_RX_IF_CTL_DEFAULT (_VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV, CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV_DEFAULT) | \ - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL, CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL_DEFAULT) | \ - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_SIZE, CY_TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_SIZE_DEFAULT)) - -/** \endcond */ - -/** TDM Macro */ -#define CY_TDM_IS_CLK_DIV_VALID(clkDiv) ( ((clkDiv) > 0UL) && ((clkDiv) <= 255U)) -/** TDM Macro */ -#define CY_TDM_IS_CHANNELS_VALID(channels) (((channels) > 0UL) && ((channels) <= 31UL)) -/** TDM Macro */ -#define CY_TDM_IS_CHANNEL_SIZE_VALID(channel_size) (((channel_size) > 2UL) && ((channel_size) <= 31UL)) -/** TDM Macro */ -#define CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_TDM_INTR_TX_MASK))) -/** TDM Macro */ -#define CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_TDM_INTR_RX_MASK))) -/** TDM Macro */ -#define CY_I2S_TDM_IS_INPUT_SIGNAL_MODE_VALID(signalInput) (signalInput <= 2UL) - -/** \} group_tdm_macros */ - - -/** -* \addtogroup group_tdm_functions -* \{ -*/ -/*******************************************************************************/ -/* Global initialization functions */ -/*******************************************************************************/ - -cy_en_tdm_status_t Cy_AudioTDM_Init( TDM_STRUCT_Type * base, cy_stc_tdm_config_t const * config); -void Cy_AudioTDM_DeInit( TDM_STRUCT_Type * base); - - -/*****************************************************************************/ -/* Audio TDM Control and Status */ -/*****************************************************************************/ - -__STATIC_INLINE void Cy_AudioTDM_EnableTx( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_DisableTx( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_EnableRx( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_DisableRx( TDM_RX_STRUCT_Type * base); - -__STATIC_INLINE void Cy_AudioTDM_WriteTxData( TDM_TX_STRUCT_Type * base, uint32_t data); -__STATIC_INLINE void Cy_AudioTDM_FreezeTxFifo( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_UnfreezeTxFifo( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_MuteTxFifo( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_ActivateTx( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_DeActivateTx( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_ReplayTxFifo( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE uint8_t Cy_AudioTDM_GetNumInTxFifo( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE uint8_t Cy_AudioTDM_GetTxReadPointer( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE uint8_t Cy_AudioTDM_GetTxWritePointer( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_EnableTxTestMode( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_DisableTxTestMode( TDM_TX_STRUCT_Type * base); - -__STATIC_INLINE uint32_t Cy_AudioTDM_ReadRxData( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_FreezeRxFifo( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_UnfreezeRxFifo( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_ActivateRx( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_DeActivateRx( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE uint32_t Cy_AudioTDM_ReadSilentRXFifo( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE uint8_t Cy_AudioTDM_GetNumInRxFifo( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE uint8_t Cy_AudioTDM_GetRxReadPointer( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE uint8_t Cy_AudioTDM_GetRxWritePointer( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_EnableRxTestMode( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_DisableRxTestMode( TDM_RX_STRUCT_Type * base); - - -__STATIC_INLINE void Cy_AudioTDM_ClearTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt); -__STATIC_INLINE void Cy_AudioTDM_SetTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt); -__STATIC_INLINE uint32_t Cy_AudioTDM_GetTxInterruptMask( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_SetTxInterruptMask( TDM_TX_STRUCT_Type * base, uint32_t interrupt); -__STATIC_INLINE uint32_t Cy_AudioTDM_GetTxInterruptStatusMasked( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_SetTxTriggerInterruptMask( TDM_TX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_ClearTxTriggerInterruptMask( TDM_TX_STRUCT_Type * base); - -__STATIC_INLINE void Cy_AudioTDM_ClearRxInterrupt( TDM_RX_STRUCT_Type * base, uint32_t interrupt); -__STATIC_INLINE void Cy_AudioTDM_SetRxInterrupt( TDM_RX_STRUCT_Type * base, uint32_t interrupt); -__STATIC_INLINE uint32_t Cy_AudioTDM_GetRxInterruptMask( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_SetRxInterruptMask( TDM_RX_STRUCT_Type * base, uint32_t interrupt); -__STATIC_INLINE uint32_t Cy_AudioTDM_GetRxInterruptStatusMasked( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_SetRxTriggerInterruptMask( TDM_RX_STRUCT_Type * base); -__STATIC_INLINE void Cy_AudioTDM_ClearRxTriggerInterruptMask( TDM_RX_STRUCT_Type * base); - - -/** \cond INTERNAL */ -/******************************************************************************* -* These are legacy API for I2S. -* for backward compatibility. -* Do not use them in new designs. -*******************************************************************************/ - -#define Cy_AudioI2S_Init Cy_AudioTDM_Init -#define Cy_AudioI2S_DeInit Cy_AudioTDM_DeInit - -#define Cy_AudioI2S_EnableTx Cy_AudioTDM_EnableTx -#define Cy_AudioI2S_DisableTx Cy_AudioTDM_DisableTx -#define Cy_AudioI2S_EnableRx Cy_AudioTDM_EnableRx -#define Cy_AudioI2S_DisableRx Cy_AudioTDM_DisableRx - -#define Cy_AudioI2S_WriteTxData Cy_AudioTDM_WriteTxData -#define Cy_AudioI2S_FreezeTxFifo Cy_AudioTDM_FreezeTxFifo -#define Cy_AudioI2S_UnfreezeTxFifo Cy_AudioTDM_UnfreezeTxFifo -#define Cy_AudioI2S_MuteTxFifo Cy_AudioTDM_MuteTxFifo -#define Cy_AudioI2S_ActivateTx Cy_AudioTDM_ActivateTx -#define Cy_AudioI2S_DeActivateTx Cy_AudioTDM_DeActivateTx -#define Cy_AudioI2S_ReplayTxFifo Cy_AudioTDM_ReplayTxFifo -#define Cy_AudioI2S_GetNumInTxFifo Cy_AudioTDM_GetNumInTxFifo -#define Cy_AudioI2S_GetTxReadPointer Cy_AudioTDM_GetTxReadPointer -#define Cy_AudioI2S_GetTxWritePointer Cy_AudioTDM_GetTxWritePointer -#define Cy_AudioI2S_EnableTxTestMode Cy_AudioTDM_EnableTxTestMode -#define Cy_AudioI2S_DisableTxTestMode Cy_AudioTDM_DisableTxTestMode - -#define Cy_AudioI2S_ReadRxData Cy_AudioTDM_ReadRxData -#define Cy_AudioI2S_FreezeRxFifo Cy_AudioTDM_FreezeRxFifo -#define Cy_AudioI2S_UnfreezeRxFifo Cy_AudioTDM_UnfreezeRxFifo -#define Cy_AudioI2S_ActivateRx Cy_AudioTDM_ActivateRx -#define Cy_AudioI2S_DeActivateRx Cy_AudioTDM_DeActivateRx -#define Cy_AudioI2S_ReadSilentRXFifo Cy_AudioTDM_ReadSilentRXFifo -#define Cy_AudioI2S_GetNumInRxFifo Cy_AudioTDM_GetNumInRxFifo -#define Cy_AudioI2S_GetRxReadPointer Cy_AudioTDM_GetRxReadPointer -#define Cy_AudioI2S_GetRxWritePointer Cy_AudioTDM_GetRxWritePointer -#define Cy_AudioI2S_EnableRxTestMode Cy_AudioTDM_EnableRxTestMode -#define Cy_AudioI2S_DisableRxTestMode Cy_AudioTDM_DisableRxTestMode - -#define Cy_AudioI2S_ClearTxInterrupt Cy_AudioTDM_ClearTxInterrupt -#define Cy_AudioI2S_SetTxInterrupt Cy_AudioTDM_SetTxInterrupt -#define Cy_AudioI2S_GetTxInterruptMask Cy_AudioTDM_GetTxInterruptMask -#define Cy_AudioI2S_SetTxInterruptMask Cy_AudioTDM_SetTxInterruptMask -#define Cy_AudioI2S_GetTxInterruptStatusMasked Cy_AudioTDM_GetTxInterruptStatusMasked -#define Cy_AudioI2S_SetTxTriggerInterruptMask Cy_AudioTDM_SetTxTriggerInterruptMask -#define Cy_AudioI2S_ClearTxTriggerInterruptMask Cy_AudioTDM_ClearTxTriggerInterruptMask - -#define Cy_AudioI2S_ClearRxInterrupt Cy_AudioTDM_ClearRxInterrupt -#define Cy_AudioI2S_SetRxInterrupt Cy_AudioTDM_SetRxInterrupt -#define Cy_AudioI2S_GetRxInterruptMask Cy_AudioTDM_GetRxInterruptMask -#define Cy_AudioI2S_SetRxInterruptMask Cy_AudioTDM_SetRxInterruptMask -#define Cy_AudioI2S_GetRxInterruptStatusMasked Cy_AudioTDM_GetRxInterruptStatusMasked -#define Cy_AudioI2S_SetRxTriggerInterruptMask Cy_AudioTDM_SetRxTriggerInterruptMask -#define Cy_AudioI2S_ClearRxTriggerInterruptMask Cy_AudioTDM_ClearRxTriggerInterruptMask - -/** \endcond */ - -/** \} group_tdm_functions */ - -/** -* \addtogroup group_tdm_functions -* \{ -*/ - -/******************************************************************************* -* Function Name: Cy_AudioTDM_EnableTx -****************************************************************************//** -* -* Starts an I2S/TDM transmission. Interrupt enabling (by the -* \ref Cy_AudioTDM_SetTxInterrupt) is required after this function call, in case -* if any I2S/TDM interrupts are used in the application. -* -* \pre Cy_AudioTDM_Init() must be called before. -* -* \param base The pointer to the I2S/TDM instance address. -* -* -*******************************************************************************/ - -__STATIC_INLINE void Cy_AudioTDM_EnableTx( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_CTL(base) |= TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_ENABLED_Msk; -} - -/******************************************************************************* -* Function Name: Cy_AudioTDM_DisableTx -****************************************************************************//** -* -* Stops an I2S/TDM transmission. -* -* \pre TX interrupt disabling (by the \ref Cy_AudioTDM_SetTxInterrupt) is required -* prior to this function call, in case any TX I2S/TDM interrupts are used. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ - -__STATIC_INLINE void Cy_AudioTDM_DisableTx( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_CTL(base) &= (uint32_t) ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_ENABLED_Msk; -} - -/******************************************************************************* -* Function Name: Cy_AudioTDM_EnableRx -****************************************************************************//** -* -* Starts an I2S/TDM transmission. Interrupt enabling (by the -* \ref Cy_AudioTDM_SetRxInterrupt) is required after this function call, in case -* if any I2S/TDM interrupts are used in the application. -* -* \pre Cy_AudioTDM_Init() must be called before. -* -* \param base The pointer to the I2S/TDM instance address. -* -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_EnableRx( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_CTL(base) |= TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_ENABLED_Msk; -} - -/******************************************************************************* -* Function Name: Cy_AudioTDM_DisableRx -****************************************************************************//** -* -* Stops an I2S/TDM transmission. -* -* \pre TX interrupt disabling (by the \ref Cy_AudioTDM_SetRxInterrupt) is required -* prior to this function call, in case any TX I2S/TDM interrupts are used. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ - -__STATIC_INLINE void Cy_AudioTDM_DisableRx( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_CTL(base) &= (uint32_t) ~TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_ENABLED_Msk; -} - -/******************************************************************************* -* Function Name: Cy_AudioTDM_WriteTxData -****************************************************************************//** -* -* Writes data to the TX FIFO. Increases the TX FIFO level. -* -* \param base The pointer to the I2S/TDM instance address. -* -* \param data Data to be written to the TX FIFO. -* -*******************************************************************************/ - -__STATIC_INLINE void Cy_AudioTDM_WriteTxData( TDM_TX_STRUCT_Type * base, uint32_t data) -{ - TDM_STRUCT_TX_FIFO_WR(base) = data; -} - -/******************************************************************************* -* Function Name: Cy_AudioTDM_FreezeTxFifo -****************************************************************************//** -* -* Freezes the TX FIFO. This function is for debug purposes. output data 0 -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_FreezeTxFifo( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_REPLAY_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE, 1u) | - _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_REPLAY, 0u); -} - -/******************************************************************************* -* Function Name: Cy_AudioTDM_UnfreezeTxFifo -****************************************************************************//** -* -* Unfreezes the TX FIFO. This function is for debug purposes. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_UnfreezeTxFifo( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE, 0u); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_MuteTxFifo */ -/***************************************************************************//** -* -* Mutes the TX FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_MuteTxFifo( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_MUTE_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_MUTE, 1u); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ActivateTx */ -/***************************************************************************//** -* -* Activate/start the TX FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_ActivateTx( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_ACTIVE_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_ACTIVE, 1u); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_DeActivateTx */ -/***************************************************************************//** -* -* Stop the TX FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_DeActivateTx( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_ACTIVE_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_ACTIVE, 0u); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ReplayTxFifo */ -/***************************************************************************//** -* -* Replay functionality (used when FREEZE is '1' or in case of a FIFO underflow event). -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -//data replay -__STATIC_INLINE void Cy_AudioTDM_ReplayTxFifo( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_REPLAY_Msk; - TDM_STRUCT_TX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE, 1u) | - _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_REPLAY, 1u); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetNumInTxFifo */ -/***************************************************************************//** -* -* Gets the number of used words in the TX FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -* \return The current number of used words in the TX FIFO. -* -*******************************************************************************/ -__STATIC_INLINE uint8_t Cy_AudioTDM_GetNumInTxFifo( TDM_TX_STRUCT_Type * base) -{ - return (TDM_STRUCT_TX_FIFO_STATUS(base) & TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_USED_Msk); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetTxReadPointer */ -/***************************************************************************//** -* -* Get the TX FIFO Read Pointer. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint8_t Cy_AudioTDM_GetTxReadPointer( TDM_TX_STRUCT_Type * base) -{ - return (TDM_STRUCT_TX_FIFO_STATUS(base) & TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_RD_PTR_Msk); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetTxWritePointer */ -/***************************************************************************//** -* -* Get the TX FIFO Write Pointer. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint8_t Cy_AudioTDM_GetTxWritePointer( TDM_TX_STRUCT_Type * base) -{ - return (TDM_STRUCT_TX_FIFO_STATUS(base) & TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_WR_PTR_Msk); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_EnableTxTestMode */ -/***************************************************************************//** -* -* Enables the test mode. Used for debugging purposes only.. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_EnableTxTestMode( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_TEST_CTL(base) |= TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_TEST_CTL_ENABLED_Msk; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_DisableTxTestMode */ -/***************************************************************************//** -* -* Disables Test mode. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_DisableTxTestMode( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_TEST_CTL(base) &= (uint32_t) ~TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_TEST_CTL_ENABLED_Msk; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ReadRxData */ -/***************************************************************************//** -* -* Read Rx data from the Rx FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_AudioTDM_ReadRxData( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_FIFO_RD(base)); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_FreezeRxFifo */ -/***************************************************************************//** -* -* Freeze RX FIFO. -* HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer. -* This functionality is intended for debugging purposes. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_FreezeRxFifo( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_FREEZE_Msk; - TDM_STRUCT_RX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_FREEZE, 1u); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_UnfreezeRxFifo */ -/***************************************************************************//** -* -* UnFreeze Rx FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_UnfreezeRxFifo( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_FREEZE_Msk; - TDM_STRUCT_RX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_FREEZE, 0u); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ActivateRx */ -/***************************************************************************//** -* -* Start Rx FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_ActivateRx( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_FIFO_CTL(base) |= TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_ACTIVE_Msk; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_DeActivateRx */ -/***************************************************************************//** -* -* Stop Rx FIFO. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_DeActivateRx( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_FIFO_CTL(base) &= ~TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_ACTIVE_Msk; - TDM_STRUCT_RX_FIFO_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_ACTIVE, 0u); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ReadSilentRXFifo */ -/***************************************************************************//** -* -* When the RX FIFO is empty, a read from this register returns "0" . -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_AudioTDM_ReadSilentRXFifo( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_FIFO_RD_SILENT(base)); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetNumInRxFifo */ -/***************************************************************************//** -* -* Reads RX FIFO status -* -* \param base The pointer to the I2S/TDM instance address. -* -* -*******************************************************************************/ -__STATIC_INLINE uint8_t Cy_AudioTDM_GetNumInRxFifo( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_FIFO_STATUS(base) & TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_USED_Msk); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetRxReadPointer */ -/***************************************************************************//** -* -* Reads RX FIFO Read Pointer -* -* \param base The pointer to the I2S/TDM instance address. -* -* \return The current RX Read pointer value. -* -*******************************************************************************/ -__STATIC_INLINE uint8_t Cy_AudioTDM_GetRxReadPointer( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_FIFO_STATUS(base) & TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_RD_PTR_Msk); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetRxWritePointer */ -/***************************************************************************//** -* -* Reads RX FIFO Write Pointer -* -* \param base The pointer to the I2S/TDM instance address. -* -* \return The current RX Write pointer value. -* -*******************************************************************************/ -__STATIC_INLINE uint8_t Cy_AudioTDM_GetRxWritePointer( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_FIFO_STATUS(base) & TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_WR_PTR_Msk); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_EnableRxTestMode */ -/***************************************************************************//** -* -* Enables Test mode (intended to be used with (master transmitter, slave receiver) configuration). -* Both TX and RX should not be set in Test mode simultaneously. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_EnableRxTestMode( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_TEST_CTL(base) |= TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_TEST_CTL_ENABLED_Msk; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_DisableRxTestMode */ -/***************************************************************************//** -* -* Disable RX test mode -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_DisableRxTestMode( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_TEST_CTL(base) &= ~TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_TEST_CTL_ENABLED_Msk; - TDM_STRUCT_RX_TEST_CTL(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_TEST_CTL_ENABLED, 0u); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ClearTxInterrupt */ -/***************************************************************************//** -* -* Clear TX interrupt -* -* \param base The pointer to the I2S/TDM instance address. -* \param interrupt interrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_ClearTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); - - TDM_STRUCT_TX_INTR_TX(base) = interrupt; - (void) TDM_STRUCT_TX_INTR_TX(base); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_SetTxInterrupt */ -/***************************************************************************//** -* -* Set the Tx Interrupt -* -* \param base The pointer to the I2S/TDM instance address. -* \param interrupt interrupts to set. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_SetTxInterrupt( TDM_TX_STRUCT_Type * base, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); - - TDM_STRUCT_TX_INTR_TX_SET(base) = interrupt; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetTxInterruptMask */ -/***************************************************************************//** -* -* Get TX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_AudioTDM_GetTxInterruptMask( TDM_TX_STRUCT_Type * base) -{ - return (TDM_STRUCT_TX_INTR_TX_MASK(base)); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_SetTxInterruptMask */ -/***************************************************************************//** -* -* Set TX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* \param interrupt interrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_SetTxInterruptMask( TDM_TX_STRUCT_Type * base, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); - - TDM_STRUCT_TX_INTR_TX_MASK(base) = interrupt; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetTxInterruptStatusMasked */ -/***************************************************************************//** -* -* Reflects a bitwise AND between the INTR_TX and INTR_TX_MASK registers. -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_AudioTDM_GetTxInterruptStatusMasked( TDM_TX_STRUCT_Type * base) -{ - return (TDM_STRUCT_TX_INTR_TX_MASKED(base)); -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_SetTxTriggerInterruptMask */ -/***************************************************************************//** -* -* Sets TX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_SetTxTriggerInterruptMask( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_INTR_TX_MASK(base) |= TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_TRIGGER_Msk; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ClearTxTriggerInterruptMask */ -/***************************************************************************//** -* -* Clears TX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_ClearTxTriggerInterruptMask( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_INTR_TX_MASK(base) &= ~TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_TRIGGER_Msk; - TDM_STRUCT_TX_INTR_TX_MASK(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_TRIGGER, 0u); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ClearRxInterrupt */ -/***************************************************************************//** -* -* Clears RX interrupt -* -* \param base The pointer to the I2S/TDM instance address. -* \param interrupt interrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_ClearRxInterrupt( TDM_RX_STRUCT_Type * base, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt)); - - TDM_STRUCT_RX_INTR_RX(base) = interrupt; - (void) TDM_STRUCT_RX_INTR_RX(base); - -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_SetRxInterrupt */ -/***************************************************************************//** -* -* Sets RX interrupt -* -* \param base The pointer to the I2S/TDM instance address. -* \param interrupt interrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_SetRxInterrupt( TDM_RX_STRUCT_Type * base, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt)); - - TDM_STRUCT_RX_INTR_RX_SET(base) = interrupt; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetRxInterruptMask */ -/***************************************************************************//** -* -* Returns RX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_AudioTDM_GetRxInterruptMask( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_INTR_RX_MASK(base)); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_SetRxInterruptMask */ -/***************************************************************************//** -* -* Sets RX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* \param interrupt interrupt -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_SetRxInterruptMask( TDM_RX_STRUCT_Type * base, uint32_t interrupt) -{ - CY_ASSERT_L2(CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt)); - - TDM_STRUCT_RX_INTR_RX_MASK(base) = interrupt; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_GetRxInterruptStatusMasked */ -/***************************************************************************//** -* -* Returns a bitwise AND between the INTR_RX and INTR_RX_MASK registers -* -* \param base The pointer to the I2S/TDM instance address. -* -* \return The interrupt bit mask(s). -* -*******************************************************************************/ -__STATIC_INLINE uint32_t Cy_AudioTDM_GetRxInterruptStatusMasked( TDM_RX_STRUCT_Type * base) -{ - return (TDM_STRUCT_RX_INTR_RX_MASKED(base)); -} -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_SetRxTriggerInterruptMask */ -/***************************************************************************//** -* -* Sets Rx Interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_SetRxTriggerInterruptMask( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_INTR_RX_MASK(base) |= TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_TRIGGER_Msk; -} - -/***************************************************************************/ -/* Function Name: Cy_AudioTDM_ClearRxTriggerInterruptMask */ -/***************************************************************************//** -* -* Clear RX interrupt Mask -* -* \param base The pointer to the I2S/TDM instance address. -* -*******************************************************************************/ -__STATIC_INLINE void Cy_AudioTDM_ClearRxTriggerInterruptMask( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_INTR_RX_MASK(base) &= ~TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_TRIGGER_Msk; - TDM_STRUCT_RX_INTR_RX_MASK(base) |= _BOOL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_TRIGGER, 0u); -} - -/** \} group_tdm_functions */ - - -#if defined(__cplusplus) -} -#endif - -#endif /* (CY_TDM_H) */ - -/** \} group_tdm */ - -#endif /* CY_IP_MXTDM */ -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/edd_int.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/edd_int.h deleted file mode 100644 index eb3603a08a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/edd_int.h +++ /dev/null @@ -1,422 +0,0 @@ -/********************************************************************** - * copyright (C) 2014-2015 Cadence Design Systems - * All rights reserved. - *********************************************************************** - * edd_int.h - * Private declarations for Ethernet DMA-MAC Driver - * - ***********************************************************************/ -#ifndef _EDD_INT_H_ -#define _EDD_INT_H_ - -#include "cy_device_headers.h" -#include "cedi.h" - -#ifndef ETH_AXI_MASTER_PRESENT - // Assumed that if "ETH_AXI_MASTER_PRESENT" did not exist in Cypress header file, AXI is present. - #define ETH_AXI_MASTER_PRESENT 1 -#endif - -/****************************************************************************** - * Private Constants - *****************************************************************************/ - -#define GEM_GXL_MODULE_ID_V0 (0x0007) -#define GEM_GXL_MODULE_ID_V1 (0x0107) -#define GEM_XL_MODULE_ID (0x0008) - -#define XGM_GXL_MODULE_ID (0x000B) - -#define OFFLOADS_GEM_GXL_REV (0x0107) - -#define CEDI_MIN_TXBD 1 -#define CEDI_MIN_RXBD 1 - -#define MAX_JUMBO_FRAME_LENGTH (16383) - -/* Tx Descriptor flags/status - word 1 only */ -#define CEDI_TXD_LAST_BUF (1 << 15) -#define CEDI_TXD_NO_AUTO_CRC (1 << 16) -#define CEDI_TXD_UFO_ENABLE (1 << 17) -#define CEDI_TXD_TSO_ENABLE (1 << 18) -#define CEDI_TXD_AUTOSEQ_SEL (1 << 19) -#define CEDI_TXD_CHKOFF_SHIFT (20) -#define CEDI_TXD_CHKOFF_MASK (7 << CEDI_TXD_CHKOFF_SHIFT) -#define CEDI_TXD_TS_VALID (1 << 23) -#define CEDI_TXD_STREAM_SHIFT (24) -#define CEDI_TXD_STREAM_MASK (3 << CEDI_TXD_STREAM_SHIFT) -#define CEDI_TXD_LATE_COLL (1 << 26) -#define CEDI_TXD_FR_CORR (1 << 27) -#define CEDI_TXD_UNDERRUN (1 << 28) -#define CEDI_TXD_RETRY_EXC (1 << 29) -#define CEDI_TXD_WRAP (1 << 30) -#define CEDI_TXD_USED (1 << 31) -/* MSS/MFS only used on word 1 of 2nd descriptor */ -#define CEDI_TXD_MSSMFS_SHIFT (16) -#define CEDI_TXD_MSSMFS_MASK (0x3FFF << CEDI_TXD_MSSMFS_SHIFT) -#define CEDI_TXD_LEN_MASK ((1 << 14) - 1) - -/* Rx Descriptor flags - word 0 */ -#define CEDI_RXD_USED (1 << 0) -#define CEDI_RXD_WRAP (1 << 1) -#define CEDI_RXD_TS_VALID (1 << 2) -#define CEDI_RXD_ADDR_MASK (0xFFFFFFFC) -#define CEDI_RXD_ADDR_SHIFT (2) - -/* Rx Descriptor flags/status - word 1 */ -#define CEDI_RXD_LEN_MASK ((1 << 13) - 1) -/*** need to include bit 13 if jumbo frames enabled ***/ -#define CEDI_RXD_LEN13_FCS_STAT (1 << 13) -#define CEDI_RXD_SOF (1 << 14) -#define CEDI_RXD_EOF (1 << 15) -#define CEDI_RXD_CFI (1 << 16) -#define CEDI_RXD_VLAN_PRI_SHIFT (17) -#define CEDI_RXD_VLAN_PRI_MASK (7 << CEDI_RXD_VLAN_PRI_SHIFT) -/* if header-data splitting, these definitions are valid when not EOF: */ -#define CEDI_RXD_HDR (1 << 16) /* header buffer */ -#define CEDI_RXD_EOH (1 << 17) /* end of header */ - -#define CEDI_RXD_PRI_TAG (1 << 20) -#define CEDI_RXD_VLAN_TAG (1 << 21) - // either Type ID match register or - // (if Rx chksum offload enabled) checksum status -#define CEDI_RXD_TYP_IDR_CHK_STA_SHIFT (22) -#define CEDI_RXD_TYP_IDR_CHK_STA_MASK (3 << CEDI_RXD_TYP_IDR_CHK_STA_SHIFT) - // either Type ID matched or - // (if Rx chksum offload enabled) SNAP encoded and no CFI -#define CEDI_RXD_TYP_MAT_SNP_NCFI (1 << 24) -#define CEDI_RXD_SPEC_REG_SHIFT (25) -#define CEDI_RXD_SPEC_REG_MASK (3 << CEDI_RXD_SPEC_REG_SHIFT) -#define CEDI_RXD_SPEC_ADD_MAT (1 << 27) -#define CEDI_RXD_EXT_ADD_MAT (1 << 28) -#define CEDI_RXD_UNI_HASH_MAT (1 << 29) -#define CEDI_RXD_MULTI_HASH_MAT (1 << 30) -#define CEDI_RXD_BROADCAST_DET (1 << 31) - -/* For Tx/Rx time stamp extraction from descriptor words */ -#define CEDI_TS_NANO_SEC_MASK (0x3FFFFFFF) -#define CEDI_TS_SEC0_SHIFT (30) -#define CEDI_TS_SEC1_MASK (0x0F) -#define CEDI_TS_SEC1_POS_SHIFT (2) -#define CEDI_TS_SEC_WIDTH (6U) -#define CEDI_TS_SEC_TOP (1U << CEDI_TS_SEC_WIDTH) -#define CEDI_TS_SEC_MASK (CEDI_TS_SEC_TOP - 1U) - - - -#define CEDI_RXD_EMPTY (0xFFAA0000) - -#define CEDI_PHY_ADDR_OP (0) -#define CEDI_PHY_WRITE_OP (1) -#define CEDI_PHY_CL22_READ_OP (2) -#define CEDI_PHY_CL45_READ_INC_OP (2) -#define CEDI_PHY_CL45_READ_OP (3) - - -#define CEDI_TWO_BD_WORD_SIZE (8) // Size required for two buffer descriptor word (in bytes). -#define CEDI_BYTES_PER_WORD_SHIFT (2) // Shift variable for number of bytes in a word -#define CEDI_DESC_WORD_NUM_MAX (6) // Maximum number of words allowed in a descriptor. - -#define CEDI_AMBD_BURST_LEN_1 (0x01) // for CEDI_DMA_DBUR_LEN_1 -#define CEDI_AMBD_BURST_LEN_4 (0x04) // for CEDI_DMA_DBUR_LEN_4 -#define CEDI_AMBD_BURST_LEN_8 (0x08) // for CEDI_DMA_DBUR_LEN_8 -#define CEDI_AMBD_BURST_LEN_16 (0x10) // for CEDI_DMA_DBUR_LEN_16 - -/****************************************************************************** - * Local macros - assume pD is privateData parameter in function scope, and - * cfg has been initialised with register base address - *****************************************************************************/ - -/* access a privateData field, via the local void *pD parameter */ -#define CEDI_PdVar(var) (((CEDI_PrivateData *)pD)->var) -/* get register address via the privateDat->cfg.regBase field */ -#define CEDI_RegAddr(reg) (&(((struct emac_regs *)(CEDI_PdVar(cfg).regBase))->reg)) - -/****************************************************************************** - * Types - *****************************************************************************/ - -/* Tx Descriptor defs */ -typedef struct { - uint32_t word[CEDI_DESC_WORD_NUM_MAX]; -} txDesc; - -typedef struct { - txDesc *bdBase; // base address of descriptor ring - txDesc *bdHead; // first available descriptor - txDesc *bdTail; // first descriptor waiting to be freed - txDesc *bd1stBuf; // first buffer of current frame - uint16_t descMax; // total number of descriptors - uint16_t descFree; // number of descriptors that can accept buffers - uintptr_t *vHead; // virt address corresponding to head BD - uintptr_t *vTail; // end of virt address circular array - uintptr_t *vAddrList; // pointer to virt addresses storage - uint8_t firstToFree; // flag indicating stage of frame clean-up: set - // when about to clear first buffer of frame - uint8_t descNum; // descriptor counter used by qTxBuf: stays at 0 until - // start 2nd desc of frame, then inc to 1, etc. -} txQueue_t; - -/* Rx Descriptor defs */ -typedef struct { - uint32_t word[CEDI_DESC_WORD_NUM_MAX]; -} rxDesc; - -typedef struct { - rxDesc *rxDescStart; // start of Rx descriptor list - rxDesc *rxDescStop; // end-stop Rx descriptor, trails behind "Tail"; - // always kept "used" but with no buffer - rxDesc *rxDescTail; // next Rx descriptor to process (one after end-stop) - rxDesc *rxDescEnd; // last descriptor in Rx list - uint16_t numRxDesc; // total number of descriptors in the list, - // including unused end-stop - uint16_t numRxBufs; // number of useable buffers/descriptors in list - uintptr_t *rxTailVA; // tail Rx virtual addr - uintptr_t *rxStopVA; // end-stop Rx virtual addr, corr. to rxDescStop - uintptr_t *rxEndVA; // end Rx virtual addr - uintptr_t *rxBufVAddr; // list of buffer virtual addresses in sync - // with physical addresses held in descriptor lists -} rxQueue_t; - -/* Driver private data - place the tx & rx virtual address lists after this - * (with these included in privateData memory requirement) */ -typedef struct { - CEDI_Config cfg; // copy of CEDI_Config info supplied to init - CEDI_Callbacks cb; // pointers to callback functions - CEDI_DesignCfg hwCfg; // copy of DesignCfg Debug registers - uint8_t numQs; // number of Qs in this h/w config. - txQueue_t txQueue[CEDI_MAX_TX_QUEUES]; // tx queue info - rxQueue_t rxQueue[CEDI_MAX_RX_QUEUES]; // rx queue info -// CPS_LockHandle isrLock; // lock used during isr calls - uint8_t anLinkStat; // retain link status (low) until read - uint8_t anRemFault; // retain link partner remote fault status - // (high) until read - uint8_t autoNegActive; // auto-negotiation in progress flag - uint8_t basePageExp; // data expected from link partner: set - // initially to indicate base page, clear - // after first received to denote next page - // expected. Set on start auto-negotiation. - - CEDI_LpPageRx lpPageRx; // reserved for passing page Rx in callback - CEDI_NetAnStatus anStatus; // reserved for a-n status in callback - CEDI_1588TimerVal ptpTime; // reserved for passing ptp event times -// CPS_LockHandle autoNegLock; // lock to protect auto-neg flags and next - // page register when isr writes null - // message page - uint16_t txDescriptorSize; // bytes per Tx descriptor - uint16_t rxDescriptorSize; // bytes per Rx descriptor -} CEDI_PrivateData; - - -/*********************** Internal Driver functions ***************************/ - -uint32_t initRxDescLists(void *pD); -uint32_t subNsTsuInc24bSupport(void *pD); - -/* Driver API function prototypes (only required if called within API) */ - -uint32_t emacSetEventEnable(void *pD, uint32_t events, uint8_t enable, - uint8_t queueNum); -uint32_t emacResetPcs(void *pD); -uint32_t emacWriteUserOutputs(void *pD, uint16_t outVal); -uint32_t emacGetJumboFramesRx(void *pD, uint8_t *enable); -uint32_t emacGetJumboFrameRxMaxLen(void *pD, uint16_t *length); -uint32_t emacGet1536ByteFramesRx(void *pD, uint8_t *enable); -uint32_t emacGetPtpFrameTxTime(void *pD, CEDI_1588TimerVal *time); -uint32_t emacGetPtpFrameRxTime(void *pD, CEDI_1588TimerVal *time); -uint32_t emacGetPtpPeerFrameTxTime(void *pD, CEDI_1588TimerVal *time); -uint32_t emacGetPtpPeerFrameRxTime(void *pD, CEDI_1588TimerVal *time); -uint32_t emacClearStats(void *pD); - -uint32_t emacSetAutoNegEnable(void *pD, uint8_t enable); -uint32_t emacGetPcsReady(void *pD, uint8_t *ready); -uint32_t emacGetLinkStatus(void *pD, uint8_t *status); -uint32_t emacSetAnAdvPage(void *pD, CEDI_AnAdvPage *advDat); -uint32_t emacGetLpAbilityPage(void *pD, CEDI_LpAbilityPage *lpAbl); -uint32_t emacGetLpNextPage(void *pD, CEDI_LpNextPage *npDat); -uint32_t emacSetNextPageTx(void *pD, CEDI_AnNextPage *npDat); - -/****************** API Prototypes for other source modules ******************/ - -/****************************** edd_tx.c *************************************/ - -uint32_t emacCalcMaxTxFrameSize(void *pD, CEDI_FrameSize *maxTxSize); - -uint32_t emacQueueTxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *bufAdd, - uint32_t length, uint8_t flags); - -uint32_t emacQTxBuf(void *pD, CEDI_qTxBufParams *prm); - -uint32_t emacDeQTxBuf(void *pD, CEDI_qTxBufParams *prm); - -uint32_t emacTxDescFree(void *pD, uint8_t queueNum, uint16_t *numFree); - -uint32_t emacFreeTxDesc(void *pD, uint8_t queueNum, CEDI_TxDescData *descData); - -void emacGetTxDescStat(void *pD, uint32_t txDStatWord, CEDI_TxDescStat *txDStat); - -void emacGetTxDescSize(void *pD, uint32_t *txDescSize); - -uint32_t emacResetTxQ(void *pD, uint8_t queueNum); - -uint32_t emacStartTx(void *pD); - -void emacStopTx(void *pD); - -void emacAbortTx(void *pD); - -uint32_t emacTransmitting(void *pD); - -void emacEnableTx(void *pD); - -uint32_t emacGetTxEnabled(void *pD); - -uint32_t emacGetTxStatus(void *pD, CEDI_TxStatus *status); - -void emacClearTxStatus(void *pD, uint32_t resetStatus); - -uint32_t emacSetTxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable); - -uint32_t emacGetTxPartialStFwd(void *pD, uint32_t *watermark, uint8_t *enable); - - -uint32_t emacEnableCbs(void *pD, uint8_t qSel, uint32_t idleSlope); - -void emacDisableCbs(void *pD, uint8_t qSel); - -uint32_t emacGetCbsQSetting(void *pD, uint8_t qSel, - uint8_t *enable, uint32_t *idleSlope); - - -uint32_t emacSetIpgStretch(void *pD, uint8_t enable, uint8_t multiplier, - uint8_t divisor); - -uint32_t emacGetIpgStretch(void *pD, uint8_t *enabled, uint8_t *multiplier, - uint8_t *divisor); - - - -/****************************** edd_rx.c *************************************/ - -uint32_t emacCalcMaxRxFrameSize(void *pD, uint32_t *maxSize); - -uint32_t emacAddRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf, - uint8_t init); - -uint32_t emacNumRxBufs(void *pD, uint8_t queueNum, uint16_t *numBufs); - -uint32_t emacNumRxUsed(void *pD, uint8_t queueNum); - -uint32_t emacReadRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf, - uint8_t init, CEDI_RxDescData *descData); - -void emacGetRxDescStat(void *pD, uint32_t rxDStatWord, CEDI_RxDescStat *rxDStat); - -void emacGetRxDescSize(void *pD, uint32_t *rxDescSize); - -uint32_t emacRxEnabled(void *pD); - -void emacEnableRx(void *pD); - -void emacDisableRx(void *pD); - -uint32_t emacRemoveRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf); - -void emacFindQBaseAddr(void *pD, uint8_t queueNum, rxQueue_t *rxQ, - uint32_t *pAddr, uintptr_t *vAddr); - -uint32_t emacResetRxQ(void *pD, uint8_t queueNum, uint8_t ptrsOnly); - -uint32_t emacGetRxStatus(void *pD, CEDI_RxStatus *status); - -void emacClearRxStatus(void *pD, uint32_t resetStatus); - - -uint32_t emacSetHdrDataSplit(void *pD, uint8_t enable); - -uint32_t emacGetHdrDataSplit(void *pD, uint8_t *enable); - -uint32_t emacSetRscEnable(void *pD, uint8_t queue, uint8_t enable); - -uint32_t emacGetRscEnable(void *pD, uint8_t queue, uint8_t *enable); - -uint32_t emacSetRscClearMask(void *pD, uint8_t setMask); - - -uint32_t emacSetRxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable); - -uint32_t emacGetRxPartialStFwd(void *pD, uint32_t *watermark, uint8_t *enable); - -uint32_t emacSetSpecificAddr(void *pD, uint8_t addrNum, CEDI_MacAddress *addr, - uint8_t specFilterType,uint8_t byteMask); - -uint32_t emacGetSpecificAddr(void *pD, uint8_t addrNum, CEDI_MacAddress *addr, - uint8_t *specFilterType, uint8_t *byteMask); - -uint32_t emacSetSpecificAddr1Mask(void *pD, CEDI_MacAddress *mask); - -uint32_t emacGetSpecificAddr1Mask(void *pD, CEDI_MacAddress *mask); - -uint32_t emacDisableSpecAddr(void *pD, uint8_t addrNum); - -uint32_t emacSetTypeIdMatch(void *pD, uint8_t matchSel, uint16_t typeId, - uint8_t enable); - -uint32_t emacGetTypeIdMatch(void *pD, uint8_t matchSel, uint16_t *typeId, - uint8_t *enabled); - -void emacSetUnicastEnable(void *pD, uint8_t enable); - -uint32_t emacGetUnicastEnable(void *pD, uint8_t *enable); - -void emacSetMulticastEnable(void *pD, uint8_t enable); - -uint32_t emacGetMulticastEnable(void *pD, uint8_t *enable); - -void emacSetNoBroadcast(void *pD, uint8_t reject); - -uint32_t emacGetNoBroadcast(void *pD, uint8_t *reject); - -void emacSetVlanOnly(void *pD, uint8_t enable); - -uint32_t emacGetVlanOnly(void *pD, uint8_t *enable); - -void emacSetStackedVlanReg(void *pD, uint8_t enable, uint16_t vlanType); - -void emacGetStackedVlanReg(void *pD, uint8_t *enable, uint16_t *vlanType); - -void emacSetCopyAllFrames(void *pD, uint8_t enable); - -uint32_t emacGetCopyAllFrames(void *pD, uint8_t *enable); - -uint32_t emacSetHashAddr(void *pD, uint32_t hAddrTop, uint32_t hAddrBot); - -uint32_t emacGetHashAddr(void *pD, uint32_t *hAddrTop, uint32_t *hAddrBot); - -void emacSetLenErrDiscard(void *pD, uint8_t enable); - -uint32_t emacGetLenErrDiscard(void *pD, uint8_t *enable); - - -uint32_t emacGetNumScreenRegs(void *pD, CEDI_NumScreeners *regNums); - -uint32_t emacSetType1ScreenReg(void *pD, uint8_t regNum, CEDI_T1Screen *regVals); - -uint32_t emacGetType1ScreenReg(void *pD, uint8_t regNum, CEDI_T1Screen *regVals); - -uint32_t emacSetType2ScreenReg(void *pD, uint8_t regNum, CEDI_T2Screen *regVals); - -uint32_t emacGetType2ScreenReg(void *pD, uint8_t regNum, CEDI_T2Screen *regVals); - -uint32_t emacSetType2EthertypeReg(void *pD, uint8_t index, uint16_t eTypeVal); - -uint32_t emacGetType2EthertypeReg(void *pD, uint8_t index, uint16_t *eTypeVal); - -uint32_t emacSetType2CompareReg(void *pD, uint8_t index, - CEDI_T2Compare *regVals); - -uint32_t emacGetType2CompareReg(void *pD, uint8_t index, - CEDI_T2Compare *regVals); - - -#endif /* multiple inclusion protection */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/emac_regs.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/emac_regs.h deleted file mode 100644 index 42908ad5af..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/emac_regs.h +++ /dev/null @@ -1,502 +0,0 @@ -/* Copyright (C) 2016 Cadence Design Systems. All rights reserved */ -/* THIS FILE IS AUTOMATICALLY GENERATED BY CADENCE BLUEPRINT, DO NOT EDIT */ -/* */ - - -#ifndef __REG_EMAC_REGS_H__ -#define __REG_EMAC_REGS_H__ - -#include "emac_regs_macro.h" - -#ifndef __REG_EMAC_REGS__ -#define __REG_EMAC_REGS__ - -struct emac_regs { - volatile uint32_t network_control; /* 0x0 - 0x4 */ - volatile uint32_t network_config; /* 0x4 - 0x8 */ - volatile uint32_t network_status; /* 0x8 - 0xc */ - volatile uint32_t user_io_register; /* 0xc - 0x10 */ - volatile uint32_t dma_config; /* 0x10 - 0x14 */ - volatile uint32_t transmit_status; /* 0x14 - 0x18 */ - volatile uint32_t receive_q_ptr; /* 0x18 - 0x1c */ - volatile uint32_t transmit_q_ptr; /* 0x1c - 0x20 */ - volatile uint32_t receive_status; /* 0x20 - 0x24 */ - volatile uint32_t int_status; /* 0x24 - 0x28 */ - volatile uint32_t int_enable; /* 0x28 - 0x2c */ - volatile uint32_t int_disable; /* 0x2c - 0x30 */ - volatile uint32_t int_mask; /* 0x30 - 0x34 */ - volatile uint32_t phy_management; /* 0x34 - 0x38 */ - volatile uint32_t pause_time; /* 0x38 - 0x3c */ - volatile uint32_t tx_pause_quantum; /* 0x3c - 0x40 */ - volatile uint32_t pbuf_txcutthru; /* 0x40 - 0x44 */ - volatile uint32_t pbuf_rxcutthru; /* 0x44 - 0x48 */ - volatile uint32_t jumbo_max_length; /* 0x48 - 0x4c */ - volatile uint32_t external_fifo_interface; /* 0x4c - 0x50 */ - volatile char pad__0[0x4]; /* 0x50 - 0x54 */ - volatile uint32_t axi_max_pipeline; /* 0x54 - 0x58 */ - volatile uint32_t rsc_control; /* 0x58 - 0x5c */ - volatile uint32_t int_moderation; /* 0x5c - 0x60 */ - volatile uint32_t sys_wake_time; /* 0x60 - 0x64 */ - volatile char pad__1[0x1c]; /* 0x64 - 0x80 */ - volatile uint32_t hash_bottom; /* 0x80 - 0x84 */ - volatile uint32_t hash_top; /* 0x84 - 0x88 */ - volatile uint32_t spec_add1_bottom; /* 0x88 - 0x8c */ - volatile uint32_t spec_add1_top; /* 0x8c - 0x90 */ - volatile uint32_t spec_add2_bottom; /* 0x90 - 0x94 */ - volatile uint32_t spec_add2_top; /* 0x94 - 0x98 */ - volatile uint32_t spec_add3_bottom; /* 0x98 - 0x9c */ - volatile uint32_t spec_add3_top; /* 0x9c - 0xa0 */ - volatile uint32_t spec_add4_bottom; /* 0xa0 - 0xa4 */ - volatile uint32_t spec_add4_top; /* 0xa4 - 0xa8 */ - volatile uint32_t spec_type1; /* 0xa8 - 0xac */ - volatile uint32_t spec_type2; /* 0xac - 0xb0 */ - volatile uint32_t spec_type3; /* 0xb0 - 0xb4 */ - volatile uint32_t spec_type4; /* 0xb4 - 0xb8 */ - volatile uint32_t wol_register; /* 0xb8 - 0xbc */ - volatile uint32_t stretch_ratio; /* 0xbc - 0xc0 */ - volatile uint32_t stacked_vlan; /* 0xc0 - 0xc4 */ - volatile uint32_t tx_pfc_pause; /* 0xc4 - 0xc8 */ - volatile uint32_t mask_add1_bottom; /* 0xc8 - 0xcc */ - volatile uint32_t mask_add1_top; /* 0xcc - 0xd0 */ - volatile uint32_t dma_addr_or_mask; /* 0xd0 - 0xd4 */ - volatile uint32_t rx_ptp_unicast; /* 0xd4 - 0xd8 */ - volatile uint32_t tx_ptp_unicast; /* 0xd8 - 0xdc */ - volatile uint32_t tsu_nsec_cmp; /* 0xdc - 0xe0 */ - volatile uint32_t tsu_sec_cmp; /* 0xe0 - 0xe4 */ - volatile uint32_t tsu_msb_sec_cmp; /* 0xe4 - 0xe8 */ - volatile uint32_t tsu_ptp_tx_msb_sec; /* 0xe8 - 0xec */ - volatile uint32_t tsu_ptp_rx_msb_sec; /* 0xec - 0xf0 */ - volatile uint32_t tsu_peer_tx_msb_sec; /* 0xf0 - 0xf4 */ - volatile uint32_t tsu_peer_rx_msb_sec; /* 0xf4 - 0xf8 */ - volatile uint32_t dpram_fill_dbg; /* 0xf8 - 0xfc */ - volatile uint32_t revision_reg; /* 0xfc - 0x100 */ - volatile uint32_t octets_txed_bottom; /* 0x100 - 0x104 */ - volatile uint32_t octets_txed_top; /* 0x104 - 0x108 */ - volatile uint32_t frames_txed_ok; /* 0x108 - 0x10c */ - volatile uint32_t broadcast_txed; /* 0x10c - 0x110 */ - volatile uint32_t multicast_txed; /* 0x110 - 0x114 */ - volatile uint32_t pause_frames_txed; /* 0x114 - 0x118 */ - volatile uint32_t frames_txed_64; /* 0x118 - 0x11c */ - volatile uint32_t frames_txed_65; /* 0x11c - 0x120 */ - volatile uint32_t frames_txed_128; /* 0x120 - 0x124 */ - volatile uint32_t frames_txed_256; /* 0x124 - 0x128 */ - volatile uint32_t frames_txed_512; /* 0x128 - 0x12c */ - volatile uint32_t frames_txed_1024; /* 0x12c - 0x130 */ - volatile uint32_t frames_txed_1519; /* 0x130 - 0x134 */ - volatile uint32_t tx_underruns; /* 0x134 - 0x138 */ - volatile uint32_t single_collisions; /* 0x138 - 0x13c */ - volatile uint32_t multiple_collisions; /* 0x13c - 0x140 */ - volatile uint32_t excessive_collisions; /* 0x140 - 0x144 */ - volatile uint32_t late_collisions; /* 0x144 - 0x148 */ - volatile uint32_t deferred_frames; /* 0x148 - 0x14c */ - volatile uint32_t crs_errors; /* 0x14c - 0x150 */ - volatile uint32_t octets_rxed_bottom; /* 0x150 - 0x154 */ - volatile uint32_t octets_rxed_top; /* 0x154 - 0x158 */ - volatile uint32_t frames_rxed_ok; /* 0x158 - 0x15c */ - volatile uint32_t broadcast_rxed; /* 0x15c - 0x160 */ - volatile uint32_t multicast_rxed; /* 0x160 - 0x164 */ - volatile uint32_t pause_frames_rxed; /* 0x164 - 0x168 */ - volatile uint32_t frames_rxed_64; /* 0x168 - 0x16c */ - volatile uint32_t frames_rxed_65; /* 0x16c - 0x170 */ - volatile uint32_t frames_rxed_128; /* 0x170 - 0x174 */ - volatile uint32_t frames_rxed_256; /* 0x174 - 0x178 */ - volatile uint32_t frames_rxed_512; /* 0x178 - 0x17c */ - volatile uint32_t frames_rxed_1024; /* 0x17c - 0x180 */ - volatile uint32_t frames_rxed_1519; /* 0x180 - 0x184 */ - volatile uint32_t undersize_frames; /* 0x184 - 0x188 */ - volatile uint32_t excessive_rx_length; /* 0x188 - 0x18c */ - volatile uint32_t rx_jabbers; /* 0x18c - 0x190 */ - volatile uint32_t fcs_errors; /* 0x190 - 0x194 */ - volatile uint32_t rx_length_errors; /* 0x194 - 0x198 */ - volatile uint32_t rx_symbol_errors; /* 0x198 - 0x19c */ - volatile uint32_t alignment_errors; /* 0x19c - 0x1a0 */ - volatile uint32_t rx_resource_errors; /* 0x1a0 - 0x1a4 */ - volatile uint32_t rx_overruns; /* 0x1a4 - 0x1a8 */ - volatile uint32_t rx_ip_ck_errors; /* 0x1a8 - 0x1ac */ - volatile uint32_t rx_tcp_ck_errors; /* 0x1ac - 0x1b0 */ - volatile uint32_t rx_udp_ck_errors; /* 0x1b0 - 0x1b4 */ - volatile uint32_t auto_flushed_pkts; /* 0x1b4 - 0x1b8 */ - volatile char pad__2[0x4]; /* 0x1b8 - 0x1bc */ - volatile uint32_t tsu_timer_incr_sub_nsec; /* 0x1bc - 0x1c0 */ - volatile uint32_t tsu_timer_msb_sec; /* 0x1c0 - 0x1c4 */ - volatile uint32_t tsu_strobe_msb_sec; /* 0x1c4 - 0x1c8 */ - volatile uint32_t tsu_strobe_sec; /* 0x1c8 - 0x1cc */ - volatile uint32_t tsu_strobe_nsec; /* 0x1cc - 0x1d0 */ - volatile uint32_t tsu_timer_sec; /* 0x1d0 - 0x1d4 */ - volatile uint32_t tsu_timer_nsec; /* 0x1d4 - 0x1d8 */ - volatile uint32_t tsu_timer_adjust; /* 0x1d8 - 0x1dc */ - volatile uint32_t tsu_timer_incr; /* 0x1dc - 0x1e0 */ - volatile uint32_t tsu_ptp_tx_sec; /* 0x1e0 - 0x1e4 */ - volatile uint32_t tsu_ptp_tx_nsec; /* 0x1e4 - 0x1e8 */ - volatile uint32_t tsu_ptp_rx_sec; /* 0x1e8 - 0x1ec */ - volatile uint32_t tsu_ptp_rx_nsec; /* 0x1ec - 0x1f0 */ - volatile uint32_t tsu_peer_tx_sec; /* 0x1f0 - 0x1f4 */ - volatile uint32_t tsu_peer_tx_nsec; /* 0x1f4 - 0x1f8 */ - volatile uint32_t tsu_peer_rx_sec; /* 0x1f8 - 0x1fc */ - volatile uint32_t tsu_peer_rx_nsec; /* 0x1fc - 0x200 */ - volatile uint32_t pcs_control; /* 0x200 - 0x204 */ - volatile uint32_t pcs_status; /* 0x204 - 0x208 */ - volatile char pad__3[0x8]; /* 0x208 - 0x210 */ - volatile uint32_t pcs_an_adv; /* 0x210 - 0x214 */ - volatile uint32_t pcs_an_lp_base; /* 0x214 - 0x218 */ - volatile uint32_t pcs_an_exp; /* 0x218 - 0x21c */ - volatile uint32_t pcs_an_np_tx; /* 0x21c - 0x220 */ - volatile uint32_t pcs_an_lp_np; /* 0x220 - 0x224 */ - volatile char pad__4[0x18]; /* 0x224 - 0x23c */ - volatile uint32_t pcs_an_ext_status; /* 0x23c - 0x240 */ - volatile char pad__5[0x20]; /* 0x240 - 0x260 */ - volatile uint32_t tx_pause_quantum1; /* 0x260 - 0x264 */ - volatile uint32_t tx_pause_quantum2; /* 0x264 - 0x268 */ - volatile uint32_t tx_pause_quantum3; /* 0x268 - 0x26c */ - volatile char pad__6[0x4]; /* 0x26c - 0x270 */ - volatile uint32_t rx_lpi; /* 0x270 - 0x274 */ - volatile uint32_t rx_lpi_time; /* 0x274 - 0x278 */ - volatile uint32_t tx_lpi; /* 0x278 - 0x27c */ - volatile uint32_t tx_lpi_time; /* 0x27c - 0x280 */ - volatile uint32_t designcfg_debug1; /* 0x280 - 0x284 */ - volatile uint32_t designcfg_debug2; /* 0x284 - 0x288 */ - volatile uint32_t designcfg_debug3; /* 0x288 - 0x28c */ - volatile uint32_t designcfg_debug4; /* 0x28c - 0x290 */ - volatile uint32_t designcfg_debug5; /* 0x290 - 0x294 */ - volatile uint32_t designcfg_debug6; /* 0x294 - 0x298 */ - volatile uint32_t designcfg_debug7; /* 0x298 - 0x29c */ - volatile uint32_t designcfg_debug8; /* 0x29c - 0x2a0 */ - volatile uint32_t designcfg_debug9; /* 0x2a0 - 0x2a4 */ - volatile uint32_t designcfg_debug10; /* 0x2a4 - 0x2a8 */ - volatile char pad__7[0x58]; /* 0x2a8 - 0x300 */ - volatile uint32_t spec_add5_bottom; /* 0x300 - 0x304 */ - volatile uint32_t spec_add5_top; /* 0x304 - 0x308 */ - volatile uint32_t spec_add6_bottom; /* 0x308 - 0x30c */ - volatile uint32_t spec_add6_top; /* 0x30c - 0x310 */ - volatile uint32_t spec_add7_bottom; /* 0x310 - 0x314 */ - volatile uint32_t spec_add7_top; /* 0x314 - 0x318 */ - volatile uint32_t spec_add8_bottom; /* 0x318 - 0x31c */ - volatile uint32_t spec_add8_top; /* 0x31c - 0x320 */ - volatile uint32_t spec_add9_bottom; /* 0x320 - 0x324 */ - volatile uint32_t spec_add9_top; /* 0x324 - 0x328 */ - volatile uint32_t spec_add10_bottom; /* 0x328 - 0x32c */ - volatile uint32_t spec_add10_top; /* 0x32c - 0x330 */ - volatile uint32_t spec_add11_bottom; /* 0x330 - 0x334 */ - volatile uint32_t spec_add11_top; /* 0x334 - 0x338 */ - volatile uint32_t spec_add12_bottom; /* 0x338 - 0x33c */ - volatile uint32_t spec_add12_top; /* 0x33c - 0x340 */ - volatile uint32_t spec_add13_bottom; /* 0x340 - 0x344 */ - volatile uint32_t spec_add13_top; /* 0x344 - 0x348 */ - volatile uint32_t spec_add14_bottom; /* 0x348 - 0x34c */ - volatile uint32_t spec_add14_top; /* 0x34c - 0x350 */ - volatile uint32_t spec_add15_bottom; /* 0x350 - 0x354 */ - volatile uint32_t spec_add15_top; /* 0x354 - 0x358 */ - volatile uint32_t spec_add16_bottom; /* 0x358 - 0x35c */ - volatile uint32_t spec_add16_top; /* 0x35c - 0x360 */ - volatile uint32_t spec_add17_bottom; /* 0x360 - 0x364 */ - volatile uint32_t spec_add17_top; /* 0x364 - 0x368 */ - volatile uint32_t spec_add18_bottom; /* 0x368 - 0x36c */ - volatile uint32_t spec_add18_top; /* 0x36c - 0x370 */ - volatile uint32_t spec_add19_bottom; /* 0x370 - 0x374 */ - volatile uint32_t spec_add19_top; /* 0x374 - 0x378 */ - volatile uint32_t spec_add20_bottom; /* 0x378 - 0x37c */ - volatile uint32_t spec_add20_top; /* 0x37c - 0x380 */ - volatile uint32_t spec_add21_bottom; /* 0x380 - 0x384 */ - volatile uint32_t spec_add21_top; /* 0x384 - 0x388 */ - volatile uint32_t spec_add22_bottom; /* 0x388 - 0x38c */ - volatile uint32_t spec_add22_top; /* 0x38c - 0x390 */ - volatile uint32_t spec_add23_bottom; /* 0x390 - 0x394 */ - volatile uint32_t spec_add23_top; /* 0x394 - 0x398 */ - volatile uint32_t spec_add24_bottom; /* 0x398 - 0x39c */ - volatile uint32_t spec_add24_top; /* 0x39c - 0x3a0 */ - volatile uint32_t spec_add25_bottom; /* 0x3a0 - 0x3a4 */ - volatile uint32_t spec_add25_top; /* 0x3a4 - 0x3a8 */ - volatile uint32_t spec_add26_bottom; /* 0x3a8 - 0x3ac */ - volatile uint32_t spec_add26_top; /* 0x3ac - 0x3b0 */ - volatile uint32_t spec_add27_bottom; /* 0x3b0 - 0x3b4 */ - volatile uint32_t spec_add27_top; /* 0x3b4 - 0x3b8 */ - volatile uint32_t spec_add28_bottom; /* 0x3b8 - 0x3bc */ - volatile uint32_t spec_add28_top; /* 0x3bc - 0x3c0 */ - volatile uint32_t spec_add29_bottom; /* 0x3c0 - 0x3c4 */ - volatile uint32_t spec_add29_top; /* 0x3c4 - 0x3c8 */ - volatile uint32_t spec_add30_bottom; /* 0x3c8 - 0x3cc */ - volatile uint32_t spec_add30_top; /* 0x3cc - 0x3d0 */ - volatile uint32_t spec_add31_bottom; /* 0x3d0 - 0x3d4 */ - volatile uint32_t spec_add31_top; /* 0x3d4 - 0x3d8 */ - volatile uint32_t spec_add32_bottom; /* 0x3d8 - 0x3dc */ - volatile uint32_t spec_add32_top; /* 0x3dc - 0x3e0 */ - volatile uint32_t spec_add33_bottom; /* 0x3e0 - 0x3e4 */ - volatile uint32_t spec_add33_top; /* 0x3e4 - 0x3e8 */ - volatile uint32_t spec_add34_bottom; /* 0x3e8 - 0x3ec */ - volatile uint32_t spec_add34_top; /* 0x3ec - 0x3f0 */ - volatile uint32_t spec_add35_bottom; /* 0x3f0 - 0x3f4 */ - volatile uint32_t spec_add35_top; /* 0x3f4 - 0x3f8 */ - volatile uint32_t spec_add36_bottom; /* 0x3f8 - 0x3fc */ - volatile uint32_t spec_add36_top; /* 0x3fc - 0x400 */ - volatile uint32_t int_q1_status; /* 0x400 - 0x404 */ - volatile uint32_t int_q2_status; /* 0x404 - 0x408 */ - volatile uint32_t int_q3_status; /* 0x408 - 0x40c */ - volatile uint32_t int_q4_status; /* 0x40c - 0x410 */ - volatile uint32_t int_q5_status; /* 0x410 - 0x414 */ - volatile uint32_t int_q6_status; /* 0x414 - 0x418 */ - volatile uint32_t int_q7_status; /* 0x418 - 0x41c */ - volatile uint32_t int_q8_status; /* 0x41c - 0x420 */ - volatile uint32_t int_q9_status; /* 0x420 - 0x424 */ - volatile uint32_t int_q10_status; /* 0x424 - 0x428 */ - volatile uint32_t int_q11_status; /* 0x428 - 0x42c */ - volatile uint32_t int_q12_status; /* 0x42c - 0x430 */ - volatile uint32_t int_q13_status; /* 0x430 - 0x434 */ - volatile uint32_t int_q14_status; /* 0x434 - 0x438 */ - volatile uint32_t int_q15_status; /* 0x438 - 0x43c */ - volatile char pad__8[0x4]; /* 0x43c - 0x440 */ - volatile uint32_t transmit_q1_ptr; /* 0x440 - 0x444 */ - volatile uint32_t transmit_q2_ptr; /* 0x444 - 0x448 */ - volatile uint32_t transmit_q3_ptr; /* 0x448 - 0x44c */ - volatile uint32_t transmit_q4_ptr; /* 0x44c - 0x450 */ - volatile uint32_t transmit_q5_ptr; /* 0x450 - 0x454 */ - volatile uint32_t transmit_q6_ptr; /* 0x454 - 0x458 */ - volatile uint32_t transmit_q7_ptr; /* 0x458 - 0x45c */ - volatile uint32_t transmit_q8_ptr; /* 0x45c - 0x460 */ - volatile uint32_t transmit_q9_ptr; /* 0x460 - 0x464 */ - volatile uint32_t transmit_q10_ptr; /* 0x464 - 0x468 */ - volatile uint32_t transmit_q11_ptr; /* 0x468 - 0x46c */ - volatile uint32_t transmit_q12_ptr; /* 0x46c - 0x470 */ - volatile uint32_t transmit_q13_ptr; /* 0x470 - 0x474 */ - volatile uint32_t transmit_q14_ptr; /* 0x474 - 0x478 */ - volatile uint32_t transmit_q15_ptr; /* 0x478 - 0x47c */ - volatile char pad__9[0x4]; /* 0x47c - 0x480 */ - volatile uint32_t receive_q1_ptr; /* 0x480 - 0x484 */ - volatile uint32_t receive_q2_ptr; /* 0x484 - 0x488 */ - volatile uint32_t receive_q3_ptr; /* 0x488 - 0x48c */ - volatile uint32_t receive_q4_ptr; /* 0x48c - 0x490 */ - volatile uint32_t receive_q5_ptr; /* 0x490 - 0x494 */ - volatile uint32_t receive_q6_ptr; /* 0x494 - 0x498 */ - volatile uint32_t receive_q7_ptr; /* 0x498 - 0x49c */ - volatile char pad__10[0x4]; /* 0x49c - 0x4a0 */ - volatile uint32_t dma_rxbuf_size_q1; /* 0x4a0 - 0x4a4 */ - volatile uint32_t dma_rxbuf_size_q2; /* 0x4a4 - 0x4a8 */ - volatile uint32_t dma_rxbuf_size_q3; /* 0x4a8 - 0x4ac */ - volatile uint32_t dma_rxbuf_size_q4; /* 0x4ac - 0x4b0 */ - volatile uint32_t dma_rxbuf_size_q5; /* 0x4b0 - 0x4b4 */ - volatile uint32_t dma_rxbuf_size_q6; /* 0x4b4 - 0x4b8 */ - volatile uint32_t dma_rxbuf_size_q7; /* 0x4b8 - 0x4bc */ - volatile uint32_t cbs_control; /* 0x4bc - 0x4c0 */ - volatile uint32_t cbs_idleslope_q_a; /* 0x4c0 - 0x4c4 */ - volatile uint32_t cbs_idleslope_q_b; /* 0x4c4 - 0x4c8 */ - volatile uint32_t upper_tx_q_base_addr; /* 0x4c8 - 0x4cc */ - volatile uint32_t tx_bd_control; /* 0x4cc - 0x4d0 */ - volatile uint32_t rx_bd_control; /* 0x4d0 - 0x4d4 */ - volatile uint32_t upper_rx_q_base_addr; /* 0x4d4 - 0x4d8 */ - volatile char pad__11[0x28]; /* 0x4d8 - 0x500 */ - volatile uint32_t screening_type_1_register_0; /* 0x500 - 0x504 */ - volatile uint32_t screening_type_1_register_1; /* 0x504 - 0x508 */ - volatile uint32_t screening_type_1_register_2; /* 0x508 - 0x50c */ - volatile uint32_t screening_type_1_register_3; /* 0x50c - 0x510 */ - volatile uint32_t screening_type_1_register_4; /* 0x510 - 0x514 */ - volatile uint32_t screening_type_1_register_5; /* 0x514 - 0x518 */ - volatile uint32_t screening_type_1_register_6; /* 0x518 - 0x51c */ - volatile uint32_t screening_type_1_register_7; /* 0x51c - 0x520 */ - volatile uint32_t screening_type_1_register_8; /* 0x520 - 0x524 */ - volatile uint32_t screening_type_1_register_9; /* 0x524 - 0x528 */ - volatile uint32_t screening_type_1_register_10; /* 0x528 - 0x52c */ - volatile uint32_t screening_type_1_register_11; /* 0x52c - 0x530 */ - volatile uint32_t screening_type_1_register_12; /* 0x530 - 0x534 */ - volatile uint32_t screening_type_1_register_13; /* 0x534 - 0x538 */ - volatile uint32_t screening_type_1_register_14; /* 0x538 - 0x53c */ - volatile uint32_t screening_type_1_register_15; /* 0x53c - 0x540 */ - volatile uint32_t screening_type_2_register_0; /* 0x540 - 0x544 */ - volatile uint32_t screening_type_2_register_1; /* 0x544 - 0x548 */ - volatile uint32_t screening_type_2_register_2; /* 0x548 - 0x54c */ - volatile uint32_t screening_type_2_register_3; /* 0x54c - 0x550 */ - volatile uint32_t screening_type_2_register_4; /* 0x550 - 0x554 */ - volatile uint32_t screening_type_2_register_5; /* 0x554 - 0x558 */ - volatile uint32_t screening_type_2_register_6; /* 0x558 - 0x55c */ - volatile uint32_t screening_type_2_register_7; /* 0x55c - 0x560 */ - volatile uint32_t screening_type_2_register_8; /* 0x560 - 0x564 */ - volatile uint32_t screening_type_2_register_9; /* 0x564 - 0x568 */ - volatile uint32_t screening_type_2_register_10; /* 0x568 - 0x56c */ - volatile uint32_t screening_type_2_register_11; /* 0x56c - 0x570 */ - volatile uint32_t screening_type_2_register_12; /* 0x570 - 0x574 */ - volatile uint32_t screening_type_2_register_13; /* 0x574 - 0x578 */ - volatile uint32_t screening_type_2_register_14; /* 0x578 - 0x57c */ - volatile uint32_t screening_type_2_register_15; /* 0x57c - 0x580 */ - volatile uint32_t tx_sched_ctrl; /* 0x580 - 0x584 */ - volatile char pad__12[0xc]; /* 0x584 - 0x590 */ - volatile uint32_t bw_rate_limit_q0to3; /* 0x590 - 0x594 */ - volatile uint32_t bw_rate_limit_q4to7; /* 0x594 - 0x598 */ - volatile uint32_t bw_rate_limit_q8to11; /* 0x598 - 0x59c */ - volatile uint32_t bw_rate_limit_q12to15; /* 0x59c - 0x5a0 */ - volatile uint32_t tx_q_seg_alloc_q0to7; /* 0x5a0 - 0x5a4 */ - volatile uint32_t tx_q_seg_alloc_q8to15; /* 0x5a4 - 0x5a8 */ - volatile char pad__13[0x18]; /* 0x5a8 - 0x5c0 */ - volatile uint32_t receive_q8_ptr; /* 0x5c0 - 0x5c4 */ - volatile uint32_t receive_q9_ptr; /* 0x5c4 - 0x5c8 */ - volatile uint32_t receive_q10_ptr; /* 0x5c8 - 0x5cc */ - volatile uint32_t receive_q11_ptr; /* 0x5cc - 0x5d0 */ - volatile uint32_t receive_q12_ptr; /* 0x5d0 - 0x5d4 */ - volatile uint32_t receive_q13_ptr; /* 0x5d4 - 0x5d8 */ - volatile uint32_t receive_q14_ptr; /* 0x5d8 - 0x5dc */ - volatile uint32_t receive_q15_ptr; /* 0x5dc - 0x5e0 */ - volatile uint32_t dma_rxbuf_size_q8; /* 0x5e0 - 0x5e4 */ - volatile uint32_t dma_rxbuf_size_q9; /* 0x5e4 - 0x5e8 */ - volatile uint32_t dma_rxbuf_size_q10; /* 0x5e8 - 0x5ec */ - volatile uint32_t dma_rxbuf_size_q11; /* 0x5ec - 0x5f0 */ - volatile uint32_t dma_rxbuf_size_q12; /* 0x5f0 - 0x5f4 */ - volatile uint32_t dma_rxbuf_size_q13; /* 0x5f4 - 0x5f8 */ - volatile uint32_t dma_rxbuf_size_q14; /* 0x5f8 - 0x5fc */ - volatile uint32_t dma_rxbuf_size_q15; /* 0x5fc - 0x600 */ - volatile uint32_t int_q1_enable; /* 0x600 - 0x604 */ - volatile uint32_t int_q2_enable; /* 0x604 - 0x608 */ - volatile uint32_t int_q3_enable; /* 0x608 - 0x60c */ - volatile uint32_t int_q4_enable; /* 0x60c - 0x610 */ - volatile uint32_t int_q5_enable; /* 0x610 - 0x614 */ - volatile uint32_t int_q6_enable; /* 0x614 - 0x618 */ - volatile uint32_t int_q7_enable; /* 0x618 - 0x61c */ - volatile char pad__14[0x4]; /* 0x61c - 0x620 */ - volatile uint32_t int_q1_disable; /* 0x620 - 0x624 */ - volatile uint32_t int_q2_disable; /* 0x624 - 0x628 */ - volatile uint32_t int_q3_disable; /* 0x628 - 0x62c */ - volatile uint32_t int_q4_disable; /* 0x62c - 0x630 */ - volatile uint32_t int_q5_disable; /* 0x630 - 0x634 */ - volatile uint32_t int_q6_disable; /* 0x634 - 0x638 */ - volatile uint32_t int_q7_disable; /* 0x638 - 0x63c */ - volatile char pad__15[0x4]; /* 0x63c - 0x640 */ - volatile uint32_t int_q1_mask; /* 0x640 - 0x644 */ - volatile uint32_t int_q2_mask; /* 0x644 - 0x648 */ - volatile uint32_t int_q3_mask; /* 0x648 - 0x64c */ - volatile uint32_t int_q4_mask; /* 0x64c - 0x650 */ - volatile uint32_t int_q5_mask; /* 0x650 - 0x654 */ - volatile uint32_t int_q6_mask; /* 0x654 - 0x658 */ - volatile uint32_t int_q7_mask; /* 0x658 - 0x65c */ - volatile char pad__16[0x4]; /* 0x65c - 0x660 */ - volatile uint32_t int_q8_enable; /* 0x660 - 0x664 */ - volatile uint32_t int_q9_enable; /* 0x664 - 0x668 */ - volatile uint32_t int_q10_enable; /* 0x668 - 0x66c */ - volatile uint32_t int_q11_enable; /* 0x66c - 0x670 */ - volatile uint32_t int_q12_enable; /* 0x670 - 0x674 */ - volatile uint32_t int_q13_enable; /* 0x674 - 0x678 */ - volatile uint32_t int_q14_enable; /* 0x678 - 0x67c */ - volatile uint32_t int_q15_enable; /* 0x67c - 0x680 */ - volatile uint32_t int_q8_disable; /* 0x680 - 0x684 */ - volatile uint32_t int_q9_disable; /* 0x684 - 0x688 */ - volatile uint32_t int_q10_disable; /* 0x688 - 0x68c */ - volatile uint32_t int_q11_disable; /* 0x68c - 0x690 */ - volatile uint32_t int_q12_disable; /* 0x690 - 0x694 */ - volatile uint32_t int_q13_disable; /* 0x694 - 0x698 */ - volatile uint32_t int_q14_disable; /* 0x698 - 0x69c */ - volatile uint32_t int_q15_disable; /* 0x69c - 0x6a0 */ - volatile uint32_t int_q8_mask; /* 0x6a0 - 0x6a4 */ - volatile uint32_t int_q9_mask; /* 0x6a4 - 0x6a8 */ - volatile uint32_t int_q10_mask; /* 0x6a8 - 0x6ac */ - volatile uint32_t int_q11_mask; /* 0x6ac - 0x6b0 */ - volatile uint32_t int_q12_mask; /* 0x6b0 - 0x6b4 */ - volatile uint32_t int_q13_mask; /* 0x6b4 - 0x6b8 */ - volatile uint32_t int_q14_mask; /* 0x6b8 - 0x6bc */ - volatile uint32_t int_q15_mask; /* 0x6bc - 0x6c0 */ - volatile char pad__17[0x20]; /* 0x6c0 - 0x6e0 */ - volatile uint32_t screening_type_2_ethertype_reg_0; - /* 0x6e0 - 0x6e4 */ - volatile uint32_t screening_type_2_ethertype_reg_1; - /* 0x6e4 - 0x6e8 */ - volatile uint32_t screening_type_2_ethertype_reg_2; - /* 0x6e8 - 0x6ec */ - volatile uint32_t screening_type_2_ethertype_reg_3; - /* 0x6ec - 0x6f0 */ - volatile uint32_t screening_type_2_ethertype_reg_4; - /* 0x6f0 - 0x6f4 */ - volatile uint32_t screening_type_2_ethertype_reg_5; - /* 0x6f4 - 0x6f8 */ - volatile uint32_t screening_type_2_ethertype_reg_6; - /* 0x6f8 - 0x6fc */ - volatile uint32_t screening_type_2_ethertype_reg_7; - /* 0x6fc - 0x700 */ - volatile uint32_t type2_compare_0_word_0; /* 0x700 - 0x704 */ - volatile uint32_t type2_compare_0_word_1; /* 0x704 - 0x708 */ - volatile uint32_t type2_compare_1_word_0; /* 0x708 - 0x70c */ - volatile uint32_t type2_compare_1_word_1; /* 0x70c - 0x710 */ - volatile uint32_t type2_compare_2_word_0; /* 0x710 - 0x714 */ - volatile uint32_t type2_compare_2_word_1; /* 0x714 - 0x718 */ - volatile uint32_t type2_compare_3_word_0; /* 0x718 - 0x71c */ - volatile uint32_t type2_compare_3_word_1; /* 0x71c - 0x720 */ - volatile uint32_t type2_compare_4_word_0; /* 0x720 - 0x724 */ - volatile uint32_t type2_compare_4_word_1; /* 0x724 - 0x728 */ - volatile uint32_t type2_compare_5_word_0; /* 0x728 - 0x72c */ - volatile uint32_t type2_compare_5_word_1; /* 0x72c - 0x730 */ - volatile uint32_t type2_compare_6_word_0; /* 0x730 - 0x734 */ - volatile uint32_t type2_compare_6_word_1; /* 0x734 - 0x738 */ - volatile uint32_t type2_compare_7_word_0; /* 0x738 - 0x73c */ - volatile uint32_t type2_compare_7_word_1; /* 0x73c - 0x740 */ - volatile uint32_t type2_compare_8_word_0; /* 0x740 - 0x744 */ - volatile uint32_t type2_compare_8_word_1; /* 0x744 - 0x748 */ - volatile uint32_t type2_compare_9_word_0; /* 0x748 - 0x74c */ - volatile uint32_t type2_compare_9_word_1; /* 0x74c - 0x750 */ - volatile uint32_t type2_compare_10_word_0; /* 0x750 - 0x754 */ - volatile uint32_t type2_compare_10_word_1; /* 0x754 - 0x758 */ - volatile uint32_t type2_compare_11_word_0; /* 0x758 - 0x75c */ - volatile uint32_t type2_compare_11_word_1; /* 0x75c - 0x760 */ - volatile uint32_t type2_compare_12_word_0; /* 0x760 - 0x764 */ - volatile uint32_t type2_compare_12_word_1; /* 0x764 - 0x768 */ - volatile uint32_t type2_compare_13_word_0; /* 0x768 - 0x76c */ - volatile uint32_t type2_compare_13_word_1; /* 0x76c - 0x770 */ - volatile uint32_t type2_compare_14_word_0; /* 0x770 - 0x774 */ - volatile uint32_t type2_compare_14_word_1; /* 0x774 - 0x778 */ - volatile uint32_t type2_compare_15_word_0; /* 0x778 - 0x77c */ - volatile uint32_t type2_compare_15_word_1; /* 0x77c - 0x780 */ - volatile uint32_t type2_compare_16_word_0; /* 0x780 - 0x784 */ - volatile uint32_t type2_compare_16_word_1; /* 0x784 - 0x788 */ - volatile uint32_t type2_compare_17_word_0; /* 0x788 - 0x78c */ - volatile uint32_t type2_compare_17_word_1; /* 0x78c - 0x790 */ - volatile uint32_t type2_compare_18_word_0; /* 0x790 - 0x794 */ - volatile uint32_t type2_compare_18_word_1; /* 0x794 - 0x798 */ - volatile uint32_t type2_compare_19_word_0; /* 0x798 - 0x79c */ - volatile uint32_t type2_compare_19_word_1; /* 0x79c - 0x7a0 */ - volatile uint32_t type2_compare_20_word_0; /* 0x7a0 - 0x7a4 */ - volatile uint32_t type2_compare_20_word_1; /* 0x7a4 - 0x7a8 */ - volatile uint32_t type2_compare_21_word_0; /* 0x7a8 - 0x7ac */ - volatile uint32_t type2_compare_21_word_1; /* 0x7ac - 0x7b0 */ - volatile uint32_t type2_compare_22_word_0; /* 0x7b0 - 0x7b4 */ - volatile uint32_t type2_compare_22_word_1; /* 0x7b4 - 0x7b8 */ - volatile uint32_t type2_compare_23_word_0; /* 0x7b8 - 0x7bc */ - volatile uint32_t type2_compare_23_word_1; /* 0x7bc - 0x7c0 */ - volatile uint32_t type2_compare_24_word_0; /* 0x7c0 - 0x7c4 */ - volatile uint32_t type2_compare_24_word_1; /* 0x7c4 - 0x7c8 */ - volatile uint32_t type2_compare_25_word_0; /* 0x7c8 - 0x7cc */ - volatile uint32_t type2_compare_25_word_1; /* 0x7cc - 0x7d0 */ - volatile uint32_t type2_compare_26_word_0; /* 0x7d0 - 0x7d4 */ - volatile uint32_t type2_compare_26_word_1; /* 0x7d4 - 0x7d8 */ - volatile uint32_t type2_compare_27_word_0; /* 0x7d8 - 0x7dc */ - volatile uint32_t type2_compare_27_word_1; /* 0x7dc - 0x7e0 */ - volatile uint32_t type2_compare_28_word_0; /* 0x7e0 - 0x7e4 */ - volatile uint32_t type2_compare_28_word_1; /* 0x7e4 - 0x7e8 */ - volatile uint32_t type2_compare_29_word_0; /* 0x7e8 - 0x7ec */ - volatile uint32_t type2_compare_29_word_1; /* 0x7ec - 0x7f0 */ - volatile uint32_t type2_compare_30_word_0; /* 0x7f0 - 0x7f4 */ - volatile uint32_t type2_compare_30_word_1; /* 0x7f4 - 0x7f8 */ - volatile uint32_t type2_compare_31_word_0; /* 0x7f8 - 0x7fc */ - volatile uint32_t type2_compare_31_word_1; /* 0x7fc - 0x800 */ - volatile uint32_t enst_start_time_q8; /* 0x800 - 0x804 */ - volatile uint32_t enst_start_time_q9; /* 0x804 - 0x808 */ - volatile uint32_t enst_start_time_q10; /* 0x808 - 0x80c */ - volatile uint32_t enst_start_time_q11; /* 0x80c - 0x810 */ - volatile uint32_t enst_start_time_q12; /* 0x810 - 0x814 */ - volatile uint32_t enst_start_time_q13; /* 0x814 - 0x818 */ - volatile uint32_t enst_start_time_q14; /* 0x818 - 0x81c */ - volatile uint32_t enst_start_time_q15; /* 0x81c - 0x820 */ - volatile uint32_t enst_on_time_q8; /* 0x820 - 0x824 */ - volatile uint32_t enst_on_time_q9; /* 0x824 - 0x828 */ - volatile uint32_t enst_on_time_q10; /* 0x828 - 0x82c */ - volatile uint32_t enst_on_time_q11; /* 0x82c - 0x830 */ - volatile uint32_t enst_on_time_q12; /* 0x830 - 0x834 */ - volatile uint32_t enst_on_time_q13; /* 0x834 - 0x838 */ - volatile uint32_t enst_on_time_q14; /* 0x838 - 0x83c */ - volatile uint32_t enst_on_time_q15; /* 0x83c - 0x840 */ - volatile uint32_t enst_off_time_q8; /* 0x840 - 0x844 */ - volatile uint32_t enst_off_time_q9; /* 0x844 - 0x848 */ - volatile uint32_t enst_off_time_q10; /* 0x848 - 0x84c */ - volatile uint32_t enst_off_time_q11; /* 0x84c - 0x850 */ - volatile uint32_t enst_off_time_q12; /* 0x850 - 0x854 */ - volatile uint32_t enst_off_time_q13; /* 0x854 - 0x858 */ - volatile uint32_t enst_off_time_q14; /* 0x858 - 0x85c */ - volatile uint32_t enst_off_time_q15; /* 0x85c - 0x860 */ - volatile char pad__18[0x20]; /* 0x860 - 0x880 */ - volatile uint32_t enst_control; /* 0x880 - 0x884 */ -}; - -#endif /* __REG_EMAC_REGS__ */ - -#endif /* __REG_EMAC_REGS_H__ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/emac_regs_macro.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/emac_regs_macro.h deleted file mode 100644 index 243793af10..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/emac_regs_macro.h +++ /dev/null @@ -1,17327 +0,0 @@ -/* Copyright (C) 2016 Cadence Design Systems. All rights reserved */ -/* THIS FILE IS AUTOMATICALLY GENERATED BY CADENCE BLUEPRINT, DO NOT EDIT */ -/* */ - - -#ifndef __REG_EMAC_REGS_MACRO_H__ -#define __REG_EMAC_REGS_MACRO_H__ - - -/* macros for BlueprintGlobalNameSpace::emac_regs::network_control */ -#ifndef __EMAC_REGS__NETWORK_CONTROL_MACRO__ -#define __EMAC_REGS__NETWORK_CONTROL_MACRO__ - -/* macros for field loopback */ -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__SHIFT 0 -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__MASK 0x00000001U -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field loopback_local */ -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SHIFT 1 -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__MASK 0x00000002U -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field enable_receive */ -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SHIFT 2 -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__MASK 0x00000004U -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field enable_transmit */ -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SHIFT 3 -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__MASK 0x00000008U -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field man_port_en */ -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SHIFT 4 -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__MASK 0x00000010U -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field clear_all_stats_regs */ -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SHIFT 5 -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MASK 0x00000020U -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field inc_all_stats_regs */ -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SHIFT 6 -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__MASK 0x00000040U -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field stats_write_en */ -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SHIFT 7 -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__MASK 0x00000080U -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field back_pressure */ -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SHIFT 8 -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__MASK 0x00000100U -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000100U) -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000100U) | (((uint32_t)(src) <<\ - 8) & 0x00000100U) -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000100U))) -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field tx_start_pclk */ -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SHIFT 9 -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__MASK 0x00000200U -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field tx_halt_pclk */ -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__SHIFT 10 -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__MASK 0x00000400U -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000400U) -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000400U) | (((uint32_t)(src) <<\ - 10) & 0x00000400U) -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000400U))) -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field tx_pause_frame_req */ -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SHIFT 11 -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MASK 0x00000800U -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field tx_pause_frame_zero */ -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SHIFT 12 -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MASK 0x00001000U -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field stats_take_snap */ -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SHIFT 13 -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__MASK 0x00002000U -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field stats_read_snap */ -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SHIFT 14 -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__MASK 0x00004000U -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x00004000U) -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00004000U) | (((uint32_t)(src) <<\ - 14) & 0x00004000U) -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x00004000U))) -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field store_rx_ts */ -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SHIFT 15 -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__MASK 0x00008000U -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field pfc_enable */ -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SHIFT 16 -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__MASK 0x00010000U -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field transmit_pfc_priority_based_pause_frame */ -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SHIFT \ - 17 -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WIDTH \ - 1 -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MASK \ - 0x00020000U -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__RESET \ - 0 -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field flush_rx_pkt_pclk */ -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SHIFT 18 -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MASK 0x00040000U -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field tx_lpi_en */ -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SHIFT 19 -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__MASK 0x00080000U -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00080000U) -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00080000U) | (((uint32_t)(src) <<\ - 19) & 0x00080000U) -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00080000U))) -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field ptp_unicast_ena */ -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SHIFT 20 -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__MASK 0x00100000U -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__READ(src) \ - (((uint32_t)(src)\ - & 0x00100000U) >> 20) -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00100000U) -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00100000U) | (((uint32_t)(src) <<\ - 20) & 0x00100000U) -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00100000U))) -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field alt_sgmii_mode */ -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SHIFT 21 -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__MASK 0x00200000U -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__READ(src) \ - (((uint32_t)(src)\ - & 0x00200000U) >> 21) -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__WRITE(src) \ - (((uint32_t)(src)\ - << 21) & 0x00200000U) -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00200000U) | (((uint32_t)(src) <<\ - 21) & 0x00200000U) -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 21) & ~0x00200000U))) -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field store_udp_offset */ -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SHIFT 22 -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__MASK 0x00400000U -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__READ(src) \ - (((uint32_t)(src)\ - & 0x00400000U) >> 22) -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__WRITE(src) \ - (((uint32_t)(src)\ - << 22) & 0x00400000U) -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00400000U) | (((uint32_t)(src) <<\ - 22) & 0x00400000U) -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 22) & ~0x00400000U))) -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field ext_tsu_port_enable */ -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SHIFT 23 -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MASK 0x00800000U -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x00800000U) -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00800000U) | (((uint32_t)(src) <<\ - 23) & 0x00800000U) -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x00800000U))) -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field one_step_sync_mode */ -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SHIFT 24 -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MASK 0x01000000U -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field pfc_ctrl */ -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SHIFT 25 -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MASK 0x02000000U -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__READ(src) \ - (((uint32_t)(src)\ - & 0x02000000U) >> 25) -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x02000000U) -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x02000000U) | (((uint32_t)(src) <<\ - 25) & 0x02000000U) -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x02000000U))) -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field ext_rxq_sel_en */ -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__SHIFT 26 -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__MASK 0x04000000U -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x04000000U) >> 26) -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x04000000U) -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x04000000U) | (((uint32_t)(src) <<\ - 26) & 0x04000000U) -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x04000000U))) -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field oss_correction_field */ -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__SHIFT 27 -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__MASK 0x08000000U -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__WRITE(src) \ - (((uint32_t)(src)\ - << 27) & 0x08000000U) -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x08000000U) | (((uint32_t)(src) <<\ - 27) & 0x08000000U) -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 27) & ~0x08000000U))) -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field sel_mii_on_rgmii */ -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__SHIFT 28 -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__MASK 0x10000000U -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field two_pt_five_gig */ -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__SHIFT 29 -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__MASK 0x20000000U -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__READ(src) \ - (((uint32_t)(src)\ - & 0x20000000U) >> 29) -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field ifg_eats_qav_credit */ -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SHIFT 30 -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MASK 0x40000000U -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0x40000000U) -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x40000000U) | (((uint32_t)(src) <<\ - 30) & 0x40000000U) -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0x40000000U))) -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31 */ -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__SHIFT 31 -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__WIDTH 1 -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__MASK 0x80000000U -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__RESET 0 -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__NETWORK_CONTROL__TYPE uint32_t -#define EMAC_REGS__NETWORK_CONTROL__READ 0xfff9c19fU -#define EMAC_REGS__NETWORK_CONTROL__WRITE 0xfff9c19fU - -#endif /* __EMAC_REGS__NETWORK_CONTROL_MACRO__ */ - - -/* macros for network_control */ -#define INST_NETWORK_CONTROL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::network_config */ -#ifndef __EMAC_REGS__NETWORK_CONFIG_MACRO__ -#define __EMAC_REGS__NETWORK_CONFIG_MACRO__ - -/* macros for field speed */ -#define EMAC_REGS__NETWORK_CONFIG__SPEED__SHIFT 0 -#define EMAC_REGS__NETWORK_CONFIG__SPEED__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__SPEED__MASK 0x00000001U -#define EMAC_REGS__NETWORK_CONFIG__SPEED__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__SPEED__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__NETWORK_CONFIG__SPEED__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__NETWORK_CONFIG__SPEED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__NETWORK_CONFIG__SPEED__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__NETWORK_CONFIG__SPEED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__NETWORK_CONFIG__SPEED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field full_duplex */ -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SHIFT 1 -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__MASK 0x00000002U -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field discard_non_vlan_frames */ -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SHIFT 2 -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__MASK 0x00000004U -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field jumbo_frames */ -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SHIFT 3 -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__MASK 0x00000008U -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field copy_all_frames */ -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SHIFT 4 -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__MASK 0x00000010U -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field no_broadcast */ -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SHIFT 5 -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__MASK 0x00000020U -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field multicast_hash_enable */ -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SHIFT 6 -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__MASK 0x00000040U -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field unicast_hash_enable */ -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SHIFT 7 -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__MASK 0x00000080U -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field receive_1536_byte_frames */ -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SHIFT 8 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__MASK 0x00000100U -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000100U) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000100U) | (((uint32_t)(src) <<\ - 8) & 0x00000100U) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000100U))) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field external_address_match_enable */ -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SHIFT 9 -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__MASK \ - 0x00000200U -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field gigabit_mode_enable */ -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SHIFT 10 -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__MASK 0x00000400U -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000400U) -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000400U) | (((uint32_t)(src) <<\ - 10) & 0x00000400U) -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000400U))) -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field pcs_select */ -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SHIFT 11 -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__MASK 0x00000800U -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field retry_test */ -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SHIFT 12 -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__MASK 0x00001000U -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field pause_enable */ -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SHIFT 13 -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__MASK 0x00002000U -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field receive_buffer_offset */ -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__SHIFT 14 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__WIDTH 2 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MASK 0x0000c000U -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__READ(src) \ - (((uint32_t)(src)\ - & 0x0000c000U) >> 14) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x0000c000U) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000c000U) | (((uint32_t)(src) <<\ - 14) & 0x0000c000U) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x0000c000U))) - -/* macros for field length_field_error_frame_discard */ -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SHIFT 16 -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__MASK \ - 0x00010000U -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field fcs_remove */ -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SHIFT 17 -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__MASK 0x00020000U -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__READ(src) \ - (((uint32_t)(src)\ - & 0x00020000U) >> 17) -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field mdc_clock_division */ -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__SHIFT 18 -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__WIDTH 3 -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MASK 0x001c0000U -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__RESET 2 -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__READ(src) \ - (((uint32_t)(src)\ - & 0x001c0000U) >> 18) -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x001c0000U) -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x001c0000U) | (((uint32_t)(src) <<\ - 18) & 0x001c0000U) -#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x001c0000U))) - -/* macros for field data_bus_width */ -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__SHIFT 21 -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__WIDTH 2 -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MASK 0x00600000U -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__READ(src) \ - (((uint32_t)(src)\ - & 0x00600000U) >> 21) -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__WRITE(src) \ - (((uint32_t)(src)\ - << 21) & 0x00600000U) -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00600000U) | (((uint32_t)(src) <<\ - 21) & 0x00600000U) -#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 21) & ~0x00600000U))) - -/* macros for field disable_copy_of_pause_frames */ -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SHIFT 23 -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__MASK \ - 0x00800000U -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x00800000U) -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00800000U) | (((uint32_t)(src) <<\ - 23) & 0x00800000U) -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x00800000U))) -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field receive_checksum_offload_enable */ -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SHIFT 24 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__MASK \ - 0x01000000U -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field en_half_duplex_rx */ -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SHIFT 25 -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__MASK 0x02000000U -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__READ(src) \ - (((uint32_t)(src)\ - & 0x02000000U) >> 25) -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x02000000U) -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x02000000U) | (((uint32_t)(src) <<\ - 25) & 0x02000000U) -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x02000000U))) -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field ignore_rx_fcs */ -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SHIFT 26 -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__MASK 0x04000000U -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__READ(src) \ - (((uint32_t)(src)\ - & 0x04000000U) >> 26) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x04000000U) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x04000000U) | (((uint32_t)(src) <<\ - 26) & 0x04000000U) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x04000000U))) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field sgmii_mode_enable */ -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SHIFT 27 -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__MASK 0x08000000U -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 27) & 0x08000000U) -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x08000000U) | (((uint32_t)(src) <<\ - 27) & 0x08000000U) -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 27) & ~0x08000000U))) -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field ipg_stretch_enable */ -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SHIFT 28 -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__MASK 0x10000000U -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field nsp_change */ -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__SHIFT 29 -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__MASK 0x20000000U -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__READ(src) \ - (((uint32_t)(src)\ - & 0x20000000U) >> 29) -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field ignore_ipg_rx_er */ -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SHIFT 30 -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__MASK 0x40000000U -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0x40000000U) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x40000000U) | (((uint32_t)(src) <<\ - 30) & 0x40000000U) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0x40000000U))) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field uni_direction_enable */ -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SHIFT 31 -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__WIDTH 1 -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__MASK 0x80000000U -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__RESET 0 -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__NETWORK_CONFIG__TYPE uint32_t -#define EMAC_REGS__NETWORK_CONFIG__READ 0xffffffffU -#define EMAC_REGS__NETWORK_CONFIG__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__NETWORK_CONFIG_MACRO__ */ - - -/* macros for network_config */ -#define INST_NETWORK_CONFIG__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::network_status */ -#ifndef __EMAC_REGS__NETWORK_STATUS_MACRO__ -#define __EMAC_REGS__NETWORK_STATUS_MACRO__ - -/* macros for field pcs_link_state */ -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__SHIFT 0 -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__MASK 0x00000001U -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field mdio_in */ -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__SHIFT 1 -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__MASK 0x00000002U -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field man_done */ -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__SHIFT 2 -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__MASK 0x00000004U -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__RESET 1 -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field mac_full_duplex */ -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__SHIFT 3 -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__MASK 0x00000008U -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field mac_pause_rx_en */ -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__SHIFT 4 -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__MASK 0x00000010U -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field mac_pause_tx_en */ -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__SHIFT 5 -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__MASK 0x00000020U -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field pfc_negotiate_pclk */ -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__SHIFT 6 -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__MASK 0x00000040U -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field lpi_indicate_pclk */ -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__SHIFT 7 -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__WIDTH 1 -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__MASK 0x00000080U -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_31_8 */ -#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__SHIFT 8 -#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__WIDTH 24 -#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__MASK 0xffffff00U -#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__RESET 0 -#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__READ(src) \ - (((uint32_t)(src)\ - & 0xffffff00U) >> 8) -#define EMAC_REGS__NETWORK_STATUS__TYPE uint32_t -#define EMAC_REGS__NETWORK_STATUS__READ 0xffffffffU - -#endif /* __EMAC_REGS__NETWORK_STATUS_MACRO__ */ - - -/* macros for network_status */ -#define INST_NETWORK_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::user_io_register */ -#ifndef __EMAC_REGS__USER_IO_REGISTER_MACRO__ -#define __EMAC_REGS__USER_IO_REGISTER_MACRO__ - -/* macros for field user_programmable_outputs */ -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__SHIFT 0 -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__WIDTH 16 -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MASK \ - 0x0000ffffU -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__RESET 0 -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field user_programmable_inputs */ -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__SHIFT 16 -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__WIDTH 16 -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__MASK 0xffff0000U -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__RESET 0 -#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__USER_IO_REGISTER__TYPE uint32_t -#define EMAC_REGS__USER_IO_REGISTER__READ 0xffffffffU -#define EMAC_REGS__USER_IO_REGISTER__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__USER_IO_REGISTER_MACRO__ */ - - -/* macros for user_io_register */ -#define INST_USER_IO_REGISTER__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::dma_config */ -#ifndef __EMAC_REGS__DMA_CONFIG_MACRO__ -#define __EMAC_REGS__DMA_CONFIG_MACRO__ - -/* macros for field amba_burst_length */ -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__SHIFT 0 -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__WIDTH 5 -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MASK 0x0000001fU -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__RESET 4 -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__READ(src) \ - ((uint32_t)(src)\ - & 0x0000001fU) -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000001fU) -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000001fU) | ((uint32_t)(src) &\ - 0x0000001fU) -#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000001fU))) - -/* macros for field hdr_data_splitting_en */ -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SHIFT 5 -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__MASK 0x00000020U -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__RESET 0b0 -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field endian_swap_management */ -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SHIFT 6 -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__MASK 0x00000040U -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__RESET 1 -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field endian_swap_packet */ -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SHIFT 7 -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__MASK 0x00000080U -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__RESET 1 -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field rx_pbuf_size */ -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__SHIFT 8 -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__WIDTH 2 -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MASK 0x00000300U -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__RESET 3 -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000300U) >> 8) -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000300U) -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000300U) | (((uint32_t)(src) <<\ - 8) & 0x00000300U) -#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000300U))) - -/* macros for field tx_pbuf_size */ -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__SHIFT 10 -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MASK 0x00000400U -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__RESET 1 -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000400U) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000400U) | (((uint32_t)(src) <<\ - 10) & 0x00000400U) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000400U))) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field tx_pbuf_tcp_en */ -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SHIFT 11 -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__MASK 0x00000800U -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__RESET 0 -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field infinite_last_dbuf_size_en */ -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__SHIFT 12 -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__MASK 0x00001000U -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__RESET 0 -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field crc_error_report */ -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__SHIFT 13 -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__MASK 0x00002000U -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__RESET 0 -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field reserved_15_14 */ -#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__SHIFT 14 -#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__WIDTH 2 -#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__MASK 0x0000c000U -#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__RESET 0 -#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__READ(src) \ - (((uint32_t)(src)\ - & 0x0000c000U) >> 14) - -/* macros for field rx_buf_size */ -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__SHIFT 16 -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__WIDTH 8 -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MASK 0x00ff0000U -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__RESET 2 -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field force_discard_on_err */ -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SHIFT 24 -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__MASK 0x01000000U -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__RESET 0 -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field force_max_amba_burst_rx */ -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SHIFT 25 -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__MASK 0x02000000U -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__RESET 0 -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__READ(src) \ - (((uint32_t)(src)\ - & 0x02000000U) >> 25) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x02000000U) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x02000000U) | (((uint32_t)(src) <<\ - 25) & 0x02000000U) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x02000000U))) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field force_max_amba_burst_tx */ -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SHIFT 26 -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__MASK 0x04000000U -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__RESET 0 -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__READ(src) \ - (((uint32_t)(src)\ - & 0x04000000U) >> 26) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x04000000U) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x04000000U) | (((uint32_t)(src) <<\ - 26) & 0x04000000U) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x04000000U))) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field reserved_27 */ -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__SHIFT 27 -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__MASK 0x08000000U -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__RESET 0 -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__DMA_CONFIG__RESERVED_27__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field rx_bd_extended_mode_en */ -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SHIFT 28 -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__MASK 0x10000000U -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__RESET 0 -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field tx_bd_extended_mode_en */ -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SHIFT 29 -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__MASK 0x20000000U -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__RESET 0 -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__READ(src) \ - (((uint32_t)(src)\ - & 0x20000000U) >> 29) -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field dma_addr_bus_width_1 */ -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SHIFT 30 -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__MASK 0x40000000U -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__RESET 0 -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0x40000000U) -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x40000000U) | (((uint32_t)(src) <<\ - 30) & 0x40000000U) -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0x40000000U))) -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31 */ -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__SHIFT 31 -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__WIDTH 1 -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__MASK 0x80000000U -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__RESET 0 -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__DMA_CONFIG__RESERVED_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__DMA_CONFIG__TYPE uint32_t -#define EMAC_REGS__DMA_CONFIG__READ 0xffffffffU -#define EMAC_REGS__DMA_CONFIG__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__DMA_CONFIG_MACRO__ */ - - -/* macros for dma_config */ -#define INST_DMA_CONFIG__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::transmit_status */ -#ifndef __EMAC_REGS__TRANSMIT_STATUS_MACRO__ -#define __EMAC_REGS__TRANSMIT_STATUS_MACRO__ - -/* macros for field used_bit_read */ -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__SHIFT 0 -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MASK 0x00000001U -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) - -/* macros for field collision_occurred */ -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__SHIFT 1 -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MASK 0x00000002U -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) - -/* macros for field retry_limit_exceeded */ -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__SHIFT 2 -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MASK 0x00000004U -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) - -/* macros for field transmit_go */ -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__SHIFT 3 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__MASK 0x00000008U -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field amba_error */ -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__SHIFT 4 -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MASK 0x00000010U -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) - -/* macros for field transmit_complete */ -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__SHIFT 5 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MASK 0x00000020U -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) - -/* macros for field transmit_under_run */ -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__SHIFT 6 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MASK 0x00000040U -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) - -/* macros for field late_collision_occurred */ -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__SHIFT 7 -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MASK 0x00000080U -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) - -/* macros for field resp_not_ok */ -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__SHIFT 8 -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__WIDTH 1 -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MASK 0x00000100U -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000100U) -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000100U) | (((uint32_t)(src) <<\ - 8) & 0x00000100U) -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000100U))) -#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) - -/* macros for field reserved_31_9 */ -#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__SHIFT 9 -#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__WIDTH 23 -#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__MASK 0xfffffe00U -#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__RESET 0 -#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffe00U) >> 9) -#define EMAC_REGS__TRANSMIT_STATUS__TYPE uint32_t -#define EMAC_REGS__TRANSMIT_STATUS__READ 0xffffffffU -#define EMAC_REGS__TRANSMIT_STATUS__WRITE 0xffffffffU -#define EMAC_REGS__TRANSMIT_STATUS__WOCLR 0x000001f7U - -#endif /* __EMAC_REGS__TRANSMIT_STATUS_MACRO__ */ - - -/* macros for transmit_status */ -#define INST_TRANSMIT_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::receive_q_ptr */ -#ifndef __EMAC_REGS__RECEIVE_Q_PTR_MACRO__ -#define __EMAC_REGS__RECEIVE_Q_PTR_MACRO__ - -/* macros for field dma_rx_dis_q */ -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__SHIFT 0 -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__WIDTH 1 -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__MASK 0x00000001U -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__RESET 0b0 -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_1_1 */ -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__SHIFT 1 -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__WIDTH 1 -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__MASK 0x00000002U -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__RESET 0b0 -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field dma_rx_q_ptr */ -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__SHIFT 2 -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__WIDTH 30 -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MASK 0xfffffffcU -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__RESET 0 -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffffcU) >> 2) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0xfffffffcU) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xfffffffcU) | (((uint32_t)(src) <<\ - 2) & 0xfffffffcU) -#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0xfffffffcU))) -#define EMAC_REGS__RECEIVE_Q_PTR__TYPE uint32_t -#define EMAC_REGS__RECEIVE_Q_PTR__READ 0xffffffffU -#define EMAC_REGS__RECEIVE_Q_PTR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__RECEIVE_Q_PTR_MACRO__ */ - - -/* macros for receive_q_ptr */ -#define INST_RECEIVE_Q_PTR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::transmit_q_ptr */ -#ifndef __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__ -#define __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__ - -/* macros for field dma_tx_dis_q */ -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__SHIFT 0 -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__WIDTH 1 -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__MASK 0x00000001U -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__RESET 0b0 -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_1_1 */ -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__SHIFT 1 -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__WIDTH 1 -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__MASK 0x00000002U -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__RESET 0b0 -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field dma_tx_q_ptr */ -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__SHIFT 2 -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__WIDTH 30 -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MASK 0xfffffffcU -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__RESET 0 -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffffcU) >> 2) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0xfffffffcU) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xfffffffcU) | (((uint32_t)(src) <<\ - 2) & 0xfffffffcU) -#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0xfffffffcU))) -#define EMAC_REGS__TRANSMIT_Q_PTR__TYPE uint32_t -#define EMAC_REGS__TRANSMIT_Q_PTR__READ 0xffffffffU -#define EMAC_REGS__TRANSMIT_Q_PTR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__ */ - - -/* macros for transmit_q_ptr */ -#define INST_TRANSMIT_Q_PTR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::receive_status */ -#ifndef __EMAC_REGS__RECEIVE_STATUS_MACRO__ -#define __EMAC_REGS__RECEIVE_STATUS_MACRO__ - -/* macros for field buffer_not_available */ -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__SHIFT 0 -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WIDTH 1 -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MASK 0x00000001U -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__RESET 0 -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) - -/* macros for field frame_received */ -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__SHIFT 1 -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__MASK 0x00000002U -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) - -/* macros for field receive_overrun */ -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__SHIFT 2 -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__WIDTH 1 -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__MASK 0x00000004U -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__RESET 0 -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) - -/* macros for field resp_not_ok */ -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__SHIFT 3 -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__WIDTH 1 -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__MASK 0x00000008U -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__RESET 0 -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) - -/* macros for field reserved_31_4 */ -#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__SHIFT 4 -#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__WIDTH 28 -#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__MASK 0xfffffff0U -#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__RESET 0 -#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffff0U) >> 4) -#define EMAC_REGS__RECEIVE_STATUS__TYPE uint32_t -#define EMAC_REGS__RECEIVE_STATUS__READ 0xffffffffU -#define EMAC_REGS__RECEIVE_STATUS__WRITE 0xffffffffU -#define EMAC_REGS__RECEIVE_STATUS__WOCLR 0x0000000fU - -#endif /* __EMAC_REGS__RECEIVE_STATUS_MACRO__ */ - - -/* macros for receive_status */ -#define INST_RECEIVE_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_status */ -#ifndef __EMAC_REGS__INT_STATUS_MACRO__ -#define __EMAC_REGS__INT_STATUS_MACRO__ - -/* macros for field management_frame_sent */ -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__SHIFT 0 -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__WIDTH 1 -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__MASK 0x00000001U -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__RESET 0b0 -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field receive_complete */ -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__SHIFT 1 -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__MASK 0x00000002U -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__RESET 0b0 -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field rx_used_bit_read */ -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__SHIFT 2 -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__MASK 0x00000004U -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__RESET 0b0 -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field tx_used_bit_read */ -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__SHIFT 3 -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__WIDTH 1 -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__MASK 0x00000008U -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__RESET 0b0 -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field transmit_under_run */ -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__SHIFT 4 -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__WIDTH 1 -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__MASK 0x00000010U -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__RESET 0b0 -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field retry_limit_exceeded_or_late_collision */ -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT 5 -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \ - 0x00000020U -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET \ - 0b0 -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field amba_error */ -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__SHIFT 6 -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__WIDTH 1 -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__MASK 0x00000040U -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__RESET 0b0 -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_STATUS__AMBA_ERROR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field transmit_complete */ -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__SHIFT 7 -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__WIDTH 1 -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__MASK 0x00000080U -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__RESET 0b0 -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_8 */ -#define EMAC_REGS__INT_STATUS__RESERVED_8__SHIFT 8 -#define EMAC_REGS__INT_STATUS__RESERVED_8__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RESERVED_8__MASK 0x00000100U -#define EMAC_REGS__INT_STATUS__RESERVED_8__RESET 0 -#define EMAC_REGS__INT_STATUS__RESERVED_8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__INT_STATUS__RESERVED_8__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__INT_STATUS__RESERVED_8__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field link_change */ -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__SHIFT 9 -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__WIDTH 1 -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__MASK 0x00000200U -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__RESET 0b0 -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__INT_STATUS__LINK_CHANGE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field receive_overrun */ -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__SHIFT 10 -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__MASK 0x00000400U -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__RESET 0b0 -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000400U) -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000400U) | (((uint32_t)(src) <<\ - 10) & 0x00000400U) -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000400U))) -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field resp_not_ok */ -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__SHIFT 11 -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__MASK 0x00000800U -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__RESET 0b0 -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field pause_frame_with_non_zero_pause_quantum_received */ -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__SHIFT \ - 12 -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__WIDTH \ - 1 -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__MASK \ - 0x00001000U -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__RESET \ - 0b0 -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field pause_time_elapsed */ -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__SHIFT 13 -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__MASK 0x00002000U -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field pause_frame_transmitted */ -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__SHIFT 14 -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__MASK 0x00004000U -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x00004000U) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00004000U) | (((uint32_t)(src) <<\ - 14) & 0x00004000U) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x00004000U))) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field external_interrupt */ -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__SHIFT 15 -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__MASK 0x00008000U -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__RESET 0b0 -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field pcs_auto_negotiation_complete */ -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__SHIFT 16 -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__MASK 0x00010000U -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field pcs_link_partner_page_received */ -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT 17 -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__MASK 0x00020000U -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00020000U) >> 17) -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field ptp_delay_req_frame_received */ -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT 18 -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__MASK 0x00040000U -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00040000U) >> 18) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field ptp_sync_frame_received */ -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__SHIFT 19 -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__MASK 0x00080000U -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00080000U) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00080000U) | (((uint32_t)(src) <<\ - 19) & 0x00080000U) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00080000U))) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field ptp_delay_req_frame_transmitted */ -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT 20 -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK \ - 0x00100000U -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__READ(src) \ - (((uint32_t)(src)\ - & 0x00100000U) >> 20) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00100000U) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00100000U) | (((uint32_t)(src) <<\ - 20) & 0x00100000U) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00100000U))) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field ptp_sync_frame_transmitted */ -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__SHIFT 21 -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__MASK 0x00200000U -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__READ(src) \ - (((uint32_t)(src)\ - & 0x00200000U) >> 21) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 21) & 0x00200000U) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00200000U) | (((uint32_t)(src) <<\ - 21) & 0x00200000U) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 21) & ~0x00200000U))) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field ptp_pdelay_req_frame_received */ -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT 22 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__MASK 0x00400000U -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00400000U) >> 22) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 22) & 0x00400000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00400000U) | (((uint32_t)(src) <<\ - 22) & 0x00400000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 22) & ~0x00400000U))) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field ptp_pdelay_resp_frame_received */ -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT 23 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__MASK 0x00800000U -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x00800000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00800000U) | (((uint32_t)(src) <<\ - 23) & 0x00800000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x00800000U))) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field ptp_pdelay_req_frame_transmitted */ -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT 24 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK \ - 0x01000000U -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field ptp_pdelay_resp_frame_transmitted */ -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT 25 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \ - 0x02000000U -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET 0b0 -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__READ(src) \ - (((uint32_t)(src)\ - & 0x02000000U) >> 25) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x02000000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x02000000U) | (((uint32_t)(src) <<\ - 25) & 0x02000000U) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x02000000U))) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field tsu_seconds_register_increment */ -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__SHIFT 26 -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__WIDTH 1 -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__MASK 0x04000000U -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__RESET 0b0 -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__READ(src) \ - (((uint32_t)(src)\ - & 0x04000000U) >> 26) -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x04000000U) -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x04000000U) | (((uint32_t)(src) <<\ - 26) & 0x04000000U) -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x04000000U))) -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field receive_lpi_indication_status_bit_change */ -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__SHIFT \ - 27 -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__WIDTH \ - 1 -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__MASK \ - 0x08000000U -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__RESET \ - 0b0 -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__WRITE(src) \ - (((uint32_t)(src)\ - << 27) & 0x08000000U) -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x08000000U) | (((uint32_t)(src) <<\ - 27) & 0x08000000U) -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 27) & ~0x08000000U))) -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field wol_interrupt */ -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__SHIFT 28 -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__MASK 0x10000000U -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__RESET 0b0 -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field tsu_timer_comparison_interrupt */ -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__SHIFT 29 -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__MASK 0x20000000U -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__RESET 0b0 -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__READ(src) \ - (((uint32_t)(src)\ - & 0x20000000U) >> 29) -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field reserved_30_30 */ -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__SHIFT 30 -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__MASK 0x40000000U -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__RESET 0 -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__INT_STATUS__RESERVED_30_30__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31_31 */ -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__SHIFT 31 -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__WIDTH 1 -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__MASK 0x80000000U -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__RESET 0 -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__INT_STATUS__RESERVED_31_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__INT_STATUS__TYPE uint32_t -#define EMAC_REGS__INT_STATUS__READ 0xffffffffU -#define EMAC_REGS__INT_STATUS__RCLR 0x3ffffeffU -#define EMAC_REGS__INT_STATUS__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__INT_STATUS_MACRO__ */ - - -/* macros for int_status */ -#define INST_INT_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_enable */ -#ifndef __EMAC_REGS__INT_ENABLE_MACRO__ -#define __EMAC_REGS__INT_ENABLE_MACRO__ - -/* macros for field enable_management_done_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SHIFT 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__MASK \ - 0x00000001U -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field enable_receive_complete_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \ - 0x00000002U -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field enable_receive_used_bit_read_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SHIFT 2 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MASK \ - 0x00000004U -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field enable_transmit_used_bit_read_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT 3 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK \ - 0x00000008U -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field enable_transmit_buffer_under_run_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SHIFT \ - 4 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MASK \ - 0x00000010U -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field enable_retry_limit_exceeded_or_late_collision_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \ - 5 -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \ - 0x00000020U -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field enable_transmit_frame_corruption_due_to_amba_error_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \ - 6 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \ - 0x00000040U -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field enable_transmit_complete_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT 7 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \ - 0x00000080U -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field not_used */ -#define EMAC_REGS__INT_ENABLE__NOT_USED__SHIFT 8 -#define EMAC_REGS__INT_ENABLE__NOT_USED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__NOT_USED__MASK 0x00000100U -#define EMAC_REGS__INT_ENABLE__NOT_USED__RESET 0 -#define EMAC_REGS__INT_ENABLE__NOT_USED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__INT_ENABLE__NOT_USED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__INT_ENABLE__NOT_USED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field enable_link_change_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SHIFT 9 -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__MASK 0x00000200U -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field enable_receive_overrun_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SHIFT 10 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__MASK \ - 0x00000400U -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000400U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000400U) | (((uint32_t)(src) <<\ - 10) & 0x00000400U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000400U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field enable_resp_not_ok_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SHIFT 11 -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MASK 0x00000800U -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field enable_pause_frame_with_non_zero_pause_quantum_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SHIFT \ - 12 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MASK \ - 0x00001000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field enable_pause_time_zero_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SHIFT 13 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__MASK \ - 0x00002000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field enable_pause_frame_transmitted_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SHIFT \ - 14 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MASK \ - 0x00004000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x00004000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00004000U) | (((uint32_t)(src) <<\ - 14) & 0x00004000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x00004000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field enable_external_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SHIFT 15 -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__MASK 0x00008000U -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field enable_pcs_auto_negotiation_complete_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SHIFT \ - 16 -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MASK \ - 0x00010000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field enable_pcs_link_partner_page_received */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT 17 -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MASK \ - 0x00020000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field enable_ptp_delay_req_frame_received */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT 18 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MASK \ - 0x00040000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field enable_ptp_sync_frame_received */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SHIFT 19 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__MASK 0x00080000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00080000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00080000U) | (((uint32_t)(src) <<\ - 19) & 0x00080000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00080000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field enable_ptp_delay_req_frame_transmitted */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT 20 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK \ - 0x00100000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00100000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00100000U) | (((uint32_t)(src) <<\ - 20) & 0x00100000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00100000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field enable_ptp_sync_frame_transmitted */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SHIFT 21 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__MASK \ - 0x00200000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 21) & 0x00200000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00200000U) | (((uint32_t)(src) <<\ - 21) & 0x00200000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 21) & ~0x00200000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field enable_ptp_pdelay_req_frame_received */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT 22 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MASK \ - 0x00400000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 22) & 0x00400000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00400000U) | (((uint32_t)(src) <<\ - 22) & 0x00400000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 22) & ~0x00400000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field enable_ptp_pdelay_resp_frame_received */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT 23 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MASK \ - 0x00800000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x00800000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00800000U) | (((uint32_t)(src) <<\ - 23) & 0x00800000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x00800000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field enable_ptp_pdelay_req_frame_transmitted */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT \ - 24 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK \ - 0x01000000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field enable_ptp_pdelay_resp_frame_transmitted */ -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT \ - 25 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH \ - 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \ - 0x02000000U -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET \ - 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x02000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x02000000U) | (((uint32_t)(src) <<\ - 25) & 0x02000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x02000000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field enable_tsu_seconds_register_increment */ -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SHIFT 26 -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__MASK \ - 0x04000000U -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x04000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x04000000U) | (((uint32_t)(src) <<\ - 26) & 0x04000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x04000000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field enable_rx_lpi_indication_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SHIFT 27 -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__MASK \ - 0x08000000U -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 27) & 0x08000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x08000000U) | (((uint32_t)(src) <<\ - 27) & 0x08000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 27) & ~0x08000000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field enable_wol_event_received_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SHIFT 28 -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__MASK \ - 0x10000000U -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field enable_tsu_timer_comparison_interrupt */ -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SHIFT 29 -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__MASK \ - 0x20000000U -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__RESET 0b0 -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field reserved_30_30 */ -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__SHIFT 30 -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__MASK 0x40000000U -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__RESET 0 -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__INT_ENABLE__RESERVED_30_30__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31_31 */ -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__SHIFT 31 -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__WIDTH 1 -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__MASK 0x80000000U -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__RESET 0 -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__INT_ENABLE__RESERVED_31_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__INT_ENABLE__TYPE uint32_t -#define EMAC_REGS__INT_ENABLE__READ 0xc0000100U -#define EMAC_REGS__INT_ENABLE__WRITE 0xc0000100U - -#endif /* __EMAC_REGS__INT_ENABLE_MACRO__ */ - - -/* macros for int_enable */ -#define INST_INT_ENABLE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_disable */ -#ifndef __EMAC_REGS__INT_DISABLE_MACRO__ -#define __EMAC_REGS__INT_DISABLE_MACRO__ - -/* macros for field disable_management_done_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SHIFT 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__MASK \ - 0x00000001U -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field disable_receive_complete_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \ - 0x00000002U -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field disable_receive_used_bit_read_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SHIFT \ - 2 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MASK \ - 0x00000004U -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field disable_transmit_used_bit_read_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT \ - 3 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK \ - 0x00000008U -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field disable_transmit_buffer_under_run_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SHIFT \ - 4 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MASK \ - 0x00000010U -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field disable_retry_limit_exceeded_or_late_collision_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \ - 5 -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \ - 0x00000020U -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field disable_transmit_frame_corruption_due_to_amba_error_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \ - 6 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \ - 0x00000040U -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field disable_transmit_complete_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT 7 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \ - 0x00000080U -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field not_used */ -#define EMAC_REGS__INT_DISABLE__NOT_USED__SHIFT 8 -#define EMAC_REGS__INT_DISABLE__NOT_USED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__NOT_USED__MASK 0x00000100U -#define EMAC_REGS__INT_DISABLE__NOT_USED__RESET 0 -#define EMAC_REGS__INT_DISABLE__NOT_USED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__INT_DISABLE__NOT_USED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__INT_DISABLE__NOT_USED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field disable_link_change_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SHIFT 9 -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__MASK 0x00000200U -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field disable_receive_overrun_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SHIFT 10 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__MASK \ - 0x00000400U -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000400U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000400U) | (((uint32_t)(src) <<\ - 10) & 0x00000400U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000400U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field disable_resp_not_ok_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SHIFT 11 -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MASK 0x00000800U -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field disable_pause_frame_with_non_zero_pause_quantum_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SHIFT \ - 12 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MASK \ - 0x00001000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field disable_pause_time_zero_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SHIFT 13 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__MASK \ - 0x00002000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field disable_pause_frame_transmitted_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SHIFT \ - 14 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MASK \ - 0x00004000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x00004000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00004000U) | (((uint32_t)(src) <<\ - 14) & 0x00004000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x00004000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field disable_external_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SHIFT 15 -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__MASK 0x00008000U -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field disable_pcs_auto_negotiation_complete_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SHIFT \ - 16 -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MASK \ - 0x00010000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field disable_pcs_link_partner_page_received */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT \ - 17 -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MASK \ - 0x00020000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field disable_ptp_delay_req_frame_received */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT 18 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MASK \ - 0x00040000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field disable_ptp_sync_frame_received */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SHIFT 19 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__MASK \ - 0x00080000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00080000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00080000U) | (((uint32_t)(src) <<\ - 19) & 0x00080000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00080000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field disable_ptp_delay_req_frame_transmitted */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT \ - 20 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK \ - 0x00100000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00100000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00100000U) | (((uint32_t)(src) <<\ - 20) & 0x00100000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00100000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field disable_ptp_sync_frame_transmitted */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SHIFT 21 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__MASK \ - 0x00200000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 21) & 0x00200000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00200000U) | (((uint32_t)(src) <<\ - 21) & 0x00200000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 21) & ~0x00200000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field disable_ptp_pdelay_req_frame_received */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT 22 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MASK \ - 0x00400000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 22) & 0x00400000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00400000U) | (((uint32_t)(src) <<\ - 22) & 0x00400000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 22) & ~0x00400000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field disable_ptp_pdelay_resp_frame_received */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT \ - 23 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MASK \ - 0x00800000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x00800000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00800000U) | (((uint32_t)(src) <<\ - 23) & 0x00800000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x00800000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field disable_ptp_pdelay_req_frame_transmitted */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT \ - 24 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK \ - 0x01000000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field disable_ptp_pdelay_resp_frame_transmitted */ -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT \ - 25 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH \ - 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \ - 0x02000000U -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET \ - 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x02000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x02000000U) | (((uint32_t)(src) <<\ - 25) & 0x02000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x02000000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field disable_tsu_seconds_register_increment */ -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SHIFT \ - 26 -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__MASK \ - 0x04000000U -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x04000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x04000000U) | (((uint32_t)(src) <<\ - 26) & 0x04000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x04000000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field disable_rx_lpi_indication_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SHIFT 27 -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__MASK \ - 0x08000000U -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 27) & 0x08000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x08000000U) | (((uint32_t)(src) <<\ - 27) & 0x08000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 27) & ~0x08000000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field disable_wol_event_received_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SHIFT 28 -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__MASK \ - 0x10000000U -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field disable_tsu_timer_comparison_interrupt */ -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SHIFT \ - 29 -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__MASK \ - 0x20000000U -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__RESET \ - 0b0 -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field reserved_30_30 */ -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__SHIFT 30 -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__MASK 0x40000000U -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__RESET 0 -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__INT_DISABLE__RESERVED_30_30__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31_31 */ -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__SHIFT 31 -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__WIDTH 1 -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__MASK 0x80000000U -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__RESET 0 -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__INT_DISABLE__RESERVED_31_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__INT_DISABLE__TYPE uint32_t -#define EMAC_REGS__INT_DISABLE__READ 0xc0000100U -#define EMAC_REGS__INT_DISABLE__WRITE 0xc0000100U - -#endif /* __EMAC_REGS__INT_DISABLE_MACRO__ */ - - -/* macros for int_disable */ -#define INST_INT_DISABLE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_mask */ -#ifndef __EMAC_REGS__INT_MASK_MACRO__ -#define __EMAC_REGS__INT_MASK_MACRO__ - -/* macros for field management_done_interrupt_mask */ -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__SHIFT 0 -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__MASK 0x00000001U -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field receive_complete_interrupt_mask */ -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SHIFT 1 -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__MASK 0x00000002U -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field receive_used_bit_read_interrupt_mask */ -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__SHIFT 2 -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__MASK \ - 0x00000004U -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field transmit_used_bit_read_interrupt_mask */ -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SHIFT 3 -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__MASK \ - 0x00000008U -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field transmit_buffer_under_run_interrupt_mask */ -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__SHIFT 4 -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__MASK \ - 0x00000010U -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field retry_limit_exceeded_or_late_collision_mask */ -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__SHIFT \ - 5 -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__WIDTH \ - 1 -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__MASK \ - 0x00000020U -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__RESET \ - 1 -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field amba_error_interrupt_mask */ -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__SHIFT 6 -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__MASK 0x00000040U -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field transmit_complete_interrupt_mask */ -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SHIFT 7 -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__MASK 0x00000080U -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field not_used */ -#define EMAC_REGS__INT_MASK__NOT_USED__SHIFT 8 -#define EMAC_REGS__INT_MASK__NOT_USED__WIDTH 1 -#define EMAC_REGS__INT_MASK__NOT_USED__MASK 0x00000100U -#define EMAC_REGS__INT_MASK__NOT_USED__RESET 1 -#define EMAC_REGS__INT_MASK__NOT_USED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__INT_MASK__NOT_USED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__INT_MASK__NOT_USED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field link_change_interrupt_mask */ -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__SHIFT 9 -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__MASK 0x00000200U -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field receive_overrun_interrupt_mask */ -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__SHIFT 10 -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__MASK 0x00000400U -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field resp_not_ok_interrupt_mask */ -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__SHIFT 11 -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__MASK 0x00000800U -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field pause_frame_with_non_zero_pause_quantum_interrupt_mask */ -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__SHIFT \ - 12 -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__WIDTH \ - 1 -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__MASK \ - 0x00001000U -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__RESET \ - 1 -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field pause_time_zero_interrupt_mask */ -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__SHIFT 13 -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__MASK 0x00002000U -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field pause_frame_transmitted_interrupt_mask */ -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__SHIFT 14 -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__MASK \ - 0x00004000U -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field external_interrupt_mask */ -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__SHIFT 15 -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__MASK 0x00008000U -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field pcs_auto_negotiation_complete_interrupt_mask */ -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__SHIFT \ - 16 -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__WIDTH \ - 1 -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__MASK \ - 0x00010000U -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__RESET \ - 1 -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field pcs_link_partner_page_mask */ -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__SHIFT 17 -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__MASK 0x00020000U -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00020000U) >> 17) -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field ptp_delay_req_frame_received_mask */ -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__SHIFT 18 -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__MASK \ - 0x00040000U -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00040000U) >> 18) -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field ptp_sync_frame_received_mask */ -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__SHIFT 19 -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__MASK 0x00080000U -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field ptp_delay_req_frame_transmitted_mask */ -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__SHIFT 20 -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__MASK \ - 0x00100000U -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00100000U) >> 20) -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field ptp_sync_frame_transmitted_mask */ -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__SHIFT 21 -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__MASK 0x00200000U -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00200000U) >> 21) -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field ptp_pdelay_req_frame_received_mask */ -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__SHIFT 22 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__MASK \ - 0x00400000U -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00400000U) >> 22) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field ptp_pdelay_resp_frame_received_mask */ -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__SHIFT 23 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__MASK \ - 0x00800000U -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field ptp_pdelay_req_frame_transmitted_mask */ -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__SHIFT 24 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__MASK \ - 0x01000000U -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field ptp_pdelay_resp_frame_transmitted_mask */ -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__SHIFT 25 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__MASK \ - 0x02000000U -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x02000000U) >> 25) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field tsu_seconds_register_increment_mask */ -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__SHIFT 26 -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__MASK \ - 0x04000000U -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x04000000U) >> 26) -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field rx_lpi_indication_mask */ -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__SHIFT 27 -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__MASK 0x08000000U -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field wol_event_received_mask */ -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__SHIFT 28 -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__MASK 0x10000000U -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field tsu_timer_comparison_mask */ -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__SHIFT 29 -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__WIDTH 1 -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__MASK 0x20000000U -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__RESET 1 -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x20000000U) >> 29) -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field reserved_30_30 */ -#define EMAC_REGS__INT_MASK__RESERVED_30_30__SHIFT 30 -#define EMAC_REGS__INT_MASK__RESERVED_30_30__WIDTH 1 -#define EMAC_REGS__INT_MASK__RESERVED_30_30__MASK 0x40000000U -#define EMAC_REGS__INT_MASK__RESERVED_30_30__RESET 0 -#define EMAC_REGS__INT_MASK__RESERVED_30_30__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__INT_MASK__RESERVED_30_30__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__INT_MASK__RESERVED_30_30__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31_31 */ -#define EMAC_REGS__INT_MASK__RESERVED_31_31__SHIFT 31 -#define EMAC_REGS__INT_MASK__RESERVED_31_31__WIDTH 1 -#define EMAC_REGS__INT_MASK__RESERVED_31_31__MASK 0x80000000U -#define EMAC_REGS__INT_MASK__RESERVED_31_31__RESET 0 -#define EMAC_REGS__INT_MASK__RESERVED_31_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__INT_MASK__RESERVED_31_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__INT_MASK__RESERVED_31_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__INT_MASK__TYPE uint32_t -#define EMAC_REGS__INT_MASK__READ 0xffffffffU - -#endif /* __EMAC_REGS__INT_MASK_MACRO__ */ - - -/* macros for int_mask */ -#define INST_INT_MASK__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::phy_management */ -#ifndef __EMAC_REGS__PHY_MANAGEMENT_MACRO__ -#define __EMAC_REGS__PHY_MANAGEMENT_MACRO__ - -/* macros for field phy_write_read_data */ -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__SHIFT 0 -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WIDTH 16 -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MASK 0x0000ffffU -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field write10 */ -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__SHIFT 16 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__WIDTH 2 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__MASK 0x00030000U -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__READ(src) \ - (((uint32_t)(src)\ - & 0x00030000U) >> 16) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00030000U) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00030000U) | (((uint32_t)(src) <<\ - 16) & 0x00030000U) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00030000U))) - -/* macros for field register_address */ -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__SHIFT 18 -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__WIDTH 5 -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MASK 0x007c0000U -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__READ(src) \ - (((uint32_t)(src)\ - & 0x007c0000U) >> 18) -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x007c0000U) -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x007c0000U) | (((uint32_t)(src) <<\ - 18) & 0x007c0000U) -#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x007c0000U))) - -/* macros for field phy_address */ -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__SHIFT 23 -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__WIDTH 5 -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MASK 0x0f800000U -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__READ(src) \ - (((uint32_t)(src)\ - & 0x0f800000U) >> 23) -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x0f800000U) -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0f800000U) | (((uint32_t)(src) <<\ - 23) & 0x0f800000U) -#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x0f800000U))) - -/* macros for field operation */ -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__SHIFT 28 -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__WIDTH 2 -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__MASK 0x30000000U -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__READ(src) \ - (((uint32_t)(src)\ - & 0x30000000U) >> 28) -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x30000000U) -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x30000000U) | (((uint32_t)(src) <<\ - 28) & 0x30000000U) -#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x30000000U))) - -/* macros for field write1 */ -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__SHIFT 30 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__WIDTH 1 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__MASK 0x40000000U -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0x40000000U) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x40000000U) | (((uint32_t)(src) <<\ - 30) & 0x40000000U) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0x40000000U))) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field write0 */ -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__SHIFT 31 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__WIDTH 1 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__MASK 0x80000000U -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__RESET 0 -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__PHY_MANAGEMENT__TYPE uint32_t -#define EMAC_REGS__PHY_MANAGEMENT__READ 0xffffffffU -#define EMAC_REGS__PHY_MANAGEMENT__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__PHY_MANAGEMENT_MACRO__ */ - - -/* macros for phy_management */ -#define INST_PHY_MANAGEMENT__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pause_time */ -#ifndef __EMAC_REGS__PAUSE_TIME_MACRO__ -#define __EMAC_REGS__PAUSE_TIME_MACRO__ - -/* macros for field quantum */ -#define EMAC_REGS__PAUSE_TIME__QUANTUM__SHIFT 0 -#define EMAC_REGS__PAUSE_TIME__QUANTUM__WIDTH 16 -#define EMAC_REGS__PAUSE_TIME__QUANTUM__MASK 0x0000ffffU -#define EMAC_REGS__PAUSE_TIME__QUANTUM__RESET 0 -#define EMAC_REGS__PAUSE_TIME__QUANTUM__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PAUSE_TIME__TYPE uint32_t -#define EMAC_REGS__PAUSE_TIME__READ 0xffffffffU - -#endif /* __EMAC_REGS__PAUSE_TIME_MACRO__ */ - - -/* macros for pause_time */ -#define INST_PAUSE_TIME__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum */ -#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__ -#define __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__ - -/* macros for field quantum */ -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__SHIFT 0 -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MASK 0x0000ffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field quantum_p1 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__SHIFT 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MASK 0xffff0000U -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffff0000U) | (((uint32_t)(src) <<\ - 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0xffff0000U))) -#define EMAC_REGS__TX_PAUSE_QUANTUM__TYPE uint32_t -#define EMAC_REGS__TX_PAUSE_QUANTUM__READ 0xffffffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__ */ - - -/* macros for tx_pause_quantum */ -#define INST_TX_PAUSE_QUANTUM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pbuf_txcutthru */ -#ifndef __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__ -#define __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__ - -/* macros for field dma_tx_cutthru_threshold */ -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__SHIFT 0 -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WIDTH 14 -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MASK 0x00003fffU -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__RESET 16383 -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__READ(src) \ - ((uint32_t)(src)\ - & 0x00003fffU) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00003fffU) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00003fffU) | ((uint32_t)(src) &\ - 0x00003fffU) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00003fffU))) - -/* macros for field reserved */ -#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__SHIFT 14 -#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__WIDTH 17 -#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__MASK 0x7fffc000U -#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__RESET 0 -#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__READ(src) \ - (((uint32_t)(src)\ - & 0x7fffc000U) >> 14) - -/* macros for field dma_tx_cutthru */ -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SHIFT 31 -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WIDTH 1 -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MASK 0x80000000U -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__RESET 0 -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__PBUF_TXCUTTHRU__TYPE uint32_t -#define EMAC_REGS__PBUF_TXCUTTHRU__READ 0xffffffffU -#define EMAC_REGS__PBUF_TXCUTTHRU__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__ */ - - -/* macros for pbuf_txcutthru */ -#define INST_PBUF_TXCUTTHRU__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pbuf_rxcutthru */ -#ifndef __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__ -#define __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__ - -/* macros for field dma_rx_cutthru_threshold */ -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__SHIFT 0 -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WIDTH 11 -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MASK 0x000007ffU -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__RESET 2047 -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__READ(src) \ - ((uint32_t)(src)\ - & 0x000007ffU) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000007ffU) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000007ffU) | ((uint32_t)(src) &\ - 0x000007ffU) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000007ffU))) - -/* macros for field reserved */ -#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__SHIFT 11 -#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__WIDTH 20 -#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__MASK 0x7ffff800U -#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__RESET 0 -#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__READ(src) \ - (((uint32_t)(src)\ - & 0x7ffff800U) >> 11) - -/* macros for field dma_rx_cutthru */ -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SHIFT 31 -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WIDTH 1 -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MASK 0x80000000U -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__RESET 0 -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__PBUF_RXCUTTHRU__TYPE uint32_t -#define EMAC_REGS__PBUF_RXCUTTHRU__READ 0xffffffffU -#define EMAC_REGS__PBUF_RXCUTTHRU__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__ */ - - -/* macros for pbuf_rxcutthru */ -#define INST_PBUF_RXCUTTHRU__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::jumbo_max_length */ -#ifndef __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__ -#define __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__ - -/* macros for field jumbo_max_length */ -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__SHIFT 0 -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__WIDTH 14 -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MASK 0x00003fffU -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__RESET 10240 -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__READ(src) \ - ((uint32_t)(src)\ - & 0x00003fffU) -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00003fffU) -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00003fffU) | ((uint32_t)(src) &\ - 0x00003fffU) -#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00003fffU))) - -/* macros for field reserved_31_14 */ -#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__SHIFT 14 -#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__WIDTH 18 -#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__MASK 0xffffc000U -#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__RESET 0 -#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__READ(src) \ - (((uint32_t)(src)\ - & 0xffffc000U) >> 14) -#define EMAC_REGS__JUMBO_MAX_LENGTH__TYPE uint32_t -#define EMAC_REGS__JUMBO_MAX_LENGTH__READ 0xffffffffU -#define EMAC_REGS__JUMBO_MAX_LENGTH__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__ */ - - -/* macros for jumbo_max_length */ -#define INST_JUMBO_MAX_LENGTH__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::external_fifo_interface */ -#ifndef __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__ -#define __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__ - -/* macros for field external_fifo_interface */ -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__SHIFT 0 -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__WIDTH 1 -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__MASK \ - 0x00000001U -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__RESET 0 -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_31_1 */ -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__SHIFT 1 -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__WIDTH 31 -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__MASK 0xfffffffeU -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__RESET 0 -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffffeU) >> 1) -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__TYPE uint32_t -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__READ 0xffffffffU -#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__ */ - - -/* macros for external_fifo_interface */ -#define INST_EXTERNAL_FIFO_INTERFACE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::axi_max_pipeline */ -#ifndef __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__ -#define __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__ - -/* macros for field ar2r_max_pipeline */ -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__SHIFT 0 -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__WIDTH 8 -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MASK 0x000000ffU -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__RESET 1 -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field aw2w_max_pipeline */ -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__SHIFT 8 -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__WIDTH 8 -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MASK 0x0000ff00U -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__RESET 1 -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field use_aw2b_fill */ -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__SHIFT 16 -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__WIDTH 1 -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__MASK 0x00010000U -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__RESET 0 -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field reserved */ -#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__SHIFT 17 -#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__WIDTH 15 -#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__MASK 0xfffe0000U -#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__RESET 0 -#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__AXI_MAX_PIPELINE__TYPE uint32_t -#define EMAC_REGS__AXI_MAX_PIPELINE__READ 0xffffffffU -#define EMAC_REGS__AXI_MAX_PIPELINE__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__ */ - - -/* macros for axi_max_pipeline */ -#define INST_AXI_MAX_PIPELINE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rsc_control */ -#ifndef __EMAC_REGS__RSC_CONTROL_MACRO__ -#define __EMAC_REGS__RSC_CONTROL_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__SHIFT 0 -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__WIDTH 1 -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__RESET 0 -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__RSC_CONTROL__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field rsc_control */ -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__SHIFT 1 -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__WIDTH 15 -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MASK 0x0000fffeU -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__RESET 0 -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__READ(src) \ - (((uint32_t)(src)\ - & 0x0000fffeU) >> 1) -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x0000fffeU) -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000fffeU) | (((uint32_t)(src) <<\ - 1) & 0x0000fffeU) -#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x0000fffeU))) - -/* macros for field rsc_clr_mask */ -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__SHIFT 16 -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__WIDTH 1 -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__MASK 0x00010000U -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__RESET 0 -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__RESET 0 -#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__RSC_CONTROL__TYPE uint32_t -#define EMAC_REGS__RSC_CONTROL__READ 0xffffffffU -#define EMAC_REGS__RSC_CONTROL__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__RSC_CONTROL_MACRO__ */ - - -/* macros for rsc_control */ -#define INST_RSC_CONTROL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_moderation */ -#ifndef __EMAC_REGS__INT_MODERATION_MACRO__ -#define __EMAC_REGS__INT_MODERATION_MACRO__ - -/* macros for field rx_int_moderation */ -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__SHIFT 0 -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__WIDTH 8 -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MASK 0x000000ffU -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__RESET 0 -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field reserved_15_8 */ -#define EMAC_REGS__INT_MODERATION__RESERVED_15_8__SHIFT 8 -#define EMAC_REGS__INT_MODERATION__RESERVED_15_8__WIDTH 8 -#define EMAC_REGS__INT_MODERATION__RESERVED_15_8__MASK 0x0000ff00U -#define EMAC_REGS__INT_MODERATION__RESERVED_15_8__RESET 0 -#define EMAC_REGS__INT_MODERATION__RESERVED_15_8__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) - -/* macros for field tx_int_moderation */ -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__SHIFT 16 -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__WIDTH 8 -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MASK 0x00ff0000U -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__RESET 0 -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field reserved_31_24 */ -#define EMAC_REGS__INT_MODERATION__RESERVED_31_24__SHIFT 24 -#define EMAC_REGS__INT_MODERATION__RESERVED_31_24__WIDTH 8 -#define EMAC_REGS__INT_MODERATION__RESERVED_31_24__MASK 0xff000000U -#define EMAC_REGS__INT_MODERATION__RESERVED_31_24__RESET 0 -#define EMAC_REGS__INT_MODERATION__RESERVED_31_24__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__INT_MODERATION__TYPE uint32_t -#define EMAC_REGS__INT_MODERATION__READ 0xffffffffU -#define EMAC_REGS__INT_MODERATION__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__INT_MODERATION_MACRO__ */ - - -/* macros for int_moderation */ -#define INST_INT_MODERATION__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::sys_wake_time */ -#ifndef __EMAC_REGS__SYS_WAKE_TIME_MACRO__ -#define __EMAC_REGS__SYS_WAKE_TIME_MACRO__ - -/* macros for field sys_wake_time */ -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__SHIFT 0 -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__WIDTH 16 -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__MASK 0x0000ffffU -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__RESET 0 -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__RESET 0 -#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__SYS_WAKE_TIME__TYPE uint32_t -#define EMAC_REGS__SYS_WAKE_TIME__READ 0xffffffffU -#define EMAC_REGS__SYS_WAKE_TIME__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SYS_WAKE_TIME_MACRO__ */ - - -/* macros for sys_wake_time */ -#define INST_SYS_WAKE_TIME__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::hash_bottom */ -#ifndef __EMAC_REGS__HASH_BOTTOM_MACRO__ -#define __EMAC_REGS__HASH_BOTTOM_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__SHIFT 0 -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__WIDTH 32 -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__MASK 0xffffffffU -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__RESET 0 -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__HASH_BOTTOM__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__HASH_BOTTOM__TYPE uint32_t -#define EMAC_REGS__HASH_BOTTOM__READ 0xffffffffU -#define EMAC_REGS__HASH_BOTTOM__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__HASH_BOTTOM_MACRO__ */ - - -/* macros for hash_bottom */ -#define INST_HASH_BOTTOM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::hash_top */ -#ifndef __EMAC_REGS__HASH_TOP_MACRO__ -#define __EMAC_REGS__HASH_TOP_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__HASH_TOP__ADDRESS__SHIFT 0 -#define EMAC_REGS__HASH_TOP__ADDRESS__WIDTH 32 -#define EMAC_REGS__HASH_TOP__ADDRESS__MASK 0xffffffffU -#define EMAC_REGS__HASH_TOP__ADDRESS__RESET 0 -#define EMAC_REGS__HASH_TOP__ADDRESS__READ(src) ((uint32_t)(src) & 0xffffffffU) -#define EMAC_REGS__HASH_TOP__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__HASH_TOP__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__HASH_TOP__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__HASH_TOP__TYPE uint32_t -#define EMAC_REGS__HASH_TOP__READ 0xffffffffU -#define EMAC_REGS__HASH_TOP__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__HASH_TOP_MACRO__ */ - - -/* macros for hash_top */ -#define INST_HASH_TOP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_add_bottom */ -#ifndef __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__ -#define __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__SHIFT 0 -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__WIDTH 32 -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__MASK 0xffffffffU -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__RESET 0 -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__SPEC_ADD_BOTTOM__TYPE uint32_t -#define EMAC_REGS__SPEC_ADD_BOTTOM__READ 0xffffffffU -#define EMAC_REGS__SPEC_ADD_BOTTOM__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__ */ - - -/* macros for spec_add1_bottom */ -#define INST_SPEC_ADD1_BOTTOM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_add_top_no_mask */ -#ifndef __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__ -#define __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__SHIFT 0 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__WIDTH 16 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MASK 0x0000ffffU -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field filter_type */ -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__SHIFT 16 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__WIDTH 1 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MASK 0x00010000U -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__TYPE uint32_t -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__READ 0xffffffffU -#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__ */ - - -/* macros for spec_add1_top */ -#define INST_SPEC_ADD1_TOP__NUM 1 - -/* macros for spec_add2_bottom */ -#define INST_SPEC_ADD2_BOTTOM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_add_top */ -#ifndef __EMAC_REGS__SPEC_ADD_TOP_MACRO__ -#define __EMAC_REGS__SPEC_ADD_TOP_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__SHIFT 0 -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__WIDTH 16 -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MASK 0x0000ffffU -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field filter_type */ -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__SHIFT 16 -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__WIDTH 1 -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MASK 0x00010000U -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field reserved_23_17 */ -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__SHIFT 17 -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__WIDTH 7 -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__MASK 0x00fe0000U -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__READ(src) \ - (((uint32_t)(src)\ - & 0x00fe0000U) >> 17) - -/* macros for field filter_byte_mask */ -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__SHIFT 24 -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__WIDTH 6 -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MASK 0x3f000000U -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x3f000000U) >> 24) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x3f000000U) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3f000000U) | (((uint32_t)(src) <<\ - 24) & 0x3f000000U) -#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x3f000000U))) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__RESET 0 -#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__SPEC_ADD_TOP__TYPE uint32_t -#define EMAC_REGS__SPEC_ADD_TOP__READ 0xffffffffU -#define EMAC_REGS__SPEC_ADD_TOP__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_ADD_TOP_MACRO__ */ - - -/* macros for spec_add2_top */ -#define INST_SPEC_ADD2_TOP__NUM 1 - -/* macros for spec_add3_bottom */ -#define INST_SPEC_ADD3_BOTTOM__NUM 1 - -/* macros for spec_add3_top */ -#define INST_SPEC_ADD3_TOP__NUM 1 - -/* macros for spec_add4_bottom */ -#define INST_SPEC_ADD4_BOTTOM__NUM 1 - -/* macros for spec_add4_top */ -#define INST_SPEC_ADD4_TOP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_type1 */ -#ifndef __EMAC_REGS__SPEC_TYPE1_MACRO__ -#define __EMAC_REGS__SPEC_TYPE1_MACRO__ - -/* macros for field match */ -#define EMAC_REGS__SPEC_TYPE1__MATCH__SHIFT 0 -#define EMAC_REGS__SPEC_TYPE1__MATCH__WIDTH 16 -#define EMAC_REGS__SPEC_TYPE1__MATCH__MASK 0x0000ffffU -#define EMAC_REGS__SPEC_TYPE1__MATCH__RESET 0 -#define EMAC_REGS__SPEC_TYPE1__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE1__MATCH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE1__MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE1__MATCH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_30_16 */ -#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__SHIFT 16 -#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__WIDTH 15 -#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__MASK 0x7fff0000U -#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__RESET 0 -#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__READ(src) \ - (((uint32_t)(src)\ - & 0x7fff0000U) >> 16) - -/* macros for field enable_copy */ -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SHIFT 31 -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__WIDTH 1 -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__MASK 0x80000000U -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__RESET 0 -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__SPEC_TYPE1__TYPE uint32_t -#define EMAC_REGS__SPEC_TYPE1__READ 0xffffffffU -#define EMAC_REGS__SPEC_TYPE1__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_TYPE1_MACRO__ */ - - -/* macros for spec_type1 */ -#define INST_SPEC_TYPE1__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_type2 */ -#ifndef __EMAC_REGS__SPEC_TYPE2_MACRO__ -#define __EMAC_REGS__SPEC_TYPE2_MACRO__ - -/* macros for field match */ -#define EMAC_REGS__SPEC_TYPE2__MATCH__SHIFT 0 -#define EMAC_REGS__SPEC_TYPE2__MATCH__WIDTH 16 -#define EMAC_REGS__SPEC_TYPE2__MATCH__MASK 0x0000ffffU -#define EMAC_REGS__SPEC_TYPE2__MATCH__RESET 0 -#define EMAC_REGS__SPEC_TYPE2__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE2__MATCH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE2__MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE2__MATCH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_30_16 */ -#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__SHIFT 16 -#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__WIDTH 15 -#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__MASK 0x7fff0000U -#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__RESET 0 -#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__READ(src) \ - (((uint32_t)(src)\ - & 0x7fff0000U) >> 16) - -/* macros for field enable_copy */ -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SHIFT 31 -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__WIDTH 1 -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__MASK 0x80000000U -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__RESET 0 -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__SPEC_TYPE2__TYPE uint32_t -#define EMAC_REGS__SPEC_TYPE2__READ 0xffffffffU -#define EMAC_REGS__SPEC_TYPE2__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_TYPE2_MACRO__ */ - - -/* macros for spec_type2 */ -#define INST_SPEC_TYPE2__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_type3 */ -#ifndef __EMAC_REGS__SPEC_TYPE3_MACRO__ -#define __EMAC_REGS__SPEC_TYPE3_MACRO__ - -/* macros for field match */ -#define EMAC_REGS__SPEC_TYPE3__MATCH__SHIFT 0 -#define EMAC_REGS__SPEC_TYPE3__MATCH__WIDTH 16 -#define EMAC_REGS__SPEC_TYPE3__MATCH__MASK 0x0000ffffU -#define EMAC_REGS__SPEC_TYPE3__MATCH__RESET 0 -#define EMAC_REGS__SPEC_TYPE3__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE3__MATCH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE3__MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE3__MATCH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_30_16 */ -#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__SHIFT 16 -#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__WIDTH 15 -#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__MASK 0x7fff0000U -#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__RESET 0 -#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__READ(src) \ - (((uint32_t)(src)\ - & 0x7fff0000U) >> 16) - -/* macros for field enable_copy */ -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SHIFT 31 -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__WIDTH 1 -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__MASK 0x80000000U -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__RESET 0 -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__SPEC_TYPE3__TYPE uint32_t -#define EMAC_REGS__SPEC_TYPE3__READ 0xffffffffU -#define EMAC_REGS__SPEC_TYPE3__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_TYPE3_MACRO__ */ - - -/* macros for spec_type3 */ -#define INST_SPEC_TYPE3__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::spec_type4 */ -#ifndef __EMAC_REGS__SPEC_TYPE4_MACRO__ -#define __EMAC_REGS__SPEC_TYPE4_MACRO__ - -/* macros for field match */ -#define EMAC_REGS__SPEC_TYPE4__MATCH__SHIFT 0 -#define EMAC_REGS__SPEC_TYPE4__MATCH__WIDTH 16 -#define EMAC_REGS__SPEC_TYPE4__MATCH__MASK 0x0000ffffU -#define EMAC_REGS__SPEC_TYPE4__MATCH__RESET 0 -#define EMAC_REGS__SPEC_TYPE4__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE4__MATCH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE4__MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SPEC_TYPE4__MATCH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_30_16 */ -#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__SHIFT 16 -#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__WIDTH 15 -#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__MASK 0x7fff0000U -#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__RESET 0 -#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__READ(src) \ - (((uint32_t)(src)\ - & 0x7fff0000U) >> 16) - -/* macros for field enable_copy */ -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SHIFT 31 -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__WIDTH 1 -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__MASK 0x80000000U -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__RESET 0 -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__SPEC_TYPE4__TYPE uint32_t -#define EMAC_REGS__SPEC_TYPE4__READ 0xffffffffU -#define EMAC_REGS__SPEC_TYPE4__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SPEC_TYPE4_MACRO__ */ - - -/* macros for spec_type4 */ -#define INST_SPEC_TYPE4__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::wol_register */ -#ifndef __EMAC_REGS__WOL_REGISTER_MACRO__ -#define __EMAC_REGS__WOL_REGISTER_MACRO__ - -/* macros for field addr */ -#define EMAC_REGS__WOL_REGISTER__ADDR__SHIFT 0 -#define EMAC_REGS__WOL_REGISTER__ADDR__WIDTH 16 -#define EMAC_REGS__WOL_REGISTER__ADDR__MASK 0x0000ffffU -#define EMAC_REGS__WOL_REGISTER__ADDR__RESET 0 -#define EMAC_REGS__WOL_REGISTER__ADDR__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__WOL_REGISTER__ADDR__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__WOL_REGISTER__ADDR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__WOL_REGISTER__ADDR__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field wol_mask_0 */ -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SHIFT 16 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__WIDTH 1 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__MASK 0x00010000U -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__RESET 0 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__READ(src) \ - (((uint32_t)(src)\ - & 0x00010000U) >> 16) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field wol_mask_1 */ -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SHIFT 17 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__WIDTH 1 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__MASK 0x00020000U -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__RESET 0 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00020000U) >> 17) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field wol_mask_2 */ -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SHIFT 18 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__WIDTH 1 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__MASK 0x00040000U -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__RESET 0 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__READ(src) \ - (((uint32_t)(src)\ - & 0x00040000U) >> 18) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field wol_mask_3 */ -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SHIFT 19 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__WIDTH 1 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__MASK 0x00080000U -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__RESET 0 -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00080000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00080000U) | (((uint32_t)(src) <<\ - 19) & 0x00080000U) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00080000U))) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field reserved_31_20 */ -#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__SHIFT 20 -#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__WIDTH 12 -#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__MASK 0xfff00000U -#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__RESET 0 -#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__READ(src) \ - (((uint32_t)(src)\ - & 0xfff00000U) >> 20) -#define EMAC_REGS__WOL_REGISTER__TYPE uint32_t -#define EMAC_REGS__WOL_REGISTER__READ 0xffffffffU -#define EMAC_REGS__WOL_REGISTER__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__WOL_REGISTER_MACRO__ */ - - -/* macros for wol_register */ -#define INST_WOL_REGISTER__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::stretch_ratio */ -#ifndef __EMAC_REGS__STRETCH_RATIO_MACRO__ -#define __EMAC_REGS__STRETCH_RATIO_MACRO__ - -/* macros for field ipg_stretch */ -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__SHIFT 0 -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__WIDTH 16 -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MASK 0x0000ffffU -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__RESET 0 -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__RESET 0 -#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__STRETCH_RATIO__TYPE uint32_t -#define EMAC_REGS__STRETCH_RATIO__READ 0xffffffffU -#define EMAC_REGS__STRETCH_RATIO__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__STRETCH_RATIO_MACRO__ */ - - -/* macros for stretch_ratio */ -#define INST_STRETCH_RATIO__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::stacked_vlan */ -#ifndef __EMAC_REGS__STACKED_VLAN_MACRO__ -#define __EMAC_REGS__STACKED_VLAN_MACRO__ - -/* macros for field match */ -#define EMAC_REGS__STACKED_VLAN__MATCH__SHIFT 0 -#define EMAC_REGS__STACKED_VLAN__MATCH__WIDTH 16 -#define EMAC_REGS__STACKED_VLAN__MATCH__MASK 0x0000ffffU -#define EMAC_REGS__STACKED_VLAN__MATCH__RESET 0x0000 -#define EMAC_REGS__STACKED_VLAN__MATCH__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__STACKED_VLAN__MATCH__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__STACKED_VLAN__MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__STACKED_VLAN__MATCH__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_30_16 */ -#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__SHIFT 16 -#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__WIDTH 15 -#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__MASK 0x7fff0000U -#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__RESET 0 -#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__READ(src) \ - (((uint32_t)(src)\ - & 0x7fff0000U) >> 16) - -/* macros for field enable_processing */ -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SHIFT 31 -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__WIDTH 1 -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__MASK 0x80000000U -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__RESET 0 -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__STACKED_VLAN__TYPE uint32_t -#define EMAC_REGS__STACKED_VLAN__READ 0xffffffffU -#define EMAC_REGS__STACKED_VLAN__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__STACKED_VLAN_MACRO__ */ - - -/* macros for stacked_vlan */ -#define INST_STACKED_VLAN__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_pfc_pause */ -#ifndef __EMAC_REGS__TX_PFC_PAUSE_MACRO__ -#define __EMAC_REGS__TX_PFC_PAUSE_MACRO__ - -/* macros for field vector_enable */ -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__SHIFT 0 -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__WIDTH 8 -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MASK 0x000000ffU -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__RESET 0 -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field vector */ -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__SHIFT 8 -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__WIDTH 8 -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__MASK 0x0000ff00U -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__RESET 0 -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TX_PFC_PAUSE__TYPE uint32_t -#define EMAC_REGS__TX_PFC_PAUSE__READ 0xffffffffU -#define EMAC_REGS__TX_PFC_PAUSE__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_PFC_PAUSE_MACRO__ */ - - -/* macros for tx_pfc_pause */ -#define INST_TX_PFC_PAUSE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::mask_add1_bottom */ -#ifndef __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__ -#define __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__ - -/* macros for field address_mask */ -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__SHIFT 0 -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__WIDTH 32 -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MASK 0xffffffffU -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__RESET 0 -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__MASK_ADD1_BOTTOM__TYPE uint32_t -#define EMAC_REGS__MASK_ADD1_BOTTOM__READ 0xffffffffU -#define EMAC_REGS__MASK_ADD1_BOTTOM__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__ */ - - -/* macros for mask_add1_bottom */ -#define INST_MASK_ADD1_BOTTOM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::mask_add1_top */ -#ifndef __EMAC_REGS__MASK_ADD1_TOP_MACRO__ -#define __EMAC_REGS__MASK_ADD1_TOP_MACRO__ - -/* macros for field address_mask */ -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__SHIFT 0 -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__WIDTH 16 -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MASK 0x0000ffffU -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__RESET 0 -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__RESET 0 -#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__MASK_ADD1_TOP__TYPE uint32_t -#define EMAC_REGS__MASK_ADD1_TOP__READ 0xffffffffU -#define EMAC_REGS__MASK_ADD1_TOP__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__MASK_ADD1_TOP_MACRO__ */ - - -/* macros for mask_add1_top */ -#define INST_MASK_ADD1_TOP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::dma_addr_or_mask */ -#ifndef __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__ -#define __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__ - -/* macros for field mask_enable */ -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__SHIFT 0 -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__WIDTH 4 -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MASK 0x0000000fU -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__RESET 0 -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000000fU) | ((uint32_t)(src) &\ - 0x0000000fU) -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000000fU))) - -/* macros for field reserved_27_4 */ -#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__SHIFT 4 -#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__WIDTH 24 -#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__MASK 0x0ffffff0U -#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__RESET 0 -#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__READ(src) \ - (((uint32_t)(src)\ - & 0x0ffffff0U) >> 4) - -/* macros for field mask_value */ -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__SHIFT 28 -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__WIDTH 4 -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MASK 0xf0000000U -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__RESET 0 -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0xf0000000U) -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xf0000000U) | (((uint32_t)(src) <<\ - 28) & 0xf0000000U) -#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0xf0000000U))) -#define EMAC_REGS__DMA_ADDR_OR_MASK__TYPE uint32_t -#define EMAC_REGS__DMA_ADDR_OR_MASK__READ 0xffffffffU -#define EMAC_REGS__DMA_ADDR_OR_MASK__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__ */ - - -/* macros for dma_addr_or_mask */ -#define INST_DMA_ADDR_OR_MASK__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_ptp_unicast */ -#ifndef __EMAC_REGS__RX_PTP_UNICAST_MACRO__ -#define __EMAC_REGS__RX_PTP_UNICAST_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__SHIFT 0 -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__WIDTH 32 -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MASK 0xffffffffU -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__RESET 0 -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__RX_PTP_UNICAST__TYPE uint32_t -#define EMAC_REGS__RX_PTP_UNICAST__READ 0xffffffffU -#define EMAC_REGS__RX_PTP_UNICAST__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__RX_PTP_UNICAST_MACRO__ */ - - -/* macros for rx_ptp_unicast */ -#define INST_RX_PTP_UNICAST__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_ptp_unicast */ -#ifndef __EMAC_REGS__TX_PTP_UNICAST_MACRO__ -#define __EMAC_REGS__TX_PTP_UNICAST_MACRO__ - -/* macros for field address */ -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__SHIFT 0 -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__WIDTH 32 -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MASK 0xffffffffU -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__RESET 0 -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__TX_PTP_UNICAST__TYPE uint32_t -#define EMAC_REGS__TX_PTP_UNICAST__READ 0xffffffffU -#define EMAC_REGS__TX_PTP_UNICAST__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_PTP_UNICAST_MACRO__ */ - - -/* macros for tx_ptp_unicast */ -#define INST_TX_PTP_UNICAST__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_nsec_cmp */ -#ifndef __EMAC_REGS__TSU_NSEC_CMP_MACRO__ -#define __EMAC_REGS__TSU_NSEC_CMP_MACRO__ - -/* macros for field comparison_value */ -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__SHIFT 0 -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__WIDTH 22 -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MASK 0x003fffffU -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__RESET 0 -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__READ(src) \ - ((uint32_t)(src)\ - & 0x003fffffU) -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x003fffffU) -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x003fffffU) | ((uint32_t)(src) &\ - 0x003fffffU) -#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x003fffffU))) - -/* macros for field reserved_31_22 */ -#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__SHIFT 22 -#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__WIDTH 10 -#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__MASK 0xffc00000U -#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__RESET 0 -#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__READ(src) \ - (((uint32_t)(src)\ - & 0xffc00000U) >> 22) -#define EMAC_REGS__TSU_NSEC_CMP__TYPE uint32_t -#define EMAC_REGS__TSU_NSEC_CMP__READ 0xffffffffU -#define EMAC_REGS__TSU_NSEC_CMP__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_NSEC_CMP_MACRO__ */ - - -/* macros for tsu_nsec_cmp */ -#define INST_TSU_NSEC_CMP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_sec_cmp */ -#ifndef __EMAC_REGS__TSU_SEC_CMP_MACRO__ -#define __EMAC_REGS__TSU_SEC_CMP_MACRO__ - -/* macros for field comparison_value */ -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__SHIFT 0 -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__WIDTH 32 -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MASK 0xffffffffU -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__RESET 0 -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__TSU_SEC_CMP__TYPE uint32_t -#define EMAC_REGS__TSU_SEC_CMP__READ 0xffffffffU -#define EMAC_REGS__TSU_SEC_CMP__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_SEC_CMP_MACRO__ */ - - -/* macros for tsu_sec_cmp */ -#define INST_TSU_SEC_CMP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_msb_sec_cmp */ -#ifndef __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__ -#define __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__ - -/* macros for field comparison_value */ -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__SHIFT 0 -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__WIDTH 16 -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MASK 0x0000ffffU -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__RESET 0 -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_MSB_SEC_CMP__TYPE uint32_t -#define EMAC_REGS__TSU_MSB_SEC_CMP__READ 0xffffffffU -#define EMAC_REGS__TSU_MSB_SEC_CMP__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__ */ - - -/* macros for tsu_msb_sec_cmp */ -#define INST_TSU_MSB_SEC_CMP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_tx_msb_sec */ -#ifndef __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__ -#define __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__ - -/* macros for field timer_seconds */ -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__SHIFT 0 -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__WIDTH 16 -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__MASK 0x0000ffffU -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__RESET 0 -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__ */ - - -/* macros for tsu_ptp_tx_msb_sec */ -#define INST_TSU_PTP_TX_MSB_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_rx_msb_sec */ -#ifndef __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__ -#define __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__ - -/* macros for field timer_seconds */ -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__SHIFT 0 -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__WIDTH 16 -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__MASK 0x0000ffffU -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__RESET 0 -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__ */ - - -/* macros for tsu_ptp_rx_msb_sec */ -#define INST_TSU_PTP_RX_MSB_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_tx_msb_sec */ -#ifndef __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__ -#define __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__ - -/* macros for field timer_seconds */ -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__SHIFT 0 -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__WIDTH 16 -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__MASK 0x0000ffffU -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__RESET 0 -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__ */ - - -/* macros for tsu_peer_tx_msb_sec */ -#define INST_TSU_PEER_TX_MSB_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_rx_msb_sec */ -#ifndef __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__ -#define __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__ - -/* macros for field timer_seconds */ -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__SHIFT 0 -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__WIDTH 16 -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__MASK 0x0000ffffU -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__RESET 0 -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__ */ - - -/* macros for tsu_peer_rx_msb_sec */ -#define INST_TSU_PEER_RX_MSB_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::dpram_fill_dbg */ -#ifndef __EMAC_REGS__DPRAM_FILL_DBG_MACRO__ -#define __EMAC_REGS__DPRAM_FILL_DBG_MACRO__ - -/* macros for field dma_tx_rx_fill_level_select */ -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__SHIFT 0 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__WIDTH 1 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__MASK \ - 0x00000001U -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__RESET 0 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_3_1 */ -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__SHIFT 1 -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__WIDTH 3 -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__MASK 0x0000000eU -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__RESET 0 -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__READ(src) \ - (((uint32_t)(src)\ - & 0x0000000eU) >> 1) - -/* macros for field dma_tx_q_fill_level_select */ -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__SHIFT 4 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__WIDTH 4 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__MASK 0x000000f0U -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__RESET 0 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__READ(src) \ - (((uint32_t)(src)\ - & 0x000000f0U) >> 4) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x000000f0U) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000f0U) | (((uint32_t)(src) <<\ - 4) & 0x000000f0U) -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x000000f0U))) - -/* macros for field reserved_15_8 */ -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__SHIFT 8 -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__WIDTH 8 -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__MASK 0x0000ff00U -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__RESET 0 -#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) - -/* macros for field dma_tx_rx_fill_level */ -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__SHIFT 16 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__WIDTH 16 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__MASK 0xffff0000U -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__RESET 0 -#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__DPRAM_FILL_DBG__TYPE uint32_t -#define EMAC_REGS__DPRAM_FILL_DBG__READ 0xffffffffU -#define EMAC_REGS__DPRAM_FILL_DBG__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__DPRAM_FILL_DBG_MACRO__ */ - - -/* macros for dpram_fill_dbg */ -#define INST_DPRAM_FILL_DBG__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::revision_reg */ -#ifndef __EMAC_REGS__REVISION_REG_MACRO__ -#define __EMAC_REGS__REVISION_REG_MACRO__ - -/* macros for field module_revision */ -#define EMAC_REGS__REVISION_REG__MODULE_REVISION__SHIFT 0 -#define EMAC_REGS__REVISION_REG__MODULE_REVISION__WIDTH 16 -#define EMAC_REGS__REVISION_REG__MODULE_REVISION__MASK 0x0000ffffU -#define EMAC_REGS__REVISION_REG__MODULE_REVISION__RESET 265 -#define EMAC_REGS__REVISION_REG__MODULE_REVISION__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field module_identification_number */ -#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__SHIFT 16 -#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__WIDTH 12 -#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__MASK 0x0fff0000U -#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__RESET 263 -#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__READ(src) \ - (((uint32_t)(src)\ - & 0x0fff0000U) >> 16) - -/* macros for field fix_number */ -#define EMAC_REGS__REVISION_REG__FIX_NUMBER__SHIFT 28 -#define EMAC_REGS__REVISION_REG__FIX_NUMBER__WIDTH 4 -#define EMAC_REGS__REVISION_REG__FIX_NUMBER__MASK 0xf0000000U -#define EMAC_REGS__REVISION_REG__FIX_NUMBER__RESET 0 -#define EMAC_REGS__REVISION_REG__FIX_NUMBER__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__REVISION_REG__TYPE uint32_t -#define EMAC_REGS__REVISION_REG__READ 0xffffffffU - -#endif /* __EMAC_REGS__REVISION_REG_MACRO__ */ - - -/* macros for revision_reg */ -#define INST_REVISION_REG__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::octets_txed_bottom */ -#ifndef __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__ -#define __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__SHIFT 0 -#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__WIDTH 32 -#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__MASK 0xffffffffU -#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__RESET 0 -#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__OCTETS_TXED_BOTTOM__TYPE uint32_t -#define EMAC_REGS__OCTETS_TXED_BOTTOM__READ 0xffffffffU -#define EMAC_REGS__OCTETS_TXED_BOTTOM__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__ */ - - -/* macros for octets_txed_bottom */ -#define INST_OCTETS_TXED_BOTTOM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::octets_txed_top */ -#ifndef __EMAC_REGS__OCTETS_TXED_TOP_MACRO__ -#define __EMAC_REGS__OCTETS_TXED_TOP_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__SHIFT 0 -#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__WIDTH 16 -#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__RESET 0 -#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__RESET 0 -#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__OCTETS_TXED_TOP__TYPE uint32_t -#define EMAC_REGS__OCTETS_TXED_TOP__READ 0xffffffffU -#define EMAC_REGS__OCTETS_TXED_TOP__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__OCTETS_TXED_TOP_MACRO__ */ - - -/* macros for octets_txed_top */ -#define INST_OCTETS_TXED_TOP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_ok */ -#ifndef __EMAC_REGS__FRAMES_TXED_OK_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_OK_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_OK__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_OK__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_OK__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_OK__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_OK__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_OK__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_OK__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_OK__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_OK_MACRO__ */ - - -/* macros for frames_txed_ok */ -#define INST_FRAMES_TXED_OK__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::broadcast_txed */ -#ifndef __EMAC_REGS__BROADCAST_TXED_MACRO__ -#define __EMAC_REGS__BROADCAST_TXED_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__BROADCAST_TXED__COUNT__SHIFT 0 -#define EMAC_REGS__BROADCAST_TXED__COUNT__WIDTH 32 -#define EMAC_REGS__BROADCAST_TXED__COUNT__MASK 0xffffffffU -#define EMAC_REGS__BROADCAST_TXED__COUNT__RESET 0 -#define EMAC_REGS__BROADCAST_TXED__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__BROADCAST_TXED__TYPE uint32_t -#define EMAC_REGS__BROADCAST_TXED__READ 0xffffffffU -#define EMAC_REGS__BROADCAST_TXED__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__BROADCAST_TXED_MACRO__ */ - - -/* macros for broadcast_txed */ -#define INST_BROADCAST_TXED__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::multicast_txed */ -#ifndef __EMAC_REGS__MULTICAST_TXED_MACRO__ -#define __EMAC_REGS__MULTICAST_TXED_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__MULTICAST_TXED__COUNT__SHIFT 0 -#define EMAC_REGS__MULTICAST_TXED__COUNT__WIDTH 32 -#define EMAC_REGS__MULTICAST_TXED__COUNT__MASK 0xffffffffU -#define EMAC_REGS__MULTICAST_TXED__COUNT__RESET 0 -#define EMAC_REGS__MULTICAST_TXED__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__MULTICAST_TXED__TYPE uint32_t -#define EMAC_REGS__MULTICAST_TXED__READ 0xffffffffU -#define EMAC_REGS__MULTICAST_TXED__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__MULTICAST_TXED_MACRO__ */ - - -/* macros for multicast_txed */ -#define INST_MULTICAST_TXED__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pause_frames_txed */ -#ifndef __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__ -#define __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__SHIFT 0 -#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__WIDTH 16 -#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__RESET 0 -#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PAUSE_FRAMES_TXED__TYPE uint32_t -#define EMAC_REGS__PAUSE_FRAMES_TXED__READ 0xffffffffU -#define EMAC_REGS__PAUSE_FRAMES_TXED__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__ */ - - -/* macros for pause_frames_txed */ -#define INST_PAUSE_FRAMES_TXED__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_64 */ -#ifndef __EMAC_REGS__FRAMES_TXED_64_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_64_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_64__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_64__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_64__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_64__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_64__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_64__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_64__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_64__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_64_MACRO__ */ - - -/* macros for frames_txed_64 */ -#define INST_FRAMES_TXED_64__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_65 */ -#ifndef __EMAC_REGS__FRAMES_TXED_65_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_65_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_65__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_65__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_65__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_65__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_65__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_65__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_65__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_65__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_65_MACRO__ */ - - -/* macros for frames_txed_65 */ -#define INST_FRAMES_TXED_65__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_128 */ -#ifndef __EMAC_REGS__FRAMES_TXED_128_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_128_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_128__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_128__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_128__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_128__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_128__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_128__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_128__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_128__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_128_MACRO__ */ - - -/* macros for frames_txed_128 */ -#define INST_FRAMES_TXED_128__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_256 */ -#ifndef __EMAC_REGS__FRAMES_TXED_256_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_256_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_256__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_256__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_256__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_256__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_256__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_256__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_256__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_256__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_256_MACRO__ */ - - -/* macros for frames_txed_256 */ -#define INST_FRAMES_TXED_256__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_512 */ -#ifndef __EMAC_REGS__FRAMES_TXED_512_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_512_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_512__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_512__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_512__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_512__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_512__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_512__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_512__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_512__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_512_MACRO__ */ - - -/* macros for frames_txed_512 */ -#define INST_FRAMES_TXED_512__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_1024 */ -#ifndef __EMAC_REGS__FRAMES_TXED_1024_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_1024_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_1024__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_1024__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_1024__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_1024__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_1024__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_1024__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_1024__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_1024__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_1024_MACRO__ */ - - -/* macros for frames_txed_1024 */ -#define INST_FRAMES_TXED_1024__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_1519 */ -#ifndef __EMAC_REGS__FRAMES_TXED_1519_MACRO__ -#define __EMAC_REGS__FRAMES_TXED_1519_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_TXED_1519__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_TXED_1519__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_TXED_1519__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_1519__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_TXED_1519__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_TXED_1519__TYPE uint32_t -#define EMAC_REGS__FRAMES_TXED_1519__READ 0xffffffffU -#define EMAC_REGS__FRAMES_TXED_1519__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_TXED_1519_MACRO__ */ - - -/* macros for frames_txed_1519 */ -#define INST_FRAMES_TXED_1519__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_underruns */ -#ifndef __EMAC_REGS__TX_UNDERRUNS_MACRO__ -#define __EMAC_REGS__TX_UNDERRUNS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__TX_UNDERRUNS__COUNT__SHIFT 0 -#define EMAC_REGS__TX_UNDERRUNS__COUNT__WIDTH 10 -#define EMAC_REGS__TX_UNDERRUNS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__TX_UNDERRUNS__COUNT__RESET 0 -#define EMAC_REGS__TX_UNDERRUNS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_22 */ -#define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__SHIFT 10 -#define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__WIDTH 22 -#define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__MASK 0xfffffc00U -#define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__RESET 0 -#define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__TX_UNDERRUNS__TYPE uint32_t -#define EMAC_REGS__TX_UNDERRUNS__READ 0xffffffffU -#define EMAC_REGS__TX_UNDERRUNS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__TX_UNDERRUNS_MACRO__ */ - - -/* macros for tx_underruns */ -#define INST_TX_UNDERRUNS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::single_collisions */ -#ifndef __EMAC_REGS__SINGLE_COLLISIONS_MACRO__ -#define __EMAC_REGS__SINGLE_COLLISIONS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__SHIFT 0 -#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__WIDTH 18 -#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__MASK 0x0003ffffU -#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__RESET 0 -#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0003ffffU) - -/* macros for field reserved_31_18 */ -#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__SHIFT 18 -#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__WIDTH 14 -#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__MASK 0xfffc0000U -#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__RESET 0 -#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__READ(src) \ - (((uint32_t)(src)\ - & 0xfffc0000U) >> 18) -#define EMAC_REGS__SINGLE_COLLISIONS__TYPE uint32_t -#define EMAC_REGS__SINGLE_COLLISIONS__READ 0xffffffffU -#define EMAC_REGS__SINGLE_COLLISIONS__RCLR 0x0003ffffU - -#endif /* __EMAC_REGS__SINGLE_COLLISIONS_MACRO__ */ - - -/* macros for single_collisions */ -#define INST_SINGLE_COLLISIONS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::multiple_collisions */ -#ifndef __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__ -#define __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__SHIFT 0 -#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__WIDTH 18 -#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__MASK 0x0003ffffU -#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__RESET 0 -#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0003ffffU) - -/* macros for field reserved_31_18 */ -#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__SHIFT 18 -#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__WIDTH 14 -#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__MASK 0xfffc0000U -#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__RESET 0 -#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__READ(src) \ - (((uint32_t)(src)\ - & 0xfffc0000U) >> 18) -#define EMAC_REGS__MULTIPLE_COLLISIONS__TYPE uint32_t -#define EMAC_REGS__MULTIPLE_COLLISIONS__READ 0xffffffffU -#define EMAC_REGS__MULTIPLE_COLLISIONS__RCLR 0x0003ffffU - -#endif /* __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__ */ - - -/* macros for multiple_collisions */ -#define INST_MULTIPLE_COLLISIONS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::excessive_collisions */ -#ifndef __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__ -#define __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__SHIFT 0 -#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__WIDTH 10 -#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__RESET 0 -#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__EXCESSIVE_COLLISIONS__TYPE uint32_t -#define EMAC_REGS__EXCESSIVE_COLLISIONS__READ 0xffffffffU -#define EMAC_REGS__EXCESSIVE_COLLISIONS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__ */ - - -/* macros for excessive_collisions */ -#define INST_EXCESSIVE_COLLISIONS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::late_collisions */ -#ifndef __EMAC_REGS__LATE_COLLISIONS_MACRO__ -#define __EMAC_REGS__LATE_COLLISIONS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__LATE_COLLISIONS__COUNT__SHIFT 0 -#define EMAC_REGS__LATE_COLLISIONS__COUNT__WIDTH 10 -#define EMAC_REGS__LATE_COLLISIONS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__LATE_COLLISIONS__COUNT__RESET 0 -#define EMAC_REGS__LATE_COLLISIONS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__LATE_COLLISIONS__TYPE uint32_t -#define EMAC_REGS__LATE_COLLISIONS__READ 0xffffffffU -#define EMAC_REGS__LATE_COLLISIONS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__LATE_COLLISIONS_MACRO__ */ - - -/* macros for late_collisions */ -#define INST_LATE_COLLISIONS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::deferred_frames */ -#ifndef __EMAC_REGS__DEFERRED_FRAMES_MACRO__ -#define __EMAC_REGS__DEFERRED_FRAMES_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__DEFERRED_FRAMES__COUNT__SHIFT 0 -#define EMAC_REGS__DEFERRED_FRAMES__COUNT__WIDTH 18 -#define EMAC_REGS__DEFERRED_FRAMES__COUNT__MASK 0x0003ffffU -#define EMAC_REGS__DEFERRED_FRAMES__COUNT__RESET 0 -#define EMAC_REGS__DEFERRED_FRAMES__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0003ffffU) - -/* macros for field reserved_31_18 */ -#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__SHIFT 18 -#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__WIDTH 14 -#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__MASK 0xfffc0000U -#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__RESET 0 -#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__READ(src) \ - (((uint32_t)(src)\ - & 0xfffc0000U) >> 18) -#define EMAC_REGS__DEFERRED_FRAMES__TYPE uint32_t -#define EMAC_REGS__DEFERRED_FRAMES__READ 0xffffffffU -#define EMAC_REGS__DEFERRED_FRAMES__RCLR 0x0003ffffU - -#endif /* __EMAC_REGS__DEFERRED_FRAMES_MACRO__ */ - - -/* macros for deferred_frames */ -#define INST_DEFERRED_FRAMES__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::crs_errors */ -#ifndef __EMAC_REGS__CRS_ERRORS_MACRO__ -#define __EMAC_REGS__CRS_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__CRS_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__CRS_ERRORS__COUNT__WIDTH 10 -#define EMAC_REGS__CRS_ERRORS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__CRS_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__CRS_ERRORS__COUNT__READ(src) ((uint32_t)(src) & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__CRS_ERRORS__TYPE uint32_t -#define EMAC_REGS__CRS_ERRORS__READ 0xffffffffU -#define EMAC_REGS__CRS_ERRORS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__CRS_ERRORS_MACRO__ */ - - -/* macros for crs_errors */ -#define INST_CRS_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::octets_rxed_bottom */ -#ifndef __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__ -#define __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__SHIFT 0 -#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__WIDTH 32 -#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__MASK 0xffffffffU -#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__RESET 0 -#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__OCTETS_RXED_BOTTOM__TYPE uint32_t -#define EMAC_REGS__OCTETS_RXED_BOTTOM__READ 0xffffffffU -#define EMAC_REGS__OCTETS_RXED_BOTTOM__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__ */ - - -/* macros for octets_rxed_bottom */ -#define INST_OCTETS_RXED_BOTTOM__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::octets_rxed_top */ -#ifndef __EMAC_REGS__OCTETS_RXED_TOP_MACRO__ -#define __EMAC_REGS__OCTETS_RXED_TOP_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__SHIFT 0 -#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__WIDTH 16 -#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__RESET 0 -#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__RESET 0 -#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__OCTETS_RXED_TOP__TYPE uint32_t -#define EMAC_REGS__OCTETS_RXED_TOP__READ 0xffffffffU -#define EMAC_REGS__OCTETS_RXED_TOP__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__OCTETS_RXED_TOP_MACRO__ */ - - -/* macros for octets_rxed_top */ -#define INST_OCTETS_RXED_TOP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_ok */ -#ifndef __EMAC_REGS__FRAMES_RXED_OK_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_OK_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_OK__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_OK__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_OK__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_OK__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_OK__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_OK__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_OK__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_OK__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_OK_MACRO__ */ - - -/* macros for frames_rxed_ok */ -#define INST_FRAMES_RXED_OK__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::broadcast_rxed */ -#ifndef __EMAC_REGS__BROADCAST_RXED_MACRO__ -#define __EMAC_REGS__BROADCAST_RXED_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__BROADCAST_RXED__COUNT__SHIFT 0 -#define EMAC_REGS__BROADCAST_RXED__COUNT__WIDTH 32 -#define EMAC_REGS__BROADCAST_RXED__COUNT__MASK 0xffffffffU -#define EMAC_REGS__BROADCAST_RXED__COUNT__RESET 0 -#define EMAC_REGS__BROADCAST_RXED__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__BROADCAST_RXED__TYPE uint32_t -#define EMAC_REGS__BROADCAST_RXED__READ 0xffffffffU -#define EMAC_REGS__BROADCAST_RXED__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__BROADCAST_RXED_MACRO__ */ - - -/* macros for broadcast_rxed */ -#define INST_BROADCAST_RXED__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::multicast_rxed */ -#ifndef __EMAC_REGS__MULTICAST_RXED_MACRO__ -#define __EMAC_REGS__MULTICAST_RXED_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__MULTICAST_RXED__COUNT__SHIFT 0 -#define EMAC_REGS__MULTICAST_RXED__COUNT__WIDTH 32 -#define EMAC_REGS__MULTICAST_RXED__COUNT__MASK 0xffffffffU -#define EMAC_REGS__MULTICAST_RXED__COUNT__RESET 0 -#define EMAC_REGS__MULTICAST_RXED__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__MULTICAST_RXED__TYPE uint32_t -#define EMAC_REGS__MULTICAST_RXED__READ 0xffffffffU -#define EMAC_REGS__MULTICAST_RXED__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__MULTICAST_RXED_MACRO__ */ - - -/* macros for multicast_rxed */ -#define INST_MULTICAST_RXED__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pause_frames_rxed */ -#ifndef __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__ -#define __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__SHIFT 0 -#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__WIDTH 16 -#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__RESET 0 -#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PAUSE_FRAMES_RXED__TYPE uint32_t -#define EMAC_REGS__PAUSE_FRAMES_RXED__READ 0xffffffffU -#define EMAC_REGS__PAUSE_FRAMES_RXED__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__ */ - - -/* macros for pause_frames_rxed */ -#define INST_PAUSE_FRAMES_RXED__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_64 */ -#ifndef __EMAC_REGS__FRAMES_RXED_64_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_64_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_64__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_64__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_64__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_64__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_64__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_64__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_64__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_64__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_64_MACRO__ */ - - -/* macros for frames_rxed_64 */ -#define INST_FRAMES_RXED_64__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_65 */ -#ifndef __EMAC_REGS__FRAMES_RXED_65_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_65_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_65__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_65__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_65__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_65__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_65__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_65__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_65__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_65__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_65_MACRO__ */ - - -/* macros for frames_rxed_65 */ -#define INST_FRAMES_RXED_65__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_128 */ -#ifndef __EMAC_REGS__FRAMES_RXED_128_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_128_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_128__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_128__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_128__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_128__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_128__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_128__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_128__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_128__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_128_MACRO__ */ - - -/* macros for frames_rxed_128 */ -#define INST_FRAMES_RXED_128__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_256 */ -#ifndef __EMAC_REGS__FRAMES_RXED_256_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_256_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_256__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_256__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_256__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_256__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_256__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_256__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_256__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_256__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_256_MACRO__ */ - - -/* macros for frames_rxed_256 */ -#define INST_FRAMES_RXED_256__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_512 */ -#ifndef __EMAC_REGS__FRAMES_RXED_512_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_512_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_512__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_512__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_512__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_512__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_512__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_512__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_512__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_512__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_512_MACRO__ */ - - -/* macros for frames_rxed_512 */ -#define INST_FRAMES_RXED_512__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_1024 */ -#ifndef __EMAC_REGS__FRAMES_RXED_1024_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_1024_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_1024__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_1024__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_1024__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_1024__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_1024__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_1024__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_1024__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_1024__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_1024_MACRO__ */ - - -/* macros for frames_rxed_1024 */ -#define INST_FRAMES_RXED_1024__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_1519 */ -#ifndef __EMAC_REGS__FRAMES_RXED_1519_MACRO__ -#define __EMAC_REGS__FRAMES_RXED_1519_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FRAMES_RXED_1519__COUNT__SHIFT 0 -#define EMAC_REGS__FRAMES_RXED_1519__COUNT__WIDTH 32 -#define EMAC_REGS__FRAMES_RXED_1519__COUNT__MASK 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_1519__COUNT__RESET 0 -#define EMAC_REGS__FRAMES_RXED_1519__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__FRAMES_RXED_1519__TYPE uint32_t -#define EMAC_REGS__FRAMES_RXED_1519__READ 0xffffffffU -#define EMAC_REGS__FRAMES_RXED_1519__RCLR 0xffffffffU - -#endif /* __EMAC_REGS__FRAMES_RXED_1519_MACRO__ */ - - -/* macros for frames_rxed_1519 */ -#define INST_FRAMES_RXED_1519__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::undersize_frames */ -#ifndef __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__ -#define __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__SHIFT 0 -#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__WIDTH 10 -#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__MASK 0x000003ffU -#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__RESET 0 -#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__RESET 0 -#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__UNDERSIZE_FRAMES__TYPE uint32_t -#define EMAC_REGS__UNDERSIZE_FRAMES__READ 0xffffffffU -#define EMAC_REGS__UNDERSIZE_FRAMES__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__ */ - - -/* macros for undersize_frames */ -#define INST_UNDERSIZE_FRAMES__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::excessive_rx_length */ -#ifndef __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__ -#define __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__SHIFT 0 -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__WIDTH 10 -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__MASK 0x000003ffU -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__RESET 0 -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__RESET 0 -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__TYPE uint32_t -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__READ 0xffffffffU -#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__ */ - - -/* macros for excessive_rx_length */ -#define INST_EXCESSIVE_RX_LENGTH__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_jabbers */ -#ifndef __EMAC_REGS__RX_JABBERS_MACRO__ -#define __EMAC_REGS__RX_JABBERS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_JABBERS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_JABBERS__COUNT__WIDTH 10 -#define EMAC_REGS__RX_JABBERS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__RX_JABBERS__COUNT__RESET 0 -#define EMAC_REGS__RX_JABBERS__COUNT__READ(src) ((uint32_t)(src) & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__RX_JABBERS__TYPE uint32_t -#define EMAC_REGS__RX_JABBERS__READ 0xffffffffU -#define EMAC_REGS__RX_JABBERS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__RX_JABBERS_MACRO__ */ - - -/* macros for rx_jabbers */ -#define INST_RX_JABBERS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::fcs_errors */ -#ifndef __EMAC_REGS__FCS_ERRORS_MACRO__ -#define __EMAC_REGS__FCS_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__FCS_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__FCS_ERRORS__COUNT__WIDTH 10 -#define EMAC_REGS__FCS_ERRORS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__FCS_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__FCS_ERRORS__COUNT__READ(src) ((uint32_t)(src) & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__FCS_ERRORS__TYPE uint32_t -#define EMAC_REGS__FCS_ERRORS__READ 0xffffffffU -#define EMAC_REGS__FCS_ERRORS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__FCS_ERRORS_MACRO__ */ - - -/* macros for fcs_errors */ -#define INST_FCS_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_length_errors */ -#ifndef __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__ -#define __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__WIDTH 10 -#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__RX_LENGTH_ERRORS__TYPE uint32_t -#define EMAC_REGS__RX_LENGTH_ERRORS__READ 0xffffffffU -#define EMAC_REGS__RX_LENGTH_ERRORS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__ */ - - -/* macros for rx_length_errors */ -#define INST_RX_LENGTH_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_symbol_errors */ -#ifndef __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__ -#define __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__WIDTH 10 -#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__RX_SYMBOL_ERRORS__TYPE uint32_t -#define EMAC_REGS__RX_SYMBOL_ERRORS__READ 0xffffffffU -#define EMAC_REGS__RX_SYMBOL_ERRORS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__ */ - - -/* macros for rx_symbol_errors */ -#define INST_RX_SYMBOL_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::alignment_errors */ -#ifndef __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__ -#define __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__WIDTH 10 -#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__ALIGNMENT_ERRORS__TYPE uint32_t -#define EMAC_REGS__ALIGNMENT_ERRORS__READ 0xffffffffU -#define EMAC_REGS__ALIGNMENT_ERRORS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__ */ - - -/* macros for alignment_errors */ -#define INST_ALIGNMENT_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_resource_errors */ -#ifndef __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__ -#define __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__WIDTH 18 -#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__MASK 0x0003ffffU -#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0003ffffU) - -/* macros for field reserved_31_18 */ -#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__SHIFT 18 -#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__WIDTH 14 -#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__MASK 0xfffc0000U -#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__RESET 0 -#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__READ(src) \ - (((uint32_t)(src)\ - & 0xfffc0000U) >> 18) -#define EMAC_REGS__RX_RESOURCE_ERRORS__TYPE uint32_t -#define EMAC_REGS__RX_RESOURCE_ERRORS__READ 0xffffffffU -#define EMAC_REGS__RX_RESOURCE_ERRORS__RCLR 0x0003ffffU - -#endif /* __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__ */ - - -/* macros for rx_resource_errors */ -#define INST_RX_RESOURCE_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_overruns */ -#ifndef __EMAC_REGS__RX_OVERRUNS_MACRO__ -#define __EMAC_REGS__RX_OVERRUNS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_OVERRUNS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_OVERRUNS__COUNT__WIDTH 10 -#define EMAC_REGS__RX_OVERRUNS__COUNT__MASK 0x000003ffU -#define EMAC_REGS__RX_OVERRUNS__COUNT__RESET 0 -#define EMAC_REGS__RX_OVERRUNS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000003ffU) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__RESET 0 -#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__RX_OVERRUNS__TYPE uint32_t -#define EMAC_REGS__RX_OVERRUNS__READ 0xffffffffU -#define EMAC_REGS__RX_OVERRUNS__RCLR 0x000003ffU - -#endif /* __EMAC_REGS__RX_OVERRUNS_MACRO__ */ - - -/* macros for rx_overruns */ -#define INST_RX_OVERRUNS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_ip_ck_errors */ -#ifndef __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__ -#define __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__WIDTH 8 -#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__MASK 0x000000ffU -#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) - -/* macros for field reserved_31_8 */ -#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__SHIFT 8 -#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__WIDTH 24 -#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__MASK 0xffffff00U -#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__RESET 0 -#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__READ(src) \ - (((uint32_t)(src)\ - & 0xffffff00U) >> 8) -#define EMAC_REGS__RX_IP_CK_ERRORS__TYPE uint32_t -#define EMAC_REGS__RX_IP_CK_ERRORS__READ 0xffffffffU -#define EMAC_REGS__RX_IP_CK_ERRORS__RCLR 0x000000ffU - -#endif /* __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__ */ - - -/* macros for rx_ip_ck_errors */ -#define INST_RX_IP_CK_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_tcp_ck_errors */ -#ifndef __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__ -#define __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__WIDTH 8 -#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__MASK 0x000000ffU -#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) - -/* macros for field reserved_31_8 */ -#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__SHIFT 8 -#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__WIDTH 24 -#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__MASK 0xffffff00U -#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__RESET 0 -#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__READ(src) \ - (((uint32_t)(src)\ - & 0xffffff00U) >> 8) -#define EMAC_REGS__RX_TCP_CK_ERRORS__TYPE uint32_t -#define EMAC_REGS__RX_TCP_CK_ERRORS__READ 0xffffffffU -#define EMAC_REGS__RX_TCP_CK_ERRORS__RCLR 0x000000ffU - -#endif /* __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__ */ - - -/* macros for rx_tcp_ck_errors */ -#define INST_RX_TCP_CK_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_udp_ck_errors */ -#ifndef __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__ -#define __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__SHIFT 0 -#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__WIDTH 8 -#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__MASK 0x000000ffU -#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__RESET 0 -#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) - -/* macros for field reserved_31_8 */ -#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__SHIFT 8 -#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__WIDTH 24 -#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__MASK 0xffffff00U -#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__RESET 0 -#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__READ(src) \ - (((uint32_t)(src)\ - & 0xffffff00U) >> 8) -#define EMAC_REGS__RX_UDP_CK_ERRORS__TYPE uint32_t -#define EMAC_REGS__RX_UDP_CK_ERRORS__READ 0xffffffffU -#define EMAC_REGS__RX_UDP_CK_ERRORS__RCLR 0x000000ffU - -#endif /* __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__ */ - - -/* macros for rx_udp_ck_errors */ -#define INST_RX_UDP_CK_ERRORS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::auto_flushed_pkts */ -#ifndef __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__ -#define __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__SHIFT 0 -#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__WIDTH 16 -#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__RESET 0 -#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__RESET 0 -#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__AUTO_FLUSHED_PKTS__TYPE uint32_t -#define EMAC_REGS__AUTO_FLUSHED_PKTS__READ 0xffffffffU -#define EMAC_REGS__AUTO_FLUSHED_PKTS__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__ */ - - -/* macros for auto_flushed_pkts */ -#define INST_AUTO_FLUSHED_PKTS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_incr_sub_nsec */ -#ifndef __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__ -#define __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__ - -/* macros for field sub_ns_incr */ -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__SHIFT 0 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__WIDTH 16 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MASK 0x0000ffffU -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_23_16 */ -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__SHIFT 16 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__WIDTH 8 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__MASK 0x00ff0000U -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) - -/* macros for field sub_ns_incr_lsb */ -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__SHIFT 24 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__WIDTH 8 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MASK 0xff000000U -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0xff000000U) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xff000000U) | (((uint32_t)(src) <<\ - 24) & 0xff000000U) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0xff000000U))) -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__READ 0xffffffffU -#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__ */ - - -/* macros for tsu_timer_incr_sub_nsec */ -#define INST_TSU_TIMER_INCR_SUB_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_msb_sec */ -#ifndef __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__ -#define __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__WIDTH 16 -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MASK 0x0000ffffU -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_TIMER_MSB_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_TIMER_MSB_SEC__READ 0xffffffffU -#define EMAC_REGS__TSU_TIMER_MSB_SEC__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__ */ - - -/* macros for tsu_timer_msb_sec */ -#define INST_TSU_TIMER_MSB_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_strobe_msb_sec */ -#ifndef __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__ -#define __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__ - -/* macros for field strobe */ -#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__SHIFT 0 -#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__WIDTH 16 -#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__MASK 0x0000ffffU -#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__RESET 0 -#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TSU_STROBE_MSB_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_STROBE_MSB_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__ */ - - -/* macros for tsu_strobe_msb_sec */ -#define INST_TSU_STROBE_MSB_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_strobe_sec */ -#ifndef __EMAC_REGS__TSU_STROBE_SEC_MACRO__ -#define __EMAC_REGS__TSU_STROBE_SEC_MACRO__ - -/* macros for field strobe */ -#define EMAC_REGS__TSU_STROBE_SEC__STROBE__SHIFT 0 -#define EMAC_REGS__TSU_STROBE_SEC__STROBE__WIDTH 32 -#define EMAC_REGS__TSU_STROBE_SEC__STROBE__MASK 0xffffffffU -#define EMAC_REGS__TSU_STROBE_SEC__STROBE__RESET 0 -#define EMAC_REGS__TSU_STROBE_SEC__STROBE__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_STROBE_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_STROBE_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_STROBE_SEC_MACRO__ */ - - -/* macros for tsu_strobe_sec */ -#define INST_TSU_STROBE_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_strobe_nsec */ -#ifndef __EMAC_REGS__TSU_STROBE_NSEC_MACRO__ -#define __EMAC_REGS__TSU_STROBE_NSEC_MACRO__ - -/* macros for field strobe */ -#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__SHIFT 0 -#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__WIDTH 30 -#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__MASK 0x3fffffffU -#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__RESET 0 -#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__RESET 0 -#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TSU_STROBE_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_STROBE_NSEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_STROBE_NSEC_MACRO__ */ - - -/* macros for tsu_strobe_nsec */ -#define INST_TSU_STROBE_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_sec */ -#ifndef __EMAC_REGS__TSU_TIMER_SEC_MACRO__ -#define __EMAC_REGS__TSU_TIMER_SEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__WIDTH 32 -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__MASK 0xffffffffU -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__TSU_TIMER_SEC__TIMER__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__TSU_TIMER_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_TIMER_SEC__READ 0xffffffffU -#define EMAC_REGS__TSU_TIMER_SEC__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_TIMER_SEC_MACRO__ */ - - -/* macros for tsu_timer_sec */ -#define INST_TSU_TIMER_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_nsec */ -#ifndef __EMAC_REGS__TSU_TIMER_NSEC_MACRO__ -#define __EMAC_REGS__TSU_TIMER_NSEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__WIDTH 30 -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__MASK 0x3fffffffU -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__RESET 0 -#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TSU_TIMER_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_TIMER_NSEC__READ 0xffffffffU -#define EMAC_REGS__TSU_TIMER_NSEC__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_TIMER_NSEC_MACRO__ */ - - -/* macros for tsu_timer_nsec */ -#define INST_TSU_TIMER_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_adjust */ -#ifndef __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__ -#define __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__ - -/* macros for field increment_value */ -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__SHIFT 0 -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__WIDTH 30 -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MASK 0x3fffffffU -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__RESET 0 -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field reserved_30_30 */ -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__SHIFT 30 -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__WIDTH 1 -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__MASK 0x40000000U -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__RESET 0 -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field add_subtract */ -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SHIFT 31 -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__WIDTH 1 -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__MASK 0x80000000U -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__RESET 0 -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__WRITE(src) \ - (((uint32_t)(src)\ - << 31) & 0x80000000U) -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x80000000U) | (((uint32_t)(src) <<\ - 31) & 0x80000000U) -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 31) & ~0x80000000U))) -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__TSU_TIMER_ADJUST__TYPE uint32_t -#define EMAC_REGS__TSU_TIMER_ADJUST__READ 0x40000000U -#define EMAC_REGS__TSU_TIMER_ADJUST__WRITE 0x40000000U - -#endif /* __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__ */ - - -/* macros for tsu_timer_adjust */ -#define INST_TSU_TIMER_ADJUST__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_incr */ -#ifndef __EMAC_REGS__TSU_TIMER_INCR_MACRO__ -#define __EMAC_REGS__TSU_TIMER_INCR_MACRO__ - -/* macros for field ns_increment */ -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__SHIFT 0 -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__WIDTH 8 -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MASK 0x000000ffU -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field alt_ns_incr */ -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__SHIFT 8 -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__WIDTH 8 -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MASK 0x0000ff00U -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field num_incs */ -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__SHIFT 16 -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__WIDTH 8 -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MASK 0x00ff0000U -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field reserved_31_24 */ -#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__SHIFT 24 -#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__WIDTH 8 -#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__MASK 0xff000000U -#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__RESET 0 -#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__TSU_TIMER_INCR__TYPE uint32_t -#define EMAC_REGS__TSU_TIMER_INCR__READ 0xffffffffU -#define EMAC_REGS__TSU_TIMER_INCR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TSU_TIMER_INCR_MACRO__ */ - - -/* macros for tsu_timer_incr */ -#define INST_TSU_TIMER_INCR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_tx_sec */ -#ifndef __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__ -#define __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__WIDTH 32 -#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__MASK 0xffffffffU -#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_PTP_TX_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PTP_TX_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__ */ - - -/* macros for tsu_ptp_tx_sec */ -#define INST_TSU_PTP_TX_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_tx_nsec */ -#ifndef __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__ -#define __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__WIDTH 30 -#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__MASK 0x3fffffffU -#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__RESET 0 -#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TSU_PTP_TX_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_PTP_TX_NSEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__ */ - - -/* macros for tsu_ptp_tx_nsec */ -#define INST_TSU_PTP_TX_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_rx_sec */ -#ifndef __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__ -#define __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__WIDTH 32 -#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__MASK 0xffffffffU -#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_PTP_RX_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PTP_RX_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__ */ - - -/* macros for tsu_ptp_rx_sec */ -#define INST_TSU_PTP_RX_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_rx_nsec */ -#ifndef __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__ -#define __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__WIDTH 30 -#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__MASK 0x3fffffffU -#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__RESET 0 -#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TSU_PTP_RX_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_PTP_RX_NSEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__ */ - - -/* macros for tsu_ptp_rx_nsec */ -#define INST_TSU_PTP_RX_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_tx_sec */ -#ifndef __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__ -#define __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__WIDTH 32 -#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__MASK 0xffffffffU -#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_PEER_TX_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PEER_TX_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__ */ - - -/* macros for tsu_peer_tx_sec */ -#define INST_TSU_PEER_TX_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_tx_nsec */ -#ifndef __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__ -#define __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__WIDTH 30 -#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__MASK 0x3fffffffU -#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__RESET 0 -#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TSU_PEER_TX_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_PEER_TX_NSEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__ */ - - -/* macros for tsu_peer_tx_nsec */ -#define INST_TSU_PEER_TX_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_rx_sec */ -#ifndef __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__ -#define __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__WIDTH 32 -#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__MASK 0xffffffffU -#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__TSU_PEER_RX_SEC__TYPE uint32_t -#define EMAC_REGS__TSU_PEER_RX_SEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__ */ - - -/* macros for tsu_peer_rx_sec */ -#define INST_TSU_PEER_RX_SEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_rx_nsec */ -#ifndef __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__ -#define __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__ - -/* macros for field timer */ -#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__SHIFT 0 -#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__WIDTH 30 -#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__MASK 0x3fffffffU -#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__RESET 0 -#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__RESET 0 -#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TSU_PEER_RX_NSEC__TYPE uint32_t -#define EMAC_REGS__TSU_PEER_RX_NSEC__READ 0xffffffffU - -#endif /* __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__ */ - - -/* macros for tsu_peer_rx_nsec */ -#define INST_TSU_PEER_RX_NSEC__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_control */ -#ifndef __EMAC_REGS__PCS_CONTROL_MACRO__ -#define __EMAC_REGS__PCS_CONTROL_MACRO__ - -/* macros for field reserved_5_0 */ -#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__SHIFT 0 -#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__WIDTH 6 -#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__MASK 0x0000003fU -#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__RESET 0 -#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__READ(src) \ - ((uint32_t)(src)\ - & 0x0000003fU) - -/* macros for field speed_select_bit_0 */ -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__SHIFT 6 -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__MASK 0x00000040U -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__RESET 1 -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field collision_test */ -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SHIFT 7 -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__MASK 0x00000080U -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__RESET 0 -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field mac_duplex_state */ -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__SHIFT 8 -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__MASK 0x00000100U -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__RESET 0 -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field restart_auto_neg */ -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SHIFT 9 -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__MASK 0x00000200U -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__RESET 0 -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field reserved_11_10 */ -#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__SHIFT 10 -#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__WIDTH 2 -#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__MASK 0x00000c00U -#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__RESET 0 -#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__READ(src) \ - (((uint32_t)(src)\ - & 0x00000c00U) >> 10) - -/* macros for field enable_auto_neg */ -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SHIFT 12 -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__MASK 0x00001000U -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__RESET 1 -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field speed_select_bit_1 */ -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__SHIFT 13 -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__MASK 0x00002000U -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__RESET 0 -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field loopback_mode */ -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SHIFT 14 -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__MASK 0x00004000U -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__RESET 0 -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x00004000U) -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00004000U) | (((uint32_t)(src) <<\ - 14) & 0x00004000U) -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x00004000U))) -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field pcs_software_reset */ -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SHIFT 15 -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__WIDTH 1 -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__MASK 0x00008000U -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__RESET 1 -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_CONTROL__TYPE uint32_t -#define EMAC_REGS__PCS_CONTROL__READ 0xffffffffU -#define EMAC_REGS__PCS_CONTROL__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__PCS_CONTROL_MACRO__ */ - - -/* macros for pcs_control */ -#define INST_PCS_CONTROL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_status */ -#ifndef __EMAC_REGS__PCS_STATUS_MACRO__ -#define __EMAC_REGS__PCS_STATUS_MACRO__ - -/* macros for field extended_capabilities */ -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__SHIFT 0 -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__MASK 0x00000001U -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__RESET 1 -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_1 */ -#define EMAC_REGS__PCS_STATUS__RESERVED_1__SHIFT 1 -#define EMAC_REGS__PCS_STATUS__RESERVED_1__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__RESERVED_1__MASK 0x00000002U -#define EMAC_REGS__PCS_STATUS__RESERVED_1__RESET 0 -#define EMAC_REGS__PCS_STATUS__RESERVED_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__PCS_STATUS__RESERVED_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__PCS_STATUS__RESERVED_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field link_status */ -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__SHIFT 2 -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__MASK 0x00000004U -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__RESET 0 -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__PCS_STATUS__LINK_STATUS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field auto_neg_ability */ -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__SHIFT 3 -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__MASK 0x00000008U -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__RESET 1 -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field remote_fault */ -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__SHIFT 4 -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__MASK 0x00000010U -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__RESET 0 -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field auto_neg_complete */ -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__SHIFT 5 -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__MASK 0x00000020U -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__RESET 0 -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field reserved_7_6 */ -#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__SHIFT 6 -#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__WIDTH 2 -#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__MASK 0x000000c0U -#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__RESET 0 -#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__READ(src) \ - (((uint32_t)(src)\ - & 0x000000c0U) >> 6) - -/* macros for field extended_status */ -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__SHIFT 8 -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__MASK 0x00000100U -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__RESET 1 -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field base_100_t2_half_duplex */ -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__SHIFT 9 -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__MASK 0x00000200U -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field base_100_t2_full_duplex */ -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__SHIFT 10 -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__MASK 0x00000400U -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field mbps_10_half_duplex */ -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__SHIFT 11 -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__MASK 0x00000800U -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field mbps_10_full_duplex */ -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__SHIFT 12 -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__MASK 0x00001000U -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field base_100_x_half_duplex */ -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__SHIFT 13 -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__MASK 0x00002000U -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field base_100_x_full_duplex */ -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__SHIFT 14 -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__MASK 0x00004000U -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field base_100_t4 */ -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__SHIFT 15 -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__WIDTH 1 -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__MASK 0x00008000U -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__RESET 0 -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_STATUS__BASE_100_T4__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_STATUS__TYPE uint32_t -#define EMAC_REGS__PCS_STATUS__READ 0xffffffffU - -#endif /* __EMAC_REGS__PCS_STATUS_MACRO__ */ - - -/* macros for pcs_status */ -#define INST_PCS_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_adv */ -#ifndef __EMAC_REGS__PCS_AN_ADV_MACRO__ -#define __EMAC_REGS__PCS_AN_ADV_MACRO__ - -/* macros for field reserved_4_0 */ -#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__SHIFT 0 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__WIDTH 5 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__MASK 0x0000001fU -#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__READ(src) \ - ((uint32_t)(src)\ - & 0x0000001fU) - -/* macros for field full_duplex */ -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SHIFT 5 -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__MASK 0x00000020U -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__RESET 1 -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field half_duplex */ -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SHIFT 6 -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__MASK 0x00000040U -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field pause */ -#define EMAC_REGS__PCS_AN_ADV__PAUSE__SHIFT 7 -#define EMAC_REGS__PCS_AN_ADV__PAUSE__WIDTH 2 -#define EMAC_REGS__PCS_AN_ADV__PAUSE__MASK 0x00000180U -#define EMAC_REGS__PCS_AN_ADV__PAUSE__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__PAUSE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000180U) >> 7) -#define EMAC_REGS__PCS_AN_ADV__PAUSE__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000180U) -#define EMAC_REGS__PCS_AN_ADV__PAUSE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000180U) | (((uint32_t)(src) <<\ - 7) & 0x00000180U) -#define EMAC_REGS__PCS_AN_ADV__PAUSE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000180U))) - -/* macros for field reserved_11_9 */ -#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__SHIFT 9 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__WIDTH 3 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__MASK 0x00000e00U -#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__READ(src) \ - (((uint32_t)(src)\ - & 0x00000e00U) >> 9) - -/* macros for field remote_fault */ -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__SHIFT 12 -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__WIDTH 2 -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MASK 0x00003000U -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__READ(src) \ - (((uint32_t)(src)\ - & 0x00003000U) >> 12) -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00003000U) -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00003000U) | (((uint32_t)(src) <<\ - 12) & 0x00003000U) -#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00003000U))) - -/* macros for field reserved_14 */ -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__SHIFT 14 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__WIDTH 1 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__MASK 0x00004000U -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field next_page */ -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SHIFT 15 -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__WIDTH 1 -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__MASK 0x00008000U -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_AN_ADV__TYPE uint32_t -#define EMAC_REGS__PCS_AN_ADV__READ 0xffffffffU -#define EMAC_REGS__PCS_AN_ADV__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__PCS_AN_ADV_MACRO__ */ - - -/* macros for pcs_an_adv */ -#define INST_PCS_AN_ADV__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_lp_base */ -#ifndef __EMAC_REGS__PCS_AN_LP_BASE_MACRO__ -#define __EMAC_REGS__PCS_AN_LP_BASE_MACRO__ - -/* macros for field reserved_4_0 */ -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__SHIFT 0 -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__WIDTH 5 -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__MASK 0x0000001fU -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__READ(src) \ - ((uint32_t)(src)\ - & 0x0000001fU) - -/* macros for field link_partner_full_duplex */ -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__SHIFT 5 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__MASK 0x00000020U -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field link_partner_half_duplex */ -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__SHIFT 6 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__MASK 0x00000040U -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field pause */ -#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__SHIFT 7 -#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__WIDTH 2 -#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__MASK 0x00000180U -#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000180U) >> 7) - -/* macros for field speed_reserved */ -#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__SHIFT 9 -#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__WIDTH 3 -#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__MASK 0x00000e00U -#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000e00U) >> 9) - -/* macros for field link_partner_remote_fault_duplex_mode */ -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__SHIFT \ - 12 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__WIDTH \ - 2 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__MASK \ - 0x00003000U -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__RESET \ - 0 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__READ(src) \ - (((uint32_t)(src)\ - & 0x00003000U) >> 12) - -/* macros for field link_partner_acknowledge */ -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__SHIFT 14 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__MASK 0x00004000U -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field link_partner_next_page_status */ -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__SHIFT 15 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__MASK \ - 0x00008000U -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_AN_LP_BASE__TYPE uint32_t -#define EMAC_REGS__PCS_AN_LP_BASE__READ 0xffffffffU - -#endif /* __EMAC_REGS__PCS_AN_LP_BASE_MACRO__ */ - - -/* macros for pcs_an_lp_base */ -#define INST_PCS_AN_LP_BASE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_exp */ -#ifndef __EMAC_REGS__PCS_AN_EXP_MACRO__ -#define __EMAC_REGS__PCS_AN_EXP_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__SHIFT 0 -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__RESET 0 -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field page_received */ -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__SHIFT 1 -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__MASK 0x00000002U -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__RESET 0 -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field next_page_capability */ -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__SHIFT 2 -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__MASK 0x00000004U -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__RESET 1 -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field reserved_31_3 */ -#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__SHIFT 3 -#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__WIDTH 29 -#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__MASK 0xfffffff8U -#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__RESET 0 -#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffff8U) >> 3) -#define EMAC_REGS__PCS_AN_EXP__TYPE uint32_t -#define EMAC_REGS__PCS_AN_EXP__READ 0xffffffffU - -#endif /* __EMAC_REGS__PCS_AN_EXP_MACRO__ */ - - -/* macros for pcs_an_exp */ -#define INST_PCS_AN_EXP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_np_tx */ -#ifndef __EMAC_REGS__PCS_AN_NP_TX_MACRO__ -#define __EMAC_REGS__PCS_AN_NP_TX_MACRO__ - -/* macros for field message */ -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__SHIFT 0 -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__WIDTH 11 -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MASK 0x000007ffU -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__READ(src) \ - ((uint32_t)(src)\ - & 0x000007ffU) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000007ffU) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000007ffU) | ((uint32_t)(src) &\ - 0x000007ffU) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000007ffU))) - -/* macros for field reserved_11 */ -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__SHIFT 11 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__WIDTH 1 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__MASK 0x00000800U -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field acknowledge_2 */ -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SHIFT 12 -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__WIDTH 1 -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__MASK 0x00001000U -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field message_page_indicator */ -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SHIFT 13 -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__WIDTH 1 -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__MASK 0x00002000U -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x00002000U) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00002000U) | (((uint32_t)(src) <<\ - 13) & 0x00002000U) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x00002000U))) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field reserved_14 */ -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__SHIFT 14 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__WIDTH 1 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__MASK 0x00004000U -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field next_page_to_transmit */ -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SHIFT 15 -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__WIDTH 1 -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__MASK 0x00008000U -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__WRITE(src) \ - (((uint32_t)(src)\ - << 15) & 0x00008000U) -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00008000U) | (((uint32_t)(src) <<\ - 15) & 0x00008000U) -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 15) & ~0x00008000U))) -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_AN_NP_TX__TYPE uint32_t -#define EMAC_REGS__PCS_AN_NP_TX__READ 0xffffffffU -#define EMAC_REGS__PCS_AN_NP_TX__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__PCS_AN_NP_TX_MACRO__ */ - - -/* macros for pcs_an_np_tx */ -#define INST_PCS_AN_NP_TX__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_lp_np */ -#ifndef __EMAC_REGS__PCS_AN_LP_NP_MACRO__ -#define __EMAC_REGS__PCS_AN_LP_NP_MACRO__ - -/* macros for field message */ -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__SHIFT 0 -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__WIDTH 11 -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__MASK 0x000007ffU -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__READ(src) \ - ((uint32_t)(src)\ - & 0x000007ffU) - -/* macros for field toggle */ -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__SHIFT 11 -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__MASK 0x00000800U -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field acknowledge_2 */ -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__SHIFT 12 -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__MASK 0x00001000U -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field message_page_indicator */ -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__SHIFT 13 -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__MASK 0x00002000U -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field acknowledge */ -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__SHIFT 14 -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__MASK 0x00004000U -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field next_page_to_receive */ -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__SHIFT 15 -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__WIDTH 1 -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__MASK 0x00008000U -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_AN_LP_NP__TYPE uint32_t -#define EMAC_REGS__PCS_AN_LP_NP__READ 0xffffffffU - -#endif /* __EMAC_REGS__PCS_AN_LP_NP_MACRO__ */ - - -/* macros for pcs_an_lp_np */ -#define INST_PCS_AN_LP_NP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_ext_status */ -#ifndef __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__ -#define __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__ - -/* macros for field reserved_11_0 */ -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__SHIFT 0 -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__WIDTH 12 -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__MASK 0x00000fffU -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__RESET 0 -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000fffU) - -/* macros for field half_duplex_1000base_t */ -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__SHIFT 12 -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__MASK 0x00001000U -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__RESET 0 -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field full_duplex_1000base_t */ -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__SHIFT 13 -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__MASK 0x00002000U -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__RESET 0 -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field half_duplex_1000base_x */ -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__SHIFT 14 -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__MASK 0x00004000U -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__RESET 0 -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field full_duplex_1000base_x */ -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__SHIFT 15 -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__WIDTH 1 -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__MASK 0x00008000U -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__RESET 1 -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__RESET 0 -#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__PCS_AN_EXT_STATUS__TYPE uint32_t -#define EMAC_REGS__PCS_AN_EXT_STATUS__READ 0xffffffffU - -#endif /* __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__ */ - - -/* macros for pcs_an_ext_status */ -#define INST_PCS_AN_EXT_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum1 */ -#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__ -#define __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__ - -/* macros for field quantum_p2 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__SHIFT 0 -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MASK 0x0000ffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field quantum_p3 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__SHIFT 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MASK 0xffff0000U -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffff0000U) | (((uint32_t)(src) <<\ - 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0xffff0000U))) -#define EMAC_REGS__TX_PAUSE_QUANTUM1__TYPE uint32_t -#define EMAC_REGS__TX_PAUSE_QUANTUM1__READ 0xffffffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM1__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__ */ - - -/* macros for tx_pause_quantum1 */ -#define INST_TX_PAUSE_QUANTUM1__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum2 */ -#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__ -#define __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__ - -/* macros for field quantum_p4 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__SHIFT 0 -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MASK 0x0000ffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field quantum_p5 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__SHIFT 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MASK 0xffff0000U -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffff0000U) | (((uint32_t)(src) <<\ - 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0xffff0000U))) -#define EMAC_REGS__TX_PAUSE_QUANTUM2__TYPE uint32_t -#define EMAC_REGS__TX_PAUSE_QUANTUM2__READ 0xffffffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM2__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__ */ - - -/* macros for tx_pause_quantum2 */ -#define INST_TX_PAUSE_QUANTUM2__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum3 */ -#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__ -#define __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__ - -/* macros for field quantum_p6 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__SHIFT 0 -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MASK 0x0000ffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field quantum_p7 */ -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__SHIFT 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__WIDTH 16 -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MASK 0xffff0000U -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__RESET 0xFFFF -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffff0000U) | (((uint32_t)(src) <<\ - 16) & 0xffff0000U) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0xffff0000U))) -#define EMAC_REGS__TX_PAUSE_QUANTUM3__TYPE uint32_t -#define EMAC_REGS__TX_PAUSE_QUANTUM3__READ 0xffffffffU -#define EMAC_REGS__TX_PAUSE_QUANTUM3__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__ */ - - -/* macros for tx_pause_quantum3 */ -#define INST_TX_PAUSE_QUANTUM3__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_lpi */ -#ifndef __EMAC_REGS__RX_LPI_MACRO__ -#define __EMAC_REGS__RX_LPI_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__RX_LPI__COUNT__SHIFT 0 -#define EMAC_REGS__RX_LPI__COUNT__WIDTH 16 -#define EMAC_REGS__RX_LPI__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__RX_LPI__COUNT__RESET 0 -#define EMAC_REGS__RX_LPI__COUNT__READ(src) ((uint32_t)(src) & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__RX_LPI__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__RX_LPI__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__RX_LPI__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__RX_LPI__RESERVED_31_16__RESET 0 -#define EMAC_REGS__RX_LPI__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__RX_LPI__TYPE uint32_t -#define EMAC_REGS__RX_LPI__READ 0xffffffffU -#define EMAC_REGS__RX_LPI__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__RX_LPI_MACRO__ */ - - -/* macros for rx_lpi */ -#define INST_RX_LPI__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_lpi_time */ -#ifndef __EMAC_REGS__RX_LPI_TIME_MACRO__ -#define __EMAC_REGS__RX_LPI_TIME_MACRO__ - -/* macros for field lpi_time */ -#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__SHIFT 0 -#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__WIDTH 24 -#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__MASK 0x00ffffffU -#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__RESET 0 -#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x00ffffffU) - -/* macros for field reserved_31_24 */ -#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__SHIFT 24 -#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__WIDTH 8 -#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__MASK 0xff000000U -#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__RESET 0 -#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__RX_LPI_TIME__TYPE uint32_t -#define EMAC_REGS__RX_LPI_TIME__READ 0xffffffffU -#define EMAC_REGS__RX_LPI_TIME__RCLR 0x00ffffffU - -#endif /* __EMAC_REGS__RX_LPI_TIME_MACRO__ */ - - -/* macros for rx_lpi_time */ -#define INST_RX_LPI_TIME__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_lpi */ -#ifndef __EMAC_REGS__TX_LPI_MACRO__ -#define __EMAC_REGS__TX_LPI_MACRO__ - -/* macros for field count */ -#define EMAC_REGS__TX_LPI__COUNT__SHIFT 0 -#define EMAC_REGS__TX_LPI__COUNT__WIDTH 16 -#define EMAC_REGS__TX_LPI__COUNT__MASK 0x0000ffffU -#define EMAC_REGS__TX_LPI__COUNT__RESET 0 -#define EMAC_REGS__TX_LPI__COUNT__READ(src) ((uint32_t)(src) & 0x0000ffffU) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__TX_LPI__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__TX_LPI__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__TX_LPI__RESERVED_31_16__MASK 0xffff0000U -#define EMAC_REGS__TX_LPI__RESERVED_31_16__RESET 0 -#define EMAC_REGS__TX_LPI__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TX_LPI__TYPE uint32_t -#define EMAC_REGS__TX_LPI__READ 0xffffffffU -#define EMAC_REGS__TX_LPI__RCLR 0x0000ffffU - -#endif /* __EMAC_REGS__TX_LPI_MACRO__ */ - - -/* macros for tx_lpi */ -#define INST_TX_LPI__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_lpi_time */ -#ifndef __EMAC_REGS__TX_LPI_TIME_MACRO__ -#define __EMAC_REGS__TX_LPI_TIME_MACRO__ - -/* macros for field lpi_time */ -#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__SHIFT 0 -#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__WIDTH 24 -#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__MASK 0x00ffffffU -#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__RESET 0 -#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x00ffffffU) - -/* macros for field reserved_31_24 */ -#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__SHIFT 24 -#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__WIDTH 8 -#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__MASK 0xff000000U -#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__RESET 0 -#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__TX_LPI_TIME__TYPE uint32_t -#define EMAC_REGS__TX_LPI_TIME__READ 0xffffffffU -#define EMAC_REGS__TX_LPI_TIME__RCLR 0x00ffffffU - -#endif /* __EMAC_REGS__TX_LPI_TIME_MACRO__ */ - - -/* macros for tx_lpi_time */ -#define INST_TX_LPI_TIME__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug1 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__ - -/* macros for field no_pcs */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__MASK 0x00000001U -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field exclude_qbv */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__SHIFT 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__MASK 0x00000002U -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field reserved_3_2 */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__SHIFT 2 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__WIDTH 2 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__MASK 0x0000000cU -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__READ(src) \ - (((uint32_t)(src)\ - & 0x0000000cU) >> 2) - -/* macros for field int_loopback */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__SHIFT 4 -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__MASK 0x00000010U -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field reserved_5 */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__SHIFT 5 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__MASK 0x00000020U -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field ext_fifo_interface */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SHIFT 6 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__MASK 0x00000040U -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field reserved_7 */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__SHIFT 7 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__MASK 0x00000080U -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_8 */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__MASK 0x00000100U -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field user_io */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__SHIFT 9 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__MASK 0x00000200U -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field user_out_width */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__SHIFT 10 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__WIDTH 5 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__MASK 0x00007c00U -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__RESET 16 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__READ(src) \ - (((uint32_t)(src)\ - & 0x00007c00U) >> 10) - -/* macros for field user_in_width */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__SHIFT 15 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__WIDTH 5 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__MASK 0x000f8000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__RESET 16 -#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__READ(src) \ - (((uint32_t)(src)\ - & 0x000f8000U) >> 15) - -/* macros for field reserved_20 */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__MASK 0x00100000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__READ(src) \ - (((uint32_t)(src)\ - & 0x00100000U) >> 20) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field no_stats */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__SHIFT 21 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__MASK 0x00200000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__READ(src) \ - (((uint32_t)(src)\ - & 0x00200000U) >> 21) -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field no_snapshot */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__SHIFT 22 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__MASK 0x00400000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__READ(src) \ - (((uint32_t)(src)\ - & 0x00400000U) >> 22) -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field irq_read_clear */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SHIFT 23 -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__MASK 0x00800000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field exclude_cbs */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__MASK 0x01000000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field dma_bus_width */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__SHIFT 25 -#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__WIDTH 3 -#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__MASK 0x0e000000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__READ(src) \ - (((uint32_t)(src)\ - & 0x0e000000U) >> 25) - -/* macros for field axi_cache_value */ -#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__SHIFT 28 -#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__MASK 0xf0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__DESIGNCFG_DEBUG1__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG1__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__ */ - - -/* macros for designcfg_debug1 */ -#define INST_DESIGNCFG_DEBUG1__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug2 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__ - -/* macros for field jumbo_max_length */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__WIDTH 14 -#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__MASK 0x00003fffU -#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__RESET 10240 -#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__READ(src) \ - ((uint32_t)(src)\ - & 0x00003fffU) - -/* macros for field reserved_15_14 */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__SHIFT 14 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__WIDTH 2 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__MASK 0x0000c000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__READ(src) \ - (((uint32_t)(src)\ - & 0x0000c000U) >> 14) - -/* macros for field hprot_value */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__SHIFT 16 -#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__MASK 0x000f0000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__READ(src) \ - (((uint32_t)(src)\ - & 0x000f0000U) >> 16) - -/* macros for field rx_pkt_buffer */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__MASK 0x00100000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__READ(src) \ - (((uint32_t)(src)\ - & 0x00100000U) >> 20) -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field tx_pkt_buffer */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SHIFT 21 -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__MASK 0x00200000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__READ(src) \ - (((uint32_t)(src)\ - & 0x00200000U) >> 21) -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field rx_pbuf_addr */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__SHIFT 22 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__MASK 0x03c00000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__RESET 11 -#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__READ(src) \ - (((uint32_t)(src)\ - & 0x03c00000U) >> 22) - -/* macros for field tx_pbuf_addr */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__SHIFT 26 -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__MASK 0x3c000000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__RESET 14 -#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__READ(src) \ - (((uint32_t)(src)\ - & 0x3c000000U) >> 26) - -/* macros for field axi */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__SHIFT 30 -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__MASK 0x40000000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field spram */ -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__SHIFT 31 -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__MASK 0x80000000U -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__DESIGNCFG_DEBUG2__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG2__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__ */ - - -/* macros for designcfg_debug2 */ -#define INST_DESIGNCFG_DEBUG2__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug3 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__ - -/* macros for field reserved_23_0 */ -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__WIDTH 24 -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__MASK 0x00ffffffU -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00ffffffU) - -/* macros for field num_spec_add_filters */ -#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__WIDTH 6 -#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__MASK 0x3f000000U -#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__RESET 36 -#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__READ(src) \ - (((uint32_t)(src)\ - & 0x3f000000U) >> 24) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__DESIGNCFG_DEBUG3__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG3__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__ */ - - -/* macros for designcfg_debug3 */ -#define INST_DESIGNCFG_DEBUG3__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug4 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__ - -/* macros for field reserved_31_0 */ -#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__WIDTH 32 -#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__MASK 0xffffffffU -#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__DESIGNCFG_DEBUG4__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG4__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__ */ - - -/* macros for designcfg_debug4 */ -#define INST_DESIGNCFG_DEBUG4__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug5 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__ - -/* macros for field rx_fifo_cnt_width */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__MASK 0x0000000fU -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__RESET 5 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) - -/* macros for field tx_fifo_cnt_width */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__SHIFT 4 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__MASK 0x000000f0U -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__READ(src) \ - (((uint32_t)(src)\ - & 0x000000f0U) >> 4) - -/* macros for field tsu */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__MASK 0x00000100U -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field phy_ident */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__SHIFT 9 -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__MASK 0x00000200U -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field dma_bus_width_def */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__SHIFT 10 -#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__WIDTH 2 -#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__MASK 0x00000c00U -#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__READ(src) \ - (((uint32_t)(src)\ - & 0x00000c00U) >> 10) - -/* macros for field mdc_clock_div */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__SHIFT 12 -#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__WIDTH 3 -#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__MASK 0x00007000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__READ(src) \ - (((uint32_t)(src)\ - & 0x00007000U) >> 12) - -/* macros for field endian_swap_def */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__SHIFT 15 -#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__WIDTH 2 -#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__MASK 0x00018000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__RESET 3 -#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__READ(src) \ - (((uint32_t)(src)\ - & 0x00018000U) >> 15) - -/* macros for field rx_pbuf_size_def */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__SHIFT 17 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__WIDTH 2 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__MASK 0x00060000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__RESET 3 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__READ(src) \ - (((uint32_t)(src)\ - & 0x00060000U) >> 17) - -/* macros for field tx_pbuf_size_def */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__SHIFT 19 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__MASK 0x00080000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field rx_buffer_length_def */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__WIDTH 8 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__MASK 0x0ff00000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__READ(src) \ - (((uint32_t)(src)\ - & 0x0ff00000U) >> 20) - -/* macros for field tsu_clk */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__SHIFT 28 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__MASK 0x10000000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field axi_prot_value */ -#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__SHIFT 29 -#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__WIDTH 3 -#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__MASK 0xe0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__READ(src) \ - (((uint32_t)(src)\ - & 0xe0000000U) >> 29) -#define EMAC_REGS__DESIGNCFG_DEBUG5__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG5__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__ */ - - -/* macros for designcfg_debug5 */ -#define INST_DESIGNCFG_DEBUG5__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug6 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field dma_priority_queue1 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__SHIFT 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__MASK 0x00000002U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field dma_priority_queue2 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__SHIFT 2 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__MASK 0x00000004U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field dma_priority_queue3 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__SHIFT 3 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__MASK 0x00000008U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field dma_priority_queue4 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__SHIFT 4 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__MASK 0x00000010U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field dma_priority_queue5 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__SHIFT 5 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__MASK 0x00000020U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field dma_priority_queue6 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__SHIFT 6 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__MASK 0x00000040U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field dma_priority_queue7 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__SHIFT 7 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__MASK 0x00000080U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field dma_priority_queue8 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__MASK 0x00000100U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field dma_priority_queue9 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__SHIFT 9 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__MASK 0x00000200U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field dma_priority_queue10 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__SHIFT 10 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__MASK 0x00000400U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field dma_priority_queue11 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__SHIFT 11 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__MASK 0x00000800U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field dma_priority_queue12 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__SHIFT 12 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__MASK 0x00001000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field dma_priority_queue13 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__SHIFT 13 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__MASK 0x00002000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__READ(src) \ - (((uint32_t)(src)\ - & 0x00002000U) >> 13) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__SET(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(1) << 13) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00002000U) | ((uint32_t)(0) << 13) - -/* macros for field dma_priority_queue14 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__SHIFT 14 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__MASK 0x00004000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__READ(src) \ - (((uint32_t)(src)\ - & 0x00004000U) >> 14) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__SET(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(1) << 14) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00004000U) | ((uint32_t)(0) << 14) - -/* macros for field dma_priority_queue15 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__SHIFT 15 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__MASK 0x00008000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field tx_pbuf_queue_segment_size */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__SHIFT 16 -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__MASK \ - 0x000f0000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__READ(src) \ - (((uint32_t)(src)\ - & 0x000f0000U) >> 16) - -/* macros for field ext_tsu_timer */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__MASK 0x00100000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__READ(src) \ - (((uint32_t)(src)\ - & 0x00100000U) >> 20) -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field tx_add_fifo_if */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SHIFT 21 -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__MASK 0x00200000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__READ(src) \ - (((uint32_t)(src)\ - & 0x00200000U) >> 21) -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field host_if_soft_select */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SHIFT 22 -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__MASK 0x00400000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__READ(src) \ - (((uint32_t)(src)\ - & 0x00400000U) >> 22) -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field dma_addr_width_is_64b */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SHIFT 23 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__MASK 0x00800000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field pfc_multi_quantum */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__MASK 0x01000000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field pbuf_cutthru */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SHIFT 25 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__MASK 0x02000000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__READ(src) \ - (((uint32_t)(src)\ - & 0x02000000U) >> 25) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SET(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(1) << 25) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__CLR(dst) \ - (dst) = ((dst) &\ - ~0x02000000U) | ((uint32_t)(0) << 25) - -/* macros for field pbuf_rsc */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__SHIFT 26 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__MASK 0x04000000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__RESET 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__READ(src) \ - (((uint32_t)(src)\ - & 0x04000000U) >> 26) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__SET(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(1) << 26) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__CLR(dst) \ - (dst) = ((dst) &\ - ~0x04000000U) | ((uint32_t)(0) << 26) - -/* macros for field pbuf_lso */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__SHIFT 27 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__WIDTH 1 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__MASK 0x08000000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field reserved_31_28 */ -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__SHIFT 28 -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__MASK 0xf0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__DESIGNCFG_DEBUG6__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG6__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__ */ - - -/* macros for designcfg_debug6 */ -#define INST_DESIGNCFG_DEBUG6__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug7 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__ - -/* macros for field tx_pbuf_num_segments_q0 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__MASK 0x0000000fU -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) - -/* macros for field tx_pbuf_num_segments_q1 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__SHIFT 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__MASK 0x000000f0U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__READ(src) \ - (((uint32_t)(src)\ - & 0x000000f0U) >> 4) - -/* macros for field tx_pbuf_num_segments_q2 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__MASK 0x00000f00U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__READ(src) \ - (((uint32_t)(src)\ - & 0x00000f00U) >> 8) - -/* macros for field tx_pbuf_num_segments_q3 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__SHIFT 12 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__MASK 0x0000f000U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__READ(src) \ - (((uint32_t)(src)\ - & 0x0000f000U) >> 12) - -/* macros for field tx_pbuf_num_segments_q4 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__SHIFT 16 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__MASK 0x000f0000U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__READ(src) \ - (((uint32_t)(src)\ - & 0x000f0000U) >> 16) - -/* macros for field tx_pbuf_num_segments_q5 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__MASK 0x00f00000U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__READ(src) \ - (((uint32_t)(src)\ - & 0x00f00000U) >> 20) - -/* macros for field tx_pbuf_num_segments_q6 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__MASK 0x0f000000U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__READ(src) \ - (((uint32_t)(src)\ - & 0x0f000000U) >> 24) - -/* macros for field tx_pbuf_num_segments_q7 */ -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__SHIFT 28 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__MASK 0xf0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__DESIGNCFG_DEBUG7__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG7__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__ */ - - -/* macros for designcfg_debug7 */ -#define INST_DESIGNCFG_DEBUG7__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug8 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__ - -/* macros for field num_scr2_compare_regs */ -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__WIDTH 8 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__MASK 0x000000ffU -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__RESET 32 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) - -/* macros for field num_scr2_ethtype_regs */ -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__WIDTH 8 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__MASK 0x0000ff00U -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__RESET 8 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) - -/* macros for field num_type2_screeners */ -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__SHIFT 16 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__WIDTH 8 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__MASK 0x00ff0000U -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__RESET 16 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) - -/* macros for field num_type1_screeners */ -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__WIDTH 8 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__MASK 0xff000000U -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__RESET 16 -#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__DESIGNCFG_DEBUG8__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG8__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__ */ - - -/* macros for designcfg_debug8 */ -#define INST_DESIGNCFG_DEBUG8__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug9 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__ - -/* macros for field tx_pbuf_num_segments_q8 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__MASK 0x0000000fU -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) - -/* macros for field tx_pbuf_num_segments_q9 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__SHIFT 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__MASK 0x000000f0U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__READ(src) \ - (((uint32_t)(src)\ - & 0x000000f0U) >> 4) - -/* macros for field tx_pbuf_num_segments_q10 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__MASK 0x00000f00U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__READ(src) \ - (((uint32_t)(src)\ - & 0x00000f00U) >> 8) - -/* macros for field tx_pbuf_num_segments_q11 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__SHIFT 12 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__MASK 0x0000f000U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__READ(src) \ - (((uint32_t)(src)\ - & 0x0000f000U) >> 12) - -/* macros for field tx_pbuf_num_segments_q12 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__SHIFT 16 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__MASK 0x000f0000U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__READ(src) \ - (((uint32_t)(src)\ - & 0x000f0000U) >> 16) - -/* macros for field tx_pbuf_num_segments_q13 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__MASK 0x00f00000U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__READ(src) \ - (((uint32_t)(src)\ - & 0x00f00000U) >> 20) - -/* macros for field tx_pbuf_num_segments_q14 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__MASK 0x0f000000U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__READ(src) \ - (((uint32_t)(src)\ - & 0x0f000000U) >> 24) - -/* macros for field tx_pbuf_num_segments_q15 */ -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__SHIFT 28 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__MASK 0xf0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__RESET 0 -#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__DESIGNCFG_DEBUG9__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG9__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__ */ - - -/* macros for designcfg_debug9 */ -#define INST_DESIGNCFG_DEBUG9__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug10 */ -#ifndef __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__ -#define __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__ - -/* macros for field axi_rx_descr_wr_buff_bits */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__SHIFT 0 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__MASK \ - 0x0000000fU -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) - -/* macros for field axi_tx_descr_wr_buff_bits */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__SHIFT 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__MASK \ - 0x000000f0U -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__READ(src) \ - (((uint32_t)(src)\ - & 0x000000f0U) >> 4) - -/* macros for field axi_rx_descr_rd_buff_bits */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__SHIFT 8 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__MASK \ - 0x00000f00U -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__READ(src) \ - (((uint32_t)(src)\ - & 0x00000f00U) >> 8) - -/* macros for field axi_tx_descr_rd_buff_bits */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__SHIFT 12 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__MASK \ - 0x0000f000U -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__READ(src) \ - (((uint32_t)(src)\ - & 0x0000f000U) >> 12) - -/* macros for field axi_access_pipeline_bits */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__SHIFT 16 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__MASK \ - 0x000f0000U -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__RESET 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__READ(src) \ - (((uint32_t)(src)\ - & 0x000f0000U) >> 16) - -/* macros for field rx_pbuf_data */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__SHIFT 20 -#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__MASK 0x00f00000U -#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__READ(src) \ - (((uint32_t)(src)\ - & 0x00f00000U) >> 20) - -/* macros for field tx_pbuf_data */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__SHIFT 24 -#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__MASK 0x0f000000U -#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__READ(src) \ - (((uint32_t)(src)\ - & 0x0f000000U) >> 24) - -/* macros for field emac_bus_width */ -#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__SHIFT 28 -#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__WIDTH 4 -#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__MASK 0xf0000000U -#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__RESET 2 -#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__READ(src) \ - (((uint32_t)(src)\ - & 0xf0000000U) >> 28) -#define EMAC_REGS__DESIGNCFG_DEBUG10__TYPE uint32_t -#define EMAC_REGS__DESIGNCFG_DEBUG10__READ 0xffffffffU - -#endif /* __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__ */ - - -/* macros for designcfg_debug10 */ -#define INST_DESIGNCFG_DEBUG10__NUM 1 - -/* macros for spec_add5_bottom */ -#define INST_SPEC_ADD5_BOTTOM__NUM 1 - -/* macros for spec_add5_top */ -#define INST_SPEC_ADD5_TOP__NUM 1 - -/* macros for spec_add6_bottom */ -#define INST_SPEC_ADD6_BOTTOM__NUM 1 - -/* macros for spec_add6_top */ -#define INST_SPEC_ADD6_TOP__NUM 1 - -/* macros for spec_add7_bottom */ -#define INST_SPEC_ADD7_BOTTOM__NUM 1 - -/* macros for spec_add7_top */ -#define INST_SPEC_ADD7_TOP__NUM 1 - -/* macros for spec_add8_bottom */ -#define INST_SPEC_ADD8_BOTTOM__NUM 1 - -/* macros for spec_add8_top */ -#define INST_SPEC_ADD8_TOP__NUM 1 - -/* macros for spec_add9_bottom */ -#define INST_SPEC_ADD9_BOTTOM__NUM 1 - -/* macros for spec_add9_top */ -#define INST_SPEC_ADD9_TOP__NUM 1 - -/* macros for spec_add10_bottom */ -#define INST_SPEC_ADD10_BOTTOM__NUM 1 - -/* macros for spec_add10_top */ -#define INST_SPEC_ADD10_TOP__NUM 1 - -/* macros for spec_add11_bottom */ -#define INST_SPEC_ADD11_BOTTOM__NUM 1 - -/* macros for spec_add11_top */ -#define INST_SPEC_ADD11_TOP__NUM 1 - -/* macros for spec_add12_bottom */ -#define INST_SPEC_ADD12_BOTTOM__NUM 1 - -/* macros for spec_add12_top */ -#define INST_SPEC_ADD12_TOP__NUM 1 - -/* macros for spec_add13_bottom */ -#define INST_SPEC_ADD13_BOTTOM__NUM 1 - -/* macros for spec_add13_top */ -#define INST_SPEC_ADD13_TOP__NUM 1 - -/* macros for spec_add14_bottom */ -#define INST_SPEC_ADD14_BOTTOM__NUM 1 - -/* macros for spec_add14_top */ -#define INST_SPEC_ADD14_TOP__NUM 1 - -/* macros for spec_add15_bottom */ -#define INST_SPEC_ADD15_BOTTOM__NUM 1 - -/* macros for spec_add15_top */ -#define INST_SPEC_ADD15_TOP__NUM 1 - -/* macros for spec_add16_bottom */ -#define INST_SPEC_ADD16_BOTTOM__NUM 1 - -/* macros for spec_add16_top */ -#define INST_SPEC_ADD16_TOP__NUM 1 - -/* macros for spec_add17_bottom */ -#define INST_SPEC_ADD17_BOTTOM__NUM 1 - -/* macros for spec_add17_top */ -#define INST_SPEC_ADD17_TOP__NUM 1 - -/* macros for spec_add18_bottom */ -#define INST_SPEC_ADD18_BOTTOM__NUM 1 - -/* macros for spec_add18_top */ -#define INST_SPEC_ADD18_TOP__NUM 1 - -/* macros for spec_add19_bottom */ -#define INST_SPEC_ADD19_BOTTOM__NUM 1 - -/* macros for spec_add19_top */ -#define INST_SPEC_ADD19_TOP__NUM 1 - -/* macros for spec_add20_bottom */ -#define INST_SPEC_ADD20_BOTTOM__NUM 1 - -/* macros for spec_add20_top */ -#define INST_SPEC_ADD20_TOP__NUM 1 - -/* macros for spec_add21_bottom */ -#define INST_SPEC_ADD21_BOTTOM__NUM 1 - -/* macros for spec_add21_top */ -#define INST_SPEC_ADD21_TOP__NUM 1 - -/* macros for spec_add22_bottom */ -#define INST_SPEC_ADD22_BOTTOM__NUM 1 - -/* macros for spec_add22_top */ -#define INST_SPEC_ADD22_TOP__NUM 1 - -/* macros for spec_add23_bottom */ -#define INST_SPEC_ADD23_BOTTOM__NUM 1 - -/* macros for spec_add23_top */ -#define INST_SPEC_ADD23_TOP__NUM 1 - -/* macros for spec_add24_bottom */ -#define INST_SPEC_ADD24_BOTTOM__NUM 1 - -/* macros for spec_add24_top */ -#define INST_SPEC_ADD24_TOP__NUM 1 - -/* macros for spec_add25_bottom */ -#define INST_SPEC_ADD25_BOTTOM__NUM 1 - -/* macros for spec_add25_top */ -#define INST_SPEC_ADD25_TOP__NUM 1 - -/* macros for spec_add26_bottom */ -#define INST_SPEC_ADD26_BOTTOM__NUM 1 - -/* macros for spec_add26_top */ -#define INST_SPEC_ADD26_TOP__NUM 1 - -/* macros for spec_add27_bottom */ -#define INST_SPEC_ADD27_BOTTOM__NUM 1 - -/* macros for spec_add27_top */ -#define INST_SPEC_ADD27_TOP__NUM 1 - -/* macros for spec_add28_bottom */ -#define INST_SPEC_ADD28_BOTTOM__NUM 1 - -/* macros for spec_add28_top */ -#define INST_SPEC_ADD28_TOP__NUM 1 - -/* macros for spec_add29_bottom */ -#define INST_SPEC_ADD29_BOTTOM__NUM 1 - -/* macros for spec_add29_top */ -#define INST_SPEC_ADD29_TOP__NUM 1 - -/* macros for spec_add30_bottom */ -#define INST_SPEC_ADD30_BOTTOM__NUM 1 - -/* macros for spec_add30_top */ -#define INST_SPEC_ADD30_TOP__NUM 1 - -/* macros for spec_add31_bottom */ -#define INST_SPEC_ADD31_BOTTOM__NUM 1 - -/* macros for spec_add31_top */ -#define INST_SPEC_ADD31_TOP__NUM 1 - -/* macros for spec_add32_bottom */ -#define INST_SPEC_ADD32_BOTTOM__NUM 1 - -/* macros for spec_add32_top */ -#define INST_SPEC_ADD32_TOP__NUM 1 - -/* macros for spec_add33_bottom */ -#define INST_SPEC_ADD33_BOTTOM__NUM 1 - -/* macros for spec_add33_top */ -#define INST_SPEC_ADD33_TOP__NUM 1 - -/* macros for spec_add34_bottom */ -#define INST_SPEC_ADD34_BOTTOM__NUM 1 - -/* macros for spec_add34_top */ -#define INST_SPEC_ADD34_TOP__NUM 1 - -/* macros for spec_add35_bottom */ -#define INST_SPEC_ADD35_BOTTOM__NUM 1 - -/* macros for spec_add35_top */ -#define INST_SPEC_ADD35_TOP__NUM 1 - -/* macros for spec_add36_bottom */ -#define INST_SPEC_ADD36_BOTTOM__NUM 1 - -/* macros for spec_add36_top */ -#define INST_SPEC_ADD36_TOP__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_q_status */ -#ifndef __EMAC_REGS__INT_Q_STATUS_MACRO__ -#define __EMAC_REGS__INT_Q_STATUS_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__SHIFT 0 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_Q_STATUS__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field receive_complete */ -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__SHIFT 1 -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__MASK 0x00000002U -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field rx_used_bit_read */ -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__SHIFT 2 -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__MASK 0x00000004U -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field reserved_4_3 */ -#define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__SHIFT 3 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__WIDTH 2 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__MASK 0x00000018U -#define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000018U) >> 3) - -/* macros for field retry_limit_exceeded_or_late_collision */ -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT \ - 5 -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH \ - 1 -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \ - 0x00000020U -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET \ - 0 -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field amba_error */ -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__SHIFT 6 -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__MASK 0x00000040U -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field transmit_complete */ -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__SHIFT 7 -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__MASK 0x00000080U -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_9_8 */ -#define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__SHIFT 8 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__WIDTH 2 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__MASK 0x00000300U -#define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000300U) >> 8) - -/* macros for field receive_overrun */ -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__SHIFT 10 -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__MASK 0x00000400U -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__READ(src) \ - (((uint32_t)(src)\ - & 0x00000400U) >> 10) -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(1) << 10) -#define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000400U) | ((uint32_t)(0) << 10) - -/* macros for field resp_not_ok */ -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__SHIFT 11 -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__WIDTH 1 -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__MASK 0x00000800U -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__RESET 0b0 -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field reserved_31_12 */ -#define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__SHIFT 12 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__WIDTH 20 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__MASK 0xfffff000U -#define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__RESET 0 -#define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__READ(src) \ - (((uint32_t)(src)\ - & 0xfffff000U) >> 12) -#define EMAC_REGS__INT_Q_STATUS__TYPE uint32_t -#define EMAC_REGS__INT_Q_STATUS__READ 0xffffffffU -#define EMAC_REGS__INT_Q_STATUS__RCLR 0x00000ce6U - -#endif /* __EMAC_REGS__INT_Q_STATUS_MACRO__ */ - - -/* macros for int_q1_status */ -#define INST_INT_Q1_STATUS__NUM 1 - -/* macros for int_q2_status */ -#define INST_INT_Q2_STATUS__NUM 1 - -/* macros for int_q3_status */ -#define INST_INT_Q3_STATUS__NUM 1 - -/* macros for int_q4_status */ -#define INST_INT_Q4_STATUS__NUM 1 - -/* macros for int_q5_status */ -#define INST_INT_Q5_STATUS__NUM 1 - -/* macros for int_q6_status */ -#define INST_INT_Q6_STATUS__NUM 1 - -/* macros for int_q7_status */ -#define INST_INT_Q7_STATUS__NUM 1 - -/* macros for int_q8_status */ -#define INST_INT_Q8_STATUS__NUM 1 - -/* macros for int_q9_status */ -#define INST_INT_Q9_STATUS__NUM 1 - -/* macros for int_q10_status */ -#define INST_INT_Q10_STATUS__NUM 1 - -/* macros for int_q11_status */ -#define INST_INT_Q11_STATUS__NUM 1 - -/* macros for int_q12_status */ -#define INST_INT_Q12_STATUS__NUM 1 - -/* macros for int_q13_status */ -#define INST_INT_Q13_STATUS__NUM 1 - -/* macros for int_q14_status */ -#define INST_INT_Q14_STATUS__NUM 1 - -/* macros for int_q15_status */ -#define INST_INT_Q15_STATUS__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::transmit_qx_ptr */ -#ifndef __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__ -#define __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__ - -/* macros for field dma_tx_dis_q */ -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__SHIFT 0 -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__WIDTH 1 -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__MASK 0x00000001U -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__RESET 0b0 -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_1_1 */ -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__SHIFT 1 -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__WIDTH 1 -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__MASK 0x00000002U -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__RESET 0b0 -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field dma_tx_q_ptr */ -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__SHIFT 2 -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__WIDTH 30 -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__MASK 0xfffffffcU -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__RESET 0 -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffffcU) >> 2) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0xfffffffcU) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xfffffffcU) | (((uint32_t)(src) <<\ - 2) & 0xfffffffcU) -#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0xfffffffcU))) -#define EMAC_REGS__TRANSMIT_QX_PTR__TYPE uint32_t -#define EMAC_REGS__TRANSMIT_QX_PTR__READ 0xffffffffU -#define EMAC_REGS__TRANSMIT_QX_PTR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__ */ - - -/* macros for transmit_q1_ptr */ -#define INST_TRANSMIT_Q1_PTR__NUM 1 - -/* macros for transmit_q2_ptr */ -#define INST_TRANSMIT_Q2_PTR__NUM 1 - -/* macros for transmit_q3_ptr */ -#define INST_TRANSMIT_Q3_PTR__NUM 1 - -/* macros for transmit_q4_ptr */ -#define INST_TRANSMIT_Q4_PTR__NUM 1 - -/* macros for transmit_q5_ptr */ -#define INST_TRANSMIT_Q5_PTR__NUM 1 - -/* macros for transmit_q6_ptr */ -#define INST_TRANSMIT_Q6_PTR__NUM 1 - -/* macros for transmit_q7_ptr */ -#define INST_TRANSMIT_Q7_PTR__NUM 1 - -/* macros for transmit_q8_ptr */ -#define INST_TRANSMIT_Q8_PTR__NUM 1 - -/* macros for transmit_q9_ptr */ -#define INST_TRANSMIT_Q9_PTR__NUM 1 - -/* macros for transmit_q10_ptr */ -#define INST_TRANSMIT_Q10_PTR__NUM 1 - -/* macros for transmit_q11_ptr */ -#define INST_TRANSMIT_Q11_PTR__NUM 1 - -/* macros for transmit_q12_ptr */ -#define INST_TRANSMIT_Q12_PTR__NUM 1 - -/* macros for transmit_q13_ptr */ -#define INST_TRANSMIT_Q13_PTR__NUM 1 - -/* macros for transmit_q14_ptr */ -#define INST_TRANSMIT_Q14_PTR__NUM 1 - -/* macros for transmit_q15_ptr */ -#define INST_TRANSMIT_Q15_PTR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::receive_qx_ptr */ -#ifndef __EMAC_REGS__RECEIVE_QX_PTR_MACRO__ -#define __EMAC_REGS__RECEIVE_QX_PTR_MACRO__ - -/* macros for field dma_rx_dis_q */ -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__SHIFT 0 -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__WIDTH 1 -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__MASK 0x00000001U -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__RESET 0b0 -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field reserved_1_1 */ -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__SHIFT 1 -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__WIDTH 1 -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__MASK 0x00000002U -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__RESET 0b0 -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field dma_rx_q_ptr */ -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__SHIFT 2 -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__WIDTH 30 -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__MASK 0xfffffffcU -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__RESET 0 -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffffcU) >> 2) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0xfffffffcU) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xfffffffcU) | (((uint32_t)(src) <<\ - 2) & 0xfffffffcU) -#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0xfffffffcU))) -#define EMAC_REGS__RECEIVE_QX_PTR__TYPE uint32_t -#define EMAC_REGS__RECEIVE_QX_PTR__READ 0xffffffffU -#define EMAC_REGS__RECEIVE_QX_PTR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__RECEIVE_QX_PTR_MACRO__ */ - - -/* macros for receive_q1_ptr */ -#define INST_RECEIVE_Q1_PTR__NUM 1 - -/* macros for receive_q2_ptr */ -#define INST_RECEIVE_Q2_PTR__NUM 1 - -/* macros for receive_q3_ptr */ -#define INST_RECEIVE_Q3_PTR__NUM 1 - -/* macros for receive_q4_ptr */ -#define INST_RECEIVE_Q4_PTR__NUM 1 - -/* macros for receive_q5_ptr */ -#define INST_RECEIVE_Q5_PTR__NUM 1 - -/* macros for receive_q6_ptr */ -#define INST_RECEIVE_Q6_PTR__NUM 1 - -/* macros for receive_q7_ptr */ -#define INST_RECEIVE_Q7_PTR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::dma_rxbuf_size_q */ -#ifndef __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__ -#define __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__ - -/* macros for field dma_rx_q_buf_size */ -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__SHIFT 0 -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__WIDTH 8 -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MASK 0x000000ffU -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__RESET 2 -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field reserved_31_8 */ -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__SHIFT 8 -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__WIDTH 24 -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__MASK 0xffffff00U -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__RESET 0 -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__READ(src) \ - (((uint32_t)(src)\ - & 0xffffff00U) >> 8) -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__TYPE uint32_t -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__READ 0xffffffffU -#define EMAC_REGS__DMA_RXBUF_SIZE_Q__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__ */ - - -/* macros for dma_rxbuf_size_q1 */ -#define INST_DMA_RXBUF_SIZE_Q1__NUM 1 - -/* macros for dma_rxbuf_size_q2 */ -#define INST_DMA_RXBUF_SIZE_Q2__NUM 1 - -/* macros for dma_rxbuf_size_q3 */ -#define INST_DMA_RXBUF_SIZE_Q3__NUM 1 - -/* macros for dma_rxbuf_size_q4 */ -#define INST_DMA_RXBUF_SIZE_Q4__NUM 1 - -/* macros for dma_rxbuf_size_q5 */ -#define INST_DMA_RXBUF_SIZE_Q5__NUM 1 - -/* macros for dma_rxbuf_size_q6 */ -#define INST_DMA_RXBUF_SIZE_Q6__NUM 1 - -/* macros for dma_rxbuf_size_q7 */ -#define INST_DMA_RXBUF_SIZE_Q7__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::cbs_control */ -#ifndef __EMAC_REGS__CBS_CONTROL_MACRO__ -#define __EMAC_REGS__CBS_CONTROL_MACRO__ - -/* macros for field cbs_enable_queue_a */ -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__SHIFT 0 -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__WIDTH 1 -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MASK 0x00000001U -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__RESET 0 -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field cbs_enable_queue_b */ -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__SHIFT 1 -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__WIDTH 1 -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MASK 0x00000002U -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__RESET 0 -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field reserved_31_2 */ -#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__SHIFT 2 -#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__WIDTH 30 -#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__MASK 0xfffffffcU -#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__RESET 0 -#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffffcU) >> 2) -#define EMAC_REGS__CBS_CONTROL__TYPE uint32_t -#define EMAC_REGS__CBS_CONTROL__READ 0xffffffffU -#define EMAC_REGS__CBS_CONTROL__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__CBS_CONTROL_MACRO__ */ - - -/* macros for cbs_control */ -#define INST_CBS_CONTROL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::cbs_idleslope_q_a */ -#ifndef __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__ -#define __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__ - -/* macros for field idleslope_a */ -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__SHIFT 0 -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__WIDTH 32 -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__MASK 0xffffffffU -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__RESET 0 -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__TYPE uint32_t -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__READ 0xffffffffU -#define EMAC_REGS__CBS_IDLESLOPE_Q_A__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__ */ - - -/* macros for cbs_idleslope_q_a */ -#define INST_CBS_IDLESLOPE_Q_A__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::cbs_idleslope_q_b */ -#ifndef __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__ -#define __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__ - -/* macros for field idleslope_b */ -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__SHIFT 0 -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__WIDTH 32 -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__MASK 0xffffffffU -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__RESET 0 -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__TYPE uint32_t -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__READ 0xffffffffU -#define EMAC_REGS__CBS_IDLESLOPE_Q_B__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__ */ - - -/* macros for cbs_idleslope_q_b */ -#define INST_CBS_IDLESLOPE_Q_B__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::upper_tx_q_base_addr */ -#ifndef __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__ -#define __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__ - -/* macros for field upper_tx_q_base_addr */ -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__SHIFT 0 -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__WIDTH 32 -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MASK 0xffffffffU -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__RESET 0 -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__TYPE uint32_t -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__READ 0xffffffffU -#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__ */ - - -/* macros for upper_tx_q_base_addr */ -#define INST_UPPER_TX_Q_BASE_ADDR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_bd_control */ -#ifndef __EMAC_REGS__TX_BD_CONTROL_MACRO__ -#define __EMAC_REGS__TX_BD_CONTROL_MACRO__ - -/* macros for field reserved_3_0 */ -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__SHIFT 0 -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__WIDTH 4 -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__MASK 0x0000000fU -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__RESET 0 -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) - -/* macros for field tx_bd_ts_mode */ -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__SHIFT 4 -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__WIDTH 2 -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MASK 0x00000030U -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__RESET 0 -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000030U) >> 4) -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000030U) -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000030U) | (((uint32_t)(src) <<\ - 4) & 0x00000030U) -#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000030U))) - -/* macros for field reserved_31_6 */ -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__SHIFT 6 -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__WIDTH 26 -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__MASK 0xffffffc0U -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__RESET 0 -#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__READ(src) \ - (((uint32_t)(src)\ - & 0xffffffc0U) >> 6) -#define EMAC_REGS__TX_BD_CONTROL__TYPE uint32_t -#define EMAC_REGS__TX_BD_CONTROL__READ 0xffffffffU -#define EMAC_REGS__TX_BD_CONTROL__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_BD_CONTROL_MACRO__ */ - - -/* macros for tx_bd_control */ -#define INST_TX_BD_CONTROL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::rx_bd_control */ -#ifndef __EMAC_REGS__RX_BD_CONTROL_MACRO__ -#define __EMAC_REGS__RX_BD_CONTROL_MACRO__ - -/* macros for field reserved_3_0 */ -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__SHIFT 0 -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__WIDTH 4 -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__MASK 0x0000000fU -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__RESET 0 -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) - -/* macros for field rx_bd_ts_mode */ -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__SHIFT 4 -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__WIDTH 2 -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MASK 0x00000030U -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__RESET 0 -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000030U) >> 4) -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000030U) -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000030U) | (((uint32_t)(src) <<\ - 4) & 0x00000030U) -#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000030U))) - -/* macros for field reserved_31_6 */ -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__SHIFT 6 -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__WIDTH 26 -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__MASK 0xffffffc0U -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__RESET 0 -#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__READ(src) \ - (((uint32_t)(src)\ - & 0xffffffc0U) >> 6) -#define EMAC_REGS__RX_BD_CONTROL__TYPE uint32_t -#define EMAC_REGS__RX_BD_CONTROL__READ 0xffffffffU -#define EMAC_REGS__RX_BD_CONTROL__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__RX_BD_CONTROL_MACRO__ */ - - -/* macros for rx_bd_control */ -#define INST_RX_BD_CONTROL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::upper_rx_q_base_addr */ -#ifndef __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__ -#define __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__ - -/* macros for field upper_rx_q_base_addr */ -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__SHIFT 0 -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__WIDTH 32 -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MASK 0xffffffffU -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__RESET 0 -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__READ(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__WRITE(src) \ - ((uint32_t)(src)\ - & 0xffffffffU) -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffffffffU) | ((uint32_t)(src) &\ - 0xffffffffU) -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0xffffffffU))) -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__TYPE uint32_t -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__READ 0xffffffffU -#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__ */ - - -/* macros for upper_rx_q_base_addr */ -#define INST_UPPER_RX_Q_BASE_ADDR__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::screening_type_1_register */ -#ifndef __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__ -#define __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__ - -/* macros for field queue_number */ -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__SHIFT 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__WIDTH 4 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MASK 0x0000000fU -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000000fU) | ((uint32_t)(src) &\ - 0x0000000fU) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000000fU))) - -/* macros for field dstc_match */ -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__SHIFT 4 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__WIDTH 8 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MASK 0x00000ff0U -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__READ(src) \ - (((uint32_t)(src)\ - & 0x00000ff0U) >> 4) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000ff0U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000ff0U) | (((uint32_t)(src) <<\ - 4) & 0x00000ff0U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000ff0U))) - -/* macros for field udp_port_match */ -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__SHIFT 12 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__WIDTH 16 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MASK 0x0ffff000U -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__READ(src) \ - (((uint32_t)(src)\ - & 0x0ffff000U) >> 12) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x0ffff000U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0ffff000U) | (((uint32_t)(src) <<\ - 12) & 0x0ffff000U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x0ffff000U))) - -/* macros for field dstc_enable */ -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__SHIFT 28 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MASK 0x10000000U -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x10000000U) >> 28) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x10000000U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x10000000U) | (((uint32_t)(src) <<\ - 28) & 0x10000000U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x10000000U))) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(1) << 28) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x10000000U) | ((uint32_t)(0) << 28) - -/* macros for field udp_port_match_enable */ -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__SHIFT 29 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MASK \ - 0x20000000U -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x20000000U) >> 29) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 29) & 0x20000000U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x20000000U) | (((uint32_t)(src) <<\ - 29) & 0x20000000U) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 29) & ~0x20000000U))) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(1) << 29) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x20000000U) | ((uint32_t)(0) << 29) - -/* macros for field reserved_31_30 */ -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__SHIFT 30 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__WIDTH 2 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__MASK 0xc0000000U -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__TYPE uint32_t -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__READ 0xffffffffU -#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__ */ - - -/* macros for screening_type_1_register_0 */ -#define INST_SCREENING_TYPE_1_REGISTER_0__NUM 1 - -/* macros for screening_type_1_register_1 */ -#define INST_SCREENING_TYPE_1_REGISTER_1__NUM 1 - -/* macros for screening_type_1_register_2 */ -#define INST_SCREENING_TYPE_1_REGISTER_2__NUM 1 - -/* macros for screening_type_1_register_3 */ -#define INST_SCREENING_TYPE_1_REGISTER_3__NUM 1 - -/* macros for screening_type_1_register_4 */ -#define INST_SCREENING_TYPE_1_REGISTER_4__NUM 1 - -/* macros for screening_type_1_register_5 */ -#define INST_SCREENING_TYPE_1_REGISTER_5__NUM 1 - -/* macros for screening_type_1_register_6 */ -#define INST_SCREENING_TYPE_1_REGISTER_6__NUM 1 - -/* macros for screening_type_1_register_7 */ -#define INST_SCREENING_TYPE_1_REGISTER_7__NUM 1 - -/* macros for screening_type_1_register_8 */ -#define INST_SCREENING_TYPE_1_REGISTER_8__NUM 1 - -/* macros for screening_type_1_register_9 */ -#define INST_SCREENING_TYPE_1_REGISTER_9__NUM 1 - -/* macros for screening_type_1_register_10 */ -#define INST_SCREENING_TYPE_1_REGISTER_10__NUM 1 - -/* macros for screening_type_1_register_11 */ -#define INST_SCREENING_TYPE_1_REGISTER_11__NUM 1 - -/* macros for screening_type_1_register_12 */ -#define INST_SCREENING_TYPE_1_REGISTER_12__NUM 1 - -/* macros for screening_type_1_register_13 */ -#define INST_SCREENING_TYPE_1_REGISTER_13__NUM 1 - -/* macros for screening_type_1_register_14 */ -#define INST_SCREENING_TYPE_1_REGISTER_14__NUM 1 - -/* macros for screening_type_1_register_15 */ -#define INST_SCREENING_TYPE_1_REGISTER_15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::screening_type_2_register */ -#ifndef __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__ -#define __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__ - -/* macros for field queue_number */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__SHIFT 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__WIDTH 4 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MASK 0x0000000fU -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__READ(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000000fU) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000000fU) | ((uint32_t)(src) &\ - 0x0000000fU) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000000fU))) - -/* macros for field vlan_priority */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__SHIFT 4 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__WIDTH 3 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MASK 0x00000070U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__READ(src) \ - (((uint32_t)(src)\ - & 0x00000070U) >> 4) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000070U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000070U) | (((uint32_t)(src) <<\ - 4) & 0x00000070U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000070U))) - -/* macros for field reserved_7 */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__SHIFT 7 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__MASK 0x00000080U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field vlan_enable */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__SHIFT 8 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MASK 0x00000100U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00000100U) >> 8) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000100U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000100U) | (((uint32_t)(src) <<\ - 8) & 0x00000100U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000100U))) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(1) << 8) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000100U) | ((uint32_t)(0) << 8) - -/* macros for field index */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__SHIFT 9 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__WIDTH 3 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__MASK 0x00000e00U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__READ(src) \ - (((uint32_t)(src)\ - & 0x00000e00U) >> 9) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000e00U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000e00U) | (((uint32_t)(src) <<\ - 9) & 0x00000e00U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000e00U))) - -/* macros for field ethertype_enable */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__SHIFT 12 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MASK \ - 0x00001000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00001000U) >> 12) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00001000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00001000U) | (((uint32_t)(src) <<\ - 12) & 0x00001000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00001000U))) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(1) << 12) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00001000U) | ((uint32_t)(0) << 12) - -/* macros for field compare_a */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__SHIFT 13 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__WIDTH 5 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MASK 0x0003e000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__READ(src) \ - (((uint32_t)(src)\ - & 0x0003e000U) >> 13) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__WRITE(src) \ - (((uint32_t)(src)\ - << 13) & 0x0003e000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0003e000U) | (((uint32_t)(src) <<\ - 13) & 0x0003e000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 13) & ~0x0003e000U))) - -/* macros for field compare_a_enable */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__SHIFT 18 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MASK \ - 0x00040000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x00040000U) >> 18) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field compare_b */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__SHIFT 19 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__WIDTH 5 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MASK 0x00f80000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__READ(src) \ - (((uint32_t)(src)\ - & 0x00f80000U) >> 19) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00f80000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00f80000U) | (((uint32_t)(src) <<\ - 19) & 0x00f80000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00f80000U))) - -/* macros for field compare_b_enable */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__SHIFT 24 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MASK \ - 0x01000000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x01000000U) >> 24) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x01000000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x01000000U) | (((uint32_t)(src) <<\ - 24) & 0x01000000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x01000000U))) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(1) << 24) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x01000000U) | ((uint32_t)(0) << 24) - -/* macros for field compare_c */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__SHIFT 25 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__WIDTH 5 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MASK 0x3e000000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__READ(src) \ - (((uint32_t)(src)\ - & 0x3e000000U) >> 25) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__WRITE(src) \ - (((uint32_t)(src)\ - << 25) & 0x3e000000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3e000000U) | (((uint32_t)(src) <<\ - 25) & 0x3e000000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 25) & ~0x3e000000U))) - -/* macros for field compare_c_enable */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__SHIFT 30 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MASK \ - 0x40000000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__READ(src) \ - (((uint32_t)(src)\ - & 0x40000000U) >> 30) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0x40000000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x40000000U) | (((uint32_t)(src) <<\ - 30) & 0x40000000U) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0x40000000U))) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__SET(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(1) << 30) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__CLR(dst) \ - (dst) = ((dst) &\ - ~0x40000000U) | ((uint32_t)(0) << 30) - -/* macros for field reserved_31 */ -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__SHIFT 31 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__WIDTH 1 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__MASK 0x80000000U -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__TYPE uint32_t -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__READ 0xffffffffU -#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__ */ - - -/* macros for screening_type_2_register_0 */ -#define INST_SCREENING_TYPE_2_REGISTER_0__NUM 1 - -/* macros for screening_type_2_register_1 */ -#define INST_SCREENING_TYPE_2_REGISTER_1__NUM 1 - -/* macros for screening_type_2_register_2 */ -#define INST_SCREENING_TYPE_2_REGISTER_2__NUM 1 - -/* macros for screening_type_2_register_3 */ -#define INST_SCREENING_TYPE_2_REGISTER_3__NUM 1 - -/* macros for screening_type_2_register_4 */ -#define INST_SCREENING_TYPE_2_REGISTER_4__NUM 1 - -/* macros for screening_type_2_register_5 */ -#define INST_SCREENING_TYPE_2_REGISTER_5__NUM 1 - -/* macros for screening_type_2_register_6 */ -#define INST_SCREENING_TYPE_2_REGISTER_6__NUM 1 - -/* macros for screening_type_2_register_7 */ -#define INST_SCREENING_TYPE_2_REGISTER_7__NUM 1 - -/* macros for screening_type_2_register_8 */ -#define INST_SCREENING_TYPE_2_REGISTER_8__NUM 1 - -/* macros for screening_type_2_register_9 */ -#define INST_SCREENING_TYPE_2_REGISTER_9__NUM 1 - -/* macros for screening_type_2_register_10 */ -#define INST_SCREENING_TYPE_2_REGISTER_10__NUM 1 - -/* macros for screening_type_2_register_11 */ -#define INST_SCREENING_TYPE_2_REGISTER_11__NUM 1 - -/* macros for screening_type_2_register_12 */ -#define INST_SCREENING_TYPE_2_REGISTER_12__NUM 1 - -/* macros for screening_type_2_register_13 */ -#define INST_SCREENING_TYPE_2_REGISTER_13__NUM 1 - -/* macros for screening_type_2_register_14 */ -#define INST_SCREENING_TYPE_2_REGISTER_14__NUM 1 - -/* macros for screening_type_2_register_15 */ -#define INST_SCREENING_TYPE_2_REGISTER_15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_sched_ctrl */ -#ifndef __EMAC_REGS__TX_SCHED_CTRL_MACRO__ -#define __EMAC_REGS__TX_SCHED_CTRL_MACRO__ - -/* macros for field tx_sched_q1 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__SHIFT 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__MASK 0x00000003U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__READ(src) \ - ((uint32_t)(src)\ - & 0x00000003U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000003U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000003U) | ((uint32_t)(src) &\ - 0x00000003U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000003U))) - -/* macros for field tx_sched_q2 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__SHIFT 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__MASK 0x0000000cU -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__READ(src) \ - (((uint32_t)(src)\ - & 0x0000000cU) >> 2) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x0000000cU) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000000cU) | (((uint32_t)(src) <<\ - 2) & 0x0000000cU) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x0000000cU))) - -/* macros for field tx_sched_q3 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__SHIFT 4 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__MASK 0x00000030U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000030U) >> 4) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000030U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000030U) | (((uint32_t)(src) <<\ - 4) & 0x00000030U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000030U))) - -/* macros for field tx_sched_q4 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__SHIFT 6 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__MASK 0x000000c0U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__READ(src) \ - (((uint32_t)(src)\ - & 0x000000c0U) >> 6) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x000000c0U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000c0U) | (((uint32_t)(src) <<\ - 6) & 0x000000c0U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x000000c0U))) - -/* macros for field tx_sched_q5 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__SHIFT 8 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__MASK 0x00000300U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__READ(src) \ - (((uint32_t)(src)\ - & 0x00000300U) >> 8) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000300U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000300U) | (((uint32_t)(src) <<\ - 8) & 0x00000300U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000300U))) - -/* macros for field tx_sched_q6 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__SHIFT 10 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__MASK 0x00000c00U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__READ(src) \ - (((uint32_t)(src)\ - & 0x00000c00U) >> 10) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__WRITE(src) \ - (((uint32_t)(src)\ - << 10) & 0x00000c00U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000c00U) | (((uint32_t)(src) <<\ - 10) & 0x00000c00U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 10) & ~0x00000c00U))) - -/* macros for field tx_sched_q7 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__SHIFT 12 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__MASK 0x00003000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__READ(src) \ - (((uint32_t)(src)\ - & 0x00003000U) >> 12) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00003000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00003000U) | (((uint32_t)(src) <<\ - 12) & 0x00003000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00003000U))) - -/* macros for field tx_sched_q8 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__SHIFT 14 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__MASK 0x0000c000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__READ(src) \ - (((uint32_t)(src)\ - & 0x0000c000U) >> 14) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__WRITE(src) \ - (((uint32_t)(src)\ - << 14) & 0x0000c000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000c000U) | (((uint32_t)(src) <<\ - 14) & 0x0000c000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 14) & ~0x0000c000U))) - -/* macros for field tx_sched_q9 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__SHIFT 16 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__MASK 0x00030000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__READ(src) \ - (((uint32_t)(src)\ - & 0x00030000U) >> 16) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00030000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00030000U) | (((uint32_t)(src) <<\ - 16) & 0x00030000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00030000U))) - -/* macros for field tx_sched_q10 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__SHIFT 18 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__MASK 0x000c0000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__READ(src) \ - (((uint32_t)(src)\ - & 0x000c0000U) >> 18) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x000c0000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000c0000U) | (((uint32_t)(src) <<\ - 18) & 0x000c0000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x000c0000U))) - -/* macros for field tx_sched_q11 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__SHIFT 20 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__MASK 0x00300000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__READ(src) \ - (((uint32_t)(src)\ - & 0x00300000U) >> 20) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00300000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00300000U) | (((uint32_t)(src) <<\ - 20) & 0x00300000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00300000U))) - -/* macros for field tx_sched_q12 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__SHIFT 22 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__MASK 0x00c00000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__READ(src) \ - (((uint32_t)(src)\ - & 0x00c00000U) >> 22) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__WRITE(src) \ - (((uint32_t)(src)\ - << 22) & 0x00c00000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00c00000U) | (((uint32_t)(src) <<\ - 22) & 0x00c00000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 22) & ~0x00c00000U))) - -/* macros for field tx_sched_q13 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__SHIFT 24 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__MASK 0x03000000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__READ(src) \ - (((uint32_t)(src)\ - & 0x03000000U) >> 24) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x03000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x03000000U) | (((uint32_t)(src) <<\ - 24) & 0x03000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x03000000U))) - -/* macros for field tx_sched_q14 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__SHIFT 26 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__MASK 0x0c000000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__READ(src) \ - (((uint32_t)(src)\ - & 0x0c000000U) >> 26) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__WRITE(src) \ - (((uint32_t)(src)\ - << 26) & 0x0c000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0c000000U) | (((uint32_t)(src) <<\ - 26) & 0x0c000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 26) & ~0x0c000000U))) - -/* macros for field tx_sched_q15 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__SHIFT 28 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__MASK 0x30000000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__READ(src) \ - (((uint32_t)(src)\ - & 0x30000000U) >> 28) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x30000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x30000000U) | (((uint32_t)(src) <<\ - 28) & 0x30000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x30000000U))) - -/* macros for field tx_sched_q16 */ -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__SHIFT 30 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__WIDTH 2 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__MASK 0xc0000000U -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__RESET 0 -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__TX_SCHED_CTRL__TYPE uint32_t -#define EMAC_REGS__TX_SCHED_CTRL__READ 0xffffffffU -#define EMAC_REGS__TX_SCHED_CTRL__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_SCHED_CTRL_MACRO__ */ - - -/* macros for tx_sched_ctrl */ -#define INST_TX_SCHED_CTRL__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q0to3 */ -#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__ -#define __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__ - -/* macros for field dwrr_ets_weight_q0 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__SHIFT 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__MASK 0x000000ffU -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field dwrr_ets_weight_q1 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__SHIFT 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__MASK 0x0000ff00U -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field dwrr_ets_weight_q2 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__SHIFT 16 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__MASK 0x00ff0000U -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field dwrr_ets_weight_q3 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__SHIFT 24 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__MASK 0xff000000U -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xff000000U) | (((uint32_t)(src) <<\ - 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0xff000000U))) -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__TYPE uint32_t -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__READ 0xffffffffU -#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__ */ - - -/* macros for bw_rate_limit_q0to3 */ -#define INST_BW_RATE_LIMIT_Q0TO3__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q4to7 */ -#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__ -#define __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__ - -/* macros for field dwrr_ets_weight_q4 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__SHIFT 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__MASK 0x000000ffU -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field dwrr_ets_weight_q5 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__SHIFT 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__MASK 0x0000ff00U -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field dwrr_ets_weight_q6 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__SHIFT 16 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__MASK 0x00ff0000U -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field dwrr_ets_weight_q7 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__SHIFT 24 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__MASK 0xff000000U -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xff000000U) | (((uint32_t)(src) <<\ - 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0xff000000U))) -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__TYPE uint32_t -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__READ 0xffffffffU -#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__ */ - - -/* macros for bw_rate_limit_q4to7 */ -#define INST_BW_RATE_LIMIT_Q4TO7__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q8to11 */ -#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__ -#define __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__ - -/* macros for field dwrr_ets_weight_q8 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__SHIFT 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__MASK 0x000000ffU -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field dwrr_ets_weight_q9 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__SHIFT 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__MASK 0x0000ff00U -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field dwrr_ets_weight_q10 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__SHIFT 16 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__MASK 0x00ff0000U -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field dwrr_ets_weight_q11 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__SHIFT 24 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__MASK 0xff000000U -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xff000000U) | (((uint32_t)(src) <<\ - 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0xff000000U))) -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__TYPE uint32_t -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__READ 0xffffffffU -#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__ */ - - -/* macros for bw_rate_limit_q8to11 */ -#define INST_BW_RATE_LIMIT_Q8TO11__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q12to15 */ -#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__ -#define __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__ - -/* macros for field dwrr_ets_weight_q12 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__SHIFT 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__MASK 0x000000ffU -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__READ(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__WRITE(src) \ - ((uint32_t)(src)\ - & 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x000000ffU) | ((uint32_t)(src) &\ - 0x000000ffU) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x000000ffU))) - -/* macros for field dwrr_ets_weight_q13 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__SHIFT 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__MASK 0x0000ff00U -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ff00U) | (((uint32_t)(src) <<\ - 8) & 0x0000ff00U) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x0000ff00U))) - -/* macros for field dwrr_ets_weight_q14 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__SHIFT 16 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__MASK 0x00ff0000U -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__READ(src) \ - (((uint32_t)(src)\ - & 0x00ff0000U) >> 16) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00ff0000U) | (((uint32_t)(src) <<\ - 16) & 0x00ff0000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00ff0000U))) - -/* macros for field dwrr_ets_weight_q15 */ -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__SHIFT 24 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__WIDTH 8 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__MASK 0xff000000U -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__RESET 0 -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xff000000U) | (((uint32_t)(src) <<\ - 24) & 0xff000000U) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0xff000000U))) -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__TYPE uint32_t -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__READ 0xffffffffU -#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__ */ - - -/* macros for bw_rate_limit_q12to15 */ -#define INST_BW_RATE_LIMIT_Q12TO15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_q_seg_alloc_q0to7 */ -#ifndef __EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7_MACRO__ -#define __EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7_MACRO__ - -/* macros for field segment_alloc_q0 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__SHIFT 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__MASK 0x00000007U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000007U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000007U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000007U) | ((uint32_t)(src) &\ - 0x00000007U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000007U))) - -/* macros for field reserved_3_3 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__SHIFT 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__MASK 0x00000008U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field segment_alloc_q1 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__SHIFT 4 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__MASK 0x00000070U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__READ(src) \ - (((uint32_t)(src)\ - & 0x00000070U) >> 4) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000070U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000070U) | (((uint32_t)(src) <<\ - 4) & 0x00000070U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000070U))) - -/* macros for field reserved_7_7 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__SHIFT 7 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__MASK 0x00000080U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field segment_alloc_q2 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__SHIFT 8 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__MASK 0x00000700U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__READ(src) \ - (((uint32_t)(src)\ - & 0x00000700U) >> 8) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000700U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000700U) | (((uint32_t)(src) <<\ - 8) & 0x00000700U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000700U))) - -/* macros for field reserved_11_11 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__SHIFT 11 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__MASK 0x00000800U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field segment_alloc_q3 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__SHIFT 12 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__MASK 0x00007000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__READ(src) \ - (((uint32_t)(src)\ - & 0x00007000U) >> 12) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00007000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00007000U) | (((uint32_t)(src) <<\ - 12) & 0x00007000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00007000U))) - -/* macros for field reserved_15_15 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__SHIFT 15 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__MASK 0x00008000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field segment_alloc_q4 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__SHIFT 16 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__MASK 0x00070000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__READ(src) \ - (((uint32_t)(src)\ - & 0x00070000U) >> 16) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00070000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00070000U) | (((uint32_t)(src) <<\ - 16) & 0x00070000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00070000U))) - -/* macros for field reserved_19_19 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__SHIFT 19 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__MASK 0x00080000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field segment_alloc_q5 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__SHIFT 20 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__MASK 0x00700000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__READ(src) \ - (((uint32_t)(src)\ - & 0x00700000U) >> 20) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00700000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00700000U) | (((uint32_t)(src) <<\ - 20) & 0x00700000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00700000U))) - -/* macros for field reserved_23_23 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__SHIFT 23 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__MASK 0x00800000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field segment_alloc_q6 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__SHIFT 24 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__MASK 0x07000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__READ(src) \ - (((uint32_t)(src)\ - & 0x07000000U) >> 24) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x07000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x07000000U) | (((uint32_t)(src) <<\ - 24) & 0x07000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x07000000U))) - -/* macros for field reserved_27_27 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__SHIFT 27 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__MASK 0x08000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field segment_alloc_q7 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__SHIFT 28 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__MASK 0x70000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__READ(src) \ - (((uint32_t)(src)\ - & 0x70000000U) >> 28) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x70000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x70000000U) | (((uint32_t)(src) <<\ - 28) & 0x70000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x70000000U))) - -/* macros for field reserved_31_31 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__SHIFT 31 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__MASK 0x80000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__TYPE uint32_t -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__READ 0xffffffffU -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7_MACRO__ */ - - -/* macros for tx_q_seg_alloc_q0to7 */ -#define INST_TX_Q_SEG_ALLOC_Q0TO7__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::tx_q_seg_alloc_q8to15 */ -#ifndef __EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15_MACRO__ -#define __EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15_MACRO__ - -/* macros for field segment_alloc_q8 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__SHIFT 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__MASK 0x00000007U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__READ(src) \ - ((uint32_t)(src)\ - & 0x00000007U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000007U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000007U) | ((uint32_t)(src) &\ - 0x00000007U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000007U))) - -/* macros for field reserved_3_3 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__SHIFT 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__MASK 0x00000008U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field segment_alloc_q9 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__SHIFT 4 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__MASK 0x00000070U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__READ(src) \ - (((uint32_t)(src)\ - & 0x00000070U) >> 4) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000070U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000070U) | (((uint32_t)(src) <<\ - 4) & 0x00000070U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000070U))) - -/* macros for field reserved_7_7 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__SHIFT 7 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__MASK 0x00000080U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field segment_alloc_q10 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__SHIFT 8 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__MASK 0x00000700U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__READ(src) \ - (((uint32_t)(src)\ - & 0x00000700U) >> 8) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__WRITE(src) \ - (((uint32_t)(src)\ - << 8) & 0x00000700U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000700U) | (((uint32_t)(src) <<\ - 8) & 0x00000700U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 8) & ~0x00000700U))) - -/* macros for field reserved_11_11 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__SHIFT 11 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__MASK 0x00000800U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field segment_alloc_q11 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__SHIFT 12 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__MASK 0x00007000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__READ(src) \ - (((uint32_t)(src)\ - & 0x00007000U) >> 12) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__WRITE(src) \ - (((uint32_t)(src)\ - << 12) & 0x00007000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00007000U) | (((uint32_t)(src) <<\ - 12) & 0x00007000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 12) & ~0x00007000U))) - -/* macros for field reserved_15_15 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__SHIFT 15 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__MASK 0x00008000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__READ(src) \ - (((uint32_t)(src)\ - & 0x00008000U) >> 15) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__SET(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(1) << 15) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00008000U) | ((uint32_t)(0) << 15) - -/* macros for field segment_alloc_q12 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__SHIFT 16 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__MASK 0x00070000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__READ(src) \ - (((uint32_t)(src)\ - & 0x00070000U) >> 16) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00070000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00070000U) | (((uint32_t)(src) <<\ - 16) & 0x00070000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00070000U))) - -/* macros for field reserved_19_19 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__SHIFT 19 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__MASK 0x00080000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__READ(src) \ - (((uint32_t)(src)\ - & 0x00080000U) >> 19) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field segment_alloc_q13 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__SHIFT 20 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__MASK 0x00700000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__READ(src) \ - (((uint32_t)(src)\ - & 0x00700000U) >> 20) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00700000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00700000U) | (((uint32_t)(src) <<\ - 20) & 0x00700000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00700000U))) - -/* macros for field reserved_23_23 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__SHIFT 23 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__MASK 0x00800000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__READ(src) \ - (((uint32_t)(src)\ - & 0x00800000U) >> 23) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field segment_alloc_q14 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__SHIFT 24 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__MASK 0x07000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__READ(src) \ - (((uint32_t)(src)\ - & 0x07000000U) >> 24) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__WRITE(src) \ - (((uint32_t)(src)\ - << 24) & 0x07000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x07000000U) | (((uint32_t)(src) <<\ - 24) & 0x07000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 24) & ~0x07000000U))) - -/* macros for field reserved_27_27 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__SHIFT 27 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__MASK 0x08000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__READ(src) \ - (((uint32_t)(src)\ - & 0x08000000U) >> 27) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__SET(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(1) << 27) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__CLR(dst) \ - (dst) = ((dst) &\ - ~0x08000000U) | ((uint32_t)(0) << 27) - -/* macros for field segment_alloc_q15 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__SHIFT 28 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__WIDTH 3 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__MASK 0x70000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__READ(src) \ - (((uint32_t)(src)\ - & 0x70000000U) >> 28) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__WRITE(src) \ - (((uint32_t)(src)\ - << 28) & 0x70000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x70000000U) | (((uint32_t)(src) <<\ - 28) & 0x70000000U) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 28) & ~0x70000000U))) - -/* macros for field reserved_31_31 */ -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__SHIFT 31 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__WIDTH 1 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__MASK 0x80000000U -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__RESET 0 -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__READ(src) \ - (((uint32_t)(src)\ - & 0x80000000U) >> 31) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__SET(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(1) << 31) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__CLR(dst) \ - (dst) = ((dst) &\ - ~0x80000000U) | ((uint32_t)(0) << 31) -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__TYPE uint32_t -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__READ 0xffffffffU -#define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15_MACRO__ */ - - -/* macros for tx_q_seg_alloc_q8to15 */ -#define INST_TX_Q_SEG_ALLOC_Q8TO15__NUM 1 - -/* macros for receive_q8_ptr */ -#define INST_RECEIVE_Q8_PTR__NUM 1 - -/* macros for receive_q9_ptr */ -#define INST_RECEIVE_Q9_PTR__NUM 1 - -/* macros for receive_q10_ptr */ -#define INST_RECEIVE_Q10_PTR__NUM 1 - -/* macros for receive_q11_ptr */ -#define INST_RECEIVE_Q11_PTR__NUM 1 - -/* macros for receive_q12_ptr */ -#define INST_RECEIVE_Q12_PTR__NUM 1 - -/* macros for receive_q13_ptr */ -#define INST_RECEIVE_Q13_PTR__NUM 1 - -/* macros for receive_q14_ptr */ -#define INST_RECEIVE_Q14_PTR__NUM 1 - -/* macros for receive_q15_ptr */ -#define INST_RECEIVE_Q15_PTR__NUM 1 - -/* macros for dma_rxbuf_size_q8 */ -#define INST_DMA_RXBUF_SIZE_Q8__NUM 1 - -/* macros for dma_rxbuf_size_q9 */ -#define INST_DMA_RXBUF_SIZE_Q9__NUM 1 - -/* macros for dma_rxbuf_size_q10 */ -#define INST_DMA_RXBUF_SIZE_Q10__NUM 1 - -/* macros for dma_rxbuf_size_q11 */ -#define INST_DMA_RXBUF_SIZE_Q11__NUM 1 - -/* macros for dma_rxbuf_size_q12 */ -#define INST_DMA_RXBUF_SIZE_Q12__NUM 1 - -/* macros for dma_rxbuf_size_q13 */ -#define INST_DMA_RXBUF_SIZE_Q13__NUM 1 - -/* macros for dma_rxbuf_size_q14 */ -#define INST_DMA_RXBUF_SIZE_Q14__NUM 1 - -/* macros for dma_rxbuf_size_q15 */ -#define INST_DMA_RXBUF_SIZE_Q15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_q_enable */ -#ifndef __EMAC_REGS__INT_Q_ENABLE_MACRO__ -#define __EMAC_REGS__INT_Q_ENABLE_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__SHIFT 0 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__WIDTH 1 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field enable_receive_complete_interrupt */ -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \ - 0x00000002U -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field enable_rx_used_bit_read_interrupt */ -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SHIFT 2 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__MASK \ - 0x00000004U -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field reserved_4_3 */ -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__SHIFT 3 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__WIDTH 2 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__MASK 0x00000018U -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000018U) >> 3) - -/* macros for field enable_retry_limit_exceeded_or_late_collision_interrupt */ -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \ - 5 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \ - 0x00000020U -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field enable_transmit_frame_corruption_due_to_amba_error_interrupt */ -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \ - 6 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \ - 0x00000040U -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field enable_transmit_complete_interrupt */ -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT 7 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \ - 0x00000080U -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_10_8 */ -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__SHIFT 8 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__WIDTH 3 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__MASK 0x00000700U -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000700U) >> 8) - -/* macros for field enable_resp_not_ok_interrupt */ -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SHIFT 11 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MASK 0x00000800U -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field reserved_31_12 */ -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__SHIFT 12 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__WIDTH 20 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__MASK 0xfffff000U -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__RESET 0 -#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__READ(src) \ - (((uint32_t)(src)\ - & 0xfffff000U) >> 12) -#define EMAC_REGS__INT_Q_ENABLE__TYPE uint32_t -#define EMAC_REGS__INT_Q_ENABLE__READ 0xfffff719U -#define EMAC_REGS__INT_Q_ENABLE__WRITE 0xfffff719U - -#endif /* __EMAC_REGS__INT_Q_ENABLE_MACRO__ */ - - -/* macros for int_q1_enable */ -#define INST_INT_Q1_ENABLE__NUM 1 - -/* macros for int_q2_enable */ -#define INST_INT_Q2_ENABLE__NUM 1 - -/* macros for int_q3_enable */ -#define INST_INT_Q3_ENABLE__NUM 1 - -/* macros for int_q4_enable */ -#define INST_INT_Q4_ENABLE__NUM 1 - -/* macros for int_q5_enable */ -#define INST_INT_Q5_ENABLE__NUM 1 - -/* macros for int_q6_enable */ -#define INST_INT_Q6_ENABLE__NUM 1 - -/* macros for int_q7_enable */ -#define INST_INT_Q7_ENABLE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_q_disable */ -#ifndef __EMAC_REGS__INT_Q_DISABLE_MACRO__ -#define __EMAC_REGS__INT_Q_DISABLE_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__SHIFT 0 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__WIDTH 1 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field disable_receive_complete_interrupt */ -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \ - 0x00000002U -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field disable_rx_used_bit_read_interrupt */ -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SHIFT 2 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__MASK \ - 0x00000004U -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field reserved_4_3 */ -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__SHIFT 3 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__WIDTH 2 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__MASK 0x00000018U -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000018U) >> 3) - -/* macros for field disable_retry_limit_exceeded_or_late_collision_interrupt */ -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \ - 5 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \ - 0x00000020U -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field disable_transmit_frame_corruption_due_to_amba_error_interrupt */ -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \ - 6 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \ - 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \ - 0x00000040U -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \ - 0 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field disable_transmit_complete_interrupt */ -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT 7 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \ - 0x00000080U -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_10_8 */ -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__SHIFT 8 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__WIDTH 3 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__MASK 0x00000700U -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000700U) >> 8) - -/* macros for field disable_resp_not_ok_interrupt */ -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SHIFT 11 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WIDTH 1 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MASK \ - 0x00000800U -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \ - (((uint32_t)(src)\ - << 11) & 0x00000800U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000800U) | (((uint32_t)(src) <<\ - 11) & 0x00000800U) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 11) & ~0x00000800U))) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field reserved_31_12 */ -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__SHIFT 12 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__WIDTH 20 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__MASK 0xfffff000U -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__RESET 0 -#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__READ(src) \ - (((uint32_t)(src)\ - & 0xfffff000U) >> 12) -#define EMAC_REGS__INT_Q_DISABLE__TYPE uint32_t -#define EMAC_REGS__INT_Q_DISABLE__READ 0xfffff719U -#define EMAC_REGS__INT_Q_DISABLE__WRITE 0xfffff719U - -#endif /* __EMAC_REGS__INT_Q_DISABLE_MACRO__ */ - - -/* macros for int_q1_disable */ -#define INST_INT_Q1_DISABLE__NUM 1 - -/* macros for int_q2_disable */ -#define INST_INT_Q2_DISABLE__NUM 1 - -/* macros for int_q3_disable */ -#define INST_INT_Q3_DISABLE__NUM 1 - -/* macros for int_q4_disable */ -#define INST_INT_Q4_DISABLE__NUM 1 - -/* macros for int_q5_disable */ -#define INST_INT_Q5_DISABLE__NUM 1 - -/* macros for int_q6_disable */ -#define INST_INT_Q6_DISABLE__NUM 1 - -/* macros for int_q7_disable */ -#define INST_INT_Q7_DISABLE__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::int_q_mask */ -#ifndef __EMAC_REGS__INT_Q_MASK_MACRO__ -#define __EMAC_REGS__INT_Q_MASK_MACRO__ - -/* macros for field reserved_0 */ -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__SHIFT 0 -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__WIDTH 1 -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__MASK 0x00000001U -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__RESET 0 -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__INT_Q_MASK__RESERVED_0__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field receive_complete_interrupt_mask */ -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SHIFT 1 -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__MASK \ - 0x00000002U -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field rx_used_interrupt_mask */ -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__SHIFT 2 -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__MASK 0x00000004U -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field reserved_4_3 */ -#define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__SHIFT 3 -#define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__WIDTH 2 -#define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__MASK 0x00000018U -#define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__RESET 0 -#define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__READ(src) \ - (((uint32_t)(src)\ - & 0x00000018U) >> 3) - -/* macros for field retry_limit_exceeded_or_late_collision_interrupt_mask */ -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__SHIFT \ - 5 -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__WIDTH \ - 1 -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__MASK \ - 0x00000020U -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__RESET \ - 1 -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field amba_error_interrupt_mask */ -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__SHIFT 6 -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__MASK 0x00000040U -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field transmit_complete_interrupt_mask */ -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SHIFT 7 -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__MASK \ - 0x00000080U -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_10_8 */ -#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__SHIFT 8 -#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__WIDTH 3 -#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__MASK 0x00000700U -#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__RESET 0 -#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__READ(src) \ - (((uint32_t)(src)\ - & 0x00000700U) >> 8) - -/* macros for field resp_not_ok_interrupt_mask */ -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__SHIFT 11 -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__WIDTH 1 -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__MASK 0x00000800U -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__RESET 1 -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000800U) >> 11) -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(1) << 11) -#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000800U) | ((uint32_t)(0) << 11) - -/* macros for field reserved_31_12 */ -#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__SHIFT 12 -#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__WIDTH 20 -#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__MASK 0xfffff000U -#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__RESET 0 -#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__READ(src) \ - (((uint32_t)(src)\ - & 0xfffff000U) >> 12) -#define EMAC_REGS__INT_Q_MASK__TYPE uint32_t -#define EMAC_REGS__INT_Q_MASK__READ 0xffffffffU - -#endif /* __EMAC_REGS__INT_Q_MASK_MACRO__ */ - - -/* macros for int_q1_mask */ -#define INST_INT_Q1_MASK__NUM 1 - -/* macros for int_q2_mask */ -#define INST_INT_Q2_MASK__NUM 1 - -/* macros for int_q3_mask */ -#define INST_INT_Q3_MASK__NUM 1 - -/* macros for int_q4_mask */ -#define INST_INT_Q4_MASK__NUM 1 - -/* macros for int_q5_mask */ -#define INST_INT_Q5_MASK__NUM 1 - -/* macros for int_q6_mask */ -#define INST_INT_Q6_MASK__NUM 1 - -/* macros for int_q7_mask */ -#define INST_INT_Q7_MASK__NUM 1 - -/* macros for int_q8_enable */ -#define INST_INT_Q8_ENABLE__NUM 1 - -/* macros for int_q9_enable */ -#define INST_INT_Q9_ENABLE__NUM 1 - -/* macros for int_q10_enable */ -#define INST_INT_Q10_ENABLE__NUM 1 - -/* macros for int_q11_enable */ -#define INST_INT_Q11_ENABLE__NUM 1 - -/* macros for int_q12_enable */ -#define INST_INT_Q12_ENABLE__NUM 1 - -/* macros for int_q13_enable */ -#define INST_INT_Q13_ENABLE__NUM 1 - -/* macros for int_q14_enable */ -#define INST_INT_Q14_ENABLE__NUM 1 - -/* macros for int_q15_enable */ -#define INST_INT_Q15_ENABLE__NUM 1 - -/* macros for int_q8_disable */ -#define INST_INT_Q8_DISABLE__NUM 1 - -/* macros for int_q9_disable */ -#define INST_INT_Q9_DISABLE__NUM 1 - -/* macros for int_q10_disable */ -#define INST_INT_Q10_DISABLE__NUM 1 - -/* macros for int_q11_disable */ -#define INST_INT_Q11_DISABLE__NUM 1 - -/* macros for int_q12_disable */ -#define INST_INT_Q12_DISABLE__NUM 1 - -/* macros for int_q13_disable */ -#define INST_INT_Q13_DISABLE__NUM 1 - -/* macros for int_q14_disable */ -#define INST_INT_Q14_DISABLE__NUM 1 - -/* macros for int_q15_disable */ -#define INST_INT_Q15_DISABLE__NUM 1 - -/* macros for int_q8_mask */ -#define INST_INT_Q8_MASK__NUM 1 - -/* macros for int_q9_mask */ -#define INST_INT_Q9_MASK__NUM 1 - -/* macros for int_q10_mask */ -#define INST_INT_Q10_MASK__NUM 1 - -/* macros for int_q11_mask */ -#define INST_INT_Q11_MASK__NUM 1 - -/* macros for int_q12_mask */ -#define INST_INT_Q12_MASK__NUM 1 - -/* macros for int_q13_mask */ -#define INST_INT_Q13_MASK__NUM 1 - -/* macros for int_q14_mask */ -#define INST_INT_Q14_MASK__NUM 1 - -/* macros for int_q15_mask */ -#define INST_INT_Q15_MASK__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::screening_type_2_ethertype_reg */ -#ifndef __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__ -#define __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__ - -/* macros for field compare_value */ -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__SHIFT 0 -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__WIDTH 16 -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MASK \ - 0x0000ffffU -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field reserved_31_16 */ -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__SHIFT 16 -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__WIDTH 16 -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__MASK \ - 0xffff0000U -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__RESET 0 -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__TYPE uint32_t -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__READ 0xffffffffU -#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__ */ - - -/* macros for screening_type_2_ethertype_reg_0 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_0__NUM 1 - -/* macros for screening_type_2_ethertype_reg_1 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_1__NUM 1 - -/* macros for screening_type_2_ethertype_reg_2 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_2__NUM 1 - -/* macros for screening_type_2_ethertype_reg_3 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_3__NUM 1 - -/* macros for screening_type_2_ethertype_reg_4 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_4__NUM 1 - -/* macros for screening_type_2_ethertype_reg_5 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_5__NUM 1 - -/* macros for screening_type_2_ethertype_reg_6 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_6__NUM 1 - -/* macros for screening_type_2_ethertype_reg_7 */ -#define INST_SCREENING_TYPE_2_ETHERTYPE_REG_7__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::type2_compare_word_0 */ -#ifndef __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__ -#define __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__ - -/* macros for field mask_value */ -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__SHIFT 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__WIDTH 16 -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MASK 0x0000ffffU -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__RESET 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__READ(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000ffffU) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000ffffU) | ((uint32_t)(src) &\ - 0x0000ffffU) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000ffffU))) - -/* macros for field compare_value */ -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__SHIFT 16 -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__WIDTH 16 -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MASK 0xffff0000U -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__RESET 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__READ(src) \ - (((uint32_t)(src)\ - & 0xffff0000U) >> 16) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0xffff0000U) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xffff0000U) | (((uint32_t)(src) <<\ - 16) & 0xffff0000U) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0xffff0000U))) -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__TYPE uint32_t -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__READ 0xffffffffU -#define EMAC_REGS__TYPE2_COMPARE_WORD_0__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__ */ - - -/* macros for type2_compare_0_word_0 */ -#define INST_TYPE2_COMPARE_0_WORD_0__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::type2_compare_word_1 */ -#ifndef __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__ -#define __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__ - -/* macros for field offset_value */ -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__SHIFT 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__WIDTH 7 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MASK 0x0000007fU -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__RESET 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__READ(src) \ - ((uint32_t)(src)\ - & 0x0000007fU) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0000007fU) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0000007fU) | ((uint32_t)(src) &\ - 0x0000007fU) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0000007fU))) - -/* macros for field compare_offset */ -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__SHIFT 7 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__WIDTH 2 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MASK 0x00000180U -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__RESET 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__READ(src) \ - (((uint32_t)(src)\ - & 0x00000180U) >> 7) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000180U) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000180U) | (((uint32_t)(src) <<\ - 7) & 0x00000180U) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000180U))) - -/* macros for field disable_mask */ -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__SHIFT 9 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__WIDTH 1 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MASK 0x00000200U -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__RESET 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__READ(src) \ - (((uint32_t)(src)\ - & 0x00000200U) >> 9) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__WRITE(src) \ - (((uint32_t)(src)\ - << 9) & 0x00000200U) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000200U) | (((uint32_t)(src) <<\ - 9) & 0x00000200U) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 9) & ~0x00000200U))) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(1) << 9) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000200U) | ((uint32_t)(0) << 9) - -/* macros for field reserved_31_10 */ -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__SHIFT 10 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__WIDTH 22 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__MASK 0xfffffc00U -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__RESET 0 -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__READ(src) \ - (((uint32_t)(src)\ - & 0xfffffc00U) >> 10) -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__TYPE uint32_t -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__READ 0xffffffffU -#define EMAC_REGS__TYPE2_COMPARE_WORD_1__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__ */ - - -/* macros for type2_compare_0_word_1 */ -#define INST_TYPE2_COMPARE_0_WORD_1__NUM 1 - -/* macros for type2_compare_1_word_0 */ -#define INST_TYPE2_COMPARE_1_WORD_0__NUM 1 - -/* macros for type2_compare_1_word_1 */ -#define INST_TYPE2_COMPARE_1_WORD_1__NUM 1 - -/* macros for type2_compare_2_word_0 */ -#define INST_TYPE2_COMPARE_2_WORD_0__NUM 1 - -/* macros for type2_compare_2_word_1 */ -#define INST_TYPE2_COMPARE_2_WORD_1__NUM 1 - -/* macros for type2_compare_3_word_0 */ -#define INST_TYPE2_COMPARE_3_WORD_0__NUM 1 - -/* macros for type2_compare_3_word_1 */ -#define INST_TYPE2_COMPARE_3_WORD_1__NUM 1 - -/* macros for type2_compare_4_word_0 */ -#define INST_TYPE2_COMPARE_4_WORD_0__NUM 1 - -/* macros for type2_compare_4_word_1 */ -#define INST_TYPE2_COMPARE_4_WORD_1__NUM 1 - -/* macros for type2_compare_5_word_0 */ -#define INST_TYPE2_COMPARE_5_WORD_0__NUM 1 - -/* macros for type2_compare_5_word_1 */ -#define INST_TYPE2_COMPARE_5_WORD_1__NUM 1 - -/* macros for type2_compare_6_word_0 */ -#define INST_TYPE2_COMPARE_6_WORD_0__NUM 1 - -/* macros for type2_compare_6_word_1 */ -#define INST_TYPE2_COMPARE_6_WORD_1__NUM 1 - -/* macros for type2_compare_7_word_0 */ -#define INST_TYPE2_COMPARE_7_WORD_0__NUM 1 - -/* macros for type2_compare_7_word_1 */ -#define INST_TYPE2_COMPARE_7_WORD_1__NUM 1 - -/* macros for type2_compare_8_word_0 */ -#define INST_TYPE2_COMPARE_8_WORD_0__NUM 1 - -/* macros for type2_compare_8_word_1 */ -#define INST_TYPE2_COMPARE_8_WORD_1__NUM 1 - -/* macros for type2_compare_9_word_0 */ -#define INST_TYPE2_COMPARE_9_WORD_0__NUM 1 - -/* macros for type2_compare_9_word_1 */ -#define INST_TYPE2_COMPARE_9_WORD_1__NUM 1 - -/* macros for type2_compare_10_word_0 */ -#define INST_TYPE2_COMPARE_10_WORD_0__NUM 1 - -/* macros for type2_compare_10_word_1 */ -#define INST_TYPE2_COMPARE_10_WORD_1__NUM 1 - -/* macros for type2_compare_11_word_0 */ -#define INST_TYPE2_COMPARE_11_WORD_0__NUM 1 - -/* macros for type2_compare_11_word_1 */ -#define INST_TYPE2_COMPARE_11_WORD_1__NUM 1 - -/* macros for type2_compare_12_word_0 */ -#define INST_TYPE2_COMPARE_12_WORD_0__NUM 1 - -/* macros for type2_compare_12_word_1 */ -#define INST_TYPE2_COMPARE_12_WORD_1__NUM 1 - -/* macros for type2_compare_13_word_0 */ -#define INST_TYPE2_COMPARE_13_WORD_0__NUM 1 - -/* macros for type2_compare_13_word_1 */ -#define INST_TYPE2_COMPARE_13_WORD_1__NUM 1 - -/* macros for type2_compare_14_word_0 */ -#define INST_TYPE2_COMPARE_14_WORD_0__NUM 1 - -/* macros for type2_compare_14_word_1 */ -#define INST_TYPE2_COMPARE_14_WORD_1__NUM 1 - -/* macros for type2_compare_15_word_0 */ -#define INST_TYPE2_COMPARE_15_WORD_0__NUM 1 - -/* macros for type2_compare_15_word_1 */ -#define INST_TYPE2_COMPARE_15_WORD_1__NUM 1 - -/* macros for type2_compare_16_word_0 */ -#define INST_TYPE2_COMPARE_16_WORD_0__NUM 1 - -/* macros for type2_compare_16_word_1 */ -#define INST_TYPE2_COMPARE_16_WORD_1__NUM 1 - -/* macros for type2_compare_17_word_0 */ -#define INST_TYPE2_COMPARE_17_WORD_0__NUM 1 - -/* macros for type2_compare_17_word_1 */ -#define INST_TYPE2_COMPARE_17_WORD_1__NUM 1 - -/* macros for type2_compare_18_word_0 */ -#define INST_TYPE2_COMPARE_18_WORD_0__NUM 1 - -/* macros for type2_compare_18_word_1 */ -#define INST_TYPE2_COMPARE_18_WORD_1__NUM 1 - -/* macros for type2_compare_19_word_0 */ -#define INST_TYPE2_COMPARE_19_WORD_0__NUM 1 - -/* macros for type2_compare_19_word_1 */ -#define INST_TYPE2_COMPARE_19_WORD_1__NUM 1 - -/* macros for type2_compare_20_word_0 */ -#define INST_TYPE2_COMPARE_20_WORD_0__NUM 1 - -/* macros for type2_compare_20_word_1 */ -#define INST_TYPE2_COMPARE_20_WORD_1__NUM 1 - -/* macros for type2_compare_21_word_0 */ -#define INST_TYPE2_COMPARE_21_WORD_0__NUM 1 - -/* macros for type2_compare_21_word_1 */ -#define INST_TYPE2_COMPARE_21_WORD_1__NUM 1 - -/* macros for type2_compare_22_word_0 */ -#define INST_TYPE2_COMPARE_22_WORD_0__NUM 1 - -/* macros for type2_compare_22_word_1 */ -#define INST_TYPE2_COMPARE_22_WORD_1__NUM 1 - -/* macros for type2_compare_23_word_0 */ -#define INST_TYPE2_COMPARE_23_WORD_0__NUM 1 - -/* macros for type2_compare_23_word_1 */ -#define INST_TYPE2_COMPARE_23_WORD_1__NUM 1 - -/* macros for type2_compare_24_word_0 */ -#define INST_TYPE2_COMPARE_24_WORD_0__NUM 1 - -/* macros for type2_compare_24_word_1 */ -#define INST_TYPE2_COMPARE_24_WORD_1__NUM 1 - -/* macros for type2_compare_25_word_0 */ -#define INST_TYPE2_COMPARE_25_WORD_0__NUM 1 - -/* macros for type2_compare_25_word_1 */ -#define INST_TYPE2_COMPARE_25_WORD_1__NUM 1 - -/* macros for type2_compare_26_word_0 */ -#define INST_TYPE2_COMPARE_26_WORD_0__NUM 1 - -/* macros for type2_compare_26_word_1 */ -#define INST_TYPE2_COMPARE_26_WORD_1__NUM 1 - -/* macros for type2_compare_27_word_0 */ -#define INST_TYPE2_COMPARE_27_WORD_0__NUM 1 - -/* macros for type2_compare_27_word_1 */ -#define INST_TYPE2_COMPARE_27_WORD_1__NUM 1 - -/* macros for type2_compare_28_word_0 */ -#define INST_TYPE2_COMPARE_28_WORD_0__NUM 1 - -/* macros for type2_compare_28_word_1 */ -#define INST_TYPE2_COMPARE_28_WORD_1__NUM 1 - -/* macros for type2_compare_29_word_0 */ -#define INST_TYPE2_COMPARE_29_WORD_0__NUM 1 - -/* macros for type2_compare_29_word_1 */ -#define INST_TYPE2_COMPARE_29_WORD_1__NUM 1 - -/* macros for type2_compare_30_word_0 */ -#define INST_TYPE2_COMPARE_30_WORD_0__NUM 1 - -/* macros for type2_compare_30_word_1 */ -#define INST_TYPE2_COMPARE_30_WORD_1__NUM 1 - -/* macros for type2_compare_31_word_0 */ -#define INST_TYPE2_COMPARE_31_WORD_0__NUM 1 - -/* macros for type2_compare_31_word_1 */ -#define INST_TYPE2_COMPARE_31_WORD_1__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q8 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q8_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q8_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q8__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q8__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q8__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q8_MACRO__ */ - - -/* macros for enst_start_time_q8 */ -#define INST_ENST_START_TIME_Q8__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q9 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q9_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q9_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q9__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q9__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q9__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q9_MACRO__ */ - - -/* macros for enst_start_time_q9 */ -#define INST_ENST_START_TIME_Q9__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q10 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q10_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q10_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q10__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q10__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q10__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q10_MACRO__ */ - - -/* macros for enst_start_time_q10 */ -#define INST_ENST_START_TIME_Q10__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q11 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q11_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q11_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q11__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q11__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q11__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q11_MACRO__ */ - - -/* macros for enst_start_time_q11 */ -#define INST_ENST_START_TIME_Q11__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q12 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q12_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q12_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q12__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q12__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q12__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q12_MACRO__ */ - - -/* macros for enst_start_time_q12 */ -#define INST_ENST_START_TIME_Q12__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q13 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q13_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q13_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q13__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q13__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q13__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q13_MACRO__ */ - - -/* macros for enst_start_time_q13 */ -#define INST_ENST_START_TIME_Q13__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q14 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q14_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q14_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q14__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q14__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q14__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q14_MACRO__ */ - - -/* macros for enst_start_time_q14 */ -#define INST_ENST_START_TIME_Q14__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q15 */ -#ifndef __EMAC_REGS__ENST_START_TIME_Q15_MACRO__ -#define __EMAC_REGS__ENST_START_TIME_Q15_MACRO__ - -/* macros for field start_time_nsec */ -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__SHIFT 0 -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__WIDTH 30 -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__MASK 0x3fffffffU -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__READ(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__WRITE(src) \ - ((uint32_t)(src)\ - & 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x3fffffffU) | ((uint32_t)(src) &\ - 0x3fffffffU) -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x3fffffffU))) - -/* macros for field start_time_sec */ -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__SHIFT 30 -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__WIDTH 2 -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__MASK 0xc0000000U -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__RESET 0 -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__READ(src) \ - (((uint32_t)(src)\ - & 0xc0000000U) >> 30) -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__WRITE(src) \ - (((uint32_t)(src)\ - << 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0xc0000000U) | (((uint32_t)(src) <<\ - 30) & 0xc0000000U) -#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 30) & ~0xc0000000U))) -#define EMAC_REGS__ENST_START_TIME_Q15__TYPE uint32_t -#define EMAC_REGS__ENST_START_TIME_Q15__READ 0xffffffffU -#define EMAC_REGS__ENST_START_TIME_Q15__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_START_TIME_Q15_MACRO__ */ - - -/* macros for enst_start_time_q15 */ -#define INST_ENST_START_TIME_Q15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q8 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q8__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q8__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q8__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__ */ - - -/* macros for enst_on_time_q8 */ -#define INST_ENST_ON_TIME_Q8__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q9 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q9__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q9__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q9__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__ */ - - -/* macros for enst_on_time_q9 */ -#define INST_ENST_ON_TIME_Q9__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q10 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q10__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q10__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q10__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__ */ - - -/* macros for enst_on_time_q10 */ -#define INST_ENST_ON_TIME_Q10__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q11 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q11__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q11__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q11__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__ */ - - -/* macros for enst_on_time_q11 */ -#define INST_ENST_ON_TIME_Q11__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q12 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q12__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q12__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q12__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__ */ - - -/* macros for enst_on_time_q12 */ -#define INST_ENST_ON_TIME_Q12__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q13 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q13__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q13__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q13__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__ */ - - -/* macros for enst_on_time_q13 */ -#define INST_ENST_ON_TIME_Q13__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q14 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q14__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q14__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q14__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__ */ - - -/* macros for enst_on_time_q14 */ -#define INST_ENST_ON_TIME_Q14__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q15 */ -#ifndef __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__ -#define __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__ - -/* macros for field on_time */ -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__SHIFT 0 -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__WIDTH 17 -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__RESET 0x1FFFF -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_ON_TIME_Q15__TYPE uint32_t -#define EMAC_REGS__ENST_ON_TIME_Q15__READ 0xffffffffU -#define EMAC_REGS__ENST_ON_TIME_Q15__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__ */ - - -/* macros for enst_on_time_q15 */ -#define INST_ENST_ON_TIME_Q15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q8 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q8__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q8__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q8__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__ */ - - -/* macros for enst_off_time_q8 */ -#define INST_ENST_OFF_TIME_Q8__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q9 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q9__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q9__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q9__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__ */ - - -/* macros for enst_off_time_q9 */ -#define INST_ENST_OFF_TIME_Q9__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q10 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q10__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q10__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q10__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__ */ - - -/* macros for enst_off_time_q10 */ -#define INST_ENST_OFF_TIME_Q10__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q11 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q11__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q11__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q11__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__ */ - - -/* macros for enst_off_time_q11 */ -#define INST_ENST_OFF_TIME_Q11__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q12 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q12__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q12__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q12__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__ */ - - -/* macros for enst_off_time_q12 */ -#define INST_ENST_OFF_TIME_Q12__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q13 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q13__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q13__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q13__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__ */ - - -/* macros for enst_off_time_q13 */ -#define INST_ENST_OFF_TIME_Q13__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q14 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q14__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q14__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q14__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__ */ - - -/* macros for enst_off_time_q14 */ -#define INST_ENST_OFF_TIME_Q14__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q15 */ -#ifndef __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__ -#define __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__ - -/* macros for field off_time */ -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__SHIFT 0 -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__WIDTH 17 -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__MASK 0x0001ffffU -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__READ(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__WRITE(src) \ - ((uint32_t)(src)\ - & 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x0001ffffU) | ((uint32_t)(src) &\ - 0x0001ffffU) -#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x0001ffffU))) - -/* macros for field reserved_31_17 */ -#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__SHIFT 17 -#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__WIDTH 15 -#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__MASK 0xfffe0000U -#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__RESET 0 -#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__READ(src) \ - (((uint32_t)(src)\ - & 0xfffe0000U) >> 17) -#define EMAC_REGS__ENST_OFF_TIME_Q15__TYPE uint32_t -#define EMAC_REGS__ENST_OFF_TIME_Q15__READ 0xffffffffU -#define EMAC_REGS__ENST_OFF_TIME_Q15__WRITE 0xffffffffU - -#endif /* __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__ */ - - -/* macros for enst_off_time_q15 */ -#define INST_ENST_OFF_TIME_Q15__NUM 1 - -/* macros for BlueprintGlobalNameSpace::emac_regs::enst_control */ -#ifndef __EMAC_REGS__ENST_CONTROL_MACRO__ -#define __EMAC_REGS__ENST_CONTROL_MACRO__ - -/* macros for field enst_enable_q8 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__SHIFT 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__MASK 0x00000001U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__READ(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__WRITE(src) \ - ((uint32_t)(src)\ - & 0x00000001U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000001U) | ((uint32_t)(src) &\ - 0x00000001U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__VERIFY(src) \ - (!(((uint32_t)(src)\ - & ~0x00000001U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(1) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000001U) | (uint32_t)(0) - -/* macros for field enst_enable_q9 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__SHIFT 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__MASK 0x00000002U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__READ(src) \ - (((uint32_t)(src)\ - & 0x00000002U) >> 1) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__WRITE(src) \ - (((uint32_t)(src)\ - << 1) & 0x00000002U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000002U) | (((uint32_t)(src) <<\ - 1) & 0x00000002U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 1) & ~0x00000002U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(1) << 1) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000002U) | ((uint32_t)(0) << 1) - -/* macros for field enst_enable_q10 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__SHIFT 2 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__MASK 0x00000004U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__READ(src) \ - (((uint32_t)(src)\ - & 0x00000004U) >> 2) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__WRITE(src) \ - (((uint32_t)(src)\ - << 2) & 0x00000004U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000004U) | (((uint32_t)(src) <<\ - 2) & 0x00000004U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 2) & ~0x00000004U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(1) << 2) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000004U) | ((uint32_t)(0) << 2) - -/* macros for field enst_enable_q11 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__SHIFT 3 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__MASK 0x00000008U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__READ(src) \ - (((uint32_t)(src)\ - & 0x00000008U) >> 3) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__WRITE(src) \ - (((uint32_t)(src)\ - << 3) & 0x00000008U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000008U) | (((uint32_t)(src) <<\ - 3) & 0x00000008U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 3) & ~0x00000008U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(1) << 3) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000008U) | ((uint32_t)(0) << 3) - -/* macros for field enst_enable_q12 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__SHIFT 4 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__MASK 0x00000010U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__READ(src) \ - (((uint32_t)(src)\ - & 0x00000010U) >> 4) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__WRITE(src) \ - (((uint32_t)(src)\ - << 4) & 0x00000010U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000010U) | (((uint32_t)(src) <<\ - 4) & 0x00000010U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 4) & ~0x00000010U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(1) << 4) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000010U) | ((uint32_t)(0) << 4) - -/* macros for field enst_enable_q13 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__SHIFT 5 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__MASK 0x00000020U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__READ(src) \ - (((uint32_t)(src)\ - & 0x00000020U) >> 5) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__WRITE(src) \ - (((uint32_t)(src)\ - << 5) & 0x00000020U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000020U) | (((uint32_t)(src) <<\ - 5) & 0x00000020U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 5) & ~0x00000020U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(1) << 5) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000020U) | ((uint32_t)(0) << 5) - -/* macros for field enst_enable_q14 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__SHIFT 6 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__MASK 0x00000040U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__READ(src) \ - (((uint32_t)(src)\ - & 0x00000040U) >> 6) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__WRITE(src) \ - (((uint32_t)(src)\ - << 6) & 0x00000040U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000040U) | (((uint32_t)(src) <<\ - 6) & 0x00000040U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 6) & ~0x00000040U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(1) << 6) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000040U) | ((uint32_t)(0) << 6) - -/* macros for field enst_enable_q15 */ -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__SHIFT 7 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__MASK 0x00000080U -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__READ(src) \ - (((uint32_t)(src)\ - & 0x00000080U) >> 7) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__WRITE(src) \ - (((uint32_t)(src)\ - << 7) & 0x00000080U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00000080U) | (((uint32_t)(src) <<\ - 7) & 0x00000080U) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 7) & ~0x00000080U))) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__SET(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(1) << 7) -#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00000080U) | ((uint32_t)(0) << 7) - -/* macros for field reserved_15_8 */ -#define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__SHIFT 8 -#define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__WIDTH 8 -#define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__MASK 0x0000ff00U -#define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__RESET 0 -#define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__READ(src) \ - (((uint32_t)(src)\ - & 0x0000ff00U) >> 8) - -/* macros for field enst_disable_q8 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__SHIFT 16 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__MASK 0x00010000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__WRITE(src) \ - (((uint32_t)(src)\ - << 16) & 0x00010000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00010000U) | (((uint32_t)(src) <<\ - 16) & 0x00010000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 16) & ~0x00010000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__SET(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(1) << 16) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00010000U) | ((uint32_t)(0) << 16) - -/* macros for field enst_disable_q9 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__SHIFT 17 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__MASK 0x00020000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__WRITE(src) \ - (((uint32_t)(src)\ - << 17) & 0x00020000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00020000U) | (((uint32_t)(src) <<\ - 17) & 0x00020000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 17) & ~0x00020000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__SET(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(1) << 17) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00020000U) | ((uint32_t)(0) << 17) - -/* macros for field enst_disable_q10 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__SHIFT 18 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__MASK 0x00040000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__WRITE(src) \ - (((uint32_t)(src)\ - << 18) & 0x00040000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00040000U) | (((uint32_t)(src) <<\ - 18) & 0x00040000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 18) & ~0x00040000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__SET(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(1) << 18) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00040000U) | ((uint32_t)(0) << 18) - -/* macros for field enst_disable_q11 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__SHIFT 19 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__MASK 0x00080000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__WRITE(src) \ - (((uint32_t)(src)\ - << 19) & 0x00080000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00080000U) | (((uint32_t)(src) <<\ - 19) & 0x00080000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 19) & ~0x00080000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__SET(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(1) << 19) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00080000U) | ((uint32_t)(0) << 19) - -/* macros for field enst_disable_q12 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__SHIFT 20 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__MASK 0x00100000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__WRITE(src) \ - (((uint32_t)(src)\ - << 20) & 0x00100000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00100000U) | (((uint32_t)(src) <<\ - 20) & 0x00100000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 20) & ~0x00100000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__SET(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(1) << 20) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00100000U) | ((uint32_t)(0) << 20) - -/* macros for field enst_disable_q13 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__SHIFT 21 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__MASK 0x00200000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__WRITE(src) \ - (((uint32_t)(src)\ - << 21) & 0x00200000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00200000U) | (((uint32_t)(src) <<\ - 21) & 0x00200000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 21) & ~0x00200000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__SET(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(1) << 21) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00200000U) | ((uint32_t)(0) << 21) - -/* macros for field enst_disable_q14 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__SHIFT 22 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__MASK 0x00400000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__WRITE(src) \ - (((uint32_t)(src)\ - << 22) & 0x00400000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00400000U) | (((uint32_t)(src) <<\ - 22) & 0x00400000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 22) & ~0x00400000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__SET(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(1) << 22) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00400000U) | ((uint32_t)(0) << 22) - -/* macros for field enst_disable_q15 */ -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__SHIFT 23 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__WIDTH 1 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__MASK 0x00800000U -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__RESET 0 -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__WRITE(src) \ - (((uint32_t)(src)\ - << 23) & 0x00800000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__MODIFY(dst, src) \ - (dst) = ((dst) &\ - ~0x00800000U) | (((uint32_t)(src) <<\ - 23) & 0x00800000U) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__VERIFY(src) \ - (!((((uint32_t)(src)\ - << 23) & ~0x00800000U))) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__SET(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(1) << 23) -#define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__CLR(dst) \ - (dst) = ((dst) &\ - ~0x00800000U) | ((uint32_t)(0) << 23) - -/* macros for field reserved_31_24 */ -#define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__SHIFT 24 -#define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__WIDTH 8 -#define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__MASK 0xff000000U -#define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__RESET 0 -#define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__READ(src) \ - (((uint32_t)(src)\ - & 0xff000000U) >> 24) -#define EMAC_REGS__ENST_CONTROL__TYPE uint32_t -#define EMAC_REGS__ENST_CONTROL__READ 0xff00ffffU -#define EMAC_REGS__ENST_CONTROL__WRITE 0xff00ffffU - -#endif /* __EMAC_REGS__ENST_CONTROL_MACRO__ */ - - -/* macros for enst_control */ -#define INST_ENST_CONTROL__NUM 1 - -#endif /* __REG_EMAC_REGS_MACRO_H__ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/log.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/log.h deleted file mode 100644 index 68697e5dd0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/log.h +++ /dev/null @@ -1,97 +0,0 @@ -/********************************************************************** - * Copyright (C) 2014-2015 Cadence Design Systems, Inc. - * All rights reserved worldwide. - *********************************************************************** - * log.h - * System wide debug log messaging framework - ***********************************************************************/ - -#ifndef _HAVE_DBG_LOG_ - -#define _HAVE_DBG_LOG_ 1 - -#include -#include - -#ifdef DEBUG - #define CFP_DBG_MSG 1 -#endif - -/** - * Modules definitions - */ -#define CLIENT_MSG 0x01000000 - -#define DBG_GEN_MSG 0xFFFFFFFF - -/** - * Log level: - * DBG_CRIT - critical - * DBG_WARN - warning - * DBG_FYI - fyi - * DBG_HIVERB - highly verbose - * DBG_INFLOOP - infinite loop debug - */ -#define DBG_CRIT 0 -#define DBG_WARN 5 -#define DBG_FYI 10 -#define DBG_HIVERB 100 -#define DBG_INFLOOP 200 - -/* module mask: */ -#ifdef _HAVE_DBG_LOG_INT_ -unsigned int g_dbg_enable_log = 0; -#else -extern unsigned int g_dbg_enable_log; -#endif - -/* level, counter, state: */ -#ifdef _HAVE_DBG_LOG_INT_ -unsigned int g_dbg_log_lvl = DBG_CRIT; -unsigned int g_dbg_log_cnt = 0; -unsigned int g_dbg_state = 0; -#else -extern unsigned int g_dbg_log_lvl; -extern unsigned int g_dbg_log_cnt; -extern unsigned int g_dbg_state; -#endif - -#define cDbgMsg( _t, _x, ...) ( ((_x)== 0) || \ - (((_t) & g_dbg_enable_log) && ((_x) <= g_dbg_log_lvl)) ? \ - printf( __VA_ARGS__): 0 ) - - -#ifdef CFP_DBG_MSG -#define DbgMsg( t, x, ...) cDbgMsg( t, x, __VA_ARGS__ ) -#else -#define DbgMsg( t, x, ...) -#endif -#ifdef CFP_VDBG_MSG -#define vDbgMsg( l, m, n, ...) DbgMsg( l, m, "[%-20.20s %4d %4d]-" n, __func__,\ - __LINE__, g_dbg_log_cnt++, __VA_ARGS__) -#else -#define vDbgMsg( t, x, n, ...) -#endif -#ifdef CFP_CVDBG_MSG -#define cvDbgMsg( l, m, n, ...) cDbgMsg( l, m, "[%-20.20s %4d %4d]-" n, __func__,\ - __LINE__, g_dbg_log_cnt++, __VA_ARGS__) -#else -#define cvDbgMsg( l, m, n, ...) -#endif -#ifdef CFP_EVDBG_MSG -#define evDbgMsg( l, m, n, ...) { cDbgMsg( l, m, "[%-20.20s %4d %4d]-" n, __func__, \ - __LINE__, g_dbg_log_cnt++, __VA_ARGS__); \ - assert(0); } -#else -#define evDbgMsg( l, m, n, ...) -#endif - -#define DbgMsgSetLvl( x ) (g_dbg_log_lvl = x) -#define DbgMsgEnableModule( x ) (g_dbg_enable_log |= (x) ) -#define DbgMsgDisableModule( x ) (g_dbg_enable_log &= ~( (unsigned int) (x) )) -#define DbgMsgClearAll( _x ) ( g_dbg_enable_log = _x ) - -#define SetDbgState( _x ) (g_dbg_state = _x ) -#define GetDbgState (g_dbg_state) - -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/ppu_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/ppu_v1.h deleted file mode 100644 index 7b946490e5..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/include/ppu_v1.h +++ /dev/null @@ -1,485 +0,0 @@ -/***************************************************************************//** -* \file ppu_v1.h -* \version 1.0 -* -* This file provides the header for ARM PPU driver -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - -#ifndef PPU_V1_H -#define PPU_V1_H - -/*! - * \cond - * @{ - */ - -#include -#include -#include "cy_syslib.h" - -/* - * PPU 1.1 register definitions - */ -struct ppu_v1_reg { - __IOM uint32_t PWPR; - __IOM uint32_t PMER; - __IM uint32_t PWSR; - uint32_t RESERVED0; - __IM uint32_t DISR; - __IM uint32_t MISR; - __IM uint32_t STSR; - __IOM uint32_t UNLK; - __IOM uint32_t PWCR; - __IOM uint32_t PTCR; - uint32_t RESERVED1[2]; - __IOM uint32_t IMR; - __IOM uint32_t AIMR; - __IOM uint32_t ISR; - __IOM uint32_t AISR; - __IOM uint32_t IESR; - __IOM uint32_t OPSR; - uint32_t RESERVED2[2]; - __IOM uint32_t FUNRR; - __IOM uint32_t FULRR; - __IOM uint32_t MEMRR; - uint8_t RESERVED3[0x160 - 0x5C]; - __IOM uint32_t EDTR0; - __IOM uint32_t EDTR1; - uint32_t RESERVED4[2]; - __IOM uint32_t DCCR0; - __IOM uint32_t DCCR1; - uint8_t RESERVED5[0xFB0 - 0x178]; - __IM uint32_t IDR0; - __IM uint32_t IDR1; - uint8_t RESERVED6[0xFC8 - 0xFB8]; - __IM uint32_t IIDR; - __IM uint32_t AIDR; - uint8_t RESERVED7[0x1000 - 0xFD0]; -}; - -enum ppu_v1_mode { - PPU_V1_MODE_OFF = 0, - PPU_V1_MODE_OFF_EMU = 1, - PPU_V1_MODE_MEM_RET = 2, - PPU_V1_MODE_MEM_RET_EMU = 3, - PPU_V1_MODE_LOGIC_RET = 4, - PPU_V1_MODE_FULL_RET = 5, - PPU_V1_MODE_MEM_OFF = 6, - PPU_V1_MODE_FUNC_RET = 7, - PPU_V1_MODE_ON = 8, - PPU_V1_MODE_WARM_RST = 9, - PPU_V1_MODE_DBG_RECOV = 10, - /* No valid modes after this line */ - PPU_V1_MODE_COUNT -}; - -enum ppu_v1_opmode { - PPU_V1_OPMODE_00, - PPU_V1_OPMODE_01, - PPU_V1_OPMODE_02, - PPU_V1_OPMODE_03, - PPU_V1_OPMODE_04, - PPU_V1_OPMODE_05, - PPU_V1_OPMODE_06, - PPU_V1_OPMODE_07, - PPU_V1_OPMODE_08, - PPU_V1_OPMODE_09, - PPU_V1_OPMODE_10, - PPU_V1_OPMODE_11, - PPU_V1_OPMODE_12, - PPU_V1_OPMODE_13, - PPU_V1_OPMODE_14, - PPU_V1_OPMODE_15, - /* No valid operating modes after this line */ - PPU_V1_OPMODE_COUNT -}; - -enum ppu_v1_op_devactive { - PPU_V1_OP_DEVACTIVE_0, - PPU_V1_OP_DEVACTIVE_1, - PPU_V1_OP_DEVACTIVE_2, - PPU_V1_OP_DEVACTIVE_3, - PPU_V1_OP_DEVACTIVE_INDEPENDENT_COUNT, - PPU_V1_OP_DEVACTIVE_4 = 4, - PPU_V1_OP_DEVACTIVE_5, - PPU_V1_OP_DEVACTIVE_6, - PPU_V1_OP_DEVACTIVE_7, - /* No valid operating mode devactive signal number after this line */ - PPU_V1_OP_DEVACTIVE_COUNT -}; - -/* - * Bit definitions for PWPR - */ -#define PPU_V1_PWPR_PWR_POLICY_POS 0 -#define PPU_V1_PWPR_OP_POLICY_POS 16 - -#define PPU_V1_PWPR_POLICY UINT32_C(0x0000000F) -#define PPU_V1_PWPR_DYNAMIC_EN UINT32_C(0x00000100) -#define PPU_V1_PWPR_OFF_LOCK_EN UINT32_C(0x00001000) -#define PPU_V1_PWPR_OP_POLICY UINT32_C(0x000F0000) -#define PPU_V1_PWPR_OP_DYN_EN UINT32_C(0x01000000) - -/* - * Bit definitions for PWSR - */ -#define PPU_V1_PWSR_PWR_STATUS_POS 0 -#define PPU_V1_PWSR_OP_STATUS_POS 16 - -#define PPU_V1_PWSR_PWR_STATUS UINT32_C(0x0000000F) -#define PPU_V1_PWSR_PWR_DYN_STATUS UINT32_C(0x00000100) -#define PPU_V1_PWSR_OFF_LOCK_STATUS UINT32_C(0x00001000) -#define PPU_V1_PWSR_OP_STATUS UINT32_C(0x000F0000) -#define PPU_V1_PWSR_OP_DYN_STATUS UINT32_C(0x01000000) - -/* - * Bit definitions for DISR - */ -#define PPU_V1_DISR_PWR_DEVACTIVE_STATUS_POS 0 -#define PPU_V1_DISR_OP_DEVACTIVE_STATUS_POS 24 - -/* - * Bit definitions for UNLK - */ -#define PPU_V1_UNLK_OFF_UNLOCK UINT32_C(0x00000001) - -/* - * Bit definitions for PWCR - */ -#define PPU_V1_PWCR_DEV_REQ_EN UINT32_C(0x000000FF) -#define PPU_V1_PWCR_DEV_ACTIVE_EN UINT32_C(0x0007FF00) -#define PPU_V1_PWCR_OP_DEV_ACTIVE_EN UINT32_C(0xFF000000) - -/* - * Definitions for IESR and OPSR - */ -enum ppu_v1_edge_sensitivity { - PPU_V1_EDGE_SENSITIVITY_MASKED, - PPU_V1_EDGE_SENSITIVITY_RISING_EDGE, - PPU_V1_EDGE_SENSITIVITY_FALLING_EDGE, - PPU_V1_EDGE_SENSITIVITY_BOTH_EDGES, - /* No valid edge sensitivity after this line */ - PPU_V1_EDGE_SENSITIVITY_COUNT -}; - -#define PPU_V1_BITS_PER_EDGE_SENSITIVITY 2 -#define PPU_V1_EDGE_SENSITIVITY_MASK 0x3 - -/* - * Bit definitions for IMR - */ -#define PPU_V1_IMR_MASK UINT32_C(0x0000003F) -#define PPU_V1_IMR_STA_POLICY_TRN_IRQ_MASK UINT32_C(0x00000001) -#define PPU_V1_IMR_STA_ACCEPT_IRQ_MASK UINT32_C(0x00000002) -#define PPU_V1_IMR_STA_DENY_IRQ_MASK UINT32_C(0x00000004) -#define PPU_V1_IMR_EMU_ACCEPT_IRQ_MASK UINT32_C(0x00000008) -#define PPU_V1_IMR_EMU_DENY_IRQ_MASK UINT32_C(0x00000010) -#define PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK UINT32_C(0x00000020) - -/* - * Bit definitions for AIMR - */ -#define PPU_V1_AIMR_MASK UINT32_C(0x0000001F) -#define PPU_V1_AIMR_UNSPT_POLICY_IRQ_MASK UINT32_C(0x00000001) -#define PPU_V1_AIMR_DYN_ACCEPT_IRQ_MASK UINT32_C(0x00000002) -#define PPU_V1_AIMR_DYN_DENY_IRQ_MASK UINT32_C(0x00000004) -#define PPU_V1_AIMR_STA_POLICY_PWR_IRQ_MASK UINT32_C(0x00000008) -#define PPU_V1_AIMR_STA_POLICY_OP_IRQ_MASK UINT32_C(0x00000010) - -/* - * Bit definitions for ISR - */ -#define PPU_V1_ISR_MASK UINT32_C(0xFF07FFBF) -#define PPU_V1_ISR_STA_POLICY_TRN_IRQ UINT32_C(0x00000001) -#define PPU_V1_ISR_STA_ACCEPT_IRQ UINT32_C(0x00000002) -#define PPU_V1_ISR_STA_DENY_IRQ UINT32_C(0x00000004) -#define PPU_V1_ISR_EMU_ACCEPT_IRQ UINT32_C(0x00000008) -#define PPU_V1_ISR_EMU_DENY_IRQ UINT32_C(0x00000010) -#define PPU_V1_ISR_DYN_POLICY_MIN_IRQ UINT32_C(0x00000020) -#define PPU_V1_ISR_OTHER_IRQ UINT32_C(0x00000080) -#define PPU_V1_ISR_ACTIVE_EDGE_POS 8 -#define PPU_V1_ISR_ACTIVE_EDGE_IRQ_MASK UINT32_C(0x0007FF00) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE0_IRQ UINT32_C(0x00000100) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE1_IRQ UINT32_C(0x00000200) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE2_IRQ UINT32_C(0x00000400) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE3_IRQ UINT32_C(0x00000800) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE4_IRQ UINT32_C(0x00001000) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE5_IRQ UINT32_C(0x00002000) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE6_IRQ UINT32_C(0x00004000) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE7_IRQ UINT32_C(0x00008000) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE8_IRQ UINT32_C(0x00010000) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE9_IRQ UINT32_C(0x00020000) -#define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE10_IRQ UINT32_C(0x00040000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_POS 24 -#define PPU_V1_ISR_OP_ACTIVE_EDGE_IRQ_MASK UINT32_C(0xFF000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE0_IRQ UINT32_C(0x01000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE1_IRQ UINT32_C(0x02000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE2_IRQ UINT32_C(0x04000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE3_IRQ UINT32_C(0x08000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE4_IRQ UINT32_C(0x10000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE5_IRQ UINT32_C(0x20000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE6_IRQ UINT32_C(0x40000000) -#define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE7_IRQ UINT32_C(0x80000000) - -/* - * Bit definitions for AISR - */ -#define PPU_V1_AISR_MASK UINT32_C(0x0000001F) -#define PPU_V1_AISR_UNSPT_POLICY_IRQ UINT32_C(0x00000001) -#define PPU_V1_AISR_DYN_ACCEPT_IRQ UINT32_C(0x00000002) -#define PPU_V1_AISR_DYN_DENY_IRQ UINT32_C(0x00000004) -#define PPU_V1_AISR_STA_POLICY_PWR_IRQ UINT32_C(0x00000008) -#define PPU_V1_AISR_STA_POLICY_OP_IRQ UINT32_C(0x00000010) - -/* - * Bit definitions for AIDR - */ -#define PPU_V1_AIDR_ARCH_REV_MINOR UINT32_C(0x0000000F) -#define PPU_V1_AIDR_ARCH_REV_MAJOR UINT32_C(0x000000F0) - -/* - * Definitions for PPU Arch version ID - */ -#define PPU_V1_ARCH_ID 0x11 - -/* - * Bit definitions for IDR0 - */ -#define PPU_V1_IDR0_NUM_OPMODE_POS 4 -#define PPU_V1_IDR0_NUM_OPMODE UINT32_C(0x000000F0) - -/* - * Initializes the PPU by masking all interrupts and acknowledging any - * previously pending interrupt. - */ -void ppu_v1_init(struct ppu_v1_reg *ppu); - -/* - * Set PPU's power mode and wait for the transition. - * Note: This function currently supports only synchronous transitions with - * limited error detection. - */ -int ppu_v1_set_power_mode(struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode); - -/* - * Request PPU's power mode and don't wait for the transition. - */ -int ppu_v1_request_power_mode(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode); - -/* - * Request a change to the PPU's operating mode. - */ -int ppu_v1_request_operating_mode(struct ppu_v1_reg *ppu, - enum ppu_v1_opmode op_mode); - -/* - * Enable PPU's dynamic operating mode transitions - */ -void ppu_v1_opmode_dynamic_enable(struct ppu_v1_reg *ppu, - enum ppu_v1_opmode min_dyn_mode); - -/* - * Enable PPU's dynamic power mode transitions - */ -void ppu_v1_dynamic_enable(struct ppu_v1_reg *ppu, - enum ppu_v1_mode min_dyn_state); - -/* - * Enable the lock in the OFF state - */ -void ppu_v1_lock_off_enable(struct ppu_v1_reg *ppu); - -/* - * Disable the lock in the OFF state - */ -void ppu_v1_lock_off_disable(struct ppu_v1_reg *ppu); - -/* - * Get the current power mode. - */ -enum ppu_v1_mode ppu_v1_get_power_mode(struct ppu_v1_reg *ppu); - -/* - * Get the current programmed power policy mode. - */ -enum ppu_v1_mode ppu_v1_get_programmed_power_mode(struct ppu_v1_reg *ppu); - -/* - * Get the current operating mode. - */ -enum ppu_v1_opmode ppu_v1_get_operating_mode(struct ppu_v1_reg *ppu); - -/* - * Get the current programmed operating mode policy. - */ -enum ppu_v1_opmode ppu_v1_get_programmed_operating_mode(struct ppu_v1_reg *ppu); - -/* - * Check whether the dynamic transitions are enabled or not. - */ -bool ppu_v1_is_dynamic_enabled(struct ppu_v1_reg *ppu); - -/* - * Check whether the locked in the MEM_RET or OFF state. - */ -bool ppu_v1_is_locked(struct ppu_v1_reg *ppu); - -/* - * Check if the DEVACTIVE signal associated to a power mode is high. - */ -bool ppu_v1_is_power_devactive_high(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode); - -/* - * Check if the DEVACTIVE signal associated to an operating mode is high. - */ -bool ppu_v1_is_op_devactive_high(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive); - -/* - * Unlock the power domain from the OFF power mode. - */ -void ppu_v1_off_unlock(struct ppu_v1_reg *ppu); - -/* - * Disable the check of the DEVACTIVE signals by the PPU logic for state - * transition. - */ -void ppu_v1_disable_devactive(struct ppu_v1_reg *ppu); - -/* - * Disable the handshake with the P-channel or the Q-channels - */ -void ppu_v1_disable_handshake(struct ppu_v1_reg *ppu); - -/* - * Set one or more bits of the interrupt mask register. - */ -void ppu_v1_interrupt_mask(struct ppu_v1_reg *ppu, unsigned int mask); - -/* - * Set one or more bits of the additional interrupt mask register. - */ -void ppu_v1_additional_interrupt_mask(struct ppu_v1_reg *ppu, - unsigned int mask); - -/* - * Clear one or more bits of the interrupt mask register. - */ -void ppu_v1_interrupt_unmask(struct ppu_v1_reg *ppu, unsigned int mask); - -/* - * Clear one or more bits of the additional interrupt mask register. - */ -void ppu_v1_additional_interrupt_unmask(struct ppu_v1_reg *ppu, - unsigned int mask); - -/* - * Check if some additional interrupts are pending. - */ -bool ppu_v1_is_additional_interrupt_pending(struct ppu_v1_reg *ppu, - unsigned int mask); - -/* - * Acknowledge one or more interrupts. - */ -void ppu_v1_ack_interrupt(struct ppu_v1_reg *ppu, unsigned int mask); - -/* - * Acknowledge one or more additional interrupts. - */ -void ppu_v1_ack_additional_interrupt(struct ppu_v1_reg *ppu, unsigned int mask); - -/* - * Set input edge sensitivity. See 'enum ppu_v1_edge_sensitivity' for the - * available sensitivities. - */ -void ppu_v1_set_input_edge_sensitivity(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode, enum ppu_v1_edge_sensitivity edge_sensitivity); - -/* - * Get input edge sensitivity. See 'enum ppu_v1_edge_sensitivity' for the - * available sensitivities. - */ -enum ppu_v1_edge_sensitivity ppu_v1_get_input_edge_sensitivity( - struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode); - -/* - * Acknowledge a power active edge interrupt. - */ -void ppu_v1_ack_power_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode); - -/* - * Check if a power active edge interrupt is pending. - */ -bool ppu_v1_is_power_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode); - -/* - * Set operating mode active edge sensitivity. See - * 'enum ppu_v1_edge_sensitivity' for the available sensitivities. - */ -void ppu_v1_set_op_active_edge_sensitivity(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive, - enum ppu_v1_edge_sensitivity edge_sensitivity); - -/* - * Get operating mode active edge sensitivity. - * See 'enum ppu_v1_edge_sensitivity for the available sensitivities. - */ -enum ppu_v1_edge_sensitivity ppu_v1_get_op_active_edge_sensitivity( - struct ppu_v1_reg *ppu, enum ppu_v1_op_devactive op_devactive); - -/* - * Acknowledge operating mode active edge interrupt. - */ -void ppu_v1_ack_op_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive); - -/* - * Check if an operating mode active edge interrupt is pending. - */ -bool ppu_v1_is_op_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive); - -/* - * Check if the DYN input edge interrupt is pending. - */ -bool ppu_v1_is_dyn_policy_min_interrupt(struct ppu_v1_reg *ppu); - -/* - * Get the number of operating modes. - */ -unsigned int ppu_v1_get_num_opmode(struct ppu_v1_reg *ppu); - -/* - * Get the PPU architecture ID. - */ -unsigned int ppu_v1_get_arch_id(struct ppu_v1_reg *ppu); - -/*! - * \endcond - * @} - */ - -#endif /* PPU_V1_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_adc.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_adc.c deleted file mode 100644 index c64b0814ff..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_adc.c +++ /dev/null @@ -1,99 +0,0 @@ -#include "cy_device.h" - -#if defined (CY_IP_MXS28ADCCOMP) - -#include "cy_adc.h" - -#define CIC_CTRL_DEFAULT (_VAL2FLD(MXS28ADCCOMP_CIC_CTRL_CIC_COMB_DELAY_SEL, 0x244U)) -//#define CIC_CLOCK_CTRL_DEFAULT (_VAL2FLD(MXS28ADCCOMP_CIC_CLOCK_CTRL_CLK_EN, 0x3UL)) - - -#define CY_ADC_PD_MASK (MXS28ADCCOMP_PD_CTRL_PD_ADC_Msk | \ - MXS28ADCCOMP_PD_CTRL_PD_ADC_GMC_CAL_Msk | \ - MXS28ADCCOMP_PD_CTRL_PD_ADC_DC_CAL_Msk) - -/******************************************************************************* -* Function Name: Cy_ADC_Init -****************************************************************************//** -* -* Initializes the ADC block from a pre-initialized configuration structure. -* -* \param base -* The pointer to the hardware ADCCOMP block. -* -* \param config -* The pointer to the configuration structure \ref cy_stc_adc_config_t. -* -* \return -* The status /ref cy_en_adc_status_t. -* -* \funcusage -* \snippet adc/snippet/main.c snippet_Cy_ADC_Init -* -*******************************************************************************/ -cy_en_adc_status_t Cy_ADC_Init(MXS28ADCCOMP_Type * base, cy_stc_adc_config_t const * config) -{ - cy_en_adc_status_t ret = CY_ADC_BAD_PARAM; - - if ((NULL != base) && (NULL != config)) - { - /* configure sigma-delta modulator */ - - if(NULL != config->cicConfig) - { - /* configure decimator */ - } - else - { - /* reset cic registers to their default values */ - base->CIC_CTRL = CIC_CTRL_DEFAULT; - base->CIC_GAIN = 0UL; -// base->CIC_CLOCK_CTRL = CIC_CLOCK_CTRL_DEFAULT; - } - - ret = CY_ADC_SUCCESS; - } - - return ret; -} - - - -void Cy_ADC_Enable(MXS28ADCCOMP_Type * base, uint32_t pdMsk) -{ - uint32_t interruptState = Cy_SysLib_EnterCriticalSection(); - base->PD_CTRL = (base->PD_CTRL & ~CY_ADC_PD_MASK) | (~pdMsk & CY_ADC_PD_MASK); - Cy_SysLib_ExitCriticalSection(interruptState); -} - -void Cy_ADC_Disable(MXS28ADCCOMP_Type * base, uint32_t pdMsk) -{ - uint32_t interruptState = Cy_SysLib_EnterCriticalSection(); - base->PD_CTRL = (base->PD_CTRL & ~CY_ADC_PD_MASK) | (pdMsk & CY_ADC_PD_MASK); - Cy_SysLib_ExitCriticalSection(interruptState); -} - - - -cy_en_adc_status_t Cy_ADC_Configure(MXS28ADCCOMP_Type * base, uint32_t clockFreq, uint32_t sampleRate, uint32_t bitWidth) -{ - cy_en_adc_status_t ret = CY_ADC_BAD_PARAM; - - if(true /* arguments are ok */) - { - cy_stc_adc_cic_config_t locCicConfig; - cy_stc_adc_config_t locConfig; - - locConfig.cicConfig = &locCicConfig; - - - /* do some math with input parameters */ - - - ret = Cy_ADC_Init(base, &locConfig); - } - - return ret; -} - -#endif /* CY_IP_MXS28ADCCOMP */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_comp.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_comp.c deleted file mode 100644 index 5a892ff069..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_comp.c +++ /dev/null @@ -1,106 +0,0 @@ -#include "cy_device.h" - -#if defined (CY_IP_MXS28ADCCOMP) - -#include "cy_comp.h" - -/******************************************************************************* -* Function Name: Cy_Comp_Init -****************************************************************************//** -* -* Initializes ADCCOMP comparators. -* -* \param *base -* LPCOMP registers structure pointer. -* -* \param *config -* The pointer to the configuration structure for PDL. -* -* \return cy_en_lpcomp_status_t -* *base checking result. If the pointer is NULL, returns error. -* -*******************************************************************************/ -cy_en_comp_status_t Cy_COMP_Init(MXS28ADCCOMP_Type* base, cy_stc_comp_config_t const * config) -{ - cy_en_comp_status_t ret = CY_COMP_BAD_PARAM; - - if ((NULL != base) && (NULL != config)) - { - uint32_t interruptState; - uint32_t locLpCompCtrlMsk = 0UL; - uint32_t locLpCompCtrlVal = 0UL; - - if (0UL != (CY_COMP_1 & config->chanMsk)) - { - locLpCompCtrlMsk = MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_HYST_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_HYST_X2_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_NTD_EN_Msk; - - locLpCompCtrlVal = _VAL2FLD(MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_HYST, config->hyst) | - _BOOL2FLD(MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_HYST_X2, config->hyst_x2) | - _BOOL2FLD(MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_NTD_EN, config->ntd_en); - } - - if (0UL != (CY_COMP_2 & config->chanMsk)) - { - locLpCompCtrlMsk |= MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_HYST_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_HYST_X2_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_NTD_EN_Msk; - - locLpCompCtrlVal |= _VAL2FLD(MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_HYST, config->hyst) | - _BOOL2FLD(MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_HYST_X2, config->hyst_x2) | - _BOOL2FLD(MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_NTD_EN, config->ntd_en); - } - - interruptState = Cy_SysLib_EnterCriticalSection(); - base->LPCOMP_CTRL = (base->LPCOMP_CTRL & ~locLpCompCtrlMsk) | locLpCompCtrlVal; - Cy_SysLib_ExitCriticalSection(interruptState); - - ret = CY_COMP_SUCCESS; - } - - return (ret); -} - - -/******************************************************************************* -* Function Name: Cy_Comp_DeInit -****************************************************************************//** -* -* Deinitializes ADCCOMP comparators. -* -* \param *base -* LPCOMP registers structure pointer. -* -* \param chanMsk -* The channel mask specifies channel(s) which should be deinitialized. -* -*******************************************************************************/ -void Cy_COMP_DeInit(MXS28ADCCOMP_Type* base, uint32_t chanMsk) -{ - if (NULL != base) - { - uint32_t interruptState; - uint32_t locLpCompCtrlMsk = 0UL; - - if (0UL != (CY_COMP_1 & chanMsk)) - { - locLpCompCtrlMsk = MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_HYST_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_HYST_X2_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP1_NTD_EN_Msk; - } - - if (0UL != (CY_COMP_2 & chanMsk)) - { - locLpCompCtrlMsk |= MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_HYST_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_HYST_X2_Msk | - MXS28ADCCOMP_LPCOMP_CTRL_LPCOMP2_NTD_EN_Msk; - } - - interruptState = Cy_SysLib_EnterCriticalSection(); - base->LPCOMP_CTRL &= ~locLpCompCtrlMsk; - Cy_SysLib_ExitCriticalSection(interruptState); - } -} - -#endif /* CY_IP_MXS28ADCCOMP */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_cryptolite.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_cryptolite.c deleted file mode 100644 index d7ddca7359..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_cryptolite.c +++ /dev/null @@ -1,471 +0,0 @@ -/***************************************************************************//** -* \file cy_cryptolite.c -* \version 1.0.0 -* -* \brief -* Provides API implementation of the Cryptolite PDL driver. -* -******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXCRYPTOLITE) - -#include "cy_cryptolite.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cy_sysint.h" -#include "cy_syslib.h" - -/*Initial Hash*/ -static const uint32_t sha256InitHash[] = -{ - 0x6A09E667uL, 0xBB67AE85uL, 0x3C6EF372uL, 0xA54FF53AuL, - 0x510E527FuL, 0x9B05688CuL, 0x1F83D9ABuL, 0x5BE0CD19uL -}; - -/***************************************************************************** -* Cy_Cryptolite_Sha256_Process (for internal use) -****************************************************************************** -* -* The function starts the hash calculation, blocks untill finished. -* -* base -* The pointer to the Cryptolite instance. -* -* cfContext -* The pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -static cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Process(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext) -{ - if(REG_CRYPTOLITE_STATUS(base) & CRYPTO_STATUS_BUSY_Msk) - { - return CY_CRYPTOLITE_HW_BUSY; - } - - /*write to SHA DESCR REG starts process - IP will block another write to SHA DESCR REG untill its busy - We poll for busy state and check for error before posting next - descriptor */ - - /*start message schedule*/ - REG_CRYPTOLITE_SHA_DESCR(base) = (uint32_t)&(cfContext->message_schedule_struct); - while(REG_CRYPTOLITE_STATUS(base) & CRYPTO_STATUS_BUSY_Msk); - if(REG_CRYPTOLITE_SHA_INTR_ERROR(base) & CRYPTO_INTR_ERROR_BUS_ERROR_Msk) - { - REG_CRYPTOLITE_SHA_INTR_ERROR(base) = CRYPTO_INTR_ERROR_BUS_ERROR_Msk; - return CY_CRYPTOLITE_BUS_ERROR; - } - - /*start process*/ - REG_CRYPTOLITE_SHA_DESCR(base) = (uint32_t)&(cfContext->message_process_struct); - while(REG_CRYPTOLITE_STATUS(base) & CRYPTO_STATUS_BUSY_Msk); - if(REG_CRYPTOLITE_SHA_INTR_ERROR(base) & CRYPTO_INTR_ERROR_BUS_ERROR_Msk) - { - REG_CRYPTOLITE_SHA_INTR_ERROR(base) = CRYPTO_INTR_ERROR_BUS_ERROR_Msk; - return CY_CRYPTOLITE_BUS_ERROR; - } - - return CY_CRYPTOLITE_SUCCESS; -} - -/***************************************************************************** -* Cy_Cryptolite_Sha256_Init -****************************************************************************** -* -* The function to initialize the SHA256 operation. -* -* base -* The pointer to the Cryptolite instance. -* -* cfContext -* The pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Init(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext) -{ - /* Input parameters verification */ - if ((NULL == base) || (NULL == cfContext)) - { - return CY_CRYPTOLITE_BAD_PARAMS; - } - - cfContext->message = (uint8_t*)cfContext->msgblock; - - return (CY_CRYPTOLITE_SUCCESS); -} - -/******************************************************************************* -* Cy_Cryptolite_Sha256_Start -****************************************************************************** -* -* Initializes the initial Hash vector. -* -* base -* The pointer to the CRYPTOLITE instance. -* -* cfContext -* The pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Start(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext) -{ - uint32_t i; - /* Input parameters verification */ - if ((NULL == base) || (NULL == cfContext)) - { - return CY_CRYPTOLITE_BAD_PARAMS; - } - - /*check if IP is busy*/ - if (REG_CRYPTOLITE_STATUS(base) & CRYPTO_STATUS_BUSY_Msk) - { - return CY_CRYPTOLITE_HW_BUSY; - } - - cfContext->msgIdx = 0U; - cfContext->messageSize = 0U; - cfContext->message_schedule_struct.data0 = (uint32_t)CY_CRYPTOLITE_MSG_SCH_CTLWD; - cfContext->message_schedule_struct.data1 = (uint32_t)cfContext->message; - cfContext->message_schedule_struct.data2 = (uint32_t)cfContext->message_schedule; - - - cfContext->message_process_struct.data0 = (uint32_t)CY_CRYPTOLITE_PROCESS_CTLWD; - cfContext->message_process_struct.data1 = (uint32_t)cfContext->hash; - cfContext->message_process_struct.data2 = (uint32_t)cfContext->message_schedule; - - /*copy initial hash*/ - for (i=0; i < CY_CRYPTOLITE_SHA256_HASH_SIZE/4; i++) - { - cfContext->hash[i] = sha256InitHash[i]; - } - - return CY_CRYPTOLITE_SUCCESS; -} - -/******************************************************************************* -* Cy_Cryptolite_Sha256_Update -******************************************************************************** -* -* Performs the SHA256 calculation on one message. -* -* base -* The pointer to the CRYPTOLITE instance. -* -* cfContext -* The pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* message -* The pointer to the message whose Hash is being computed. -* -* messageSize -* The size of the message whose Hash is being computed. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Update(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext, - uint8_t const *message, - uint32_t messageSize) -{ - cy_en_cryptolite_status_t err = CY_CRYPTOLITE_BAD_PARAMS; - uint32_t idx = 0U; - - /* Input parameters verification */ - if ((NULL == base) || (NULL == cfContext) || (NULL == message)|| (0 == messageSize)) - { - return err; - } - - /*check if IP is busy*/ - if (REG_CRYPTOLITE_STATUS(base) & CRYPTO_STATUS_BUSY_Msk) - { - return CY_CRYPTOLITE_HW_BUSY; - } - - while((cfContext->msgIdx + messageSize) >= CY_CRYPTOLITE_SHA256_BLOCK_SIZE) - { - uint32_t tocopy = CY_CRYPTOLITE_SHA256_BLOCK_SIZE - cfContext->msgIdx; - /* Create a message block */ - for ( ; idx < tocopy; idx++ ) - { - cfContext->message[cfContext->msgIdx] = message[idx]; - } - /* calculate message schedule and process */ - err = Cy_Cryptolite_Sha256_Process(base, cfContext); - if(CY_CRYPTOLITE_SUCCESS != err) - { - return err; - } - messageSize-= tocopy; - cfContext->messageSize+= CY_CRYPTOLITE_SHA256_BLOCK_SIZE; - cfContext->msgIdx = 0U; - } - /* Copy message fragment*/ - for ( ; idx < messageSize; idx++ ) - { - cfContext->message[cfContext->msgIdx] = message[idx]; - cfContext->msgIdx++; - } - /*size of total bytes of message processed */ - cfContext->messageSize+= messageSize; - - return CY_CRYPTOLITE_SUCCESS; -} - -/******************************************************************************* -* Cy_Cryptolite_Sha256_Finish -****************************************************************************** -* -* Completes the SHA256 calculation. -* -* base -* The pointer to the CRYPTOLITE instance. -* -* cfContext -* the pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* digest -* The pointer to the calculated Hash digest. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Finish(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext, - uint8_t *digest) -{ - cy_en_cryptolite_status_t err = CY_CRYPTOLITE_SUCCESS; - uint8_t *hashptr; - uint32_t idx; - uint64_t totalMessageSizeInBits; - - /* Input parameters verification */ - if ((NULL == base) || (NULL == cfContext) || (NULL == digest)) - { - return err; - } - - /*check if IP is busy*/ - if (REG_CRYPTOLITE_STATUS(base) & CRYPTO_STATUS_BUSY_Msk) - { - return CY_CRYPTOLITE_HW_BUSY; - } - - totalMessageSizeInBits = (uint64_t)cfContext->messageSize * 8U; - /*Append one bit to end and clear rest of block*/ - cfContext->message[cfContext->msgIdx] = 0x80U; - idx = cfContext->msgIdx + 1; - - for ( ; idx < CY_CRYPTOLITE_SHA256_BLOCK_SIZE; idx++ ) - { - cfContext->message[idx] = 0U; - } - - /*if message size is more than pad size process the block*/ - if (cfContext->msgIdx >= CY_CRYPTOLITE_SHA256_PAD_SIZE) - { - err = Cy_Cryptolite_Sha256_Process(base, cfContext); - if(CY_CRYPTOLITE_SUCCESS != err) - { - return err; - } - /*clear the message block to finish*/ - for ( idx = 0; idx < CY_CRYPTOLITE_SHA256_PAD_SIZE; idx++ ) - { - cfContext->message[idx] = 0U; - } - } - - /*append total message size in bits from 57 to 64 bytes */ - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 1] = (uint8_t)totalMessageSizeInBits; - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 2] = (uint8_t)(totalMessageSizeInBits >> 8); - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 3] = (uint8_t)(totalMessageSizeInBits >> 16); - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 4] = (uint8_t)(totalMessageSizeInBits >> 24); - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 5] = (uint8_t)(totalMessageSizeInBits >> 32); - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 6] = (uint8_t)(totalMessageSizeInBits >> 40); - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 7] = (uint8_t)(totalMessageSizeInBits >> 48); - cfContext->message[CY_CRYPTOLITE_SHA256_BLOCK_SIZE - 8] = (uint8_t)(totalMessageSizeInBits >> 56); - - /*Process the last block*/ - err = Cy_Cryptolite_Sha256_Process(base, cfContext); - if(CY_CRYPTOLITE_SUCCESS != err) - { - return err; - } - - /* This implementation uses little endian ordering and SHA uses big endian, - reverse all the bytes in 32bit word when copying the final output hash.*/ - idx = (uint32_t)(CY_CRYPTOLITE_SHA256_HASH_SIZE / 4U); - hashptr = (uint8_t*)cfContext->hash; - - for( ; idx != 0U; idx--) - { - *(digest) = *(hashptr+3); - *(digest+1) = *(hashptr+2); - *(digest+2) = *(hashptr+1); - *(digest+3) = *(hashptr); - - digest += 4U; - hashptr += 4U; - } - - return CY_CRYPTOLITE_SUCCESS; -} - -/******************************************************************************* -* Cy_Cryptolite_Sha256_Free -****************************************************************************** -* -* Clears the used memory and context data. -* -* base -* The pointer to the CRYPTOLITE instance. -* -* cfContext -* the pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Free(CRYPTO_Type *base, - cy_stc_cryptolite_context_sha_t *cfContext) -{ - uint32_t idx; - (void)base; - - /* Input parameters verification */ - if (NULL == cfContext) - { - return CY_CRYPTOLITE_BAD_PARAMS; - } - - /* Clear the context memory */ - for ( idx = 0; idx < CY_CRYPTOLITE_SHA256_BLOCK_SIZE; idx++ ) - { - cfContext->message[idx] = 0U; - cfContext->message_schedule[idx] = 0U; - } - for ( idx = 0; idx < CY_CRYPTOLITE_SHA256_HASH_SIZE/4 ; idx++ ) - { - cfContext->hash[idx] = 0U; - } - - return CY_CRYPTOLITE_SUCCESS; -} - -/******************************************************************************* -* Cy_Cryptolite_Sha256_Run -****************************************************************************** -* -* This function performs the SHA256 Hash function. -* Provide the required parameters and the pointer -* to the context structure when making this function call. -* It is independent of the previous Crypto state because it already contains -* preparation, calculation, and finalization steps. -* -* base -* The pointer to the CRYPTOLITE instance. -* -* message -* The pointer to a message whose hash value is being computed. -* -* messageSize -* The size of a message in bytes. -* -* digest -* The pointer to the hash digest. -* -* cfContext -* the pointer to the cy_stc_cryptolite_context_sha_t structure that stores all -* internal variables for Cryptolite driver. -* -* return -* cy_en_cryptolite_status_t -* -*******************************************************************************/ -cy_en_cryptolite_status_t Cy_Cryptolite_Sha256_Run(CRYPTO_Type *base, - uint8_t const *message, - uint32_t messageSize, - uint8_t *digest, - cy_stc_cryptolite_context_sha_t *cfContext) -{ - cy_en_cryptolite_status_t err = CY_CRYPTOLITE_BAD_PARAMS; - /* Input parameters verification */ - if ((NULL == base) || (NULL == cfContext) || (NULL == message)|| (NULL == digest) || (0 == messageSize)) - { - return err; - } - - err = Cy_Cryptolite_Sha256_Init (base, cfContext); - - if (CY_CRYPTOLITE_SUCCESS == err) - { - err = Cy_Cryptolite_Sha256_Start (base, cfContext); - } - if (CY_CRYPTOLITE_SUCCESS == err) - { - err = Cy_Cryptolite_Sha256_Update (base, cfContext, message, messageSize); - } - if (CY_CRYPTOLITE_SUCCESS == err) - { - err = Cy_Cryptolite_Sha256_Finish (base, cfContext, digest); - } - if (CY_CRYPTOLITE_SUCCESS == err) - { - err = Cy_Cryptolite_Sha256_Free (base, cfContext); - } - - return (err); -} - -#if defined(__cplusplus) -} -#endif - - -#endif /* CY_IP_MXCRYPTOLITE */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_efuse_v3.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_efuse_v3.c deleted file mode 100644 index d70c4eafd2..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_efuse_v3.c +++ /dev/null @@ -1,387 +0,0 @@ -/***************************************************************************//** -* \file cy_efuse_v3.c -* \version 2.0 -* -* \brief -* Provides API implementation of the eFuse version_3 driver. -* -******************************************************************************** -* \copyright -* Copyright 2017-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXEFUSE) && (CY_IP_MXEFUSE_VERSION >= 3) - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include "cy_efuse.h" - -/*****************************************************************************/ -/* Local pre-processor symbols/macros ('#define') */ -/*****************************************************************************/ -/** \cond INTERNAL */ -#define EFUSE_MACRO_NUM (EFUSE_EFUSE_NR) -#define EFUSE_MACRO_SIZE (32UL) -#define EFUSE_SIZE (EFUSE_MACRO_SIZE * EFUSE_MACRO_NUM) -#define CY_EFUSE_WRITE_TIMEOUT_US (10UL) -/** \endcond */ - -/*****************************************************************************/ -/* Global variable definitions (declared in header file with 'extern') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local type definitions ('typedef') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local variable definitions ('static') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local function prototypes ('static') */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Function implementation - global ('extern') and local ('static') */ -/*****************************************************************************/ -/** - ***************************************************************************** - ** Cy_EFUSE_Enable - ** Enables the EFUSE block. - *****************************************************************************/ -void Cy_EFUSE_Enable(EFUSE_Type *base) -{ - EFUSE_CTL(base) = EFUSE_CTL_ENABLED_Msk; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_Disable - ** Disables the EFUSE block. All non-retention registers (command and status - ** registers) are reset to their default values when the IP is disabled. - *****************************************************************************/ -void Cy_EFUSE_Disable(EFUSE_Type *base) -{ - EFUSE_CTL(base) = 0UL; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_Init - ** This function enables the EFUSE block and initializes the registers with - ** the default values. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_Init(EFUSE_Type *base) -{ - /* Input parameter verification */ - if (NULL == base) - { - return CY_EFUSE_BAD_PARAM; - } - Cy_EFUSE_Disable(base); - Cy_EFUSE_Enable(base); - - return CY_EFUSE_SUCCESS; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_DeInit - ** Disables the EFUSE block. All non-retention registers (command and status - ** registers) are reset to their default values when the IP is disabled. - *****************************************************************************/ -void Cy_EFUSE_DeInit(EFUSE_Type *base) -{ - Cy_EFUSE_Disable(base); -} - -/** - ***************************************************************************** - ** Cy_EFUSE_WriteBit - ** Writes a bit to EFUSE by blowing a fuse, so this function is able to write - ** 1s only. Before write operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_WriteBit(EFUSE_Type *base, uint32_t bitPos, uint32_t offset) -{ - if((offset > EFUSE_SIZE) || (bitPos > CY_EFUSE_BITS_PER_BYTE)) - { - return CY_EFUSE_BAD_PARAM; - } - - cy_en_efuse_status_t ret = CY_EFUSE_WRITE_BUSY; - uint32_t timeout = CY_EFUSE_WRITE_TIMEOUT_US; - - /* Check whether EFUSE is busy or not. If the sequencer is busy, wait for a 10us */ - while ((0UL != (EFUSE_CMD(base) & EFUSE_CMD_START_Msk)) && (0UL < timeout)) - { - Cy_SysLib_DelayUs(1U); - --timeout; - } - - if (0UL == (EFUSE_CMD(base) & EFUSE_CMD_START_Msk)) - { - uint8_t readByte; - /* NOTE: This only supports 4 EFUSE macros */ - uint32_t byteAddr = offset / EFUSE_MACRO_NUM; - uint32_t macroAddr = offset % EFUSE_MACRO_NUM; - EFUSE_CMD(base) = _VAL2FLD(EFUSE_CMD_BIT_ADDR, bitPos) | /* Bit position within byte */ - _VAL2FLD(EFUSE_CMD_BYTE_ADDR, byteAddr) | /* Byte address within EFUSE macro */ - _VAL2FLD(EFUSE_CMD_MACRO_ADDR, macroAddr) | /* EFUSE macro number */ - EFUSE_CMD_START_Msk; - - /* Wait for program access to complete */ - timeout = CY_EFUSE_WRITE_TIMEOUT_US; - while ((0UL != (EFUSE_CMD(base) & EFUSE_CMD_START_Msk)) && (0UL < timeout)) - { - Cy_SysLib_DelayUs(1U); - --timeout; - } - - if(0 == timeout) - { - /* The program access is not completed */ - return CY_EFUSE_WRITE_TIMEOUT_ERROR; - } - - /* Check whether the program operation succeeded */ - (void)Cy_EFUSE_ReadByte(base, &readByte, offset); - ret = (0UL != (readByte & (1UL << bitPos))) ? CY_EFUSE_SUCCESS : CY_EFUSE_WRITE_ERROR; - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_WriteByte - ** Writes one byte. - ** Before write operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_WriteByte(EFUSE_Type *base, uint32_t src, uint32_t offset) -{ - cy_en_efuse_status_t ret = CY_EFUSE_BAD_PARAM; - - if ((offset < EFUSE_SIZE) && (src <= 0xFFUL)) - { - uint32_t bitPos = 0UL; - /* Clear the src bits that are already set */ - uint8_t readByte; - /* No error check since the function parameters are already checked */ - (void)Cy_EFUSE_ReadByte(base, &readByte, offset); - src &= (uint32_t)~readByte; - - ret = CY_EFUSE_SUCCESS; - while ((0U != src) && (CY_EFUSE_SUCCESS == ret)) - { - if (0UL != (src & 0x01UL)) - { - ret = Cy_EFUSE_WriteBit(base, bitPos, offset); - } - src >>= 1UL; - ++bitPos; - } - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_WriteWord - ** Writes every bit set in src that was not already programmed. - ** Before write operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_WriteWord(EFUSE_Type *base, uint32_t src, uint32_t offset) -{ - cy_en_efuse_status_t ret = CY_EFUSE_BAD_PARAM; - - if (offset < EFUSE_SIZE) - { - /* Clear the src bits that are already set */ - uint32_t readWord; - /* No error check since the function parameters are already checked */ - (void)Cy_EFUSE_ReadWord(base, &readWord, offset); - src &= (uint32_t)~readWord; - - /* Perform a sequence of byte writes to write a word */ - ret = CY_EFUSE_SUCCESS; - while ((0U != src) && (CY_EFUSE_SUCCESS == ret)) - { - uint32_t val = src & 0xFFUL; - if (0UL != val) - { - ret = Cy_EFUSE_WriteByte(base, val, offset); - } - src >>= 8UL; - ++offset; - } - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_WriteWordArray - ** Writes the values of num 32-bit words from the location pointed to by src - ** to the EFUSE location pointed to by offset. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_WriteWordArray(EFUSE_Type *base, const uint32_t *src, uint32_t offset, uint32_t num) -{ - cy_en_efuse_status_t ret = CY_EFUSE_BAD_PARAM; - - if ((offset < EFUSE_SIZE) && ((EFUSE_SIZE - offset) >= (num * sizeof(uint32_t)))) - { - ret = CY_EFUSE_SUCCESS; - for(; (0UL != num) && (CY_EFUSE_SUCCESS == ret); --num) - { - if (0UL != *src) - { - ret = Cy_EFUSE_WriteWord(base, *src, offset); - } - ++src; - offset += 4UL; /* One 4-byte word is written at a time */ - } - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_ReadByte - ** Reads byte from EFUSE. - ** Before read operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_ReadByte(EFUSE_Type *base, uint8_t *dst, uint32_t offset) -{ - cy_en_efuse_status_t ret = CY_EFUSE_BAD_PARAM; - if (offset < EFUSE_SIZE) - { - uint32_t word; - - /* Byte number within a 4-byte word */ - uint32_t byteNum = offset & 3UL; - - /* Offset must be 4-byte aligned for addressing MMIO space */ - offset &= ~3UL; - - /* No error check since the function parameters are already checked */ - (void) Cy_EFUSE_ReadWord(base, &word, offset); - - /* Extract the byte using the byte number */ - *dst = (uint8_t)(word >> (byteNum * 8UL)); - ret = CY_EFUSE_SUCCESS; - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_ReadWord - ** Reads a 32-bit word from EFUSE. - ** Before read operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_ReadWord(EFUSE_Type *base, uint32_t *dst, uint32_t offset) -{ - /* Suppress a compiler warning about unused variables */ - (void) base; - - cy_en_efuse_status_t ret = CY_EFUSE_BAD_PARAM; - if (offset < EFUSE_SIZE) - { - *dst = CY_GET_REG32(CY_EFUSE_BASE + offset); - ret = CY_EFUSE_SUCCESS; - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_ReadWordArray - ** Reads an array of 32-bit words from EFUSE. - ** Before read operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_ReadWordArray(EFUSE_Type *base, uint32_t *dst, uint32_t offset, uint32_t num) -{ - /* Suppress a compiler warning about unused variables */ - (void) base; - - cy_en_efuse_status_t ret = CY_EFUSE_BAD_PARAM; - - if ((offset < EFUSE_SIZE) && ((EFUSE_SIZE - offset) >= (num * sizeof(uint32_t)))) - { - for (; num != 0UL; ++num) - { - *dst = CY_GET_REG32(CY_EFUSE_BASE + offset); - ++dst; - offset += 4UL; /* One 4-byte word is read at a time */ - } - ret = CY_EFUSE_SUCCESS; - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_EFUSE_WriteBootRow - ** Writes data into BOsOTROW. - ** Before write operations you must call \ref Cy_EFUSE_Init(). - ** It is recommended to disable the block when not using it. - ** Call \ref Cy_EFUSE_Disable() to disable the EFUSE block. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_WriteBootRow(EFUSE_Type *base, uint32_t bootrow) -{ - /* Boot row is stored at address 0 of EFUSE macros 3-0 */ - return Cy_EFUSE_WriteWord(base, bootrow, 0UL); -} - -/** - ***************************************************************************** - ** Cy_EFUSE_ReadBootRow - ** Reads data from BOOTROW. - ** The BOOTROW information is latched upon system reset and is readable as - ** MMIO register. - *****************************************************************************/ -cy_en_efuse_status_t Cy_EFUSE_ReadBootRow(EFUSE_Type *base, uint32_t *bootrow) -{ - /* Suppress a compiler warning about unused variables */ - (void) base; - - *bootrow = EFUSE_BOOTROW; - return CY_EFUSE_SUCCESS; -} - - -#endif /* #ifdef (CY_IP_MXEFUSE) && (CY_IP_MXEFUSE_VERSION >= 3) */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ephy.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ephy.c deleted file mode 100644 index 1b42ddf5f4..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ephy.c +++ /dev/null @@ -1,279 +0,0 @@ -/***************************************************************************//** -* \file cy_ephy.c -* \version 1.0 -* -* Provides an API implementation of the Ethernet PHY driver -* -******************************************************************************** -* \copyright -* Copyright 2020, Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXETH) - -#include "cy_ephy.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DEFAULT_PHY_ADDRESS 0 -#define CY_EPHY_INVALID_VALUE 0xFFFF - -cy_en_ephy_status_t Cy_EPHY_Init( cy_stc_ephy_t *phy, phy_read_handle fnRead, phy_write_handle fnWrite ) -{ - CY_ASSERT_L2(phy != NULL); - CY_ASSERT_L2(fnRead != NULL); - CY_ASSERT_L2(fnWrite != NULL); - - phy->fnPhyRead = fnRead; - phy->fnPhyWrite = fnWrite; - phy->phyId = CY_EPHY_INVALID_VALUE; - phy->state = CY_EPHY_DOWN; - phy->anar=0; - phy->bmcr=0; - - return CY_EPHY_SUCCESS; -} - -/* discover connected phy. updated phy-id in ephy structure */ -cy_en_ephy_status_t Cy_EPHY_Discover( cy_stc_ephy_t *phy ) -{ - uint32_t phyAddress = DEFAULT_PHY_ADDRESS; - uint32_t ulLowerID = 0; - uint32_t ulUpperID = 0; - uint32_t ulPhyID = 0; - - CY_ASSERT_L2(phy->fnPhyRead != NULL); - CY_ASSERT_L2(phy->fnPhyWrite != NULL); - - phy->fnPhyRead( phyAddress, PHYREG_03_PHYSID2, &ulLowerID ); - if ( CY_EPHY_INVALID_VALUE == ulLowerID ) - return CY_EPHY_ERROR; - /* A valid PHY id can not be all zeros or all ones. */ - if( ( ulLowerID != ( uint16_t )~0UL ) && ( ulLowerID != ( uint16_t )0UL ) ) - { - phy->fnPhyRead( phyAddress, PHYREG_02_PHYSID1, &ulUpperID ); - if ( CY_EPHY_INVALID_VALUE == ulUpperID ) - return CY_EPHY_ERROR; - ulPhyID = ( _VAL2FLD( PHYID_ID1, ulUpperID ) | _VAL2FLD( PHYID_ID2, ulLowerID ) ); - } - phy->phyId = ulPhyID; - return CY_EPHY_SUCCESS; -} - -cy_en_ephy_status_t Cy_EPHY_Reset(cy_stc_ephy_t *phy) -{ - uint32_t ulConfig; - uint32_t phyAddress = DEFAULT_PHY_ADDRESS; - uint32_t delay, max_delay=10; - - CY_ASSERT_L2(phy->fnPhyRead != NULL); - CY_ASSERT_L2(phy->fnPhyWrite != NULL); - - /* Read Control register. */ - phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); - phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( ulConfig | PHYBMCR_RESET_Msk ) ); - /* The reset should last less than a second. */ - for( delay=0; delay < max_delay; delay++ ) - { - phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); - if( _FLD2VAL(PHYBMCR_RESET, ulConfig) == 0 ) - { - break; - } - Cy_SysLib_Delay(100); - } - - /* Clear the reset bits. */ - phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); - phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( ulConfig & ( ~PHYBMCR_RESET_Msk ) ) ); - Cy_SysLib_Delay(50); - return CY_EPHY_SUCCESS; -} - -cy_en_ephy_status_t Cy_EPHY_Configure( cy_stc_ephy_t *phy, cy_stc_ephy_config_t *config ) -{ - uint32_t ulConfig, ulAdvertise = 0; - uint32_t phyAddress = DEFAULT_PHY_ADDRESS; - - CY_ASSERT_L2(phy->fnPhyRead != NULL); - CY_ASSERT_L2(phy->fnPhyWrite != NULL); - - if( ( config->speed == CY_EPHY_SPEED_AUTO ) && ( config->duplex == CY_EPHY_DUPLEX_AUTO ) ) - { - ulAdvertise = PHYANAR_CSMA_Msk | PHYANAR_ALL_Msk; - } - else - { - if( config->speed == CY_EPHY_SPEED_AUTO ) - { - if( config->duplex == CY_EPHY_DUPLEX_FULL ) - { - ulAdvertise |= PHYANAR_10BASE_T_FD_Msk | PHYANAR_100BASE_TX_FD_Msk; - } - else - { - ulAdvertise |= PHYANAR_10BASE_T_Msk | PHYANAR_100BASE_TX_Msk; - } - } - else if( config->duplex == CY_EPHY_DUPLEX_AUTO ) - { - if( config->speed == CY_EPHY_SPEED_10 ) - { - ulAdvertise |= PHYANAR_10BASE_T_Msk | PHYANAR_10BASE_T_FD_Msk; - } - else - { - ulAdvertise |= PHYANAR_100BASE_TX_Msk | PHYANAR_100BASE_TX_FD_Msk; - } - } - else if( config->speed == CY_EPHY_SPEED_100 ) - { - if( config->duplex == CY_EPHY_DUPLEX_FULL ) - { - ulAdvertise |= PHYANAR_100BASE_TX_FD_Msk; - } - else - { - ulAdvertise |= PHYANAR_100BASE_TX_Msk; - } - } - else - { - if( config->duplex == CY_EPHY_DUPLEX_FULL ) - { - ulAdvertise |= PHYANAR_10BASE_T_FD_Msk; - } - else - { - ulAdvertise |= PHYANAR_10BASE_T_Msk; - } - } - } - - /* Send a reset commando to a set of PHY-ports. */ - Cy_EPHY_Reset( phy ); - - /* Write advertise register. */ - phy->fnPhyWrite( phyAddress, PHYREG_04_ADVERTISE, ulAdvertise ); - -// Cy_SysLib_Delay(500); - - /* Read Control register. */ - phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); - - ulConfig &= ~( PHYBMCR_SPEED_100_Msk | PHYBMCR_FULL_DUPLEX_Msk ); - - ulConfig |= PHYBMCR_AN_ENABLE_Msk; - - if( ( config->speed == CY_EPHY_SPEED_100 ) || ( config->speed == CY_EPHY_SPEED_AUTO ) ) - { - ulConfig |= PHYBMCR_SPEED_100_Msk; - } - else if( config->speed == CY_EPHY_SPEED_10 ) - { - ulConfig &= ~PHYBMCR_SPEED_100_Msk; - } - - if( ( config->duplex == CY_EPHY_DUPLEX_FULL ) || ( config->duplex == CY_EPHY_DUPLEX_AUTO ) ) - { - ulConfig |= PHYBMCR_FULL_DUPLEX_Msk; - } - else if( config->duplex == CY_EPHY_DUPLEX_HALF ) - { - ulConfig &= ~PHYBMCR_FULL_DUPLEX_Msk; - } - - /* Keep these values for later use. */ - phy->bmcr = ulConfig & ~PHYBMCR_ISOLATE_Msk; - phy->anar = ulAdvertise; - return CY_EPHY_SUCCESS; -} - -cy_en_ephy_status_t Cy_EPHY_StartAutoNegotiation(cy_stc_ephy_t *phy) -{ - uint32_t phyAddress=DEFAULT_PHY_ADDRESS; - uint32_t ulRegValue; - uint32 delay = 0, max_try=30; - - CY_ASSERT_L2(phy->fnPhyRead != NULL); - CY_ASSERT_L2(phy->fnPhyWrite != NULL); - - /* Enable Auto-Negotiation. */ - phy->fnPhyWrite( phyAddress, PHYREG_04_ADVERTISE, phy->anar ); - phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( phy->bmcr | PHYBMCR_AN_RESTART_Msk ) ); - - /* Wait until the auto-negotiation will be completed */ - /* max wait = 3s */ - for( delay=0; delayfnPhyRead( phyAddress, PHYREG_01_BMSR, &ulRegValue ); - if( _FLD2VAL( PHYBMSR_AN_COMPLETE,ulRegValue) != 0 ) - { - break; - } - Cy_SysLib_Delay(100); - } - - if(delay < max_try) - return CY_EPHY_SUCCESS; - else - return CY_EPHY_ERROR; -} - -/* - * we need to read the status register twice, keeping the second value. - */ - -uint32_t Cy_EPHY_GetLinkStatus(cy_stc_ephy_t *phy) -{ - uint32_t phyAddress=DEFAULT_PHY_ADDRESS; - uint32_t status; - - CY_ASSERT_L2(phy->fnPhyRead != NULL); - CY_ASSERT_L2(phy->fnPhyWrite != NULL); - - /* read bmcr */ - phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &status ); - - /* check for auto-neg-restart. Autoneg is being started, therefore disregard - * BMSR value and report link as down. - */ - if (status & PHYBMCR_AN_RESTART_Msk ) - return 0; - - /* Read link and autonegotiation status */ - status = 0; - phy->fnPhyRead( phyAddress, PHYREG_01_BMSR, &status ); - - if (CY_EPHY_INVALID_VALUE == status) - return 0; - else - return _FLD2VAL( PHYBMSR_LINK_STATUS, status ); -} - - - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXETH */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ethif.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ethif.c deleted file mode 100644 index 9aa15ff3ef..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ethif.c +++ /dev/null @@ -1,1761 +0,0 @@ -/***************************************************************************//** -* \file cy_ethif.c -* \version 1.0 -* -* Provides an API implementation of the ETHIF driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXETH) - -#include "cy_ethif.h" -#include -#include - -#if defined(__cplusplus) -extern "C" { -#endif - -/*************************************** -* Local Variables -***************************************/ -/** Cadence driver instantiation */ -static CEDI_OBJ *cyp_ethif_gemgxlobj; - -/** Ethernet configurations */ -static CEDI_Config cy_ethif_cfg; - -/** Cadence driver memory requirements */ -static CEDI_SysReq cy_ethif_sysreq; - -/** Private data structures required for each instance of Ethernet IPs */ -static CEDI_PrivateData * cyp_ethif_pd; - -/** Variables holding Statistics register values */ -static CEDI_Statistics * cyp_ethif_statistic; - -/** Tx and Rx buffer */ -uint8_t u8TxBuf[CY_ETH_TOTAL_TX_BUF][CY_ETH_SIZE_MAX_FRAME]; -uint8_t u8RxBuf[CY_ETH_TOTAL_RX_BUF][CY_ETH_SIZE_MAX_FRAME]; - -/** Tx and Rx buffer status */ -cy_stc_ethif_bufstatus_t cy_ethif_txBufStatus[CY_ETH_TOTAL_TX_BUF]; /** Buffer status will be CY_ETHIF_BUFFER_UNINIT */ -cy_stc_ethif_bufstatus_t cy_ethif_rxBufStatus[CY_ETH_TOTAL_RX_BUF]; /** Buffer status will be CY_ETHIF_BUFFER_UNINIT */ - -/** Private data memory allocation */ -uint8_t cy_ethif_privatedata[1800] = {0}; - -/** Tx descriptors */ -uint8_t cy_ethif_tx_desc_list[CY_ETH_DEFINE_NUM_TXQS][CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE + 1][CY_ETH_BD_SIZE]; - -/** Rx descriptors */ -/** Cadence driver requires another set of buffers to replace the existing -* buffers after a frame has been received. so, number of required BDs would not -* be same as number of buffers */ -uint8_t cy_ethif_rx_desc_list[CY_ETH_DEFINE_NUM_RXQS][((CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE + 1) * 2)][CY_ETH_BD_SIZE]; - -/** Statistics registers */ -uint8_t cy_ethif_statistic[160]; - -cy_stc_ethif_cb_t stccallbackfunctions; -cy_stc_ethif_queue_disablestatus_t stcQueueDisStatus; -bool bBufferInitialized = false; - -/***************************************************************************** -* Local function prototypes ('static') -*****************************************************************************/ -static void Cy_ETHIF_EnableInterrupts(cy_stc_ethif_interruptconfig_t * pstcInterruptList); -static void Cy_ETHIF_PrepareConfiguration(cy_stc_ethif_config_t * pstcEthIfConfig); -static void Cy_ETHIF_AssignMemory(void); -static void Cy_ETHIF_EventTx(void *pcy_privatedata, uint32_t u32event, uint8_t u8qnum); -static void Cy_ETHIF_EventTxError(void *pcy_privatedata, uint32_t u32event, uint8_t u8qnum); -static void Cy_ETHIF_EventRxFrame(void *pcy_privatedata, uint8_t u8qnum); -static void Cy_ETHIF_EventRxError(void *pcy_privatedata, uint32_t a_event, uint8_t a_qnum); -static void Cy_ETHIF_EventPhyManComplete(void *pcy_privatedata, uint8_t u8read, uint16_t u16ReadData); -static void Cy_ETHIF_EventhrespError(void *pcy_privatedata, uint8_t u8qnum); -static void Cy_ETHIF_EventLpPageRx(void* pcy_privatedata, struct CEDI_LpPageRx* pageRx); -static void Cy_ETHIF_EventAn(void* pcy_privatedata, struct CEDI_NetAnStatus* netStat); -static void Cy_ETHIF_EventLinkChange(void *pcy_privatedata, uint8_t a_linkstate); -static void Cy_ETHIF_EventTsu(void *pcy_privatedata, uint32_t u32event); -static void Cy_ETHIF_EventPauseFrame(void *pcy_privatedata, uint32_t u32event); -static void Cy_ETHIF_EventPtp(void* pcy_privatedata, uint32_t u32type, struct CEDI_1588TimerVal* time); -static void Cy_ETHIF_EventExternalInt(void * pcy_privatedata); -static void Cy_ETHIF_EventWol(void * pcy_privatedata); -static void Cy_ETHIF_EventLpi(void * pcy_privatedata); -static void Cy_ETHIF_InitializeBuffers(void); -static void Cy_ETHIF_ClearBuffer(uint32_t * pu32Buffer); -static uint8_t Cy_ETHIF_GetBuf(bool bTransmitBuf); -static cy_en_ethif_status_t Cy_ETHIF_WrapperConfig(cy_stc_ethif_wrapper_config_t * pstcWrapperConfig); -static void Cy_ETHIF_IPEnable(void); -static void Cy_ETHIF_IPDisable(void); -static cy_en_ethif_status_t Cy_ETHIF_TSUInit(cy_stc_ethif_tsu_config_t * pstcTSUConfig); -static cy_en_ethif_status_t Cy_ETHIF_DisableQueues(cy_stc_ethif_config_t * pstcEthIfConfig); - -/***************************************************************************** -* Local Call back function supplied to Cadence driver -*****************************************************************************/ -CEDI_Callbacks Cy_ETHIF_Callbacks = { - .phyManComplete = (CEDI_CbPhyManComplete)Cy_ETHIF_EventPhyManComplete, - .txEvent = (CEDI_CbTxEvent)Cy_ETHIF_EventTx, - .txError = (CEDI_CbTxError)Cy_ETHIF_EventTxError, - .rxFrame = (CEDI_CbRxFrame)Cy_ETHIF_EventRxFrame, - .rxError = (CEDI_CbRxError)Cy_ETHIF_EventRxError, - .hrespError = (CEDI_CbHrespError)Cy_ETHIF_EventhrespError, - .lpPageRx = (CEDI_CbLpPageRx)Cy_ETHIF_EventLpPageRx, - .anComplete = (CEDI_CbAnComplete)Cy_ETHIF_EventAn, - .linkChange = (CEDI_CbLinkChange)Cy_ETHIF_EventLinkChange, - .tsuEvent = (CEDI_CbTsuEvent)Cy_ETHIF_EventTsu, - .pauseEvent = (CEDI_CbPauseEvent)Cy_ETHIF_EventPauseFrame, - .ptpPriFrameTx = (CEDI_CbPtpPriFrameTx)Cy_ETHIF_EventPtp, - .ptpPeerFrameTx = (CEDI_CbPtpPeerFrameTx)Cy_ETHIF_EventPtp, - .ptpPriFrameRx = (CEDI_CbPtpPriFrameRx)Cy_ETHIF_EventPtp, - .ptpPeerFrameRx = (CEDI_CbPtpPeerFrameRx)Cy_ETHIF_EventPtp, - .lpiStatus = (CEDI_CbLpiStatus)Cy_ETHIF_EventLpi, - .wolEvent = (CEDI_CbWolEvent)Cy_ETHIF_EventWol, - .extInpIntr = (CEDI_CbExtInpIntr)Cy_ETHIF_EventExternalInt -}; - -/******************************************************************************* -* Function Name: Cy_ETHIF_Init -****************************************************************************//** -* -* \brief Initializes the Ethernet MAC, Cadence Driver, EthIf and PHY -* -* \param pstcEthIfConfig -* Pointer to Ethernet configuration parameters -* -* \param pstcInterruptList -* List of Interrupts to enable -* -* \return CY_ETHIF_SUCCESS Ethernet MAC has been initialized along with -* Cadence driver and external PHY -* \return CY_ETHIF_BAD_PARAM If following conditions are met: -* pstcEth == NULL -* pstcEthIfConfig == NULL -* pstcInterruptList == NULL -* GEM_GXL Object could not be created -* Memory assigned by Interface layer is not enough -* Cadence driver could not initialize Ethernet MAC -* CY_ETHIF_MEMORY_NOT_ENOUGH -* Assigned memory for BDs or for Private data is -* not enough -* CY_ETHIF_LINK_DOWN Link is not yet up -* -* \ Note: -* This function Initializes the Ethernet MAC, Cadence driver, EthIf layer and -* external PHY with the provided parameters. Port init for the Ethernet must be -* done before calling Cy_EthIf_Init function. Buffer configuration parameters -* shall be done in EthIf.h file -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_Init(cy_stc_ethif_config_t * pstcEthIfConfig, cy_stc_ethif_interruptconfig_t * pstcInterruptList) -{ - // local variable declaration - uint32_t u32RetValue = 0; - uint8_t u8tmpcounter = 0; - uint8_t u8tmpintrcntr = 0; - bool bClearAll = true; - bool bTransmitBuf = true; - uint16_t u16SysReqTxBDLength = 0; - uint16_t u16SysReqRxBDLength = 0; - - /* Parameter checks */ - if ((pstcEthIfConfig == NULL) || (pstcInterruptList == NULL)) - return CY_ETHIF_BAD_PARAM; - else if (pstcEthIfConfig->pstcWrapperConfig == NULL) - { - return CY_ETHIF_BAD_PARAM; - } - - if (bBufferInitialized == false) - { - /* Create GEM_GXL object */ - cyp_ethif_gemgxlobj = CEDI_GetInstance(); - if (cyp_ethif_gemgxlobj == NULL) - { - return CY_ETHIF_BAD_PARAM; - } - } - - /* Load Init parameter */ - Cy_ETHIF_PrepareConfiguration(pstcEthIfConfig); - - if (pstcEthIfConfig->bintrEnable == true) - { - /* Configure Interrupts */ - Cy_ETHIF_EnableInterrupts(pstcInterruptList); - - /* Init Callback functions */ - stccallbackfunctions.rxframecb = NULL; - stccallbackfunctions.txerrorcb = NULL; - stccallbackfunctions.txcompletecb = NULL; - stccallbackfunctions.tsuSecondInccb = NULL; - } - - /* Initialize ENET MAC Wrapper */ - if (CY_ETHIF_BAD_PARAM == Cy_ETHIF_WrapperConfig(pstcEthIfConfig->pstcWrapperConfig)) - { - Cy_ETHIF_IPDisable(); - return CY_ETHIF_BAD_PARAM; - } - - /* Enable the IP to access EMAC registers set */ - Cy_ETHIF_IPEnable(); - - /* Probe for checking configuration parameters and calculating memory size */ - (void)cyp_ethif_gemgxlobj->probe(&cy_ethif_cfg, &cy_ethif_sysreq); - - /* Check for assigned memory and required memory match */ - u16SysReqTxBDLength = ((cy_ethif_sysreq.txDescListSize / CY_ETH_DEFINE_NUM_TXQS)/(CY_ETH_DEFINE_TOTAL_BD_PER_TXQUEUE + 1)); - u16SysReqRxBDLength = ((cy_ethif_sysreq.rxDescListSize / CY_ETH_DEFINE_NUM_RXQS)/(CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE + 1)); - - if ((u16SysReqTxBDLength != CY_ETH_BD_SIZE) || (u16SysReqRxBDLength != CY_ETH_BD_SIZE)) - { - /* Memory not enough */ - return CY_ETHIF_MEMORY_NOT_ENOUGH; - } - - if (sizeof(cy_ethif_privatedata)< cy_ethif_sysreq.privDataSize) - { - /* Memory not enough */ - return CY_ETHIF_MEMORY_NOT_ENOUGH; - } - - /* assign starting addresses to local variable */ - Cy_ETHIF_AssignMemory(); - - /* Initialization EMAC registers */ - u32RetValue = cyp_ethif_gemgxlobj->init((void *)cyp_ethif_pd, &cy_ethif_cfg, &Cy_ETHIF_Callbacks); - if (u32RetValue == EINVAL || u32RetValue == ENOTSUP) - { - Cy_ETHIF_IPDisable(); - return CY_ETHIF_BAD_PARAM; - } - - /* Disable Transmit and Receive Queues */ - Cy_ETHIF_DisableQueues(pstcEthIfConfig); - - /* TSU Initialization */ - if (NULL != pstcEthIfConfig->pstcTSUConfig) - { - if (CY_ETHIF_BAD_PARAM == Cy_ETHIF_TSUInit(pstcEthIfConfig->pstcTSUConfig)) - { - Cy_ETHIF_IPDisable(); - return CY_ETHIF_BAD_PARAM; - } - } - - /* Initialize Buffer status */ - if (bBufferInitialized == false) - { - Cy_ETHIF_InitializeBuffers(); - bBufferInitialized = true; - } - else - { - /* clear all released transmit buffer */ - Cy_ETHIF_ClearReleasedBuf(bClearAll, bTransmitBuf); - bTransmitBuf = false; - /* clear all released receive buffer */ - Cy_ETHIF_ClearReleasedBuf(bClearAll, bTransmitBuf); - } - - /* allocate assign buffers to RX BDs */ - for (u8tmpcounter = 0; u8tmpcounter < cy_ethif_cfg.rxQs; u8tmpcounter++) - { - for (u8tmpintrcntr = 0; u8tmpintrcntr < cy_ethif_cfg.rxQLen[u8tmpcounter]; u8tmpintrcntr++) - { - cyp_ethif_gemgxlobj->addRxBuf((void *)cyp_ethif_pd, - u8tmpcounter, - (CEDI_BuffAddr *)&cy_ethif_rxBufStatus[(u8tmpintrcntr + (u8tmpcounter*CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE))].cy_ethif_bufaddr.vAddr, - 0); - cy_ethif_rxBufStatus[(u8tmpintrcntr + (u8tmpcounter*CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE))].enBufStatus = CY_ETHIF_BUFFER_OCCUPIED; - } - } - - /* additional Receive configurations */ - cyp_ethif_gemgxlobj->setCopyAllFrames((void *)cyp_ethif_pd, CY_ETH_ENABLE_1); - cyp_ethif_gemgxlobj->setRxBadPreamble((void *)cyp_ethif_pd, CY_ETH_ENABLE_1); - - /* Do not drop frames with CRC error */ - cyp_ethif_gemgxlobj->setIgnoreFcsRx((void *)cyp_ethif_pd, CY_ETH_ENABLE_1); - - // Optional: Setting Filter configuration - // Optional: setting screen registers - - /* Enable MDIO */ - cyp_ethif_gemgxlobj->setMdioEnable((void *)(void *)cyp_ethif_pd, CY_ETH_ENABLE_1); - /* driver start */ - cyp_ethif_gemgxlobj->start((void *)cyp_ethif_pd); - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_Init -****************************************************************************//** -* -* \brief Function loads callback functions to its local data structures -* -* \param cbFuncsList pointer to callback function list -* -*******************************************************************************/ -void Cy_ETHIF_RegisterCallbacks(cy_stc_ethif_cb_t *cbFuncsList) -{ - /* Load Callback functions */ - stccallbackfunctions.rxframecb = cbFuncsList->rxframecb; - stccallbackfunctions.txerrorcb = cbFuncsList->txerrorcb; - stccallbackfunctions.txcompletecb = cbFuncsList->txcompletecb; - stccallbackfunctions.tsuSecondInccb = cbFuncsList->tsuSecondInccb; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_TransmitFrame -****************************************************************************//** -* -* \brief Function initiates transmission based on passed arguments -* -* \param pu8TxBuffer pointer to Transmit source buffer -* u16Length Length of data to transmit from source buffer, Length should include source -* and destination buffer address. CRC bytes shall not be included in the length -* u8QueueIndex Queue to be used to transmit the frame -* bEndBuffer True - Last buffer of the frame to be transmitted -* False - Other Buffers to be provided after function call -* IP will not start transmitting until it gets EndBuffer True -* -* \param u16Length u16Length -* -* \param u8QueueIndex u8QueueIndex -* -* \param bEndBuffer bEndBuffer -* -* \return CY_ETHIF_SUCCESS Frame transmission started -* CY_ETHIF_BAD_PARAM Parameter passed contains invalid values -* CY_ETHIF_BUFFER_NOT_AVAILABLE Buffer not available to load the source data -* -* \note -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_TransmitFrame(uint8_t * pu8TxBuffer, uint16_t u16Length, uint8_t u8QueueIndex, bool bEndBuffer) -{ - uint8_t u8BufferIndex = 0; - uint8_t * pu8LocalBuf = 0; - bool bTransmitBuffer = true; - bool bClearAll = false; - uint8_t u8flags = 0; - // uint16_t u16idx = 0; - uint32_t u32result = 0; - - /* Check for arguments */ - if ((pu8TxBuffer == NULL) || (u16Length > CY_ETH_SIZE_MAX_FRAME) || (u8QueueIndex > CY_ETH_QS2_2)) - { - return CY_ETHIF_BAD_PARAM; - } - - /* Check requested queue enabled or not */ - if (stcQueueDisStatus.bTxQueueDisable[u8QueueIndex] == true) - { - /* Requested Queue is disabled */ - return CY_ETHIF_BAD_PARAM; - } - - /* Get available Tx Buffer from the Transmit buffer Pool */ - u8BufferIndex = Cy_ETHIF_GetBuf(bTransmitBuffer); - if (CY_ETHIF_NO_BUFFER_AVAILABLE == u8BufferIndex) - { - /* check for first released buffer */ - u8BufferIndex = Cy_ETHIF_ClearReleasedBuf(bClearAll, bTransmitBuffer); - if (CY_ETHIF_NO_BUFFER_AVAILABLE == u8BufferIndex) - { - return CY_ETHIF_BUFFER_NOT_AVAILABLE; // No buffer available - } - } - - /* Load the buffer address of available Buffer */ - pu8LocalBuf = (uint8_t *)cy_ethif_txBufStatus[u8BufferIndex].cy_ethif_bufaddr.vAddr; - - /* change buffer's status to OCCUPIED, Buffer will be released in case of error or after Tx complete interrupt occurs */ - cy_ethif_txBufStatus[u8BufferIndex].enBufStatus = CY_ETHIF_BUFFER_OCCUPIED; - - /* Copy data to un-cached aligned EthIf Tx buffer */ - memcpy((&pu8LocalBuf[0]), &pu8TxBuffer[0], u16Length); - - /* Typecast bEndBuffer to Flag type */ - // TODO: adapt function for CEDI_TXB_NO_AUTO_CRC and CEDI_TXB_NO_AUTO_START - if (bEndBuffer == true) - { - u8flags = CEDI_TXB_LAST_BUFF; - } - - /* Clear transmit status register before begin to transmit */ - cyp_ethif_gemgxlobj->clearTxStatus((void *)cyp_ethif_pd, CY_ETHIF_TX_STATUS_CLEAR); - - /* Trigger Internal transmit function */ - u32result = cyp_ethif_gemgxlobj->queueTxBuf((void *)cyp_ethif_pd, - u8QueueIndex, - &cy_ethif_txBufStatus[u8BufferIndex].cy_ethif_bufaddr, - u16Length, - u8flags); - if (u32result != 0) - { - /* error */ - cy_ethif_txBufStatus[u8BufferIndex].enBufStatus = CY_ETHIF_BUFFER_RELEASED; - return CY_ETHIF_BAD_PARAM; - } - - // TODO: wait until tx done successfully? - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_TxPauseFrame -****************************************************************************//** -* -* \brief Transmits IEEE 802.3X standard Pause Frame -* -* \param bZeroTQ True - Zero Time Quanta -* bZeroTQ False - Transmit pause frame with set time quanta -* -* \return none -* \note: If interrupt enabled, interrupt will be triggered at the end of the transmission -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_TxPauseFrame(bool bZeroTQ) -{ - /* check for arguments */ - - if (bZeroTQ == true) - { - /* trigger Pause frame with Zero Time Quanta */ - cyp_ethif_gemgxlobj->txZeroQPause((void *)cyp_ethif_pd); - } - else - { - cyp_ethif_gemgxlobj->txPauseFrame((void *)cyp_ethif_pd); - } - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_ConfigPause -****************************************************************************//** -* -* \brief Configures the Pause Frame transmission according to IEEE 802.3X standard -* -* \param u16PauseQuanta Time Quanta -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_ConfigPause(uint16_t u16PauseQuanta) -{ - /* Set Tx Pause Quanta for Priority 0 */ - if (EOK != cyp_ethif_gemgxlobj->setTxPauseQuantum((void *)cyp_ethif_pd, u16PauseQuanta, CY_ETHIF_PAUSE_P0)) - { - return CY_ETHIF_BAD_PARAM; - } - - /* Enable Receive Pause Frames */ - cyp_ethif_gemgxlobj->setCopyPauseDisable((void *)cyp_ethif_pd, CY_ETH_DISABLE_0); - - /* Enable Pause Frames */ - cyp_ethif_gemgxlobj->setPauseEnable((void *)cyp_ethif_pd, CY_ETH_ENABLE_1); - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_SetNoBroadCast -****************************************************************************//** -* -* \brief Disable/Enable receipt of broadcast frames -* -* \param rejectBC if =0 broadcasts are accepted, if =1 they are rejected. -* -*******************************************************************************/ -void Cy_ETHIF_SetNoBroadCast(bool rejectBC) -{ - cyp_ethif_gemgxlobj->setNoBroadcast((void *)cyp_ethif_pd,rejectBC); -} - - -/******************************************************************************* -* Function Name: Cy_EthIf_SetCopyAllFrames -****************************************************************************//** -* -* \brief Enable/Disable copy all frames mode -* -* \param toBeEnabled if =1 enables copy all frames mode, if =0 then this is disabled -* -*******************************************************************************/ -void Cy_ETHIF_SetCopyAllFrames(bool toBeEnabled) -{ - cyp_ethif_gemgxlobj->setCopyAllFrames((void *)cyp_ethif_pd,toBeEnabled); -} - -/******************************************************************************* -* Function : Cy_ETHIF_SetFilterAddress -****************************************************************************//** -* -* \brief Set Filter Address with specific filter number -* -* \param filterNo Filter number -* config Filter configuration for Ethernet MAC -* -* \param config config -* -* \return CY_ETHIF_SUCCESS Filter is set -* CY_ETHIF_BAD_PARAM Parameter passed contains invalid values -* -* \note -* Maximum 4 filters can be set -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_SetFilterAddress(cy_en_ethif_filter_num_t filterNo, const cy_stc_ethif_filter_config_t* config) -{ - if(filterNo >= CY_ETH_FILTER_NUM_INV) - { - return CY_ETHIF_BAD_PARAM; - } - - if(config == NULL) - { - return CY_ETHIF_BAD_PARAM; - } - - /* add some address filters */ - cyp_ethif_gemgxlobj->setSpecificAddr((void *)cyp_ethif_pd, - filterNo, - (CEDI_MacAddress*)&config->filterAddr, - config->typeFilter, - config->ignoreBytes); - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_PhyRegRead -****************************************************************************//** -* -* \brief Local function used by other APIs to read the PHY register -* -* \param u8RegNo Register to read -* -* \param u8PHYAddr u8PHYAddr -* -* \return read data from the register -* -* \note -* CY_ETH_PHY_ADDR must match with PHY. -* PHY data-sheet and hardware schematic shall be checked -* -*******************************************************************************/ -uint32_t Cy_ETHIF_PhyRegRead(uint8_t u8RegNo, uint8_t u8PHYAddr) -{ - uint32_t u32result; - uint16_t u16ReadData; - uint32_t nw_status; - - cyp_ethif_gemgxlobj->phyStartMdioRead( (void *)cyp_ethif_pd, CY_ETHIF_PHY_FLAG, u8PHYAddr, u8RegNo); - while(1) - { - nw_status = cyp_ethif_gemgxlobj->getMdioIdle((void *)cyp_ethif_pd); - if (nw_status != CY_ETH_MDIO_BUSY_0) - break; - } - - /* additional wait */ - Cy_SysLib_DelayUs(800); // 800us delay - - u32result = cyp_ethif_gemgxlobj->getMdioReadData((void *)cyp_ethif_pd, &u16ReadData); - if (u32result!=0) - { - // debug_printf("[ETH] PHY register read not success.\r\n"); - } - - return (uint32_t)u16ReadData; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_PhyRegWrite -****************************************************************************//** -* -* \brief Local function used by other APIs to write the PHY register -* -* \param u8RegNo Register to write -* \param u16Data data to write -* \param u8PHYAddr u8PHYAddr -* \return -* -* \note -* u8PHYAddr must match with PHY. -* PHY data-sheet and hardware schematic shall be checked -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_PhyRegWrite(uint8_t u8RegNo, uint16_t u16Data, uint8_t u8PHYAddr) -{ - cyp_ethif_gemgxlobj->phyStartMdioWrite( (void *)cyp_ethif_pd, CY_ETHIF_PHY_FLAG, u8PHYAddr, u8RegNo, u16Data ); - while (cyp_ethif_gemgxlobj->getMdioIdle((void *)cyp_ethif_pd) != CY_ETH_MDIO_BUSY_0); - - /* additional wait */ - Cy_SysLib_DelayUs(200); // 200usec - return CY_ETHIF_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_ETHIF_ClearReleasedBuf -****************************************************************************//** -* -* \brief Each buffer goes through cycle of FREE - OCCUPIED - RELEASED - FREE -* Function looks into status of each buffer and reset them to default values if status is RELEASED -* -* \param bClearAll True - Free all buffers which have status "CY_ETHIF_BUFFER_RELEASED" -* False - Only first buffer found to be "CY_ETHIF_BUFFER_RELEASED" will be free -* bTransmitBuf True - Free buffer from Transmit pool -* False - Free buffer from Receive pool -* -* \param bTransmitBuf bTransmitBuf -* -* \return CY_ETHIF_BUFFER_AVAILABLE when Free all released buffers -* CY_ETHIF_NO_BUFFER_AVAILABLE No Buffer in a state of "CY_ETHIF_BUFFER_RELEASED" -* u8tmpcounter in case of bClearAll to false, function will break right after locating first released buffer -* -*******************************************************************************/ -uint8_t Cy_ETHIF_ClearReleasedBuf (bool bClearAll, bool bTransmitBuf) -{ - bool bBufferReleased = false; - - if (bTransmitBuf) - { - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_TX_BUF; u8tmpcounter++) - { - if (cy_ethif_txBufStatus[u8tmpcounter].enBufStatus == CY_ETHIF_BUFFER_RELEASED) - { - Cy_ETHIF_ClearBuffer((uint32_t *)cy_ethif_txBufStatus[u8tmpcounter].cy_ethif_bufaddr.vAddr); - cy_ethif_txBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_FREE; - - bBufferReleased = true; - if (bClearAll == false) - { - return u8tmpcounter; - } - } - } - } - else - { - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_RX_BUF; u8tmpcounter++) - { - if (cy_ethif_rxBufStatus[u8tmpcounter].enBufStatus == CY_ETHIF_BUFFER_RELEASED) - { - Cy_ETHIF_ClearBuffer((uint32_t *)cy_ethif_rxBufStatus[u8tmpcounter].cy_ethif_bufaddr.vAddr); - cy_ethif_rxBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_FREE; - - bBufferReleased = true; - if (bClearAll == false) - { - return u8tmpcounter; - } - } - } - } - - if (bClearAll && bBufferReleased) - return CY_ETHIF_BUFFER_AVAILABLE; - else - return CY_ETHIF_NO_BUFFER_AVAILABLE; -} - - -/******************************************************************************* -* Function Name: Cy_ETHIF_GetTimerValue -****************************************************************************//** -* -* \brief Returns the current timer value from TSU register -* -* \param pstcRetTmrValue [out] pointer to data structure to return the values -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_Get1588TimerValue(CEDI_1588TimerVal* pstcRetTmrValue) -{ - if (pstcRetTmrValue == NULL) - { - return CY_ETHIF_BAD_PARAM; - } - - cyp_ethif_gemgxlobj->get1588Timer((void *)cyp_ethif_pd, pstcRetTmrValue); - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_SetTimerValue -****************************************************************************//** -* -* \brief Setting the current timer value in TSU register -* -* \param pstcTmrValue pointer to data structure to configure register with -* -*******************************************************************************/ -cy_en_ethif_status_t Cy_ETHIF_Set1588TimerValue(CEDI_1588TimerVal * pstcTmrValue) -{ - if (pstcTmrValue == NULL) - { - return CY_ETHIF_BAD_PARAM; - } - - if (EOK != cyp_ethif_gemgxlobj->set1588Timer((void *)cyp_ethif_pd, pstcTmrValue)) - { - /* Reason could be Null pointer, hardware does not support TSU or pstcTimerValue.nanosecs>0x3FFFFFFF */ - return CY_ETHIF_BAD_PARAM; - } - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_DecodeEvent -****************************************************************************//** -* -* \brief Interrupt handler for Ethernet instance ETH0 -* Function calls isr function to decode the event. -* -*******************************************************************************/ -void Cy_ETHIF_DecodeEvent(void) -{ -// volatile uint32_t u32result; - - cyp_ethif_gemgxlobj->isr((void *)cyp_ethif_pd); - //if (u32result!=0) debug_printf("NG4 (0x%08x)\r\n", result); - - return; -} - - -/*############################################################################*/ - -/******************************************************************************* -* Function Name: Cy_ETHIF_EnableInterrupts -****************************************************************************//** -* -* \brief Function initializes enabled Interrupt -* -* \param pstcInterruptList pointer to structure list -* -*******************************************************************************/ -static void Cy_ETHIF_EnableInterrupts (cy_stc_ethif_interruptconfig_t * pstcInterruptList) -{ - uint32_t u32InterruptEn = 0; - - if (pstcInterruptList->btsu_time_match == true) - u32InterruptEn |= CEDI_EV_TSU_TIME_MATCH; - if (pstcInterruptList->bwol_rx == true) - u32InterruptEn |= CEDI_EV_WOL_RX; - if (pstcInterruptList->blpi_ch_rx == true) - u32InterruptEn |= CEDI_EV_LPI_CH_RX; - if (pstcInterruptList->btsu_sec_inc == true) - u32InterruptEn |= CEDI_EV_TSU_SEC_INC; - if (pstcInterruptList->bptp_tx_pdly_rsp == true) - u32InterruptEn |= CEDI_EV_PTP_TX_PDLY_RSP; - if (pstcInterruptList->bptp_tx_pdly_req == true) - u32InterruptEn |= CEDI_EV_PTP_TX_PDLY_REQ; - if (pstcInterruptList->bptp_rx_pdly_rsp == true) - u32InterruptEn |= CEDI_EV_PTP_RX_PDLY_RSP; - if (pstcInterruptList->bptp_rx_pdly_req == true) - u32InterruptEn |= CEDI_EV_PTP_RX_PDLY_REQ; - if (pstcInterruptList->bptp_tx_sync == true) - u32InterruptEn |= CEDI_EV_PTP_TX_SYNC; - if (pstcInterruptList->bptp_tx_dly_req == true) - u32InterruptEn |= CEDI_EV_PTP_TX_DLY_REQ; - if (pstcInterruptList->bptp_rx_sync == true) - u32InterruptEn |= CEDI_EV_PTP_RX_SYNC; - if (pstcInterruptList->bptp_rx_dly_req == true) - u32InterruptEn |= CEDI_EV_PTP_RX_DLY_REQ; - if (pstcInterruptList->bpause_frame_tx == true) - u32InterruptEn |= CEDI_EV_PAUSE_FRAME_TX; - if (pstcInterruptList->bpause_time_zero == true) - u32InterruptEn |= CEDI_EV_PAUSE_TIME_ZERO; - if (pstcInterruptList->bpause_nz_qu_rx == true) - u32InterruptEn |= CEDI_EV_PAUSE_NZ_QU_RX; - if (pstcInterruptList->bhresp_not_ok == true) - u32InterruptEn |= CEDI_EV_HRESP_NOT_OK; - if (pstcInterruptList->brx_overrun == true) - u32InterruptEn |= CEDI_EV_RX_OVERRUN; - if (pstcInterruptList->btx_complete == true) - u32InterruptEn |= CEDI_EV_TX_COMPLETE; - if (pstcInterruptList->btx_fr_corrupt == true) - u32InterruptEn |= CEDI_EV_TX_FR_CORRUPT; - if (pstcInterruptList->btx_retry_ex_late_coll == true) - u32InterruptEn |= CEDI_EV_TX_RETRY_EX_LATE_COLL; - if (pstcInterruptList->btx_underrun == true) - u32InterruptEn |= CEDI_EV_TX_UNDERRUN; - if (pstcInterruptList->btx_used_read == true) - u32InterruptEn |= CEDI_EV_TX_USED_READ; - if (pstcInterruptList->brx_used_read == true) - u32InterruptEn |= CEDI_EV_RX_USED_READ; - if (pstcInterruptList->brx_complete == true) - u32InterruptEn |= CEDI_EV_RX_COMPLETE; - if (pstcInterruptList->bman_frame == true) - u32InterruptEn |= CEDI_EV_MAN_FRAME; - - cy_ethif_cfg.intrEnable = u32InterruptEn; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_PrepareConfiguration -****************************************************************************//** -* -* \brief prepares configuration based on the parameter passed to Cy_ETHIF_Init -* function. This prepared configuration which is dedicated for specific Ethernet -* instance would be used to initialize Ethernet MAC -* -* \param config Pointer to Ethernet configuration passed from Application layer -* -* \Note: -* -*******************************************************************************/ -static void Cy_ETHIF_PrepareConfiguration( cy_stc_ethif_config_t * config ) -{ - uint8_t u8QueueCounter = 0; - - /* Clear configuration table */ - memset((void *)&cy_ethif_cfg, 0, sizeof(cy_ethif_cfg)); - - /* Load GEM_GXL register base address */ - cy_ethif_cfg.regBase = CY_ETH0_GEMGXL_ADDR_REGBASE; - - /* Prepare Queues */ - cy_ethif_cfg.rxQs = CY_ETH_DEFINE_NUM_RXQS; - cy_ethif_cfg.txQs = CY_ETH_DEFINE_NUM_TXQS; - - for (u8QueueCounter=0; u8QueueCounteru8enRxBadPreamble; /* bit29 nsp_change */ - // cy_ethif_cfg[u8EthIfInstance].ifTypeSel = pstcEthIfConfig->ifTypeSel; /* bit27 sgmii_mode_enable (reserved) */ - /* (see the following) */ - // don't care /* bit26 ignore_rx_fcs */ - cy_ethif_cfg.enRxHalfDupTx = 0; /* bit25 en_half_duplex_rx, not supported by hardware */ - cy_ethif_cfg.chkSumOffEn = config->u8chkSumOffEn; /* bit24 receive_checksum_offload_enable */ - cy_ethif_cfg.disCopyPause = config->u8disCopyPause; /* bit23 disable_copy_of_pause_frames */ - if(ETH_AXI_MASTER_PRESENT == 1) - { - cy_ethif_cfg.dmaBusWidth = CEDI_DMA_BUS_WIDTH_64; /* bit22:21 data bus with */ - } - else - { - cy_ethif_cfg.dmaBusWidth = CEDI_DMA_BUS_WIDTH_32; /* bit22:21 data bus with */ - } - /* 00:32bit 01:64bit */ - cy_ethif_cfg.mdcPclkDiv = config->mdcPclkDiv; /* bit20:18 mdc_clock_division */ - /* 010: Divide 32 */ - /* 011: Divide 48 */ - // don't care /* bit17 fcs_remove */ - cy_ethif_cfg.rxLenErrDisc = config->u8rxLenErrDisc; /* bit16 length_field_error_frame_discard */ - cy_ethif_cfg.rxBufOffset = 0; /* bit15:14 receive_buffer_offset */ - // don't care /* bit13 pause_enable */ - // don't care /* bit12 retry_test */ - //cy_ethif_cfg[u8EthIfInstance].ifTypeSel = pstcEthIfConfig->ifTypeSel /* bit11 pcs_select (reserved)*/ - /* (see the following) */ - //cy_ethif_cfg[u8EthIfInstance].ifTypeSel = pstcEthIfConfig->ifTypeSel /* bit10 gigabit_mode_enable */ - /* (see the following) */ - cy_ethif_cfg.extAddrMatch = 0; /* bit9 external_address_match_enable, not supported by hardware */ - cy_ethif_cfg.rx1536ByteEn = config->u8rx1536ByteEn; /* bit8 receive_1536_byte_frames */ - // don't care /* bit7 unicast_hash_enable */ - // don't care /* bit6 multicast_hash_enable */ - // don't care /* bit5 no_broadcast */ - // don't care /* bit4 copy_all_frames */ - cy_ethif_cfg.rxJumboFrEn = config->u8rxJumboFrEn; /* bit3 jumbo_frames */ - // don't care /* bit2 discard_non_vlan_frames */ - cy_ethif_cfg.fullDuplex = 1; /* bit1 full_duplex */ - //cy_ethif_cfg[u8EthIfInstance].ifTypeSel = pstcEthIfConfig->ifTypeSel /* bit0 speed */ - - /* configuration for cy_ethif_cfg[u8EthIfInstance].ifTypeSel */ - if ((config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_MII_10) || - (config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RGMII_10) || - (config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RMII_10)) - { - cy_ethif_cfg.ifTypeSel = CEDI_IFSP_10M_MII; - } - else if ((config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_MII_100) || - (config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RMII_100) || - (config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RGMII_100)) - { - cy_ethif_cfg.ifTypeSel = CEDI_IFSP_100M_MII; - } - else if ((config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_GMII_1000) || - (config->pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RGMII_1000)) - { - cy_ethif_cfg.ifTypeSel = CEDI_IFSP_1000M_GMII; - } - - /*=================================================================================================*/ - /* CTL.ETH_MODE | Network_config[0] | Network_config[10] | PHY mode */ - /* | (speed) | (gigabit_mode_enable) | */ - /*=================================================================================================*/ - /* 2'd0 | 0 | 0 | MII - 10Mbps */ - /* 2'd0 | 1 | 0 | MII - 100Mbps */ - /* 2'd1 | 0 | 1 | GMII - 1000Mbps */ - /* 2'd2 | 0 | 0 | RGMII - 10Mbps (4bits/Cycle) */ - /* 2'd2 | 1 | 0 | RGMII - 100Mbps (4bits/Cycle) */ - /* 2'd2 | 0 | 1 | RGMII - 1000Mbps (8bits/Cycle) */ - /* 2'd3 | 0 | 0 | RMII - 10Mbps */ - /* 2'd3 | 1 | 0 | RMII - 100Mbps */ - /*=================================================================================================*/ - - /* Prepare DMA Config register */ - cy_ethif_cfg.dmaAddrBusWidth = 0; /* bit30 dma_addr_bus_width_1 */ - /* 0:32bit 1:64bit */ - cy_ethif_cfg.enTxExtBD = CY_ETH_DEFINE_BD; /* bit29 tx_bd_extended_mode_en */ - cy_ethif_cfg.enRxExtBD = CY_ETH_DEFINE_BD; /* bit28 rx_bd_extended_mode_en */ - cy_ethif_cfg.dmaCfgFlags = config->u8dmaCfgFlags; /* bit26 force_max_amba_burst_tx */ - /* bit25 force_max_amba_burst_rx */ - /* bit24 force_discard_on_err */ - for (u8QueueCounter=0; u8QueueCounter> 6; /* bit23:16 rx_buf_size */ - } - - cy_ethif_cfg.txPktBufSize = CY_ETH_TX_PBUF_SIZE; /* bit10 tx_pbuf_size */ - cy_ethif_cfg.rxPktBufSize = CY_ETH_RX_PBUF_SIZE; /* bit9:8 rx_pbuf_size */ - cy_ethif_cfg.dmaEndianism = 0; /* bit7 endian_swap_packet */ - /* 0: little endian mode */ - /* 1: endian swap mode enable for packet data (CEDI_END_SWAP_DATA) */ - /* bit6 endian_swap_management */ - /* 0: little endian mode */ - /* 1: endian swap mode enable for management descriptor (CEDI_END_SWAP_DESC) */ - cy_ethif_cfg.dmaDataBurstLen = config->dmaDataBurstLen; /* bit4:0 amba_burst_length */ - /* 1xxxx: attempt use burst up to 16 (CEDI_DMA_DBUR_LEN_16) */ - /* 01xxx: attempt use burst up to 8 (CEDI_DMA_DBUR_LEN_8) */ - /* 001xx: attempt use burst up to 4 (CEDI_DMA_DBUR_LEN_4) */ - /* 0001x: always use single burst */ - /* 00001: always use single burst (CEDI_AMBD_BURST_LEN_1) */ - /* 00000: best AXI burst up to 256 beats */ - - /* Prepare ddr and upper_rx_q_base_addr register (0x4c8, 0x4D4) */ - cy_ethif_cfg.upper32BuffTxQAddr = 0; /* bit31:0 not used */ - cy_ethif_cfg.upper32BuffRxQAddr = 0; /* bit31:0 not used */ - - /* axi_max_ */ - cy_ethif_cfg.aw2wMaxPipeline = config->u8aw2wMaxPipeline; /* bit15:8 aw2w_max_pipeline */ - cy_ethif_cfg.ar2rMaxPipeline = config->u8ar2rMaxPipeline; /* bit 7:0 ar2r_max_pipeline */ -} - - -/******************************************************************************* -* Function Name: Cy_ETHIF_WrapperConfig -****************************************************************************//** -* -* \brief Function initializes Ethernet Wrapper to configure Interface mode, reference clock/divider etc -* -* \param u8EthIfInstance Ethernet Instance -* \param pstcInterruptList pointer to structure list -* -*******************************************************************************/ -static cy_en_ethif_status_t Cy_ETHIF_WrapperConfig( cy_stc_ethif_wrapper_config_t * pstcWrapperConfig ) -{ - uint32_t mode=0; - - if (pstcWrapperConfig->stcInterfaceSel > CY_ETHIF_CTL_RMII_100) - { - return CY_ETHIF_BAD_PARAM; - } - - if ((pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_MII_10) || - (pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_MII_100)) - { - mode = 0; - } - else if (pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_GMII_1000) - { - mode = 1; - } - else if ((pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RGMII_10) || - (pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RGMII_100) || - (pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RGMII_1000)) - { - mode = 2; - } - else if ((pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RMII_10) || - (pstcWrapperConfig->stcInterfaceSel == CY_ETHIF_CTL_RMII_100)) - { - mode = 3; - } - - ETH_CTL = (ETH_CTL & (uint32_t)~(ETH_CTL_ETH_MODE_Msk | - ETH_CTL_REFCLK_SRC_SEL_Msk | - ETH_CTL_REFCLK_DIV_Msk)) | - _VAL2FLD(ETH_CTL_ETH_MODE,mode) | - _VAL2FLD(ETH_CTL_REFCLK_SRC_SEL, pstcWrapperConfig->bRefClockSource) | - _VAL2FLD(ETH_CTL_REFCLK_DIV, (pstcWrapperConfig->u8RefClkDiv - 1)); - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_IPEnable -****************************************************************************//** -* -* \brief Function enables Ethernet MAC -* -* \param -* -*******************************************************************************/ -static void Cy_ETHIF_IPEnable(void) -{ - ETH_CTL |=_VAL2FLD(ETH_CTL_ENABLED, CY_ETH_ENABLE_1); -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_IPDisable -****************************************************************************//** -* -* \brief Function Disables Ethernet MAC -* -* \param -* -*******************************************************************************/ -static void Cy_ETHIF_IPDisable(void) -{ - ETH_CTL &= (uint32_t)~(ETH_CTL_ENABLED_Msk); -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_AssignMemory -****************************************************************************//** -* -* \brief Local function is used to initialize private data structure, tx and rx queue start address -* -* \param -* -*******************************************************************************/ -static void Cy_ETHIF_AssignMemory(void) -{ - cyp_ethif_pd = (CEDI_PrivateData *)cy_ethif_privatedata; - cy_ethif_cfg.rxQAddr = (uintptr_t)cy_ethif_rx_desc_list; - cy_ethif_cfg.txQAddr = (uintptr_t)cy_ethif_tx_desc_list; - cyp_ethif_statistic = (CEDI_Statistics *)cy_ethif_statistic; - cy_ethif_cfg.statsRegs = (uintptr_t)cyp_ethif_statistic; - /** get the physical address */ - cy_ethif_cfg.rxQPhyAddr = cy_ethif_cfg.rxQAddr; - /** get the physical address */ - cy_ethif_cfg.txQPhyAddr = cy_ethif_cfg.txQAddr; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_DisableQueues -****************************************************************************//** -* \brief By default all activated queues in the IP are enabled. However, only required -* queues for tx and rx shall be enabled to make internal process faster. -* -* \brief Function Disables Ethernet MAC -* -* \param u8EthIfInstance Ethernet Instance -* -*******************************************************************************/ -static cy_en_ethif_status_t Cy_ETHIF_DisableQueues (cy_stc_ethif_config_t * pstcEthIfConfig) -{ - uint8_t u8TxQueueCounter = 0; - uint8_t u8RxQueueCounter = 0; - - /* Transmit Queue 0 */ - if (pstcEthIfConfig->btxq0enable == false) - { - /* Disable the queue pointer */ - ETH_TX_Q_PTR = (ETH_TX_Q_PTR&(uint32_t)~(ETH_TRANSMIT_Q_PTR_DMA_TX_DIS_Q_Msk)) | _VAL2FLD(ETH_TRANSMIT_Q_PTR_DMA_TX_DIS_Q, 1UL); - stcQueueDisStatus.bTxQueueDisable[0] = true; - } - else - u8TxQueueCounter++; - - /* Transmit Queue 1 */ - if (pstcEthIfConfig->btxq1enable == false) - { - /* Disable the queue pointer */ - ETH_TX_Q1_PTR = (ETH_TX_Q1_PTR&(uint32_t)~(ETH_TRANSMIT_Q1_PTR_DMA_TX_DIS_Q_Msk)) | _VAL2FLD(ETH_TRANSMIT_Q1_PTR_DMA_TX_DIS_Q, 1UL); - stcQueueDisStatus.bTxQueueDisable[1] = true; - } - else - u8TxQueueCounter++; - - /* Transmit Queue 2 */ - if (pstcEthIfConfig->btxq2enable == false) - { - /* Disable the queue pointer */ - ETH_TX_Q2_PTR = (ETH_TX_Q2_PTR&(uint32_t)~(ETH_TRANSMIT_Q2_PTR_DMA_TX_DIS_Q_Msk)) | _VAL2FLD(ETH_TRANSMIT_Q2_PTR_DMA_TX_DIS_Q, 1UL); - stcQueueDisStatus.bTxQueueDisable[2] = true; - } - else - u8TxQueueCounter++; - - /* Receive Queue 0 */ - if (pstcEthIfConfig->brxq0enable == false) - { - /* Disable the queue pointer */ - ETH_RX_Q_PTR = (ETH_RX_Q_PTR&(uint32_t)~(ETH_RECEIVE_Q_PTR_DMA_RX_DIS_Q_Msk)) | _VAL2FLD(ETH_RECEIVE_Q_PTR_DMA_RX_DIS_Q, 1UL); - stcQueueDisStatus.bRxQueueDisable[0] = true; - } - else - u8RxQueueCounter++; - - /* Receive Queue 1 */ - if (pstcEthIfConfig->brxq1enable == false) - { - /* Disable the queue pointer */ - ETH_RX_Q1_PTR = (ETH_RX_Q1_PTR&(uint32_t)~(ETH_RECEIVE_Q1_PTR_DMA_RX_DIS_Q_Msk)) | _VAL2FLD(ETH_RECEIVE_Q1_PTR_DMA_RX_DIS_Q, 1UL); - stcQueueDisStatus.bRxQueueDisable[1] = true; - } - else - u8RxQueueCounter++; - - /* Receive Queue 2 */ - if (pstcEthIfConfig->brxq2enable == false) - { - /* Disable the queue pointer */ - ETH_RX_Q2_PTR = (ETH_RX_Q2_PTR&(uint32_t)~(ETH_RECEIVE_Q2_PTR_DMA_RX_DIS_Q_Msk)) | _VAL2FLD(ETH_RECEIVE_Q2_PTR_DMA_RX_DIS_Q, 1UL); - stcQueueDisStatus.bRxQueueDisable[2] = true; - } - else - u8RxQueueCounter++; - - /* TODO: Temporarily in the driver. MUST be removed once IP is updated || Q3 for both Transmit and Receive has been removed from the IP - Changes will apply to bitfile after 0513 release */ - - /* TODO: Idea of cross checking BD memory vs enabled queues */ - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_TSUInit -****************************************************************************//** -* -* \brief Function enables Time stamp unit in EMAC -* -* \param pstcTSUConfig Pointer to TSU parameters -* -* \return -* -*******************************************************************************/ -static cy_en_ethif_status_t Cy_ETHIF_TSUInit (cy_stc_ethif_tsu_config_t * pstcTSUConfig) -{ - /* set 1588 timer value */ - /* Load Timer Value */ - if (EOK != cyp_ethif_gemgxlobj->set1588Timer((void *)cyp_ethif_pd, pstcTSUConfig->pstcTimerValue)) - { - /* Reason could be Null pointer, hardware does not support TSU or pstcTimerValue.nanosecs>0x3FFFFFFF */ - return CY_ETHIF_BAD_PARAM; - } - - /* Timer increment register to achieve 1 second as precise as possible */ - if (EOK != cyp_ethif_gemgxlobj->set1588TimerInc((void *)cyp_ethif_pd, pstcTSUConfig->pstcTimerIncValue)) - { - /* Reason could be Null pointer, hardware does not support TSU */ - return CY_ETHIF_BAD_PARAM; - } - - /* one step sync enabled */ - if (EOK != cyp_ethif_gemgxlobj->set1588OneStepTxSyncEnable((void *)cyp_ethif_pd, (uint8_t) pstcTSUConfig->bOneStepTxSyncEnable)) - { - /* Reason could be Null pointer, hardware does not support TSU or bOneStepTxSyncEnable > 1 */ - return CY_ETHIF_BAD_PARAM; - } - - /* Set the descriptor time stamp Mode */ - if (EOK != cyp_ethif_gemgxlobj->setDescTimeStampMode((void *)cyp_ethif_pd, - pstcTSUConfig->enTxDescStoreTimeStamp, pstcTSUConfig->enRxDescStoreTimeStamp)) - { - /** Reason could be Null pointer, hardware does not support TSU, enTxDescStoreTimeStamp > CEDI_TX_TS_ALL, enRxDescStoreTimeStamp > CEDI_RX_TS_ALL */ - return CY_ETHIF_BAD_PARAM; - } - - /* disabled storing nanosecond in CRC field of received frame */ - if (EOK != cyp_ethif_gemgxlobj->setStoreRxTimeStamp((void *)cyp_ethif_pd, (uint8_t) pstcTSUConfig->bStoreNSinRxDesc)) - { - /* Reason could be Null pointer, hardware does not support TSU or bStoreNSinRxDesc > 1 */ - return CY_ETHIF_BAD_PARAM; - } - - return CY_ETHIF_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_InitializeBuffers -****************************************************************************//** -* -* \brief Function initializes the buffer status and clears the memory with -* CY_EHTIF_EMPTYVALUE value. -* -* \param none -* -*******************************************************************************/ -static void Cy_ETHIF_InitializeBuffers (void) -{ - uint8_t u8tmpcounter; - - // Clear all TX buffers - for (u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_TX_BUF; u8tmpcounter++) - { - cy_ethif_txBufStatus[u8tmpcounter].cy_ethif_bufaddr.vAddr = (uintptr_t) &u8TxBuf[u8tmpcounter][0]; - cy_ethif_txBufStatus[u8tmpcounter].cy_ethif_bufaddr.pAddr = (uintptr_t) &u8TxBuf[u8tmpcounter][0]; - cy_ethif_txBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_FREE; - - // Load Buffer with dummy values - Cy_ETHIF_ClearBuffer((uint32_t*)&u8TxBuf[u8tmpcounter][0]); - } - - // Clear all RX buffers - for (u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_RX_BUF; u8tmpcounter++) - { - cy_ethif_rxBufStatus[u8tmpcounter].cy_ethif_bufaddr.vAddr = (uintptr_t) &u8RxBuf[u8tmpcounter][0]; - cy_ethif_rxBufStatus[u8tmpcounter].cy_ethif_bufaddr.pAddr = (uintptr_t) &u8RxBuf[u8tmpcounter][0]; - cy_ethif_rxBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_FREE; - - // Load Buffer with dummy values - Cy_ETHIF_ClearBuffer((uint32_t*)&u8RxBuf[u8tmpcounter][0]); - } -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_ClearBuffer -****************************************************************************//** -* -* \brief Initializes buffer with the CY_EHTIF_EMPTYVALUE value -* -* \param pu32Buffer start address for the buffer -* -*******************************************************************************/ -static void Cy_ETHIF_ClearBuffer (uint32_t * pu32Buffer) -{ - for (uint16_t u16tmpcounter = 0; u16tmpcounter < (CY_ETH_SIZE_MAX_FRAME/4); u16tmpcounter++) - { - /* Load Buffer with dummy values */ - pu32Buffer[u16tmpcounter] = CY_EHTIF_EMPTYVALUE; - } -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_GetBuf -****************************************************************************//** -* -* \brief returns the free buffer number which driver can start working with. -* -* \param bTransmitBuf To identify which pool caller wants to find free Buffer from -* -* \return u8invalid CY_ETHIF_NO_BUFFER_AVAILABLE when no buffer is free -* u8tmpcounter counter value loaded with the free buffer instance -* -*******************************************************************************/ -static uint8_t Cy_ETHIF_GetBuf (bool bTransmitBuf) -{ - uint8_t u8invalid = CY_ETHIF_NO_BUFFER_AVAILABLE; - static uint8_t u8TxBufferPtr = 0; - static uint8_t u8RxBufferPtr = 0; - - if (bTransmitBuf) - { - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_TX_BUF; u8tmpcounter++) - { - if (cy_ethif_txBufStatus[(u8TxBufferPtr + u8tmpcounter)].enBufStatus == CY_ETHIF_BUFFER_FREE) - { - u8tmpcounter = u8TxBufferPtr; - - u8TxBufferPtr++; - if (u8TxBufferPtr >= CY_ETH_TOTAL_TX_BUF) - u8TxBufferPtr = 0; - - return u8tmpcounter; - } - - u8TxBufferPtr++; - if (u8TxBufferPtr >= CY_ETH_TOTAL_TX_BUF) - u8TxBufferPtr = 0; - } - } - else - { - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_RX_BUF; u8tmpcounter++) - { - if (cy_ethif_rxBufStatus[(u8RxBufferPtr + u8tmpcounter)].enBufStatus == CY_ETHIF_BUFFER_FREE) - { - u8tmpcounter = u8RxBufferPtr; - - u8RxBufferPtr++; - if (u8RxBufferPtr >= CY_ETH_TOTAL_RX_BUF) - u8RxBufferPtr = 0; - - return u8tmpcounter; - } - - u8RxBufferPtr++; - if (u8RxBufferPtr >= CY_ETH_TOTAL_RX_BUF) - u8RxBufferPtr = 0; - } - } - - return u8invalid; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventTx -****************************************************************************//** -* -* \brief Function called by cadence driver upon getting Tx Event -* -* \param pcy_privatedata Instance specific private data -* \param u32event occurred event -* \param u8qnum Queue number -* -*******************************************************************************/ -static void Cy_ETHIF_EventTx(void *pcy_privatedata, uint32_t u32event, uint8_t u8qnum) -{ - CEDI_TxDescData Tx_DescData; - - if ((u32event&CEDI_EV_TX_COMPLETE) != 0) - { - cyp_ethif_gemgxlobj->freeTxDesc((void *)cyp_ethif_pd, u8qnum, &Tx_DescData); - - /* application callback function */ - if (stccallbackfunctions.txcompletecb != NULL) - { - stccallbackfunctions.txcompletecb(u8qnum); - } - - /* Release the buffer */ - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_TX_BUF; u8tmpcounter++) - { - if ((uint32_t*)Tx_DescData.bufAdd.pAddr == (uint32_t*)cy_ethif_txBufStatus[u8tmpcounter].cy_ethif_bufaddr.pAddr) - { - /* Release the buffer */ - cy_ethif_txBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_RELEASED; - break; - } - } - } - - return; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventTxError -****************************************************************************//** -* -* \brief Function called by cadence driver upon getting Tx Error Event -* -* \param pcy_privatedata Instance specific private data -* \param u32event occurred event -* \param u8qnum Queue number -* -*******************************************************************************/ -static void Cy_ETHIF_EventTxError(void *pcy_privatedata, uint32_t u32event, uint8_t u8qnum) -{ - CEDI_TxDescData Tx_DescData; - - cyp_ethif_gemgxlobj->freeTxDesc((void *)cyp_ethif_pd, u8qnum, &Tx_DescData); - - /** application callback function */ - if (stccallbackfunctions.txerrorcb != NULL) - { - stccallbackfunctions.txerrorcb(u8qnum); - } - - /* Release the buffer */ - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_TX_BUF; u8tmpcounter++) - { - if ((uint32_t*)Tx_DescData.bufAdd.pAddr == (uint32_t*)cy_ethif_txBufStatus[u8tmpcounter].cy_ethif_bufaddr.pAddr) - { - cy_ethif_txBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_RELEASED; - break; - } - } - - return; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventRxFrame -****************************************************************************//** -* -* \brief Function called by cadence driver upon getting Rx Event -* -* \param pcy_privatedata Instance specific private data -* \param u8qnum Queue number -* -*******************************************************************************/ -static void Cy_ETHIF_EventRxFrame(void *pcy_privatedata, uint8_t u8qnum) -{ - uint32_t u32Result; - uint32_t u32RxNum; - // uint32_t u32RxStatus = 0; - CEDI_BuffAddr TmpBufAddr; - CEDI_RxDescData Rx_DescData; - CEDI_RxDescStat Rx_DescStat; - bool bReceiveBuffer = false; /* Value must be false for Receive buffers */ - uint8_t u8BufferIndex = 255; - bool bClearAll = false; - - /* number of used buffers */ - u32RxNum = cyp_ethif_gemgxlobj->numRxUsed((void *)cyp_ethif_pd, u8qnum); - - /** read receive queue */ - while (u32RxNum!=0) - { - /* Get the new Buffer to replace the used one */ - u8BufferIndex = Cy_ETHIF_GetBuf(bReceiveBuffer); - if (CY_ETHIF_NO_BUFFER_AVAILABLE == u8BufferIndex) - { - /* check for first released buffer */ - u8BufferIndex = Cy_ETHIF_ClearReleasedBuf(bClearAll, bReceiveBuffer); - if (CY_ETHIF_NO_BUFFER_AVAILABLE == u8BufferIndex) - { - return; // No buffer available - } - } - - TmpBufAddr.vAddr = cy_ethif_rxBufStatus[u8BufferIndex].cy_ethif_bufaddr.vAddr; - TmpBufAddr.pAddr = cy_ethif_rxBufStatus[u8BufferIndex].cy_ethif_bufaddr.pAddr; - - u32Result = cyp_ethif_gemgxlobj->readRxBuf((void *)cyp_ethif_pd, - u8qnum, - &TmpBufAddr, - CY_ETHIF_BUFFER_CLEARED_0, - &Rx_DescData); - if (u32Result != 0) - { - // debug_printf("[ETH] NG4 (0x%08x)\r\n", u32Result); - } - else - { - /* change buffer status to OCCUPIED */ - cy_ethif_rxBufStatus[u8BufferIndex].enBufStatus = CY_ETHIF_BUFFER_OCCUPIED; - } - - switch (Rx_DescData.status) - { - case CEDI_RXDATA_SOF_EOF: // 0 - /* receive start and end frame */ - cyp_ethif_gemgxlobj->getRxDescStat((void *)cyp_ethif_pd, - Rx_DescData.rxDescStat, - &Rx_DescStat); - - /* application callback function */ - if (stccallbackfunctions.rxframecb != NULL) - { - stccallbackfunctions.rxframecb((uint8_t*)TmpBufAddr.pAddr, Rx_DescStat.bufLen); - } - - /* Release the buffer */ - for (uint8_t u8tmpcounter = 0; u8tmpcounter < CY_ETH_TOTAL_RX_BUF; u8tmpcounter++) - { - if ((uint32_t*)TmpBufAddr.pAddr == (uint32_t*)cy_ethif_rxBufStatus[u8tmpcounter].cy_ethif_bufaddr.pAddr) - { - cy_ethif_rxBufStatus[u8tmpcounter].enBufStatus = CY_ETHIF_BUFFER_RELEASED; - break; - } - } - break; - case CEDI_RXDATA_SOF_ONLY: // 1 - /* fragment start */ - // debug_printf("[ETH] (SOF)Don't use fragment yet...\r\n"); - break; //return; - case CEDI_RXDATA_NO_FLAG: // 2 - /* fragment */ - // debug_printf("[ETH] (NOF)Don't use fragment yet...\r\n"); - break; //return; - case CEDI_RXDATA_EOF_ONLY: // 3 - /* fragment end */ - // debug_printf("[ETH] (EOF)Don't use fragment yet...\r\n"); - break; - case CEDI_RXDATA_NODATA: // 4 - /* normal leaving */ - // debug_printf("[ETH] NG5 RXDATA_NODATA\r\n"); - return; /* from here it breaks while loop */ - default: - /* Unknown status */ - break; - } - u32RxNum--; - } -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventRxError -****************************************************************************//** -* -* \brief Function called by cadence driver upon getting Rx Error Event -* -* \param pcy_privatedata Instance specific private data -* \param u32event occurred event -* \param u8qnum Queue number -* -*******************************************************************************/ -static void Cy_ETHIF_EventRxError(void *pcy_privatedata, uint32_t a_event, uint8_t a_qnum) -{ - //printf("[ETH] (Event) RxError received.\r\n"); - return; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventPhyManComplete -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventPhyManComplete(void *pcy_privatedata, uint8_t u8read, uint16_t u16ReadData) -{ - // uint32_t u32temp; - // uint32_t u32addr; - - // u32temp = *((volatile uint32_t*)0xXXXX); - // u32addr = (u32temp & 0x007C0000) >> 18; - - // debug_printf("[ETH] (Event) PhyManComplete.\r\n"); - // debug_printf("[ETH] w/r=%d, addr=0x%02x, data=0x%04x\r\n", (uint32_t)u8read, addr, (uint32_t)u16ReadData); - - return; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventhrespError -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventhrespError(void *pcy_privatedata, uint8_t u8qnum) -{ - // debug_printf("[ETH] (Event) hrespError received.\r\n"); - // debug_printf("[ETH] queue num=%d\r\n", u8qnum); - - return; -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventLpPageRx -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventLpPageRx(void* pcy_privatedata, struct CEDI_LpPageRx* pageRx) -{ - // debug_printf("Reports PCS auto-negotiation page received"); -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventAn -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventAn(void* pcy_privatedata, struct CEDI_NetAnStatus* netStat) -{ - // debug_printf("Auto Negotiation Event"); -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventLinkChange -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventLinkChange(void *pcy_privatedata, uint8_t a_linkstate) -{ - // debug_printf("[ETH] (Event) linkChange received.\r\n"); - // debug_printf("[ETH] link state=%d\r\n", a_linkstate); - - return; -} -/******************************************************************************* -* Function Name: Cy_ETHIF_EventTsu -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventTsu (void *pcy_privatedata, uint32_t u32event) -{ - /** Event generated if second count of the timer has incremented */ - if (u32event & CEDI_EV_TSU_SEC_INC) - { - /** application callback function */ - if (stccallbackfunctions.tsuSecondInccb != NULL) - { - stccallbackfunctions.tsuSecondInccb(); - } - } - - /** Timer count matched event */ - if (u32event & CEDI_EV_TSU_TIME_MATCH) - { - - } -} -/******************************************************************************* -* Function Name: Cy_ETHIF_EventPauseFrame -****************************************************************************//** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventPauseFrame(void *pcy_privatedata, uint32_t u32event) -{ - if (u32event & CEDI_EV_PAUSE_FRAME_TX) - { - // debug_printf("Pause frame transmitted"); - } - - if (u32event & CEDI_EV_PAUSE_NZ_QU_RX) - { - // debug_printf("Pause frame received"); - } -} -/******************************************************************************* -* Function Name: Cy_ETHIF_EventPtp -******************************************************************************** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventPtp (void* pcy_privatedata, uint32_t u32type, struct CEDI_1588TimerVal* time) -{ - if (u32type & CEDI_EV_PTP_TX_SYNC) - { - // printf("Sync frame transmitted"); - } - - if (u32type & CEDI_EV_PTP_TX_PDLY_REQ) - { - // printf("PTP PDelay Req frame transmitted"); - } - - if (u32type & CEDI_EV_PTP_TX_PDLY_RSP) - { - // printf("PTP PDelay Resp frame transmitted"); - } - - if (u32type & CEDI_EV_PTP_RX_SYNC) - { - // printf("Sync frame received"); - } - - if (u32type & CEDI_EV_PTP_RX_PDLY_REQ) - { - // printf("PTP PDelay Req frame received"); - } - - if (u32type & CEDI_EV_PTP_RX_PDLY_RSP) - { - // printf("PTP PDelay Resp frame received"); - } -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventExternalInt -******************************************************************************** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventExternalInt(void * pcy_privatedata) -{ - // debug_printf("External Event Occurred"); -} - -/******************************************************************************* -* Function Name: Cy_ETHIF_EventWol -******************************************************************************** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventWol(void * pcy_privatedata) -{ - // debug_printf("Wake On LAN Event Occurred"); -} -/******************************************************************************* -* Function Name: Cy_ETHIF_EventLpi -******************************************************************************** -* -* \brief -* -* \param -* -* -*******************************************************************************/ -static void Cy_ETHIF_EventLpi(void * pcy_privatedata) -{ - // debug_printf("LPI Status changed Event"); -} - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXETH */ -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_i3c.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_i3c.c deleted file mode 100644 index cfd76f8adf..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_i3c.c +++ /dev/null @@ -1,5738 +0,0 @@ -/***************************************************************************//** -* \file cy_i3c.c -* \version 1.00 -* -* Provides API implementation for the I3C Controller. -* -******************************************************************************** -* \copyright -* Copyright 2019-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXI3C) - -#include "cy_i3c.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* -* Function Prototypes -*******************************************************************************/ -static uint8_t even_parity(uint8_t address); -static uint32_t ffs(uint32_t value); -static void SetAddrslotStatus(uint8_t address, cy_en_i3c_addr_slot_status_t status, cy_stc_i3c_context_t *context); -static void InitAddrslots(cy_stc_i3c_context_t *context); -static void DeInitAddrslots(cy_stc_i3c_context_t *context); -static uint32_t GetI2CDevAddrPos(I3C_CORE_Type *base, uint8_t staticAddress, cy_stc_i3c_context_t *context); -static uint32_t GetI3CDevAddrPos(I3C_CORE_Type *base, uint8_t dynamicAddress, cy_stc_i3c_context_t *context); -static uint32_t GetDATFreePos(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static cy_en_i3c_addr_slot_status_t GetAaddrslotStatus(uint8_t address, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t ResponseError(uint32_t respCmd); -static uint32_t ResponseErrorEvent(uint32_t respCmd); -static void WriteArray(I3C_CORE_Type *base, void *buffer, uint32_t size); -static void ReadArray(I3C_CORE_Type *base, void *buffer, uint32_t size); -static void MasterHandleDataTransmit(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static void MasterHandleDataReceive(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static void RetrieveI3CDeviceInfo(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, bool basicInfo, cy_stc_i3c_context_t *context); -static void CCC_Set(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static void CCC_Get(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t enec_disec_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t rstdaa_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t setmrwl_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static void setda_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t setdasa_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t setnewda_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t entas_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t enthdr0_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getmrwl_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getpid_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getbcr_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getdcr_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getstatus_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getmxds_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t gethdrcap_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t getaccmst_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t defslvs_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t MasterHDRWrite(I3C_CORE_Type *base, cy_stc_i3c_hdr_cmd_t *hdrCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t MasterHDRRead(I3C_CORE_Type *base, cy_stc_i3c_hdr_cmd_t *hdrCmd, cy_stc_i3c_context_t *context); -static void MasterRespReadyStsHandle(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static void MasterHandleWriteInterrupt(I3C_CORE_Type *base, uint32_t respCmdPort, cy_stc_i3c_context_t *context); -static void MasterHandleReadInterrupt(I3C_CORE_Type *base, uint32_t respCmdPort, cy_stc_i3c_context_t *context); -static void MasterHandleIBIInterrupt(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t RearrangeAddrTable(I3C_CORE_Type *base, uint32_t devIndex, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t DeviceIBIControl(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, uint8_t cccCmd, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t CCCSlaveAddressValidation(uint8_t address, bool unicastOnly, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t MasterHandleCCCResponse(I3C_CORE_Type *base, uint32_t *resp, cy_stc_i3c_context_t *context); -static void SlaveRespReadyStsHandle(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static void SlaveHandleDataReceive(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static void SlaveHandleDataTransmit(I3C_CORE_Type *base, cy_stc_i3c_context_t *context); -static cy_en_i3c_status_t SecondaryMasterInit(I3C_CORE_Type *base, bool isMaster, cy_stc_i3c_context_t *context); - -/******************************************************************************* -* Function Name: Cy_I3C_Init -****************************************************************************//** -* -* Initializes the I3C block. -* -* \param base -* The pointer to the I3C instance. -* -* \param config -* The pointer to the configuration structure \ref cy_stc_i3c_config_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -* \note -* Ensure that the I3C block is disabled before calling this function. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_Init(I3C_CORE_Type *base, cy_stc_i3c_config_t const *config, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == config) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - CY_ASSERT_L3(CY_I3C_IS_MODE_VALID(config->i3cMode)); - CY_ASSERT_L3(CY_I3C_IS_BUS_MODE_VALID(config->i3cBusMode)); - - /* Main master init */ - I3C->CTRL= I3C_CTRL_ENABLED_Msk; //Outside core register - - if(CY_I3C_MASTER == config->i3cMode) - { - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint8_t address; - cy_en_i3c_status_t retStatus; - - i3cMaster->freePos = 0x7FFUL; - i3cMaster->lastAddress = 0; - i3cMaster->devCount = 0; - i3cMaster->i2cDeviceCount = 0; - i3cMaster->dynAddrDevCount = 0; - - // Prepare the address slot status array - InitAddrslots(context); - - //Assigning address to the master - retStatus = Cy_I3C_MasterGetFreeDeviceAddress(base, &address, context); - if(CY_I3C_MASTER_FREE_ADDR_UNAVIAL == retStatus) - return retStatus; - - I3C_CORE_DEVICE_ADDR(base) = _VAL2FLD( I3C_CORE_DEVICE_ADDR_DYNAMIC_ADDR, address) | I3C_CORE_DEVICE_ADDR_DYNAMIC_ADDR_VALID_Msk; - - SetAddrslotStatus(address, CY_I3C_ADDR_SLOT_I3C_DEV, context); - - i3cMaster->lastAddress = address; - I3C_CORE_DEVICE_CTRL(base) = I3C_CORE_DEVICE_CTRL_IBA_INCLUDE_Msk; - //Setting the device operation mode to Master - I3C_CORE_DEVICE_CTRL_EXTENDED(base) = _VAL2FLD(I3C_CORE_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE, 0); - - Cy_I3C_SetDataRate(base, config->i3cSclRate, config->i3cClockHz, context); - - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - - } - - if((config->i3cMode == CY_I3C_SLAVE) || (config->i3cMode == CY_I3C_SECONDARY_MASTER)) - { - if(config->staticAddress) - { - /* The reset value of these fields are set from strap input static_addr_en and statis_addr. - The application can overwrite this value by programming this register before enabling the controller */ - - I3C->STATIC_ADDR = I3C_STATIC_ADDR_STATIC_ADDR_EN_Msk; - - I3C_CORE_DEVICE_ADDR(base) |= _VAL2FLD(I3C_CORE_DEVICE_ADDR_STATIC_ADDR, config->staticAddress) | - I3C_CORE_DEVICE_ADDR_STATIC_ADDR_VALID_Msk; - } - - /* - 1. Configure the SLV_CHAR_CTRL register - 2. Configure the two PID registers - 3. Configure DEVICE_CTRL_EXTENDED register - 4. Configure ADAPTIVE_I2C_I3C field in DEVICE_CTRL register - */ - - I3C_CORE_SLV_CHAR_CTRL(base) &= _VAL2FLD(I3C_CORE_SLV_CHAR_CTRL_MAX_DATA_SPEED_LIMIT, config->speedLimit) | - _VAL2FLD(I3C_CORE_SLV_CHAR_CTRL_HDR_CAPABLE, config->hdrCapable) | - _VAL2FLD(I3C_CORE_SLV_CHAR_CTRL_DEVICE_ROLE, 0); - - I3C_CORE_DEVICE_CTRL_EXTENDED(base) = _VAL2FLD(I3C_CORE_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE, config->i3cMode); - - //I3C_CORE_SLV_PID_VALUE(base) = (uint32_t)config->pid; - - /* On setting this ADAPTIVE_I2C_I3C bit, the controller generates hot-join request only when the is in/changes to I3C mode of operation. */ - //I3C_CORE_DEVICE_CTRL(base) |= I3C_CORE_DEVICE_CTRL_ADAPTIVE_I2C_I3C_Msk; //tbd - ask about the idle count multiplier - - /* Note: - 1. If this bit is set, the controller is allowed to send hot-join request intr on the bus. This bit, if set, can be set or cleared by the I3C master - via ENEC or DISEC CCCs. - 2. If this bit is set to 0, the controller will not be allowed to send hot-join request intr on the bus. The CCCs will not have any effects on this field. - */ - - I3C_CORE_SLV_EVENT_STATUS(base) &= (config->hotjoinEnable)?I3C_CORE_SLV_EVENT_STATUS_HJ_EN_Msk:(~I3C_CORE_SLV_EVENT_STATUS_HJ_EN_Msk); - - //Sets the number of entries in the Receive FIFO that trigger the interrupt to 1 word - I3C_CORE_DATA_BUFFER_THLD_CTRL(base) &= _VAL2FLD(I3C_CORE_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD, 5) | - _VAL2FLD(I3C_CORE_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC, 1); - - if(config->i3cMode == CY_I3C_SECONDARY_MASTER) - { - Cy_I3C_SetInterruptMask(base, CY_I3C_SLV_INTR_Msk | CY_I3C_INTR_DEFSLV_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_SLV_INTR_Msk | CY_I3C_INTR_DEFSLV_STS); - } - - else - { - Cy_I3C_SetInterruptMask(base, CY_I3C_SLV_INTR_Msk); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_SLV_INTR_Msk); - } - - context->i3cSclRate = config->i3cSclRate; - } - - // Configure the registers - - //Sets the number of entries in the Response Queue that trigger the interrupt to 1 word - //and the number of entries in the IBI Queue that trigger the interrupt to 1 word - - I3C_CORE_QUEUE_THLD_CTRL(base) = _VAL2FLD(I3C_CORE_QUEUE_THLD_CTRL_RESP_BUF_THLD, 0) | - _VAL2FLD(I3C_CORE_QUEUE_THLD_CTRL_IBI_STATUS_THLD, 0); - - /* Initialize the context */ - context->i3cMode = config->i3cMode; - context->i3cBusMode = config->i3cBusMode; - context->i3cClockHz = config->i3cClockHz; - context->state = CY_I3C_IDLE; - - /* Master specific */ - context->masterBuffer = NULL; - context->masterStatus = 0UL; - context->masterBufferIdx = 0UL; - context->masterBufferSize = 0UL; - context->destDeviceAddr = 0UL; - context->hdrCmd = NULL; - - /*Slave specific */ - context->slaveStatus = 0UL; - - context->slaveRxBuffer = NULL; - context->slaveRxBufferIdx = 0UL; - context->slaveRxBufferSize = 0UL; - context->slaveRxBufferCnt = 0UL; - - context->slaveTxBuffer = NULL; - context->slaveTxBufferIdx = 0UL; - context->slaveTxBufferSize = 0UL; - context->slaveTxBufferCnt = 0UL; - - /* Unregister callbacks */ - context->cbEvents = NULL; - context->cbIbi = NULL; - - return CY_I3C_SUCCESS; - -} - - -/******************************************************************************* -* Function Name: Cy_I3C_Deinit -****************************************************************************//** -* -* Deinitializes the I3C block. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_DeInit(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - uint8_t index; - - Cy_I3C_Disable(base); - if(CY_I3C_SLAVE != context->i3cMode) //Test: Should this be done for secondary master too? - { - //Set the address slot statuses to zero - DeInitAddrslots(context); - - for(index = 0; (index < CY_I3C_MAX_DEVS); index++) - { - //Clears the DAT entries - Cy_I3C_WriteIntoDeviceAddressTable(base, index, 0UL); - } - } - I3C_CORE_QUEUE_THLD_CTRL(base) = I3C_CORE_QUEUE_THLD_CTRL_DEF_VAL; - I3C_CORE_DATA_BUFFER_THLD_CTRL(base) = I3C_CORE_DATA_BUFFER_THLD_CTRL_DEF_VAL; - - I3C_CORE_INTR_STATUS_EN(base) = 0UL; - I3C_CORE_INTR_SIGNAL_EN(base) = 0UL; - -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterI2CAttachDevice -****************************************************************************//** -* -* Attaches an I2C device to the bus as defined by \ref cy_stc_i2c_device_t. -* It is required to provide device static address and lvr information -* in \ref cy_stc_i2c_device_t. -* -* \param base -* The pointer to the I3C instance. -* -* \param i2cDevice -* The pointer to the I2C device description structure \ref cy_stc_i2c_device_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterAttachI2CDevice(I3C_CORE_Type *base, cy_stc_i2c_device_t *i2cDevice, cy_stc_i3c_context_t *context) -{ - - if((NULL == base) || (NULL == i2cDevice) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint32_t value, pos; - uint8_t lvr; - - if(CY_I3C_MAX_DEVS <= (i3cMaster->devCount)) //cannot initialize the device as the bus already has 11 devices on it - return CY_I3C_MASTER_MAX_DEVS_PRESENT; - - /* LVR: Legacy Virtual Register - - bit[7-5]: 000 - Legacy I2C only with 50ns IO Spike Filter - 001 and 010 - Legacy I2C only without 50ns IO Spike Filter - others - reserved */ - - lvr = i2cDevice->lvr; - - if( CY_I3C_ADDR_SLOT_FREE != GetAaddrslotStatus(i2cDevice->staticAddress, context)) - return CY_I3C_MASTER_FREE_ADDR_UNAVIAL; - - if(0 != (CY_I3C_LVR_LEGACY_I2C_INDEX_MASK & lvr)) //does not have a 50ns Spike Filter, So return - BROS mentions not to support devices that lack the spike filters - return CY_I3C_MASTER_BAD_I2C_DEVICE; - - SetAddrslotStatus(i2cDevice->staticAddress, CY_I3C_ADDR_SLOT_I2C_DEV, context); - - // populate the device address table with the static address of the device - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR, i2cDevice->staticAddress) | - I3C_CORE_DEV_ADDR_TABLE_LOC1_LEGACY_I2C_DEVICE_Msk; - - pos = GetDATFreePos(base, context); - - Cy_I3C_WriteIntoDeviceAddressTable(base, pos, value); - - //Maintaining a local list of i2c devices - Cy_I3C_UpdateI2CDevInList(i2cDevice, pos, context); - - //increment the free position index of the device address table - (i3cMaster->freePos) = ~ (CY_I3C_BIT(pos)); - (i3cMaster->devCount)++; - (i3cMaster->i2cDeviceCount)++; - - I3C_CORE_DEVICE_CTRL(base) |= I3C_CORE_DEVICE_CTRL_I2C_SLAVE_PRESENT_Msk; - - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterDetachI2CDevice -****************************************************************************//** -* -* Detaches an I2C device from the bus defined by \ref cy_stc_i2c_device_t. -* -* \param base -* The pointer to the I3C instance. -* -* \param i2cDevice -* pointer to the I2C device description structure \ref cy_stc_i2c_device_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterDetachI2CDevice(I3C_CORE_Type *base, cy_stc_i2c_device_t *i2cDevice, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i2cDevice) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - uint32_t devIndex; - - //"devIndex" - Position of the device which has to be detached - devIndex = GetI2CDevAddrPos(base, i2cDevice->staticAddress, context); - if(devIndex == CY_I3C_BAD_PARAM) - return CY_I3C_BAD_PARAM; - - RearrangeAddrTable(base, devIndex, context); - - context->i3cMaster.devCount--; - context->i3cMaster.i2cDeviceCount--; - SetAddrslotStatus((i2cDevice->staticAddress), CY_I3C_ADDR_SLOT_FREE, context); - - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterI3CAttachDevice -****************************************************************************//** -* -* Attaches an I3C device to the bus defined by \ref cy_stc_i3c_device_t. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDevice -* The pointer to the i3c device description structure \ref cy_stc_i3c_device_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -/* This is blocking function, where we wait for the response packet, - assuming the master treats no response as NACK after waiting for a decent amount of time */ -cy_en_i3c_status_t Cy_I3C_MasterAttachI3CDevice(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i3cDevice) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - uint8_t dynamicAddress = 0; - cy_en_i3c_status_t retStatus; - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - cy_stc_i3c_ccc_cmd_t cmd; - cy_stc_i3c_ccc_setda_t i3cCccSetda; - cy_stc_i3c_ccc_payload_t payload; - - if(CY_I3C_MAX_DEVS <= (i3cMaster->devCount)) //cannot initialize the device as the bus already has 11 devices on it - return CY_I3C_MASTER_MAX_DEVS_PRESENT; - - if(0 != i3cDevice->dynamicAddress) - { - /* device has a expected dynamic address */ - - /* check if the expected dynamic address is available to be assigned */ - /* If not available, return */ - - if(CY_I3C_ADDR_SLOT_FREE != GetAaddrslotStatus(i3cDevice->dynamicAddress, context)) - return CY_I3C_MASTER_FREE_ADDR_UNAVIAL; - - dynamicAddress = i3cDevice->dynamicAddress; - } - - else - { - /* If the Slave device doesn't have a expected dynamic address, pick a free address from the list */ - retStatus = Cy_I3C_MasterGetFreeDeviceAddress(base, &dynamicAddress, context); - if(CY_I3C_MASTER_FREE_ADDR_UNAVIAL == retStatus) - return retStatus; - - i3cMaster->lastAddress = dynamicAddress; - } - - //Send SETDASA CCC command - i3cCccSetda.address = dynamicAddress; - cmd.data = &payload; - cmd.data->data = &(i3cCccSetda.address); //check - cmd.data->len = sizeof(i3cCccSetda); - cmd.cmd = CY_I3C_CCC_SETDASA; - cmd.address = i3cDevice->staticAddress; - retStatus = setdasa_ccc(base, &cmd, context); - - return retStatus; - -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterDetachI3CDevice -****************************************************************************//** -* -* Detaches an I3C device from the bus defined by \ref cy_stc_i3c_device_t. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDevice -* The pointer to the I3C device description structure \ref cy_stc_i3c_device_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -//TBD - Check if the device is hot-join capable, if yes send DISEC with HOT-JOIN event -cy_en_i3c_status_t Cy_I3C_MasterDetachI3CDevice(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i3cDevice) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - uint32_t devIndex ; - cy_en_i3c_status_t retstatus; - cy_stc_i3c_ccc_cmd_t cccCmd; - cy_stc_i3c_ccc_payload_t payload; - - devIndex = GetI3CDevAddrPos(base, i3cDevice->dynamicAddress, context); - if(CY_I3C_BAD_PARAM == devIndex) - return CY_I3C_BAD_PARAM; - - cccCmd.address = i3cDevice->dynamicAddress; - cccCmd.cmd = CY_I3C_CCC_RSTDAA(false); - cccCmd.data = &payload; - cccCmd.data->data = NULL; - cccCmd.data->len = 0; - - retstatus = rstdaa_ccc(base, &cccCmd, context); - if(CY_I3C_SUCCESS != retstatus) - return retstatus; - - RearrangeAddrTable(base, devIndex, context); - - context->i3cMaster.devCount--; - SetAddrslotStatus((i3cDevice->dynamicAddress), CY_I3C_ADDR_SLOT_FREE, context); - - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_Enable -****************************************************************************//** -* Enables the I3C block. -* -* \param base -* The pointer to the I3C instance. -* -*******************************************************************************/ -void Cy_I3C_Enable(I3C_CORE_Type *base) -{ - CY_ASSERT_L1(NULL != base); - - I3C_CORE_DEVICE_CTRL(base) |= I3C_CORE_DEVICE_CTRL_ENABLE_Msk; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_Disable -****************************************************************************//** -* Disables the I3C block. -* -* \param base -* The pointer to the I3C instance. -* -* \note -* The I3C controller will complete any pending bus transaction before it gets -* disabled. -*******************************************************************************/ -void Cy_I3C_Disable(I3C_CORE_Type *base) -{ - CY_ASSERT_L1(NULL != base); - - I3C_CORE_DEVICE_CTRL(base) |= (~I3C_CORE_DEVICE_CTRL_ENABLE_Msk); - - do - { - //Wait until the master comes to IDLE state - }while(I3C_CORE_PRESENT_STATE(base)); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_Resume -****************************************************************************//** -* -* Resumes the I3C Controller after an error state. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \note -* When the controller enters any error condition it pauses all operation until -* user resumes manually. User must call this API once error status is returned -* for any I3C bus transactions like Read/Write or other operations. -* -*******************************************************************************/ -void Cy_I3C_Resume(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - (void)context; - - //uint32_t status; - //status = Cy_I3C_GetBusStatus(base, context); -#if 0 - if(status & CY_I3C_MASTER_HALT_STATE) - { - I3C_CORE_DEVICE_CTRL(base) |= I3C_CORE_DEVICE_CTRL_RESUME_Msk; - } -#endif - - I3C_CORE_DEVICE_CTRL(base) |= I3C_CORE_DEVICE_CTRL_RESUME_Msk; - -} - - -/******************************************************************************* -* Function Name: Cy_I3C_GetI2CDeviceCount -****************************************************************************//** -* -* Provides the number of I2C devices attached to the bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Number of I2C devices attached to the bus. -* -*******************************************************************************/ -uint32_t Cy_I3C_GetI2CDeviceCount(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - /* Suppress a compiler warning about unused variables */ - (void) base; - - return (context->i3cMaster.i2cDeviceCount); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_GetI3CDeviceCount -****************************************************************************//** -* -* Provides the number of I3C devices attached to the bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Number of I3C devices attached to the bus. -* -*******************************************************************************/ -uint32_t Cy_I3C_GetI3CDeviceCount(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - /* Suppress a compiler warning about unused variables */ - (void) base; - - return ((context->i3cMaster.devCount)-(context->i3cMaster.i2cDeviceCount)); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterGetI2CDevices -****************************************************************************//** -* -* Provides the list of I2C devices on the bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param i2cDeviceList -* The pointer to the I2C device list array. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterGetI2CDevices(I3C_CORE_Type *base, cy_stc_i2c_device_t *i2cDeviceList, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i2cDeviceList) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint8_t index; - cy_stc_i3c_master_devlist_t *ptr = context->devList; - - for(index = 0; index < i3cMaster->i2cDeviceCount;) - { - if(ptr->i2c) - { - *i2cDeviceList = ptr->i2cDevice; - index++; - i2cDeviceList++; - } - ptr++; - } - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterGetI3CDevices -****************************************************************************//** -* -* Provides the list of I3C devices on the bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDeviceList -* The pointer to the I3C device list array. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterGetI3CDevices(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDeviceList, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i3cDeviceList) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint8_t index, count; - cy_stc_i3c_master_devlist_t *ptr = context->devList; - count = (i3cMaster->devCount) - (i3cMaster->i2cDeviceCount); - - for(index = 0; index < count;) - { - if(!ptr->i2c) - { - *i3cDeviceList = ptr->i3cDevice; - index++; - i3cDeviceList++; - } - ptr++; - } - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_GetFreeDeviceAddress -****************************************************************************//** -* -* Provides the next dynamic address available to be assigned. -* -* \param base -* The pointer to the I3C instance. -* -* \param address -* The pointer to the address. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterGetFreeDeviceAddress(I3C_CORE_Type *base, uint8_t *address, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == address) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - cy_en_i3c_addr_slot_status_t status; - uint8_t freeAddress; - uint8_t startAddress = (i3cMaster->lastAddress) + 1; - - for(freeAddress = startAddress; freeAddress < CY_I3C_MAX_ADDR; freeAddress++) - { - status = GetAaddrslotStatus(freeAddress, context); - if(CY_I3C_ADDR_SLOT_FREE == status) - { - *address = freeAddress; - return CY_I3C_SUCCESS; - } - } - - //case when a device is detached from the bus and the address is available - for(freeAddress = 1; freeAddress < startAddress; freeAddress++) - { - status = GetAaddrslotStatus(freeAddress, context); - if(CY_I3C_ADDR_SLOT_FREE == status) - { - *address = freeAddress; - return CY_I3C_SUCCESS; - } - } - - return CY_I3C_MASTER_FREE_ADDR_UNAVIAL; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_isCCCCmdSupported -****************************************************************************//** -* -* Checks if the CCC command is supported. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The CCC command to be checked. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ture: If the specified command is supported -* false: If the specified command is not supported. -* -*******************************************************************************/ -bool Cy_I3C_isCCCCmdSupported(I3C_CORE_Type *base, uint8_t cccCmd, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - /* Suppress a compiler warning about unused variables */ - (void) base; - - switch (cccCmd) - { - case CY_I3C_CCC_ENEC(true): - case CY_I3C_CCC_ENEC(false): - case CY_I3C_CCC_DISEC(true): - case CY_I3C_CCC_DISEC(false): - case CY_I3C_CCC_ENTAS(0, true): - case CY_I3C_CCC_ENTAS(0, false): - case CY_I3C_CCC_RSTDAA(true): - case CY_I3C_CCC_RSTDAA(false): - case CY_I3C_CCC_ENTDAA: - case CY_I3C_CCC_SETMWL(true): - case CY_I3C_CCC_SETMWL(false): - case CY_I3C_CCC_SETMRL(true): - case CY_I3C_CCC_SETMRL(false): - case CY_I3C_CCC_ENTHDR(0): - case CY_I3C_CCC_SETDASA: - case CY_I3C_CCC_SETNEWDA: - case CY_I3C_CCC_GETMWL: - case CY_I3C_CCC_GETMRL: - case CY_I3C_CCC_GETPID: - case CY_I3C_CCC_GETBCR: - case CY_I3C_CCC_GETDCR: - case CY_I3C_CCC_GETSTATUS: - case CY_I3C_CCC_GETMXDS: - case CY_I3C_CCC_GETHDRCAP: - case CY_I3C_CCC_GETACCMST: - case CY_I3C_CCC_DEFSLVS: - return true; - default: - return false; - } -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SendCCCCmd -****************************************************************************//** -* -* Post the specified CCC command to command queue. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the CCC command description structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_SendCCCCmd(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == cccCmd) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_en_i3c_status_t retStatus; - - context->masterStatus = CY_I3C_MASTER_BUSY; - switch(cccCmd->cmd) - { - case CY_I3C_CCC_ENEC(true): - case CY_I3C_CCC_ENEC(false): - case CY_I3C_CCC_DISEC(true): - case CY_I3C_CCC_DISEC(false): - { - retStatus = enec_disec_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_RSTDAA(true): - case CY_I3C_CCC_RSTDAA(false): - { - retStatus = rstdaa_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_SETMWL(true): - case CY_I3C_CCC_SETMWL(false): - case CY_I3C_CCC_SETMRL(true): - case CY_I3C_CCC_SETMRL(false): - { - retStatus = setmrwl_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_SETDASA: - { - retStatus = setdasa_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_SETNEWDA: - { - retStatus = setnewda_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETMWL: - case CY_I3C_CCC_GETMRL: - { - retStatus = getmrwl_ccc(base, cccCmd, context); - break; - } - - case CY_I3C_CCC_GETPID: - { - retStatus = getpid_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETBCR: - { - retStatus = getbcr_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETDCR: - { - retStatus = getdcr_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETSTATUS: - { - retStatus = getstatus_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETMXDS: - { - retStatus = getmxds_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETHDRCAP: - { - retStatus = gethdrcap_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_ENTAS(0, true): - case CY_I3C_CCC_ENTAS(0, false): - case CY_I3C_CCC_ENTAS(1, true): - case CY_I3C_CCC_ENTAS(1, false): - case CY_I3C_CCC_ENTAS(2, true): - case CY_I3C_CCC_ENTAS(2, false): - case CY_I3C_CCC_ENTAS(3, true): - case CY_I3C_CCC_ENTAS(3, false): - { - retStatus = entas_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_ENTHDR(0): - { - retStatus = enthdr0_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_GETACCMST: - { - retStatus = getaccmst_ccc(base, cccCmd, context); - break; - } - case CY_I3C_CCC_DEFSLVS: - { - retStatus = defslvs_ccc(base, cccCmd, context); - break; - } - default: - { - retStatus = CY_I3C_MASTER_CCC_NOT_SUPPORTED; - } - } - - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - return retStatus; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_DisableDeviceIbi -****************************************************************************//** -* -* Disables all IBI events from specified device. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDevice -* pointer to the i3c device description structure \ref cy_stc_i3c_device_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_DisableDeviceIbi(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i3cDevice) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_en_i3c_status_t retStatus; - - retStatus = DeviceIBIControl(base, i3cDevice, CY_I3C_CCC_DISEC(false), context); - - return retStatus; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_EnableDeviceIbi -****************************************************************************//** -* -* Enables all IBI events from specified device. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDevice -* pointer to the i3c device description structure \ref cy_stc_i3c_device_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_config_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_EnableDeviceIbi(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == i3cDevice) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - uint32_t sirmap, bitpos, mrmap; - cy_en_i3c_status_t retStatus; - - //Slave Interrupt Request - sirmap = I3C_CORE_IBI_SIR_REQ_REJECT(base); - bitpos = CY_I3C_IBI_SIR_REQ_ID(i3cDevice->dynamicAddress); - sirmap &= ~((1UL) << bitpos); //Setting the corresponding bit to 0: 0 -> Ack the SIR from the corresponding device - I3C_CORE_IBI_SIR_REQ_REJECT(base) = sirmap; - - //Mastership Request - mrmap = I3C_CORE_IBI_MR_REQ_REJECT(base); - mrmap &= ~((1UL) << bitpos); //Setting the corresponding bit to 0: 0 -> Ack the MR from the corresponding device - I3C_CORE_IBI_MR_REQ_REJECT(base) = mrmap; - - retStatus = DeviceIBIControl(base, i3cDevice, CY_I3C_CCC_ENEC(false), context); - - return retStatus; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SetDataRate -****************************************************************************//** -* -* Sets desired maximum I3C bus data rate for transfers. -* -* \param base -* The pointer to the I3C instance. -* -* \param dataRateHz -* The desired I3C data rate in Hz. -* -* \param i3cClockHz -* The frequency of the clock connected to the I3C Block in Hz. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* The achieved data rate in Hz. -* When zero value is returned there is an error in the input parameters: -* data rate or clk_i3c is out of valid range. -* -*******************************************************************************/ -uint32_t Cy_I3C_SetDataRate(I3C_CORE_Type *base, uint32_t dataRateHz, uint32_t i3cClockHz, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - CY_ASSERT_L2(i3cClockHz > 0UL); - CY_ASSERT_L3(CY_I3C_IS_SDR_DATA_RATE_VALID(dataRateHz)); - - uint32_t i3cClockPeriod; //in nanoSeconds - uint32_t resDataRate; //stores the achieved data rate - uint8_t hcnt,lcnt; - - //CY_I3C_DIV_ROUND_UP - quotient will be rounded to the next number in non-integer cases - i3cClockPeriod = CY_I3C_DIV_ROUND_UP(1000000000, i3cClockHz); //time period in nanoseconds - - //high phase will be 41ns irrespective of whether the bus is in PureBusMode or MixedBusMode - - hcnt = CY_I3C_DIV_ROUND_UP(CY_I3C_BUS_THIGH_MAX_NS, i3cClockPeriod) - 1; - if (hcnt < CY_I3C_SCL_I3C_TIMING_CNT_MIN) - hcnt = CY_I3C_SCL_I3C_TIMING_CNT_MIN; - - lcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, dataRateHz) - hcnt; - if (lcnt < CY_I3C_SCL_I3C_TIMING_CNT_MIN) - lcnt = CY_I3C_SCL_I3C_TIMING_CNT_MIN; - - I3C_CORE_SCL_I3C_PP_TIMING(base) = _VAL2FLD(I3C_CORE_SCL_I3C_PP_TIMING_I3C_PP_HCNT, hcnt) | - _VAL2FLD(I3C_CORE_SCL_I3C_PP_TIMING_I3C_PP_LCNT, lcnt); - - //configure the BUS_FREE_AVAIL_TIMING register - I3C_CORE_BUS_FREE_AVAIL_TIMING(base) = _VAL2FLD(I3C_CORE_BUS_FREE_AVAIL_TIMING_BUS_FREE_TIME, lcnt); - - resDataRate = CY_I3C_DIV_ROUND_UP(1000000000,((hcnt + lcnt) * (i3cClockPeriod))); - - lcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, (dataRateHz < CY_I3C_SDR1_DATA_RATE) ? dataRateHz : CY_I3C_SDR1_DATA_RATE) - hcnt; - I3C_CORE_SCL_EXT_LCNT_TIMING(base) |= _VAL2FLD(I3C_CORE_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_1, lcnt); - lcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, (dataRateHz < CY_I3C_SDR2_DATA_RATE) ? dataRateHz : CY_I3C_SDR2_DATA_RATE) - hcnt; - I3C_CORE_SCL_EXT_LCNT_TIMING(base) |= _VAL2FLD(I3C_CORE_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_2, lcnt); - lcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, (dataRateHz < CY_I3C_SDR3_DATA_RATE) ? dataRateHz : CY_I3C_SDR3_DATA_RATE) - hcnt; - I3C_CORE_SCL_EXT_LCNT_TIMING(base) |= _VAL2FLD(I3C_CORE_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_3, lcnt); - lcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, (dataRateHz < CY_I3C_SDR4_DATA_RATE) ? dataRateHz : CY_I3C_SDR4_DATA_RATE) - hcnt; - I3C_CORE_SCL_EXT_LCNT_TIMING(base) |= _VAL2FLD(I3C_CORE_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_4, lcnt); - - if(CY_I3C_BUS_PURE != context->i3cBusMode) - { - //Mixed mode bus - - lcnt = CY_I3C_DIV_ROUND_UP(CY_I3C_BUS_I2C_FMP_TLOW_MIN_NS, i3cClockPeriod); - hcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, CY_I3C_I2C_FMP_DATA_RATE) - lcnt; - - I3C_CORE_SCL_I2C_FMP_TIMING(base) = _VAL2FLD(I3C_CORE_SCL_I2C_FMP_TIMING_I2C_FMP_HCNT, hcnt) | - _VAL2FLD(I3C_CORE_SCL_I2C_FMP_TIMING_I2C_FMP_LCNT, lcnt); - - lcnt = CY_I3C_DIV_ROUND_UP(CY_I3C_BUS_I2C_FM_TLOW_MIN_NS, i3cClockPeriod); - hcnt = CY_I3C_DIV_ROUND_UP(i3cClockHz, CY_I3C_I2C_FM_DATA_RATE) - lcnt; - - I3C_CORE_SCL_I2C_FM_TIMING(base) = _VAL2FLD(I3C_CORE_SCL_I2C_FM_TIMING_I2C_FM_HCNT, hcnt) | - _VAL2FLD(I3C_CORE_SCL_I2C_FM_TIMING_I2C_FM_LCNT, lcnt); - - //configure the BUS_FREE_AVAIL_TIMING register with lcnt from Fast-Mode - - I3C_CORE_BUS_FREE_AVAIL_TIMING(base) = _VAL2FLD(I3C_CORE_BUS_FREE_AVAIL_TIMING_BUS_FREE_TIME, lcnt); - - } - - context->i3cSclRate = resDataRate; - return resDataRate; - -} - - -/******************************************************************************* -* Function Name: Cy_I3C_I3CGetDataRate -****************************************************************************//** -* -* Provides the supported I3C bus data rate for I3C devices. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_data_speed_t -* -*******************************************************************************/ -uint32_t Cy_I3C_GetDataRate(I3C_CORE_Type const *base, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - /* Suppress a compiler warning about unused variables */ - (void) base; - - return (context->i3cSclRate); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_IsBusBusy -****************************************************************************//** -* -* Indicates the whether the bus is busy or not. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* true: if bus is BUSY. -* false: if bus is IDLE. -* -*******************************************************************************/ -bool Cy_I3C_IsBusBusy(I3C_CORE_Type const *base) -{ - CY_ASSERT_L1(NULL != base); - - uint32_t retStatus; - - retStatus = I3C_CORE_PRESENT_STATE(base) & I3C_CORE_PRESENT_STATE_CM_TFR_STS_Msk; - - if(0 == retStatus) - return false; - - return true; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_IsMaster -****************************************************************************//** -* -* Indicates the whether the bus is busy or not. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* true: if controller is current bus master. -* false: otherwise. -* -*******************************************************************************/ -bool Cy_I3C_IsMaster(I3C_CORE_Type const *base) -{ - CY_ASSERT_L1(NULL != base); - - uint32_t value = _FLD2VAL(I3C_CORE_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE, I3C_CORE_DEVICE_CTRL_EXTENDED(base)); - - if(value) - return false; - - else - return true; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_GetMode -****************************************************************************//** -* -* Provides the mode of the device. -* -* \param base -* The pointer to the I3C instance. -* -* \return -* \ref cy_en_i3c_mode_t -* -*******************************************************************************/ -cy_en_i3c_mode_t Cy_I3C_GetMode(I3C_CORE_Type const *base) -{ - CY_ASSERT_L1(NULL != base); - - uint32_t mode; - - mode = I3C_CORE_DEVICE_CTRL_EXTENDED(base); - mode = _FLD2VAL(I3C_CORE_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE, mode); - - if(mode) - return CY_I3C_SLAVE; - - else - return CY_I3C_MASTER; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterWrite -****************************************************************************//** -* -* Writes data provided by xferConfig structure \ref cy_stc_i3c_master_xfer_config_t -* to a specific device. -* -* \param base -* The pointer to the I3C instance. -* -* \param xferConfig -* Master transfer configuration structure. -* \ref cy_stc_i3c_master_xfer_config_t -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterWrite(I3C_CORE_Type *base, cy_stc_i3c_master_xfer_config_t *xferConfig, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == xferConfig) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - CY_ASSERT_L1(CY_IS_I3C_BUFFER_VALID(xferConfig->buffer, xferConfig->bufferSize)); - CY_ASSERT_L2(CY_IS_I3C_ADDR_VALID(xferConfig->slaveAddress)); - - if(CY_I3C_FIFO_SIZE < xferConfig->bufferSize) - return CY_I3C_BAD_BUFFER_SIZE; - - cy_en_i3c_status_t retStatus = CY_I3C_MASTER_NOT_READY; - - if(0 != (CY_I3C_IDLE_MASK & context->state)) - { - uint8_t validBytes, res; - uint8_t *data; - cy_stc_i3c_ccc_t cmd; - uint8_t pos = 0; - cy_stc_i3c_master_devlist_t *i3cDeviceList; - uint8_t writeDSMode = CY_I3C_SDR0; - - context->masterBuffer = xferConfig->buffer; - context->masterBufferSize = xferConfig->bufferSize; - context->masterBufferIdx = 0; - data = context->masterBuffer; - context->masterStatus = CY_I3C_MASTER_BUSY; - - cmd.cmdHigh = 0UL; - cmd.cmdLow = 0UL; - - //Clear the interrupts - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - //Reset the Tx FIFO - I3C_CORE_RESET_CTRL(base) |= I3C_CORE_RESET_CTRL_TX_FIFO_RST_Msk; - - res = GetAaddrslotStatus(xferConfig->slaveAddress, context); - - //This helps to check if the device is actively present on the bus - if((CY_I3C_ADDR_SLOT_I3C_DEV != res ) && (CY_I3C_ADDR_SLOT_I2C_DEV != res)) - return CY_I3C_BAD_PARAM; - - if(CY_I3C_ADDR_SLOT_I2C_DEV == res) - { - //The target device is an i2cDevice - pos = GetI2CDevAddrPos(base, xferConfig->slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - writeDSMode = (i3cDeviceList->i2cDevice.lvr & CY_I3C_LVR_I2C_MODE_INDICATOR) ? CY_I3C_FM_I2C: CY_I3C_FMP_I2C; - context->masterStatus |= CY_I3C_MASTER_I2C_SDR_WR_XFER; - } - - else - { - //The target is an i3cDevice - pos = GetI3CDevAddrPos(base, xferConfig->slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - if(CY_I3C_CORE_BCR_MAX_DATA_SPEED_LIM_Msk == (i3cDeviceList->i3cDevice.bcr)) - { - writeDSMode = (i3cDeviceList->i3cDevice.maxWriteDs) & 0x07; - } - context->masterStatus |= CY_I3C_MASTER_I3C_SDR_WR_XFER; - } - - switch(xferConfig->bufferSize) - { - case 1: { - validBytes = CY_I3C_BYTE_STROBE1; - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, validBytes) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0,*data); - context->masterBufferSize -= 1; - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - break; } - case 2: { - validBytes = CY_I3C_BYTE_STROBE2; - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, validBytes) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0,*(data)) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_1,*(data + 1)); - context->masterBufferSize -= 2; - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - break; } - case 3: { - validBytes = CY_I3C_BYTE_STROBE3; - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, validBytes) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0,*data) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_1,*(data + 1)) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_2,*(data + 2)); - context->masterBufferSize -= 3; - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - break; } - default: { - - //Write transfer with data greater than 3 bytes - MasterHandleDataTransmit(base, context); - if(xferConfig->toc) - { - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - } - - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, context->masterBufferSize); - break; } - } - - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TID, CY_I3C_MASTER_SDR_WRITE_TID) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED, writeDSMode) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk; - - context->state = CY_I3C_MASTER_TX; - //send the command - Cy_I3C_SetInterruptMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; - - retStatus = CY_I3C_SUCCESS; - } - - return retStatus; -} - -/******************************************************************************* -* Function Name: Cy_I3C_MasterRead -****************************************************************************//** -* -* Reads data from a device specified by xferConfig structure -* \ref cy_stc_i3c_master_xfer_config_t. -* -* \param base -* The pointer to the I3C instance. -* -* \param xferConfig -* Master transfer configuration structure. -* \ref cy_stc_i3c_master_xfer_config_t -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterRead (I3C_CORE_Type *base, cy_stc_i3c_master_xfer_config_t* xferConfig, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == xferConfig) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - CY_ASSERT_L1(CY_IS_I3C_BUFFER_VALID(xferConfig->buffer, xferConfig->bufferSize)); - CY_ASSERT_L2(CY_IS_I3C_ADDR_VALID(xferConfig->slaveAddress)); - - if(CY_I3C_FIFO_SIZE < xferConfig->bufferSize) - return CY_I3C_BAD_BUFFER_SIZE; - - cy_en_i3c_status_t retStatus = CY_I3C_MASTER_NOT_READY; - - if(0 != (CY_I3C_IDLE_MASK & context->state)) - { - cy_stc_i3c_ccc_t cmd; - uint8_t pos = 0; - cy_stc_i3c_master_devlist_t *i3cDeviceList; - uint8_t readDSMode = CY_I3C_SDR0; - uint8_t res; - - context->masterBuffer = xferConfig->buffer; - context->masterBufferSize = xferConfig->bufferSize; - context->masterBufferIdx = 0; - context->masterStatus = CY_I3C_MASTER_BUSY; - - cmd.cmdHigh = 0UL; - cmd.cmdLow = 0UL; - - //Clear the interrupts - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - //Reset the Rx FIFO - I3C_CORE_RESET_CTRL(base) |= I3C_CORE_RESET_CTRL_RX_FIFO_RST_Msk; - - res = GetAaddrslotStatus(xferConfig->slaveAddress, context); - - //This helps to check if the device is actively present on the bus - if((CY_I3C_ADDR_SLOT_I3C_DEV != res ) && (CY_I3C_ADDR_SLOT_I2C_DEV != res)) - return CY_I3C_BAD_PARAM; - - if(CY_I3C_ADDR_SLOT_I2C_DEV == res) - { - //The target device is an i2cDevice - pos = GetI2CDevAddrPos(base, xferConfig->slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - readDSMode = (i3cDeviceList->i2cDevice.lvr & CY_I3C_LVR_I2C_MODE_INDICATOR) ? CY_I3C_FM_I2C: CY_I3C_FMP_I2C; - context->masterStatus |= CY_I3C_MASTER_I2C_SDR_RD_XFER; - } - else - { - //The target is an i3cDevice - pos = GetI3CDevAddrPos(base, xferConfig->slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - if(CY_I3C_CORE_BCR_MAX_DATA_SPEED_LIM_Msk == (i3cDeviceList->i3cDevice.bcr)) - { - readDSMode = (i3cDeviceList->i3cDevice.maxReadDs) & 0x07; - } - context->masterStatus |= CY_I3C_MASTER_I3C_SDR_RD_XFER; - } - - if(xferConfig->toc) - { - //There are no bytes remaining to be read from the next READ, so terminate this READ with STOP - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - } - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, context->masterBufferSize); - - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TID, CY_I3C_MASTER_SDR_READ_TID) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED, readDSMode) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_RnW_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk; - - context->state = CY_I3C_MASTER_RX; - - Cy_I3C_SetInterruptMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; - - - return CY_I3C_SUCCESS; - } - return retStatus; -} - -/******************************************************************************* -* Function Name: Cy_I3C_MasterAbortTransfer -****************************************************************************//** -* -* Aborts an ongoing transfer. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_MasterAbortTransfer(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - if(CY_I3C_IDLE != context->state) - { - uint32_t intrState; - I3C_CORE_DEVICE_CTRL(base) = I3C_CORE_DEVICE_CTRL_ABORT_Msk; - - intrState = Cy_SysLib_EnterCriticalSection(); - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_TRANSFER_ABORT_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_TRANSFER_ABORT_STS); - Cy_SysLib_ExitCriticalSection(intrState); - } -} - -/******************************************************************************* -* Function Name: Cy_I3C_MasterWriteByte -****************************************************************************//** -* -* Sends one byte to a slave. -* This function is blocking. -* -* \param base -* The pointer to the I3C instance. -* -* \param slaveAddress -* The dynamic address of the target I3C slave device. -* -* \param data -* The byte to write to the slave. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterWriteByte(I3C_CORE_Type *base, uint8_t slaveAddress, int8_t data, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - CY_ASSERT_L2(CY_IS_I3C_ADDR_VALID(slaveAddress)); - - cy_en_i3c_status_t retStatus = CY_I3C_MASTER_NOT_READY; - - if(0 != (CY_I3C_IDLE_MASK & context->state)) - { - uint8_t res; - cy_stc_i3c_ccc_t cmd; - uint8_t pos = 0; - cy_stc_i3c_master_devlist_t *i3cDeviceList; - uint8_t writeDSMode = CY_I3C_SDR0; - uint32_t respCmdPort; - - context->masterStatus = CY_I3C_MASTER_BUSY; - - cmd.cmdHigh = 0UL; - cmd.cmdLow = 0UL; - - //Clear the interrupts - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - //Reset the Tx FIFO - I3C_CORE_RESET_CTRL(base) |= I3C_CORE_RESET_CTRL_TX_FIFO_RST_Msk; - - res = GetAaddrslotStatus(slaveAddress, context); - - //This helps to check if the device is actively present on the bus - if((CY_I3C_ADDR_SLOT_I3C_DEV != res ) && (CY_I3C_ADDR_SLOT_I2C_DEV != res)) - return CY_I3C_BAD_PARAM; - - if(CY_I3C_ADDR_SLOT_I2C_DEV == res) - { - //The target device is an i2cDevice - pos = GetI2CDevAddrPos(base, slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - writeDSMode = (i3cDeviceList->i2cDevice.lvr & CY_I3C_LVR_I2C_MODE_INDICATOR) ? CY_I3C_FM_I2C: CY_I3C_FMP_I2C; - context->masterStatus |= CY_I3C_MASTER_I2C_SDR_WR_XFER; - } - - else - { - //The target is an i3cDevice - pos = GetI3CDevAddrPos(base, slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - if(CY_I3C_CORE_BCR_MAX_DATA_SPEED_LIM_Msk == (i3cDeviceList->i3cDevice.bcr)) - { - writeDSMode = (i3cDeviceList->i3cDevice.maxWriteDs) & 0x07; - } - context->masterStatus |= CY_I3C_MASTER_I3C_SDR_WR_XFER; - } - - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, 1) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0, data); - - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED, writeDSMode) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - - context->state = CY_I3C_MASTER_TX; - - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; - - do - { - //wait till the interrupt of response is received - }while(0 == ((CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS) & Cy_I3C_GetInterruptStatus(base))); - - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - Cy_I3C_SetInterruptStatusMask(base, 0); - - if(0 != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS_Msk)) - { - retStatus = ResponseError(respCmdPort); //unsuccessful due to transfer error - context->masterStatus |= CY_I3C_MASTER_HALT_STATE; - } - - else - { - retStatus = CY_I3C_SUCCESS; - } - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - context->state = CY_I3C_IDLE; - } - - return retStatus; -} - -/******************************************************************************* -* Function Name: Cy_I3C_MasterReadByte -****************************************************************************//** -* -* Reads one byte from a slave. -* This function is blocking. -* -* \param base -* The pointer to the I3C instance. -* -* \param slaveAddress -* The dynamic address of the target I3C slave device. -* -* \param data -* The pointer to the location to store the Read byte. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterReadByte(I3C_CORE_Type *base, uint8_t slaveAddress, int8_t *data, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - CY_ASSERT_L2(CY_IS_I3C_ADDR_VALID(slaveAddress)); - - cy_en_i3c_status_t retStatus = CY_I3C_MASTER_NOT_READY; - - if(0 != (CY_I3C_IDLE_MASK & context->state)) - { - uint8_t res; - cy_stc_i3c_ccc_t cmd; - uint8_t pos = 0; - cy_stc_i3c_master_devlist_t *i3cDeviceList; - uint8_t readDSMode = CY_I3C_SDR0; - uint32_t respCmdPort, datalen; - - context->masterStatus = CY_I3C_MASTER_BUSY; - - cmd.cmdHigh = 0UL; - cmd.cmdLow = 0UL; - - //Clear the interrupts - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - //Reset the Tx FIFO - I3C_CORE_RESET_CTRL(base) |= I3C_CORE_RESET_CTRL_TX_FIFO_RST_Msk; - - res = GetAaddrslotStatus(slaveAddress, context); - - //This helps to check if the device is actively present on the bus - if((CY_I3C_ADDR_SLOT_I3C_DEV != res ) && (CY_I3C_ADDR_SLOT_I2C_DEV != res)) - return CY_I3C_BAD_PARAM; - - if(CY_I3C_ADDR_SLOT_I2C_DEV == res) - { - //The target device is an i2cDevice - pos = GetI2CDevAddrPos(base, slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - readDSMode = (i3cDeviceList->i2cDevice.lvr & CY_I3C_LVR_I2C_MODE_INDICATOR) ? CY_I3C_FM_I2C: CY_I3C_FMP_I2C; - context->masterStatus |= CY_I3C_MASTER_I2C_SDR_RD_XFER; - } - - else - { - //The target is an i3cDevice - pos = GetI3CDevAddrPos(base, slaveAddress, context); - i3cDeviceList = &(context->devList[pos]); //pointing to the device position in the local list of devices on the bus - if(CY_I3C_CORE_BCR_MAX_DATA_SPEED_LIM_Msk == (i3cDeviceList->i3cDevice.bcr)) - { - readDSMode = (i3cDeviceList->i3cDevice.maxReadDs) & 0x07; - } - context->masterStatus |= CY_I3C_MASTER_I3C_SDR_RD_XFER; - } - - cmd.cmdHigh |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, 1); - - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED, readDSMode) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_RnW_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - - context->state = CY_I3C_MASTER_RX; - - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; - - do - { - //wait till the interrupt of response is received - }while(0 == ((CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS) & Cy_I3C_GetInterruptStatus(base))); - - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - Cy_I3C_SetInterruptStatusMask(base, 0); - - if(0 != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS_Msk)) - { - retStatus = ResponseError(respCmdPort); //unsuccessful due to transfer error - context->masterStatus |= CY_I3C_MASTER_HALT_STATE; - } - - else - { - datalen = (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk); - if(1 == datalen) - { - *data = (uint8_t)Cy_I3C_ReadRxFIFO(base); - retStatus = CY_I3C_SUCCESS; - } - else - { - retStatus = CY_I3C_MASTER_ERROR_M0; - } - } - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - context->state = CY_I3C_IDLE; - } - - return retStatus; -} - -/******************************************************************************* -* Function Name: Cy_I3C_GetBusStatus -****************************************************************************//** -* -* Returns the current I2C master status. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref group_i3c_macros_master_status. -* Note that not all I3C master statuses are returned by this function. Refer to -* more details of each status. -* -*******************************************************************************/ -uint32_t Cy_I3C_GetBusStatus(I3C_CORE_Type const *base, cy_stc_i3c_context_t const *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - (void) base; - #if 0 - uint32_t ret; - ret = _FLD2VAL(I3C_CORE_PRESENT_STATE_CM_TFR_STS, I3C_CORE_PRESENT_STATE(base)); - //Gives the state of the transfer currently being executed by the controller - - return ret; - #endif - - if(CY_I3C_MASTER == Cy_I3C_GetMode(base)) - return (context->masterStatus); - - else - return(context->slaveStatus); - -} - -/* DAA */ -/* About DAA: -1. This has the responsibility of finding the number of devices required to be assigned dynamic addresses -2. Getting the free addresses -3. Polpulating the DAT -4. Populating the COMMAND DATA PORT -5. Poll for the response and update the DAT free pos index based on the response received */ - -/******************************************************************************* -* Function Name: Cy_I3C_MasterStartEntDaa -****************************************************************************//** -* -* Issues ENTDAA CCC command to discover the i3c devices on the bus and assigns -* valid dynamic addreses to the discovered devices. -* This CCC is to be issued also when a device hot joins the bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterStartEntDaa(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - cy_stc_i3c_device_t i3cDev; - uint8_t i3cDevCount; //to store the number of devices to be assigned the dynamic address - uint8_t dynamicAddress; - uint8_t index, parity, pos; - uint32_t respCmdPort; - uint16_t respLeftDevCount; - uint32_t value; - cy_en_i3c_status_t retStatus; - cy_stc_i3c_ccc_cmd_t cccCmd; - cy_stc_i3c_ccc_payload_t payload; - - if(CY_I3C_MAX_DEVS <= (i3cMaster->devCount)) //cannot initialize the device as the bus already has 11 devices on it - return CY_I3C_MASTER_MAX_DEVS_PRESENT; - - i3cDevCount = CY_I3C_MAX_DEVS - (i3cMaster->devCount); - - //Get "free address" position - pos = GetDATFreePos(base, context); - - //Get the 'i3cDevCount' number of free addresses and populate the DAT before issuing ENTDAA CCC - for(index = pos; index < i3cDevCount; index++) - { - retStatus = Cy_I3C_MasterGetFreeDeviceAddress(base, &dynamicAddress, context); - if(CY_I3C_MASTER_FREE_ADDR_UNAVIAL == retStatus) - return retStatus; - - parity = even_parity(dynamicAddress); - i3cMaster->lastAddress = dynamicAddress; - dynamicAddress |= (parity << 7); - - //populate the device address table with the dynmaic address of the device - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR, dynamicAddress); - - Cy_I3C_WriteIntoDeviceAddressTable(base, index, value); - } - - context->masterStatus = CY_I3C_MASTER_BUSY | CY_I3C_MASTER_ENTDAA_XFER; - - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_ADDR_ASSGN_CMD | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_CMD, CY_I3C_CCC_ENTDAA) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_INDX, pos) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_COUNT, i3cDevCount) | - I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_TOC_Msk; - - //Handling the response - do - { - //wait till the interrupt of response is received - }while(0 == (CY_I3C_INTR_MASK & Cy_I3C_GetInterruptStatus(base))); - - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - respLeftDevCount = (uint16_t)(respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk); //represents the remaining device count - - if(0 != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS_Msk)) - { - if(4 != (_FLD2VAL(I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS, respCmdPort))) //TO DO: Use a macro instead of '4' - { - /* Error in transfer */ - retStatus = ResponseError(respCmdPort); - context->masterStatus |= CY_I3C_MASTER_HALT_STATE; - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - return retStatus; - } - } - - Cy_I3C_Resume(base, context); - - i3cMaster->dynAddrDevCount = i3cDevCount - respLeftDevCount; //Doubt - Will NACK be received here too? - i3cMaster->devCount += i3cMaster->dynAddrDevCount; - - //Maintaining a local list of i3c devices - for( index = 0; index < i3cMaster->dynAddrDevCount; index++) - { - Cy_I3C_ReadFromDevCharTable(base, index, &i3cDev); - SetAddrslotStatus(i3cDev.dynamicAddress, CY_I3C_ADDR_SLOT_I3C_DEV, context); - RetrieveI3CDeviceInfo(base, &i3cDev, false, context); - i3cDev.staticAddress = 0; - Cy_I3C_UpdateI3CDevInList(&i3cDev, pos, context); - i3cMaster->freePos &= ~(CY_I3C_BIT(pos)); - pos++; - } - - if(0 != i3cMaster->dynAddrDevCount) - { - //Send DEFSLVS and ENEC CCC commands - cccCmd.address = CY_I3C_BROADCAST_ADDR; - cccCmd.cmd = CY_I3C_CCC_DEFSLVS; - cccCmd.data = &payload; - - defslvs_ccc(base, &cccCmd, context); - } - - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - return CY_I3C_SUCCESS; - - -} - -/******************************************************************************* -* Function Name: Cy_I3C_MasterSendHdrCmds -****************************************************************************//** -* -* Writes data provided by xferConfig structure \ref cy_stc_i3c_master_xfer_config_t -* to a specific device. -* -* \param base -* The pointer to the I3C instance. -* -* \param slaveAddress -* The dynamic address of the target I3C device. -* -* \param hdrCmd -* The pointer to HDR command description structure \ref cy_stc_i3c_hdr_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_MasterSendHdrCmds(I3C_CORE_Type *base, uint8_t slaveAddress, cy_stc_i3c_hdr_cmd_t *hdrCmd, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == hdrCmd) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - uint8_t pos, res; - cy_en_i3c_status_t retStatus = CY_I3C_MASTER_NOT_READY; - - if(0 != (CY_I3C_IDLE_MASK & context->state)) - { - res = GetAaddrslotStatus(slaveAddress, context); - - //This helps to check if the device is actively present on the bus - if((CY_I3C_ADDR_SLOT_I3C_DEV != res ) && (CY_I3C_ADDR_SLOT_I2C_DEV != res)) - return CY_I3C_BAD_PARAM; - - pos = GetI3CDevAddrPos( base, slaveAddress, context); - - cy_stc_i3c_master_devlist_t *i3cDevice = &(context->devList[pos]); - - if(false == (i3cDevice->i3cDevice.hdrSupport)) - { - // The device doesn't support HDR mode - return CY_I3C_NOT_HDR_CAP; - } - - if(hdrCmd->code & CY_I3C_HDR_IS_READ_CMD) - { - uint8_t numToRead; - numToRead = (hdrCmd->ndatawords*2); - //Read command - context->hdrCmd = hdrCmd; - context->masterBuffer = (uint8_t *)hdrCmd->data.in; - context->masterBufferSize = numToRead; - context->destDeviceAddr = slaveAddress; - context->masterStatus = CY_I3C_MASTER_BUSY; - - MasterHDRRead(base, hdrCmd, context); - } - - else - { - // WRITE command - context->hdrCmd = hdrCmd; - context->masterBuffer = (uint8_t *)hdrCmd->data.out; - context->masterBufferSize = (hdrCmd->ndatawords * 2); - context->destDeviceAddr = slaveAddress; - context->masterStatus = CY_I3C_MASTER_BUSY; - - MasterHDRWrite(base, hdrCmd, context); - } - retStatus = CY_I3C_SUCCESS; - } - - return retStatus; -} - -/******************************************************************************* -* Function Name: Cy_I3C_Interrupt -****************************************************************************//** -* -* This is an I3C interrupt handler helper function. -* This function must be called inside the user-defined interrupt service. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_Interrupt (I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - if (0UL == (I3C_CORE_DEVICE_CTRL_EXTENDED(base) & I3C_CORE_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_Msk)) - { - /* Execute a transfer as the master */ - Cy_I3C_MasterInterrupt(base, context); - } - else - { - /* Execute a transfer as the slave */ - Cy_I3C_SlaveInterrupt(base, context); - } -} - - -/******************************************************************************* -* Function Name: Cy_I3C_RegisterEventCallback -****************************************************************************//** -* -* Registers an event handler callback function of type cy_cb_i3c_handle_events_t -* which will be invoked by the PDL to indicate i3c events and results. -* -* \param base -* The pointer to the I3C instance. -* -* \param callback -* The pointer to a callback function. -* See \ref cy_cb_i3c_handle_events_t for the function prototype. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \note -* To remove the callback, pass NULL as the pointer to the callback function. -* -*******************************************************************************/ -void Cy_I3C_RegisterEventCallback(I3C_CORE_Type const *base, cy_cb_i3c_handle_events_t callback, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - /* Suppress a compiler warning about unused variable */ - (void) base; - - context->cbEvents = callback; -} - -/******************************************************************************* -* Function Name: Cy_I3C_RegisterIbiCallback -****************************************************************************//** -* -* Registers an IBI handler callback function of type cy_cb_i3c_handle_ibi_t -* which will be invoked when an IBI event is triggered on bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param callback -* The pointer to a callback function. -* See \ref cy_cb_i3c_handle_events_t for the function prototype. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \note -* To remove the callback, pass NULL as the pointer to the callback function. -* -*******************************************************************************/ -void Cy_I3C_RegisterIbiCallback (I3C_CORE_Type const *base, cy_cb_i3c_handle_ibi_t callback, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - /* Suppress a compiler warning about unused variable */ - (void) base; - - context->cbIbi = callback; - -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveGetDynamicAddress -****************************************************************************//** -* -* Provides the master assigned dynamic address of the slave device. -* -* \param base -* The pointer to the I3C instance. -* -* \param address -* The pointer to the address. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_SlaveGetDynamicAddress(I3C_CORE_Type const *base, uint8_t *address, cy_stc_i3c_context_t const *context) -{ - if((NULL == base) || (NULL == address) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - if(_FLD2VAL(I3C_CORE_DEVICE_ADDR_DYNAMIC_ADDR_VALID, I3C_CORE_DEVICE_ADDR(base))) - { - *address = (uint8_t)_FLD2VAL(I3C_CORE_DEVICE_ADDR_DYNAMIC_ADDR, I3C_CORE_DEVICE_ADDR(base)); - return CY_I3C_SUCCESS; - } - - return CY_I3C_ADDR_INVALID; -} - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveGetMaxReadLength -****************************************************************************//** -* -* Provides the maximum data read lenght of the slave. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Max data read length. -* -*******************************************************************************/ -uint32_t Cy_I3C_SlaveGetMaxReadLength(I3C_CORE_Type const *base, cy_stc_i3c_context_t const *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - return (uint32_t)_FLD2VAL(I3C_CORE_SLV_MAX_LEN_MRL, I3C_CORE_SLV_MAX_LEN(base)); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveGetMaxWriteLength -****************************************************************************//** -* -* Provides the maximum data write lenght of the slave. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Max write data length. -* -*******************************************************************************/ -uint32_t Cy_I3C_SlaveGetMaxWriteLength(I3C_CORE_Type const *base, cy_stc_i3c_context_t const *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - - return (uint32_t)_FLD2VAL(I3C_CORE_SLV_MAX_LEN_MWL, I3C_CORE_SLV_MAX_LEN(base)); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveGenerateIbi -****************************************************************************//** -* -* Generates the specified IBI on the bus. -* -* \param base -* The pointer to the I3C instance. -* -* \param ibitype -* The pointer to the ibi structure \ref cy_stc_i3c_ibi_t containing the -* type of ibi event to be generated. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_SlaveGenerateIbi(I3C_CORE_Type *base, cy_stc_i3c_ibi_t *ibitype, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == ibitype) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - uint8_t res; - uint32_t value = 0; - cy_en_i3c_status_t ret = CY_I3C_SUCCESS; - - //Generate a SIR - if(CY_I3C_IBI_SIR == ibitype->event) - { - if(_FLD2VAL(I3C_CORE_SLV_EVENT_STATUS_SIR_EN, I3C_CORE_SLV_EVENT_STATUS(base))) - { - //When set, the controller attempts to issue the SIR on the bus. Once set, the applicatio cannot clear this bit - //SIR_CTRL field of this reg is to be set to 0 - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_UPDATED_STS); - I3C_CORE_SLV_INTR_REQ(base) = I3C_CORE_SLV_INTR_REQ_SIR_Msk; - } - else - { - //Return that Master has disabled SIR IBI - return CY_I3C_SIR_DISABLED; - } - } - - //Generate a mastership request - else if((CY_I3C_IBI_MASTER_REQ == ibitype->event) && (CY_I3C_SECONDARY_MASTER == context->i3cMode)) - { - //ASK - Should the DEVICE_ROLE be checked here for secondary master?? - if( _FLD2VAL(I3C_CORE_SLV_EVENT_STATUS_MR_EN, I3C_CORE_SLV_EVENT_STATUS(base))) - { - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_UPDATED_STS); - //When set, the controller attempts to issue the MR on the bus. Once set, the application cannot clear this bit - I3C_CORE_SLV_INTR_REQ(base) = I3C_CORE_SLV_INTR_REQ_MR_Msk; - } - else - { - //Return that Master has disabled MR IBI - return CY_I3C_MR_DISABLED; - } - } - - else - { - /* - When slaves initiates a hot-join ibi genearation event or - when a non-secondary master tries requesting for Mastership - */ - - return CY_I3C_BAD_EVENT_REQ; - } - - //Handling the response - do - { - //wait till the interrupt of response is received - }while(0 == (CY_I3C_INTR_IBI_UPDATED_STS & Cy_I3C_GetInterruptStatus(base))); - - //Handle the response - res = (uint8_t)_FLD2VAL(I3C_CORE_SLV_INTR_REQ_IBI_CPLT_STS, I3C_CORE_SLV_INTR_REQ(base)); - - if(3 == res) - { - /* IBI not attempted, if - * 1. Master has not assigned the dynamic address - * 2. Master has cleared the assigned dynamic address - * 3. Master has disabled the IBI (DISEC) - * 4. The controller has switched to master mode */ - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - Cy_I3C_SetInterruptMask(base, CY_I3C_SLV_INTR_Msk); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_SLV_INTR_Msk); - ret = CY_I3C_IBI_NOT_ATTEMPTED; - } - - else - { - /* IBI is ACKed */ - if(CY_I3C_IBI_MASTER_REQ == ibitype->event) - { - /* IBI is acked, check if the mastership is delivered */ - Cy_SysLib_Delay(1000); - - value = I3C_CORE_DEVICE_CTRL_EXTENDED(base); - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - if(0x01 & value) - { - ret = CY_I3C_MR_DISABLED; - Cy_I3C_SetInterruptMask(base, CY_I3C_SLV_INTR_Msk); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_SLV_INTR_Msk); - } - - else - { - Cy_I3C_Resume(base, context); - SecondaryMasterInit(base, true, context); - } - } - } - return ret; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveConfigReadBuf -****************************************************************************//** -* -* Configures the buffer pointer and the read buffer size. This is the buffer -* from which the master reads data. After this function is called, data -* transfer from the read buffer to the master is handled by -* \ref Cy_I3C_Interrupt. -* -* When the Read transaction is completed \ref CY_I3C_SLAVE_WR_CMPLT is set. -* Also the \ref CY_I3C_SLAVE_WR_CMPLT_EVENT event is generated. -* -* \param base -* The pointer to the I3C instance. -* -* \param buffer -* The pointer to the buffer with data to be read by the master. -* -* \param size -* Size of the buffer. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_SlaveConfigReadBuf (I3C_CORE_Type const *base, uint8_t *buffer, uint32_t size, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - CY_ASSERT_L1(CY_IS_I3C_BUFFER_VALID(buffer, size)); - - /* Suppress a compiler warning about unused variables */ - (void) base; - - context->slaveTxBuffer = buffer; - context->slaveTxBufferSize = size; - context->slaveTxBufferIdx = 0UL; - context->slaveTxBufferCnt = 0UL; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveGetReadTransferCount -****************************************************************************//** -* -* Returns the number of bytes read by the master since the last time -* \ref Cy_I3C_SlaveConfigReadBuf was called. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* The number of bytes read by the master. -* -*******************************************************************************/ -uint32_t Cy_I3C_SlaveGetReadTransferCount (I3C_CORE_Type const *base, cy_stc_i3c_context_t const *context) -{ - CY_ASSERT_L1(NULL != base); - - /* Suppress a compiler warning about unused variables */ - (void)base; - - return (context->slaveTxBufferCnt); -} - -//TBD - Check RD/WR macro from I2C -/******************************************************************************* -* Function Name: Cy_I3C_SlaveConfigWriteBuf -****************************************************************************//** -* -* Configures the buffer pointer and the write buffer size. This is the buffer -* that the master writes data to. After this function is called, data -* transfer from the master into the write buffer is handled by -* \ref Cy_I3C_Interrupt. -* -* When the write transaction is completed \ref CY_I3C_SLAVE_RD_CMPLT is set. -* Also the \ref CY_I3C_SLAVE_RD_CMPLT_EVENT event is generated. -* -* \param base -* The pointer to the I3C instance. -* -* \param buffer -* The pointer to buffer to store data written by the master. -* -* \param size -* Size of the buffer. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_SlaveConfigWriteBuf(I3C_CORE_Type const *base, uint8_t *buffer, uint32_t size, cy_stc_i3c_context_t *context) -{ - CY_ASSERT_L1(NULL != base); - CY_ASSERT_L1(NULL != context); - CY_ASSERT_L1(CY_IS_I3C_BUFFER_VALID(buffer, size)); - - /* Suppress a compiler warning about unused variables */ - (void) base; - - context->slaveRxBuffer = buffer; - context->slaveRxBufferSize = size; - context->slaveRxBufferIdx = 0UL; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveGetWriteTransferCount -****************************************************************************//** -* -* Returns the number of bytes written by the master since the last time -* \ref Cy_I3C_SlaveConfigWriteBuf was called. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* The number of bytes written by the master. -* -*******************************************************************************/ -uint32_t Cy_I3C_SlaveGetWriteTransferCount (I3C_CORE_Type const *base, cy_stc_i3c_context_t const *context) -{ - CY_ASSERT_L1(NULL != base); - - /* Suppress a compiler warning about unused variables */ - (void) base; - - return (context->slaveRxBufferCnt); -} - - -/******************************************************************************* -* Function Name: Cy_I3C_DeliverMastership -****************************************************************************//** -* Delivers the bus mastership to the requesting secondary master. -* -* \param base -* The pointer to the I3C instance. -* -* \param SecMasterAddress -* The address of the I3C device to which the mastership has to be delivered. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \note -* This should be called by the user when a mastership request IBI is received -* through cy_cb_i3c_handle_ibi_t callback and user wants to deliver master ship. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_DeliverMastership(I3C_CORE_Type *base, uint8_t SecMasterAddress, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - cy_stc_i3c_ccc_cmd_t cccCmd; - cy_stc_i3c_ccc_getaccmst_t getaccmst; - cy_stc_i3c_ccc_payload_t payload; - uint8_t addr; - cy_en_i3c_status_t errorStatus; - - addr = SecMasterAddress; - - cccCmd.address = addr; //Check this slave address - cccCmd.cmd = CY_I3C_CCC_GETACCMST; - cccCmd.data = &payload; - cccCmd.data->data = &(getaccmst.newmaster); - - errorStatus = getaccmst_ccc(base, &cccCmd, context); - - if(CY_I3C_SUCCESS == errorStatus) - { - if(addr != (getaccmst.newmaster >> 1)) - { - errorStatus = CY_I3C_ADDR_MISMATCH; - } - - else - { - //Mastership is transferred and the controller is in the Slave Mode - - uint32_t value; - - value = _FLD2VAL(I3C_CORE_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE,I3C_CORE_DEVICE_CTRL_EXTENDED(base)); - - if(value) - { - //Mode is changed to slave - cy_en_i3c_status_t status; - - Cy_I3C_Resume(base, context); - I3C_CORE_RESET_CTRL(base) |= (I3C_CORE_RESET_CTRL_IBI_QUEUE_RST_Msk | I3C_CORE_RESET_CTRL_SOFT_RST_Msk); - status = SecondaryMasterInit(base, false, context); - - return status; - } - - } - } - return errorStatus; -} - - -/******************************************************************************* -* Function Name: Cy_I3C_RequestMastership -****************************************************************************//** -* -* Requests mastership from the current master. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -cy_en_i3c_status_t Cy_I3C_RequestMastership(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if((NULL == base) || (NULL == context)) - { - return CY_I3C_BAD_PARAM; - } - - if(CY_I3C_SECONDARY_MASTER != context->i3cMode) - { - return CY_I3C_NOT_SECONDARY_MASTER; - } - - cy_en_i3c_status_t retStatus; - cy_stc_i3c_ibi_t ibi; - - retStatus = Cy_I3C_SlaveGetDynamicAddress(base, &(ibi.slaveAddress), context); - - if(CY_I3C_SUCCESS == retStatus) - { - ibi.event = CY_I3C_IBI_MASTER_REQ; - retStatus = Cy_I3C_SlaveGenerateIbi(base, &ibi, context); - } - - return retStatus; -} - -/******************************************************************************* -* Function Name: SecondaryMasterInit -****************************************************************************//** -* -* This function does the basic Master Mode configurations when the operation -* mode of the Secondary Master is changed from I3C Slave to I3C Master. -* -* \param base -* The pointer to the I3C instance. -* -* \isMaster -* true: Master mode initializations. -* false: Slave mode initializations. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -cy_en_i3c_status_t SecondaryMasterInit(I3C_CORE_Type *base, bool isMaster, cy_stc_i3c_context_t *context) -{ - if(isMaster) - { - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint8_t address, idx; - uint32_t value; - uint32_t staticAddress, dynamicAddress, bcr, dcr, i2c; - cy_stc_i3c_device_t i3cDevice; - cy_stc_i2c_device_t i2cDevice; - - i3cMaster->freePos = 0x7FFUL; - i3cMaster->lastAddress = 0; - i3cMaster->devCount = 0; - i3cMaster->i2cDeviceCount = 0; - i3cMaster->dynAddrDevCount = 0; - - address = _FLD2VAL(I3C_CORE_DEVICE_ADDR_DYNAMIC_ADDR, I3C_CORE_DEVICE_ADDR(base)); - - InitAddrslots(context); - SetAddrslotStatus(address, CY_I3C_ADDR_SLOT_I3C_DEV, context); - - Cy_I3C_SetDataRate(base, context->i3cSclRate, context->i3cClockHz, context); - - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - - for(idx = 0; idx < context->slaveRxBufferCnt; idx++) - { - dynamicAddress = I3C_CORE_DEV_CHAR_TABLE1_LOC1(base) & 0xFFUL; - staticAddress = (I3C_CORE_DEV_CHAR_TABLE1_LOC1(base) & 0xFF000000UL) >> 24; - dcr = (I3C_CORE_DEV_CHAR_TABLE1_LOC1(base) & 0xFF00UL) >> 8; - bcr = (I3C_CORE_DEV_CHAR_TABLE1_LOC1(base) & 0xFF0000UL) >> 16; - - i2c = dynamicAddress? 0 : 1; - - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR, dynamicAddress) | - _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR, staticAddress) | - _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC10_LEGACY_I2C_DEVICE, i2c); - - Cy_I3C_WriteIntoDeviceAddressTable(base, idx, value); - - if(i2c) - { - /* I2C Device */ - SetAddrslotStatus(staticAddress, CY_I3C_ADDR_SLOT_I2C_DEV, context); - i2cDevice.lvr = dcr; - i2cDevice.staticAddress = staticAddress; - - Cy_I3C_UpdateI2CDevInList(&i2cDevice, idx, context); - - (i3cMaster->freePos) = ~ (CY_I3C_BIT(idx)); - (i3cMaster->devCount)++; - (i3cMaster->i2cDeviceCount)++; - } - else - { - /* I3C Device */ - SetAddrslotStatus(dynamicAddress, CY_I3C_ADDR_SLOT_I3C_DEV, context); - - i3cDevice.bcr = bcr; - i3cDevice.dcr = dcr; - i3cDevice.dynamicAddress = dynamicAddress; - RetrieveI3CDeviceInfo(base, &i3cDevice, false, context); - i3cDevice.staticAddress = 0; - Cy_I3C_UpdateI3CDevInList(&i3cDevice, idx, context); - - i3cMaster->freePos &= ~(CY_I3C_BIT(idx)); - (i3cMaster->devCount)++; - } - } - } - - else - { - I3C_CORE_SLV_EVENT_STATUS(base) &= (~I3C_CORE_SLV_EVENT_STATUS_HJ_EN_Msk); - - //Sets the number of entries in the Receive FIFO that trigger the interrupt to 1 word - I3C_CORE_DATA_BUFFER_THLD_CTRL(base) &= _VAL2FLD(I3C_CORE_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD, 5) | - _VAL2FLD(I3C_CORE_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC, 1); - - Cy_I3C_SetInterruptMask(base, CY_I3C_SLV_INTR_Msk | CY_I3C_INTR_DEFSLV_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_SLV_INTR_Msk | CY_I3C_INTR_DEFSLV_STS); - } - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_I3C_SlaveInterrupt -****************************************************************************//** -* -* This is the interrupt function for the I3C configured in slave mode. -* This function should be called inside the user-defined interrupt service routine. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_SlaveInterrupt (I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t intrCause; - intrCause = Cy_I3C_GetInterruptStatus(base); - - if(0 != (CY_I3C_INTR_TX_BUFFER_THLD_STS & intrCause)) - { - SlaveHandleDataTransmit(base, context); - } - - if(0 != (CY_I3C_INTR_RX_BUFFER_THLD_STS & intrCause))//TBD - Add callbacks - { - //TBD - Check if the Rx buffer is configured or not - SlaveHandleDataReceive(base, context); - } - - if(0 != (CY_I3C_INTR_RESP_READY_STS & intrCause)) - { - SlaveRespReadyStsHandle(base, context); - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_RESP_READY_STS); - } - - if(0 != (CY_I3C_INTR_CCC_UPDATED_STS & intrCause)) - { - if(_FLD2VAL(I3C_CORE_SLV_EVENT_STATUS_MRL_UPDATED, I3C_CORE_SLV_EVENT_STATUS(base))) - { - context->cbEvents(CY_I3C_SLAVE_MAX_RD_LEN_UPDT_EVENT); - I3C_CORE_SLV_EVENT_STATUS(base) |= I3C_CORE_SLV_EVENT_STATUS_MRL_UPDATED_Msk; - } - else if(_FLD2VAL(I3C_CORE_SLV_EVENT_STATUS_MWL_UPDATED, I3C_CORE_SLV_EVENT_STATUS(base))) - { - context->cbEvents(CY_I3C_SLAVE_MAX_WR_LEN_UPDT_EVENT); - I3C_CORE_SLV_EVENT_STATUS(base) |= I3C_CORE_SLV_EVENT_STATUS_MWL_UPDATED_Msk; - } - else - { - context->cbEvents(CY_I3C_SLAVE_CCC_REG_UPDATED_EVENT); - } - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_CCC_UPDATED_STS); - } - - if(0 != (CY_I3C_INTR_DYN_ADDR_ASSGN_STS & intrCause)) - { - context->cbEvents(CY_I3C_SLAVE_ASSIGNED_DYN_ADDR_EVENT); - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_DYN_ADDR_ASSGN_STS); - } - - /* Read request from the master */ - if(0 != (CY_I3C_INTR_READ_REQ_RECV_STS & intrCause)) - { - if(NULL != (context->cbEvents)) - { - //Callback - in case of error - - uint32_t event; - event = CY_I3C_SLAVE_NO_VALID_CMD_IN_CMDQ_EVENT; - if(_FLD2VAL(I3C_CORE_CCC_DEVICE_STATUS_DATA_NOT_READY, I3C_CORE_CCC_DEVICE_STATUS(base))) - { - event |= CY_I3C_SLAVE_DATA_NOT_READY_EVENT; - } - context->cbEvents(event); - } - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - } - - if(0 != (CY_I3C_INTR_BUSOWNER_UPDATED_STS & intrCause)) - { - if(NULL != (context->cbEvents)) - { - //Callback - in case of error - context->cbEvents(CY_I3C_CONTROLLER_ROLE_UPDATED_EVENT); - } - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - return; - } - - if(0 != (CY_I3C_INTR_DEFSLV_STS & intrCause)) - { - uint32_t idx; - idx = context->slaveRxBufferCnt; - - I3C_CORE_DEV_CHAR_TABLE_POINTER(base) |= _VAL2FLD(I3C_CORE_DEV_CHAR_TABLE_POINTER_PRESENT_DEV_CHAR_TABLE_INDX,idx); - if(NULL != (context->cbEvents)) - { - //Callback - in case of error - context->cbEvents(CY_I3C_DEFSLV_EVENT); - } - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - return; - } -} - - -/******************************************************************************* -* Function Name: Cy_I3C_MasterInterrupt -****************************************************************************//** -* -* This is the interrupt function for the I3C configured in master mode. -* This function should be called inside the user-defined interrupt service routine. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -void Cy_I3C_MasterInterrupt (I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t intrCause; - intrCause = Cy_I3C_GetInterruptStatus(base); - - if(0 != (CY_I3C_INTR_RESP_READY_STS & intrCause)) - { - if(0 != (CY_I3C_INTR_TRANSFER_ERR_STS & intrCause)) - { - uint32_t respCmdPort, errorEvent; - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - errorEvent = ResponseErrorEvent(respCmdPort); - context->masterStatus |= CY_I3C_MASTER_HALT_STATE; - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - context->state = CY_I3C_IDLE; - - if(NULL != (context->cbEvents)) - { - //Callback - in case of error - context->cbEvents(errorEvent); - } - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); //Check if this clearing in not harmful - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - return; - } - - else - { - MasterRespReadyStsHandle(base, context); - } - - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - return; - } - - if(0 != (CY_I3C_INTR_TRANSFER_ABORT_STS & intrCause)) - { - //Test - Check: Does this set the TRANSFER_ERROR_STS and the error field too? - - context->masterStatus |= CY_I3C_MASTER_XFER_ABORTED | CY_I3C_MASTER_HALT_STATE; - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - context->state = CY_I3C_IDLE; - - I3C_CORE_RESET_CTRL(base) = I3C_CORE_RESET_CTRL_SOFT_RST_Msk; - - if(NULL != context->cbEvents) - { - context->cbEvents(CY_I3C_XFER_ABORTED_ERROR_EVENT); - } - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - - return; - } - - if(0 != (CY_I3C_INTR_IBI_BUFFER_THLD_STS & intrCause)) - { - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - MasterHandleIBIInterrupt(base, context); - - return; - } - - if(0 != (CY_I3C_INTR_BUSOWNER_UPDATED_STS & intrCause)) - { - if(NULL != (context->cbEvents)) - { - //Callback - in case of error - context->cbEvents(CY_I3C_CONTROLLER_ROLE_UPDATED_EVENT); - } - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - return; - } - -} - -/******************************************************************************* -* Function Name: Cy_I3C_DeepSleepCallback -****************************************************************************//** -* -* This function handles transition of I3C controller into and out of -* deep sleep mode. -* -* \param callbackParams -* The pointer to the callback parameters structure -* \ref cy_stc_syspm_callback_params_t. -* -* \param mode -* Callback mode, see \ref cy_en_syspm_callback_mode_t -* -* \return -* \ref cy_en_syspm_status_t -* -*******************************************************************************/ -cy_en_syspm_status_t Cy_I3C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode) -{ - //TBD - return CY_SYSPM_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_I3C_HibernateCallback -****************************************************************************//** -* -* This function handles transition of I3C controller into hibernate mode. -* -* \param callbackParams -* The pointer to the callback parameters structure -* \ref cy_stc_syspm_callback_params_t. -* -* \param mode -* Callback mode, see \ref cy_en_syspm_callback_mode_t -* -* \return -* \ref cy_en_syspm_status_t -* -*******************************************************************************/ -cy_en_syspm_status_t Cy_I3C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode) -{ - //TBD - return CY_SYSPM_SUCCESS; -} - -/******************************************************************************* -* Function Name: even_parity -****************************************************************************//** -* -* Finds the parity of the address. -* -* \param address -* 7-bit right justified address. -* -* \return -* The parity of the address. -* 0: odd number of one bits in the address -* 1: even number of one bits in the address. -* -*******************************************************************************/ -static uint8_t even_parity(uint8_t address) -{ - address ^= address >> 4; - address &= 0xF; - - return ((0x9669 >> address) & 1); -} - -/******************************************************************************* -* Function Name: ffs -****************************************************************************//** -* -* Finds the position of the first set bit in the given value. -* -* \param address -* 7-bit right justified address. -* -* \return -* The position of the first set bit. -* -*******************************************************************************/ -static uint32_t ffs(uint32_t value) -{ - uint32_t r = 1; - - if (!value) - return 0; - if (!(value & 0xffff)) { - value >>= 16; - r += 16; - } - if (!(value & 0xff)) { - value >>= 8; - r += 8; - } - if (!(value & 0xf)) { - value >>= 4; - r += 4; - } - if (!(value & 3)) { - value >>= 2; - r += 2; - } - if (!(value & 1)) { - value >>= 1; - r += 1; - } - return r; -} - -/******************************************************************************* -* Function Name: SetAddrslotStatus -****************************************************************************//** -* -* Marks the status of the address parameter as defined -* by \ref cy_en_i3c_addr_slot_status_t. -* -* \param address -* 7-bit right justified address. -* -* \param status -* The status to be assigned to the address. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_config_t allocated -* by the user. The structure is used during the I2C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void SetAddrslotStatus(uint8_t address, cy_en_i3c_addr_slot_status_t status, cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint8_t bitPos = address * 2; - unsigned long *ptr; - - ptr = i3cMaster->addrslotsStatusArray + (bitPos / CY_I3C_BITS_PER_LONG); - *ptr &= ~((unsigned long)CY_I3C_ADDR_SLOT_STATUS_MASK << (bitPos % CY_I3C_BITS_PER_LONG)); - *ptr |= (unsigned long)status << (bitPos % CY_I3C_BITS_PER_LONG); -} - -/******************************************************************************* -* Function Name: InitAddrslots -****************************************************************************//** -* -* Initializes the status \ref cy_en_i3c_addr_slot_status_t of the addresses. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_config_t allocated -* by the user. The structure is used during the I2C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void InitAddrslots(cy_stc_i3c_context_t *context) -{ - uint8_t index; - - //Set all the addresses as free initially - for(index = 0; index < ((CY_I3C_MAX_ADDR + 1) * 2) / CY_I3C_BITS_PER_LONG; index++) - { - SetAddrslotStatus(index, CY_I3C_ADDR_SLOT_FREE, context); - } - - //assigning reserved status for addresses from 1-7 - - for(index = 0; index < 8; index++) - { - SetAddrslotStatus(index, CY_I3C_ADDR_SLOT_RSVD, context); - } - - // assigning reserved status for the broadcast and other I3C reserved broadcast addresses - - SetAddrslotStatus(CY_I3C_BROADCAST_ADDR, CY_I3C_ADDR_SLOT_RSVD, context); - - for (index = 0; index < 7; index++) - { - SetAddrslotStatus(CY_I3C_BROADCAST_ADDR ^ CY_I3C_BIT(index), CY_I3C_ADDR_SLOT_RSVD, context); - } - -} - -/******************************************************************************* -* Function Name: DeInitAddrslots -****************************************************************************//** -* -* Sets the status of the addresses to free. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void DeInitAddrslots(cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - uint8_t index; - // Sets status of all the addresses free - for(index = 0; index < (((CY_I3C_MAX_ADDR + 1) * 2) / CY_I3C_BITS_PER_LONG); index++) - { - i3cMaster->addrslotsStatusArray[index] = 0UL; - } -} - -/******************************************************************************* -* Function Name: GetI2CDevAddrPos -****************************************************************************//** -* -* Obtains the position of the I2C device with the specified static address -* in the DAT. -* -* \param base -* The pointer to the I3C instance. -* -* \param staticAddress -* The static address of the I2C device. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Position of the I2C device in the DAT. -* -*******************************************************************************/ -static uint32_t GetI2CDevAddrPos(I3C_CORE_Type *base, uint8_t staticAddress, cy_stc_i3c_context_t *context) -{ - uint8_t index; - for(index = 0; index < CY_I3C_MAX_DEVS; index++) - { - if(staticAddress == Cy_I3C_ReadStaticAddrFromDAT(base, index)) - return index; - } - - return CY_I3C_BAD_PARAM; -} - -/******************************************************************************* -* Function Name: GetI3CDevAddrPos -****************************************************************************//** -* -* Obtains the position of the I3C device with the specified dynamic address -* in the DAT. -* -* \param base -* The pointer to the I3C instance. -* -* \param dynamicAddress -* The dynamic address of the I3C device. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Position of the I3C device in the DAT. -* -*******************************************************************************/ -static uint32_t GetI3CDevAddrPos(I3C_CORE_Type *base, uint8_t dynamicAddress, cy_stc_i3c_context_t *context) -{ - uint8_t index; - for(index = 0; index < CY_I3C_MAX_DEVS; index++) - { - uint32_t ret; - ret = Cy_I3C_ReadDynAddrFromDAT(base, index); - if(dynamicAddress == ret) - return index; - } - - return CY_I3C_BAD_PARAM; -} - -/******************************************************************************* -* Function Name: GetDATFreePos -****************************************************************************//** -* -* Obtains the position of free location in the DAT. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* Position of the free location in the DAT. -* -*******************************************************************************/ -static uint32_t GetDATFreePos(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t ret; - ret = ffs(context->i3cMaster.freePos) - 1; - - return ret; -} - -/******************************************************************************* -* Function Name: GetAaddrslotStatus -****************************************************************************//** -* -* Obtains the status of the address parameter. -* -* \param address -* 7-bit right justified address. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_addr_slot_status_t. -* -*******************************************************************************/ -static cy_en_i3c_addr_slot_status_t GetAaddrslotStatus(uint8_t address, cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - int status, bitPos = address * 2; - - if (address > CY_I3C_MAX_ADDR) - return CY_I3C_ADDR_SLOT_RSVD; - - status = i3cMaster->addrslotsStatusArray[bitPos / CY_I3C_BITS_PER_LONG]; - status >>= bitPos % CY_I3C_BITS_PER_LONG; - - return (cy_en_i3c_addr_slot_status_t)(status & CY_I3C_ADDR_SLOT_STATUS_MASK); -} - -/******************************************************************************* -* Function Name: ResponseError -****************************************************************************//** -* -* Provides the error type recieved in the response status. -* -* \param respCmd. -* The value read from the response queue port register -* -* \return -* \ref cy_en_i3c_status_t. - -*******************************************************************************/ -static cy_en_i3c_status_t ResponseError(uint32_t respCmd) -{ - uint8_t error; - error = _FLD2VAL(I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS, respCmd); - int ret = 0U;//DOUBT - What should be the default return value? - - switch (error) - { - case 1: ret = CY_I3C_MASTER_CRC_ERROR; break; - case 2: ret = CY_I3C_MASTER_PARITY_ERROR; break; - case 3: ret = CY_I3C_MASTER_FRAME_ERROR; break; - case 4: ret = CY_I3C_MASTER_BROADCAST_ADDR_NACK_ERROR; break; - case 5: ret = CY_I3C_MASTER_ADDR_NACK_ERROR; break; //This is same as ERROR M2 - case 6: ret = CY_I3C_MASTER_BUFFER_OVERFLOW_ERROR; break; - case 8: ret = CY_I3C_MASTER_XFER_ABORTED_ERROR; break; - case 9: ret = CY_I3C_MASTER_I2C_SLV_WDATA_NACK_ERROR; break; - default: /* Unknow Error */ break; - } - return (cy_en_i3c_status_t)ret; -} - -/******************************************************************************* -* Function Name: ResponseErrorEvent -****************************************************************************//** -* -* Provides error events to be passed by \ref cy_cb_i3c_handle_events_t callback -* based on the type of error type received in the response status. -* -* \param respCmd. -* The value read from the response queue port register. -* -* \return -* \ref group_i3c_macros_callback_events. - -******************************************************************************/ -static uint32_t ResponseErrorEvent(uint32_t respCmd) -{ - uint8_t error; - error = _FLD2VAL(I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS, respCmd); - uint32_t ret = 0; //DOUBT - What should be the default return value? - - switch (error) - { - case 1: ret = CY_I3C_CRC_ERROR_EVENT; break; - case 2: ret = CY_I3C_PARITY_ERROR_EVENT; break; - case 3: ret = CY_I3C_FRAME_ERROR_EVENT; break; - case 4: ret = CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT; break; - case 5: ret = CY_I3C_ADDR_NACK_ERROR_EVENT; break; - case 6: ret = CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT; break; - case 8: ret = CY_I3C_XFER_ABORTED_ERROR_EVENT; break; - case 9: ret = CY_I3C_I2C_SLV_WDATA_NACK_ERROR_EVENT; break; - case 10: ret = CY_I3C_MASTER_EARLY_TERMINATION_EVENT; break; - default: /* Unknown Error */ break; - - } - return ret; -} - -/******************************************************************************* -* Function Name: WriteArray -****************************************************************************//** -* -* Places an array of data in the transmit FIFO. -* This function does not block. It returns how many data elements were -* placed in the transmit FIFO. -* -* \param base -* The pointer to the I3C instance. -* -* \param buffer -* The pointer to data to place in the transmit FIFO. -* -* \param size -* The number of data elements to transmit. -* -*******************************************************************************/ -static void WriteArray(I3C_CORE_Type *base, void *buffer, uint32_t size) -{ - uint32_t *buf = buffer; - uint32_t index; - - /*Put data in TX FIFO */ - for(index = 0UL; index < (size/4); ++index) - { - Cy_I3C_WriteTxFIFO(base, *(buf + index)); - } - - if(size & 3) - { - uint8_t cnt = size & 3; - uint8_t *ptr; - uint32_t value = 0UL; - - ptr = (uint8_t *)(buf + index); - - for(index = 0; index < cnt; index++) - { - value |= (*ptr) << (index * 8); - ptr++; - } - Cy_I3C_WriteTxFIFO(base, value); - } -} - - -/******************************************************************************* -* Function Name: ReadArray -****************************************************************************//** -* -* Reads an array of data out of the receive FIFO. -* This function does not block. -* -* \param base -* The pointer to the I3C instance. -* -* \param buffer -* The pointer to location to place data read from receive FIFO. -* -* \param size -* The number of data elements to read from the receive FIFO. -* -*******************************************************************************/ -static void ReadArray(I3C_CORE_Type *base, void *buffer, uint32_t size) -{ - uint32_t index; - uint32_t *buf = buffer; - - for(index = 0UL; index < size/4; ++index) - { - *(buf + index) = Cy_I3C_ReadRxFIFO(base); - } - - if(size & 3) - { - *(buf + index) = Cy_I3C_ReadRxFIFO(base); - } -} - -/******************************************************************************* -* Function Name: MasterHandleDataTransmit -****************************************************************************//** -* -* Loads TX FIFO with data provided by \ref Cy_I3C_MasterWrite. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void MasterHandleDataTransmit(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if (context->masterBufferSize > 1UL) - { - /* Get the number of bytes to copy into TX FIFO */ - uint32_t numToCopy = context->masterBufferSize; - - /* Write data into TX FIFO */ - WriteArray(base, context->masterBuffer, numToCopy); - } -} - -/******************************************************************************* -* Function Name: MasterHandleDataReceive -****************************************************************************//** -* -* Reads data from RX FIFO into the buffer provided by \ref Cy_I3C_MasterRead. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void MasterHandleDataReceive(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t numToRead; - numToRead = context->masterBufferSize; - //Read from the RX FIFO - ReadArray(base, context->masterBuffer, numToRead); -} - - -/******************************************************************************* -* Function Name: RetrieveI3CDeviceInfo -****************************************************************************//** -* -* To retrieve device information which includes: max write len, max read len, -* max data speed, HDR capability, BCR, DCR and PID. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDevice -* The pointer to the I3C device description structure \ref cy_stc_i3c_device_t. -* -* \basicInfo -* true: obtains BCR, DCR and PID of the device -* false: otherwise -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static void RetrieveI3CDeviceInfo(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, bool basicInfo, cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_ccc_cmd_t cccCmd; - cy_stc_i3c_ccc_payload_t payload; - cccCmd.address = i3cDevice->dynamicAddress; - cccCmd.data = &payload; - - if(true == basicInfo) - { - cy_stc_i3c_ccc_getbcr_t bcr; - cccCmd.data->data = &bcr; - cccCmd.cmd = CY_I3C_CCC_GETBCR; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - i3cDevice->bcr = bcr.bcr; - - cy_stc_i3c_ccc_getdcr_t dcr; - cccCmd.data->data = &dcr; - cccCmd.cmd = CY_I3C_CCC_GETDCR; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - i3cDevice->dcr = dcr.dcr; - - cy_stc_i3c_ccc_getpid_t pid; - cccCmd.data->data = &pid; - cccCmd.cmd = CY_I3C_CCC_GETPID; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - - uint8_t *ptr; - uint8_t cnt, shift; - ptr = pid.pid; - i3cDevice->provisonalID = 0; - - for(cnt = 0; cnt < sizeof(pid); cnt++) - { - shift = (sizeof(pid) - cnt - 1) * 8; - (i3cDevice->provisonalID) |= ((uint64_t)(*ptr)) << shift; - ptr++; - } - } - - //Get max read len - cy_stc_i3c_ccc_mrwl_t mrwl; - cccCmd.data->data = &mrwl; - cccCmd.cmd = CY_I3C_CCC_GETMRL; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - - i3cDevice->mrl = mrwl.len; - - //Get max write len - cccCmd.cmd = CY_I3C_CCC_GETMWL; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - i3cDevice->mwl = mrwl.len; - - if(0 != (CY_I3C_CORE_BCR_MAX_DATA_SPEED_LIM_Msk & (i3cDevice->bcr))) - { - cy_stc_i3c_ccc_getmxds_t mxds; - i3cDevice->speedLimit = true; - cccCmd.data->data = &mxds; - cccCmd.cmd = CY_I3C_CCC_GETMXDS; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - i3cDevice->maxReadDs = mxds.maxrd; - i3cDevice->maxWriteDs = mxds.maxwr; - i3cDevice->maxReadTurnaround[0] = mxds.maxrdturn[0]; - i3cDevice->maxReadTurnaround[1] = mxds.maxrdturn[1]; - i3cDevice->maxReadTurnaround[2] = mxds.maxrdturn[2]; - } - - else - { - i3cDevice->speedLimit = false; - } - - if(0!= (CY_I3C_CORE_BCR_HDR_CAP_Msk & (i3cDevice->bcr))) - { - cy_stc_i3c_ccc_gethdrcap_t hdrcap; - i3cDevice->hdrSupport = true; - cccCmd.data->data = &hdrcap; - cccCmd.cmd = CY_I3C_CCC_GETHDRCAP; - Cy_I3C_SendCCCCmd(base, &cccCmd, context); - i3cDevice->HDRCap = hdrcap.modes; - } - - else - { - i3cDevice->hdrSupport = false; - } - -} - -/******************************************************************************* -* Function Name: CCC_Set -****************************************************************************//** -* -* Prepares commands for scheduling CCC transfers where the CCCs are not required -* to retrieve data from the slave device.. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void CCC_Set(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint8_t pos = 0; //pos = 0 in case of broadcast command. - uint8_t dataLen = cccCmd->data->len; - cy_stc_i3c_ccc_t cmd; - - //Check if the cmd is a Direct or broadcast command; - //If Direct command, get the address offset in the DAT - if(cccCmd->address & CY_I3C_CCC_DIRECT) - pos = GetI3CDevAddrPos(base, cccCmd->address, context); - - uint8_t validBytes; - uint8_t *data; - data = (uint8_t *)cccCmd->data->data; - - switch(dataLen) - { - case 0: { cmd.cmdHigh = 0; - cmd.cmdLow = 0; - break; } - - case 1: { - validBytes = CY_I3C_BYTE_STROBE1; - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, validBytes) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0,*data); - - cmd.cmdLow = I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk; - break; } - case 2: { - validBytes = CY_I3C_BYTE_STROBE2; - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, validBytes) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0,*(data + 1)) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_1,*(data)); - - cmd.cmdLow = I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk; - - break; } - case 3: { - validBytes = CY_I3C_BYTE_STROBE3; - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_SHORT_DATA_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_BYTE_STRB, validBytes) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_0,*(data+2))| - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_1,*(data + 1)) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_SHORT_DATA_ARG_DATA_BYTE_2,*data); - - cmd.cmdLow = I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SDAP_Msk; - - break; } - default: { - //Commands with greater than 3 bytes of payload - //Commands without payload; Also broadcast commands - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, dataLen); - - cmd.cmdLow = 0UL; - break; } - } - - cmd.cmdLow |= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CP_Msk | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CMD, cccCmd->cmd) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; -} - -/******************************************************************************* -* Function Name: CCC_Get -****************************************************************************//** -* -* Prepares commands for scheduling CCC transfers where the CCCs should retrieve -* data from the slave device. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param cmd -* The 64-bit command \ref cy_stc_i3c_ccc_t . -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void CCC_Get(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint8_t pos = 0; - cy_stc_i3c_ccc_t cmd; - uint8_t dataLen = cccCmd->data->len; - - //Direct command, get the address offset in the DAT - pos = GetI3CDevAddrPos(base, cccCmd->address, context); - - // DATA_LENGTH field indicates the expected number of bytes from the Slave. - // DATA_LENGTH should be provided by the calling API and not the user - - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, dataLen); - - - cmd.cmdLow = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CP_Msk | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CMD, cccCmd->cmd) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_RnW_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh ; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow ; -} - -/******************************************************************************* -* Function Name: enec_disec_ccc -****************************************************************************//** -* -* Enable/Disable Slave Events Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t enec_disec_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, false, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - /* Expects 1 byte of data */ - if(0 == cccCmd->data->len) - return CY_I3C_BAD_PARAM; - - CCC_Set(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, NULL, context); - - return retStatus; -} - -/******************************************************************************* -* Function Name: rstdaa_ccc -****************************************************************************//** -* -* Reset Dynamic Address Assignment Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t rstdaa_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - uint32_t pos = 0; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, false, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - CCC_Set(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, NULL, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - //handling of unicast command - if(CY_I3C_BROADCAST_ADDR != cccCmd->address) - { - pos = GetI3CDevAddrPos(base, cccCmd->address, context); - - Cy_I3C_WriteIntoDeviceAddressTable(base, pos, 0); - - context->i3cMaster.freePos |= CY_I3C_BIT(pos); - context->i3cMaster.devCount--; - - SetAddrslotStatus(cccCmd->address, CY_I3C_ADDR_SLOT_FREE, context); - } - - //handling of broadcast command - else - { - for(pos = 0; pos < (context->i3cMaster.devCount); pos++) - { - Cy_I3C_WriteIntoDeviceAddressTable(base, pos, 0); - - context->i3cMaster.freePos |= CY_I3C_BIT(pos); - context->i3cMaster.devCount--; - } - - DeInitAddrslots(context); - - } - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: setmrwl_ccc -****************************************************************************//** -* -* Set Maximum Read/Write Length Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t setmrwl_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint8_t pos, idx; - cy_en_i3c_status_t retStatus; - uint16_t *data; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, false, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - /* Expects 2 byte of data */ - if(0 == cccCmd->data->len) - return CY_I3C_BAD_PARAM; - - CCC_Set(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, NULL, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - if( CY_I3C_CCC_SETMRL(false) == cccCmd->cmd) //Set maximum read length for the target device - { - pos = GetI3CDevAddrPos(base, cccCmd->address, context); - data = (uint16_t *)(cccCmd->data->data); - context->devList[pos].i3cDevice.mrl = *data; - } - - else if(CY_I3C_CCC_SETMWL(false) == cccCmd->cmd) //Set maximum write length for the target device - { - pos = GetI3CDevAddrPos(base, cccCmd->address, context); - data = (uint16_t *)(cccCmd->data->data); - context->devList[pos].i3cDevice.mwl = *data; - } - - else if(CY_I3C_CCC_SETMRL(true) == cccCmd->cmd) //Set maximum read length for all the slave I3C devices - broadcast command - { - cy_stc_i3c_master_devlist_t *devList = context->devList; - for(idx = 0; idx < (Cy_I3C_GetI3CDeviceCount(base, context)); idx++) - { - if(!devList->i2c) - { - data = (uint16_t *)(cccCmd->data->data); - devList->i3cDevice.mrl = *data; - } - devList++; - } - } - - else //Set maximum write length for all the slave I3C devices - broadcast command - { - cy_stc_i3c_master_devlist_t *devList = context->devList; - for(idx = 0; idx < (Cy_I3C_GetI3CDeviceCount(base, context)); idx++) - { - if(!devList->i2c) - { - data = (uint16_t *)(cccCmd->data->data); - devList->i3cDevice.mwl = *data; - } - devList++; - } - } - - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - return CY_I3C_SUCCESS; - -} - -/******************************************************************************* -* Function Name: setda_ccc -****************************************************************************//** -* -* Prepares and sends commands into the command queue for SETDASA and SETNEWDA CCCs. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void setda_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint8_t pos; - uint8_t *data; - uint32_t value; - data = (uint8_t *)cccCmd->data->data; - - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR, *data) | - _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR, cccCmd->address); - - pos = GetDATFreePos(base, context); - Cy_I3C_WriteIntoDeviceAddressTable(base, pos, value); - - // Disbale the interrupt signals by clearing the bits - Cy_I3C_SetInterruptMask(base, 0UL); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base)= I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_ADDR_ASSGN_CMD | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_CMD, cccCmd->cmd) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_INDX, pos) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_DEV_COUNT, 1) | - I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_ADDR_ASSGN_CMD_TOC_Msk; - -} - -/******************************************************************************* -* Function Name: setdasa_ccc -****************************************************************************//** -* -* Set Dynamic Address from Static Address Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t setdasa_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint32_t pos ; - cy_en_i3c_status_t retStatus; - uint8_t dynAddr; - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - cy_stc_i3c_device_t i3cDevice; - - /* Expects 1 byte of data */ - if(0 == cccCmd->data->len) - return CY_I3C_BAD_PARAM; - - context->masterStatus |= CY_I3C_MASTER_DIRECTED_CCC_WR_XFER; - - pos = GetDATFreePos(base, context); - - setda_ccc(base, cccCmd, context); - - //Handling the response - retStatus = MasterHandleCCCResponse(base, NULL, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - dynAddr = *(uint8_t *)(cccCmd->data->data); - - i3cDevice.dynamicAddress = dynAddr; - i3cDevice.staticAddress = cccCmd->address; - - //Maintaining a local list of i3c devices - i3cDevice.bcr = 0; - SetAddrslotStatus(dynAddr, CY_I3C_ADDR_SLOT_I3C_DEV, context); - RetrieveI3CDeviceInfo(base, &i3cDevice, true, context); - Cy_I3C_UpdateI3CDevInList(&i3cDevice, pos, context); - - (i3cMaster->freePos) = ~ (CY_I3C_BIT(pos)); - (i3cMaster->devCount)++; - - //Update the local list - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: setnewda_ccc -****************************************************************************//** -* -* Set New Dynamic Address Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t setnewda_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint32_t pos, value; - cy_en_i3c_status_t retStatus; - uint8_t *data; - uint8_t parity; - - /* Expects 1 byte of data */ - if(0 == cccCmd->data->len) - return CY_I3C_BAD_PARAM; - - data = (uint8_t *)cccCmd->data->data; - - (*data) = (*data << 1); - - cccCmd->data->data = data; - - context->masterStatus |= CY_I3C_MASTER_DIRECTED_CCC_WR_XFER; - - CCC_Set(base, cccCmd, context); - - (*data) = (*data >> 1); - - //Handling the response - retStatus = MasterHandleCCCResponse(base, NULL, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - pos = GetI3CDevAddrPos(base, cccCmd->address, context); - - SetAddrslotStatus(*data, CY_I3C_ADDR_SLOT_I3C_DEV, context); - - context->devList[pos].i3cDevice.dynamicAddress = *data; //Updating the local list - - parity = even_parity(*data); - - (*data) |= (parity << 7); - - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR, *data); - - Cy_I3C_WriteIntoDeviceAddressTable(base, pos, value); //Updating the Device Address Table - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: entas_ccc -****************************************************************************//** -* -* Enter Activity State Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t entas_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; //response queue port - - retStatus = CCCSlaveAddressValidation(cccCmd->address, false, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - CCC_Set(base, cccCmd, context); - - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - - return retStatus; -} - -/******************************************************************************* -* Function Name: enthdr0_ccc -****************************************************************************//** -* -* Enter HDR0 Mode Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t enthdr0_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - if(CY_I3C_BROADCAST_ADDR != cccCmd->address) - return CY_I3C_BAD_PARAM; - - cccCmd->data->len = 0; - - context->masterStatus |= CY_I3C_MASTER_BROADCAST_CCC_WR_XFER; - - CCC_Set(base, cccCmd, context); - - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getmrwl_ccc -****************************************************************************//** -* -* Get Maximum Read/Write Length Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getmrwl_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - uint16_t data; - cy_stc_i3c_ccc_mrwl_t *mrwl; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*mrwl); //Expects 2 bytes of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; -/* if(sizeof(*mrwl) != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk)) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - //Read data from the FIFO to the data_field of the cmd structure - data = Cy_I3C_ReadRxFIFO(base); - data = CY_I3C_SWAP16(data); //MSB byte will be returned first and then LSB - - mrwl = (cy_stc_i3c_ccc_mrwl_t *)cccCmd->data->data; - mrwl->len = data; - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getpid_ccc -****************************************************************************//** -* -* Get Provisional ID Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getpid_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint8_t index; - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - uint8_t data[6]; - cy_stc_i3c_ccc_getpid_t *getpid; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*getpid); //Expects 2 bytes of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - /*if(sizeof(*getpid) != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk)) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - //Read data from the FIFO to the data_field of the cmd structure - ReadArray(base, data, sizeof(*getpid)); - getpid = (cy_stc_i3c_ccc_getpid_t *)cccCmd->data->data; - - for(index = 0; index< sizeof(*getpid); index++) - { - getpid->pid[5 - index] = data[index];//MSB byte will be received first - } - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getbcr_ccc -****************************************************************************//** -* -* Get Bus Characteristic Register Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getbcr_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - uint8_t data; - cy_stc_i3c_ccc_getbcr_t *getbcr; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*getbcr); //Expects 1 byte of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - -/* if(sizeof(*getbcr) != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk)) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - - //Read data from the FIFO to the data_field of the cmd structure - data = Cy_I3C_ReadRxFIFO(base); - - getbcr = (cy_stc_i3c_ccc_getbcr_t *)cccCmd->data->data; - getbcr->bcr = data; - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getdcr_ccc -****************************************************************************//** -* -* Get Bus Characteristic Register Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getdcr_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - uint8_t data; - cy_stc_i3c_ccc_getdcr_t *getdcr; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*getdcr); //Expects 1 byte of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - /*if(sizeof(*getdcr) != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk)) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - //Read data from the FIFO to the data_field of the cmd structure - data = Cy_I3C_ReadRxFIFO(base); - - getdcr = (cy_stc_i3c_ccc_getdcr_t *)cccCmd->data->data; - getdcr->dcr = data; - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getstatus_ccc -****************************************************************************//** -* -* Get Devie Status Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getstatus_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - uint16_t data; - cy_stc_i3c_ccc_getstatus_t *getStatus; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*getStatus); //Expects 2 bytes of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - -/* if(sizeof(*getStatus) != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk)) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - //Read data from the FIFO to the data_field of the cmd structure - data = Cy_I3C_ReadRxFIFO(base); - data = CY_I3C_SWAP16(data); - - getStatus = (cy_stc_i3c_ccc_getstatus_t *)cccCmd->data->data; - getStatus->status = data; - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getmxds_ccc -****************************************************************************//** -* -* Get Max Data Speed Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getmxds_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - - uint8_t idx; - uint16_t data; - uint8_t dataMTR[5]; - uint32_t recvDataLen; - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - cy_stc_i3c_ccc_getmxds_t *getmxds; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*getmxds); //Expects 2 or 5 bytes of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - recvDataLen = respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk; - if(!((2 & recvDataLen) || (5 & recvDataLen))) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC - - //Read data from the FIFO to the data_field of the cmd structure - - if(2 == recvDataLen) - { - data = Cy_I3C_ReadRxFIFO(base); - getmxds = (cy_stc_i3c_ccc_getmxds_t *)cccCmd->data->data; - - getmxds->maxwr = (uint8_t)data; - getmxds->maxrd = (uint8_t)(data >> 8); - } - - //Read data from the FIFO to the data_field of the cmd structure - - else if(5 == recvDataLen) - { - ReadArray(base, dataMTR, sizeof(*getmxds)); - getmxds = (cy_stc_i3c_ccc_getmxds_t *)cccCmd->data->data; - getmxds->maxwr = dataMTR[0]; - getmxds->maxrd = dataMTR[1]; - - for( idx = 2; idx < sizeof(*getmxds); idx++) - { - getmxds->maxrdturn[idx - 2] = dataMTR[idx]; //CHECK - if MSB of maxrdturn is copied into first element of struct array while checking - } - } - return CY_I3C_SUCCESS; - -} - -/******************************************************************************* -* Function Name: gethdrcap_ccc -****************************************************************************//** -* -* Get HDR Capability Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t gethdrcap_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - uint32_t respCmdPort = 0; - uint8_t data; - cy_stc_i3c_ccc_gethdrcap_t *gethdrcap; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(*gethdrcap); //Expects 1 byte of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - -/* if(sizeof(*gethdrcap) != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk)) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - //Read data from the FIFO to the data_field of the cmd structure - data = Cy_I3C_ReadRxFIFO(base); - - gethdrcap = (cy_stc_i3c_ccc_gethdrcap_t *)cccCmd->data->data; - gethdrcap->modes = data; - - return CY_I3C_SUCCESS; -} - -/******************************************************************************* -* Function Name: getaccmst_ccc -****************************************************************************//** -* -* Get Accept Mastership Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t getaccmst_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - cy_en_i3c_status_t retStatus; - //uint32_t recvDataLen; - uint32_t respCmdPort = 0; - uint8_t data; - cy_stc_i3c_ccc_getaccmst_t *getaccmst; - - retStatus = CCCSlaveAddressValidation(cccCmd->address, true, context); - - if(retStatus != CY_I3C_SUCCESS) - return retStatus; - - cccCmd->data->len = sizeof(getaccmst); //Excepts 1 byte of data - - CCC_Get(base, cccCmd, context); - - retStatus = MasterHandleCCCResponse(base, &respCmdPort, context); - - if(CY_I3C_SUCCESS != retStatus) - return retStatus; - - -/* recvDataLen = respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk; - if(sizeof(*getaccmst) & recvDataLen) - return CY_I3C_MASTER_ERROR_M0; //ERROR_M0 - Illegally formatted CCC */ - - data = Cy_I3C_ReadRxFIFO(base); - - getaccmst = (cy_stc_i3c_ccc_getaccmst_t *)cccCmd->data->data; - getaccmst->newmaster = data; - - return CY_I3C_SUCCESS; - -} - - -/******************************************************************************* -* Function Name: defslvs_ccc -****************************************************************************//** -* -* Define List of Slaves Command. -* -* \param base -* The pointer to the I3C instance. -* -* \param cccCmd -* The pointer to the I3C CCC structure \ref cy_stc_i3c_ccc_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t defslvs_ccc(I3C_CORE_Type *base, cy_stc_i3c_ccc_cmd_t *cccCmd, cy_stc_i3c_context_t *context) -{ - uint8_t index; - cy_stc_i3c_master_t *i3cMaster = &(context->i3cMaster); - cy_stc_i3c_master_devlist_t *devList = context->devList; - uint8_t i3cDevCnt; - bool send = false; - cy_stc_i3c_ccc_defslvs_t defslvs; //Stores the list to be sent - the slaves list - cy_stc_i3c_ccc_dev_desc_t slaves[CY_I3C_MAX_DEVS]; - - //Where to get the master related info - like bcr, dcr and pid?! - // The data to this CCC is prepared here - - //Check for the presence of any secondary masters on the bus - i3cDevCnt = i3cMaster->devCount - i3cMaster->i2cDeviceCount; - - for(index = 0; index < (i3cDevCnt);) - { - if(!devList->i2c) - { - //it is an i3c device - if((devList->i3cDevice.bcr & CY_I3C_CORE_BCR_DEVICE_ROLE_Msk) == CY_I3C_CORE_BCR_I3C_MASTER) - { - //The device is secondary master capable - //Secondary Master will also have MASTER value in this field - send = true; - } - index++; - } - devList++; - } - - if(!send) - { - return CY_I3C_NO_SECONDARY_MASTER_DEVICES; - } - - context->masterStatus |= CY_I3C_MASTER_BROADCAST_CCC_WR_XFER; - - //Maintain the list of devices - devList = context->devList; - - for(index = 0; index < (i3cMaster->devCount); index++) - { - if(devList->i2c) - { - //i2c device - slaves[index].staticAddress = (devList->i2cDevice.staticAddress) << 1; - slaves[index].dynAddress = 0; - slaves[index].lvr = devList->i2cDevice.lvr; - slaves[index].bcr = 0; - } - - else - { - //i3c device - slaves[index].staticAddress = (devList->i3cDevice.staticAddress) << 1; - slaves[index].dynAddress = (devList->i3cDevice.dynamicAddress) << 1; - slaves[index].dcr = devList->i3cDevice.dcr; - slaves[index].bcr = devList->i3cDevice.bcr; - } - } - - //DOUBT - Where to get the master info from? - //defslvs.master = - defslvs.count = i3cMaster->devCount; //DOUBT - Should this count include the main master too? - defslvs.slaves = slaves; - - cccCmd->data->data = &(defslvs); - /* The second term here is the number of bytes holding the I3C Slaves' information */ - cccCmd->data->len = sizeof(defslvs) + ((sizeof(slaves)/CY_I3C_MAX_DEVS)*(index-1)) - sizeof(cy_stc_i3c_ccc_dev_desc_t); - - //Put the data into the TX fifo - WriteArray(base, &defslvs, cccCmd->data->len); - - CCC_Set(base, cccCmd, context); - - //Should the response be handled here? - return CY_I3C_SUCCESS; - -} - -/******************************************************************************* -* Function Name: MasterHDRWrite -****************************************************************************//** -* -* Writes data provided in the HDR command structure \ref cy_stc_i3c_hdr_cmd_t -* to a specific device in HDR Mode. -* -* \param base -* The pointer to the I3C instance. -* -* \param hdrCmd -* The pointer to the I3C HDR command structure \ref cy_stc_i3c_hdr_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t MasterHDRWrite(I3C_CORE_Type *base, cy_stc_i3c_hdr_cmd_t *hdrCmd, cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_ccc_t cmd; - uint32_t pos; - - //Clear the interrupts - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - //Reset the Tx FIFO - I3C_CORE_RESET_CTRL(base) |= I3C_CORE_RESET_CTRL_TX_FIFO_RST_Msk; - - pos = GetI3CDevAddrPos(base, context->destDeviceAddr, context); - - //Prepare the data for the transfer - MasterHandleDataTransmit(base, context); - - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, (context->masterBufferSize)); - - - cmd.cmdLow = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CP_Msk | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TID, CY_I3C_MASTER_HDR_WRITE_TID) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CMD, hdrCmd->code) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED, CY_I3C_HDR_DDR) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - - context->masterStatus |= CY_I3C_MASTER_HDR_DDR_WR_XFER; - context->state = CY_I3C_MASTER_TX; - - Cy_I3C_SetInterruptMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; - - return CY_I3C_SUCCESS; - -} - -/******************************************************************************* -* Function Name: MasterHDRWrite -****************************************************************************//** -* -* Reads data from a device specified by HDR command structure -* \ref cy_stc_i3c_hdr_cmd_t. -* -* \param base -* The pointer to the I3C instance. -* -* \param hdrCmd -* The pointer to the I3C HDR command structure \ref cy_stc_i3c_hdr_cmd_t. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t MasterHDRRead(I3C_CORE_Type *base, cy_stc_i3c_hdr_cmd_t *hdrCmd, cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_ccc_t cmd; - uint8_t pos; - - pos = GetI3CDevAddrPos(base, context->destDeviceAddr, context); - - cmd.cmdHigh = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_ARG | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_ARG_DATA_LENGTH, (context->masterBufferSize)); - - cmd.cmdLow = I3C_CORE_COMMAND_QUEUE_PORT_CMD_ATTR_TRANSFER_CMD | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CP_Msk | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TID, CY_I3C_MASTER_HDR_READ_TID) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_CMD, hdrCmd->code) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_DEV_INDX, pos) | - _VAL2FLD(I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_SPEED, CY_I3C_HDR_DDR) | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_RnW_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_ROC_Msk | - I3C_CORE_COMMAND_QUEUE_PORT_TRANSFER_CMD_TOC_Msk; - - context->masterStatus |= CY_I3C_MASTER_HDR_DDR_RD_XFER; - context->state = CY_I3C_MASTER_RX; - - Cy_I3C_SetInterruptMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - Cy_I3C_SetInterruptStatusMask(base, (CY_I3C_INTR_TRANSFER_ERR_STS | CY_I3C_INTR_RESP_READY_STS)); - - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdHigh; - I3C_CORE_COMMAND_QUEUE_PORT(base) = cmd.cmdLow; - - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: MasterRespReadyStsHandle -****************************************************************************//** -* -* Handles the response queue ready status interrupt \ref group_i3c_intr_macros -* for master mode of operation. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void MasterRespReadyStsHandle(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t respCmdPort; - uint32_t tid; - - - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - tid = _FLD2VAL(I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_TID, respCmdPort); - - - /* Handling the receive response for Master SDR WRITE transfer */ - /* --------------------SDR/HDR WRITE TRANSFER----------------*/ - if((CY_I3C_MASTER_SDR_WRITE_TID == tid) || (CY_I3C_MASTER_HDR_WRITE_TID == tid)) - { - MasterHandleWriteInterrupt(base, respCmdPort, context); - } - - /* Handling the receive response for Master SDR READ transfer */ - /* --------------------SDR/HDR READ TRANSFER----------------*/ - - else if((CY_I3C_MASTER_SDR_READ_TID == tid) || (CY_I3C_MASTER_HDR_READ_TID == tid)) - { - MasterHandleReadInterrupt(base, respCmdPort, context); - } - - else - { - //Unkonwn TID - //Do Nothing - } -} - - -/******************************************************************************* -* Function Name: MasterHandleWriteInterrupt -****************************************************************************//** -* -* Handles the response queue ready status interrupt \ref group_i3c_intr_macros -* with HDR/SDR write TID \ref cy_en_i3c_tid_t in the response status. -* -* \param base -* The pointer to the I3C instance. -* -* \param respCmdPort -* The value read from the response queue port register. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static void MasterHandleWriteInterrupt(I3C_CORE_Type *base, uint32_t respCmdPort, cy_stc_i3c_context_t *context) -{ - //Expected number of bytes were not transmitted, WRITE terminated early - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - context->state = CY_I3C_IDLE; - - uint32_t dataLen; - - dataLen = (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk); - - if(NULL != context->cbEvents) - { - (dataLen == 0) ? context->cbEvents(CY_I3C_MASTER_WR_CMPLT_EVENT): context->cbEvents(CY_I3C_MASTER_WR_EARLY_TERMINATION_EVENT); - } -} - -/******************************************************************************* -* Function Name: MasterHandleReadInterrupt -****************************************************************************//** -* -* Handles the response queue ready status interrupt \ref group_i3c_intr_macros -* with HDR/SDR read TID \ref cy_en_i3c_tid_t in the response status. -* -* \param base -* The pointer to the I3C instance. -* -* \param respCmdPort -* The value read from the response queue port register. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static void MasterHandleReadInterrupt(I3C_CORE_Type *base, uint32_t respCmdPort, cy_stc_i3c_context_t *context) -{ - if(respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_DATA_LENGTH_Msk) - { - MasterHandleDataReceive(base, context); - context->state = CY_I3C_IDLE; - context->masterStatus &= (~CY_I3C_MASTER_BUSY); - - if(NULL != context->cbEvents) - { - context->cbEvents(CY_I3C_MASTER_RD_CMPLT_EVENT); - } - } -} - -/******************************************************************************* -* Function Name: MasterHandleIBIInterrupt -****************************************************************************//** -* -* Handles the IBI interrupts \ref group_i3c_intr_macros. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void MasterHandleIBIInterrupt(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t ibiData; - uint8_t ibiType, ibiStatus; - cy_stc_i3c_ibi_t ibiCallback; - - ibiData = I3C_CORE_IBI_QUEUE_STATUS(base); - - ibiType = _FLD2VAL(I3C_CORE_IBI_QUEUE_STATUS_IBI_ID, ibiData); - ibiStatus = _FLD2VAL(I3C_CORE_IBI_QUEUE_STATUS_IBI_RESP_STS, ibiData); - - /* Hot-join */ - if(CY_I3C_IBI_TYPE_HOT_JOIN(ibiType)) - { - ibiCallback.event = CY_I3C_IBI_HOTJOIN; - ibiCallback.slaveAddress = 0; - ibiCallback.status = (0 == ibiStatus) ? (uint32_t)CY_I3C_MASTER_HOTJOIN_IBI_ACK: (uint32_t)CY_I3C_MASTER_IBI_NACK; - - if(NULL != context->cbIbi) - { - context->cbIbi(&ibiCallback); - } - } - - /* Mastership request */ - else if(CY_I3C_IBI_TYPE_MASTERSHIP_REQUEST(ibiType)) - { - ibiCallback.event = CY_I3C_IBI_MASTER_REQ; - ibiCallback.slaveAddress = (uint8_t)(_FLD2VAL(I3C_CORE_IBI_QUEUE_STATUS_IBI_ID, ibiData) & 0x7FUL); //Check the msb/lsb alignment - ibiCallback.status = (0 == ibiStatus) ? (uint32_t)CY_I3C_MASTER_MR_IBI_ACK : (uint32_t)CY_I3C_MASTER_IBI_NACK; - - if(NULL != context->cbIbi) - { - context->cbIbi(&ibiCallback); - } - } - - /* Slave Interrupt Request */ - else if(CY_I3C_IBI_TYPE_SIR_REQUEST(ibiType)) - { - ibiCallback.event = CY_I3C_IBI_SIR; - ibiCallback.slaveAddress = (uint8_t)(_FLD2VAL(I3C_CORE_IBI_QUEUE_STATUS_IBI_ID, ibiData) & 0x7FUL); - ibiCallback.status = (0 == ibiStatus) ? (uint32_t)CY_I3C_MASTER_SIR_IBI_ACK : (uint32_t)CY_I3C_MASTER_IBI_NACK; - - if(NULL != context->cbIbi) - { - context->cbIbi(&ibiCallback); - } - } -} - - -/******************************************************************************* -* Function Name: RearrangeAddrTable -****************************************************************************//** -* -* Rearranges the DAT and local list of devices /ref cy_stc_i3c_master_devlist_t -* when a device detaches from the bus and thus maintaining continuous free -* locations on the top of the DAT and local list of devices. -* -* \param base -* The pointer to the I3C instance. -* -* \param devIndex -* The position of the device being detached. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t RearrangeAddrTable(I3C_CORE_Type *base, uint32_t devIndex, cy_stc_i3c_context_t *context) -{ - cy_stc_i3c_device_t i3cDeviceTop; - cy_stc_i2c_device_t i2cDeviceTop; - uint32_t topDevPos, value; - - - topDevPos = (context->i3cMaster.devCount) - 1; - //Case where the device being detached is not the top device on the list - if(devIndex != topDevPos) - { - /* - 1. Check if the top device is an i2c device or i3c device - 2. Update the DAT and the local list - 3. Also check for the case if the device to be detached is the top most device? Then do not perform the exchange - */ - if(context->devList[topDevPos].i2c) - { - //Top device is an i2c device - - //Moving the top device to the detached device position - i2cDeviceTop = context->devList[topDevPos].i2cDevice; - context->devList[devIndex].i2cDevice=i2cDeviceTop; - context->devList[devIndex].i2c = true; - - //Erase the top position entries and mark the position free - context->i3cMaster.freePos |= CY_I3C_BIT(topDevPos); - - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR, i2cDeviceTop.staticAddress) | - I3C_CORE_DEV_ADDR_TABLE_LOC1_LEGACY_I2C_DEVICE_Msk; - - Cy_I3C_WriteIntoDeviceAddressTable(base, devIndex, value); - - Cy_I3C_WriteIntoDeviceAddressTable(base, topDevPos, 0UL); - } - - else - { - //Top Device is an i3c device - - //Moving the top device to the detached device position - i3cDeviceTop = context->devList[topDevPos].i3cDevice; - context->devList[devIndex].i3cDevice = i3cDeviceTop; - context->devList[devIndex].i2c = false; - - //Erase the top position entries and mark the position free - context->i3cMaster.freePos |= CY_I3C_BIT(topDevPos); - - value = _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR, i3cDeviceTop.dynamicAddress) | - _VAL2FLD(I3C_CORE_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR, i3cDeviceTop.staticAddress); - - Cy_I3C_WriteIntoDeviceAddressTable(base, devIndex, value); - - Cy_I3C_WriteIntoDeviceAddressTable(base, topDevPos, 0UL); - } - } - - //Case where the device getting detached is the top device on the list and thus no rearrangement is not required - else - { - Cy_I3C_WriteIntoDeviceAddressTable(base, devIndex, 0UL); - - context->i3cMaster.freePos |= CY_I3C_BIT(devIndex); - } - - return CY_I3C_SUCCESS; -} - - -/******************************************************************************* -* Function Name: DeviceIBIControl -****************************************************************************//** -* -* Handles enabling and disabling of IBI events from specified devices. -* -* \param base -* The pointer to the I3C instance. -* -* \param i3cDevice -* The pointer to the i3c device description structure \ref cy_stc_i3c_device_t. -* -* \param cccCmd -* The CCC command to be sent ENEC/DISEC. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t DeviceIBIControl(I3C_CORE_Type *base, cy_stc_i3c_device_t *i3cDevice, uint8_t cccCmd, cy_stc_i3c_context_t *context) -{ - uint32_t sirmap, bitpos, mrmap; - cy_en_i3c_status_t retStatus; - cy_stc_i3c_ccc_cmd_t cmd; - cy_stc_i3c_ccc_events_t i3cCccENEC; - cy_stc_i3c_ccc_payload_t payload; - - //Sending DISEC command - i3cCccENEC.events = CY_I3C_CCC_EVENT_SIR | CY_I3C_CCC_EVENT_MR; - cmd.cmd = cccCmd; - cmd.data = &payload; - cmd.data->len = sizeof(i3cCccENEC); - cmd.data->data = &(i3cCccENEC.events); - cmd.address = i3cDevice->dynamicAddress; - - retStatus = enec_disec_ccc(base, &cmd, context); //Should the response be checked for any errors? - - //In case of successful CCC command - if(retStatus == CY_I3C_SUCCESS) - { - sirmap = I3C_CORE_IBI_SIR_REQ_REJECT(base); - bitpos = CY_I3C_IBI_SIR_REQ_ID(i3cDevice->dynamicAddress); - sirmap |= ((1UL) << bitpos); //Setting the corresponding bit to 1: 1 -> Nack the SIR from the corresponding device - I3C_CORE_IBI_SIR_REQ_REJECT(base) = sirmap; - - mrmap = I3C_CORE_IBI_MR_REQ_REJECT(base); - mrmap |= ((1UL) << bitpos); //Setting the corresponding bit to 1: 1 -> Nack the MR from the corresponding device - I3C_CORE_IBI_MR_REQ_REJECT(base) = mrmap; - } - - return retStatus; -} - - -/******************************************************************************* -* Function Name: MasterHandleCCCResponse -****************************************************************************//** -* -* Validates whether the slave address is an I3C device address on the bus/ -* broadcast address. -* -* \param address -* The address to be validated. -* -* \param uincastOnly -* true: address is checked for I3C device address on the bus only. -* false: otherwise. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t CCCSlaveAddressValidation(uint8_t address, bool uincastOnly, cy_stc_i3c_context_t *context) -{ - uint32_t res; - - res = GetAaddrslotStatus(address, context); - - if(uincastOnly) - { - if(CY_I3C_ADDR_SLOT_I3C_DEV != res) - return CY_I3C_BAD_PARAM; - - context->masterStatus |= CY_I3C_MASTER_DIRECTED_CCC_WR_XFER; - - return CY_I3C_SUCCESS; - } - - else - { - //This helps to check if the device is actively present on the bus - if((CY_I3C_ADDR_SLOT_I3C_DEV != res ) && (CY_I3C_ADDR_SLOT_RSVD != res)) - return CY_I3C_BAD_PARAM; - - if(CY_I3C_BROADCAST_ADDR == address) - { - context->masterStatus |= CY_I3C_MASTER_BROADCAST_CCC_WR_XFER; - } - - else - { - context->masterStatus |= CY_I3C_MASTER_DIRECTED_CCC_WR_XFER; - } - - return CY_I3C_SUCCESS; - } -} - - -/******************************************************************************* -* Function Name: MasterHandleCCCResponse -****************************************************************************//** -* -* Handles the response of CCCs sent. -* -* \param base -* The pointer to the I3C instance. -* -* \param resp -* The pointer to the response queue port register value. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -* \return -* \ref cy_en_i3c_status_t -* -*******************************************************************************/ -static cy_en_i3c_status_t MasterHandleCCCResponse(I3C_CORE_Type *base, uint32_t *resp, cy_stc_i3c_context_t *context) -{ - uint32_t respCmdPort; - cy_en_i3c_status_t retStatus = CY_I3C_SUCCESS; - - //Handling the response - do - { - //wait till the interrupt of response is received - }while(0 == ((CY_I3C_INTR_RESP_READY_STS | CY_I3C_INTR_TRANSFER_ERR_STS) & Cy_I3C_GetInterruptStatus(base))); - - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - Cy_I3C_ClearInterrupt(base, CY_I3C_INTR_MASK); - - if(0 != (respCmdPort & I3C_CORE_MASTER_RESPONSE_QUEUE_PORT_ERR_STS_Msk)) - { - retStatus = ResponseError(respCmdPort); //unsuccessful due to transfer error - context->masterStatus |= CY_I3C_MASTER_HALT_STATE; - } - - Cy_I3C_SetInterruptMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - Cy_I3C_SetInterruptStatusMask(base, CY_I3C_INTR_IBI_BUFFER_THLD_STS); - - return retStatus; -} - -/******************************************************************************* -* Function Name: SlaveRespReadyStsHandle -****************************************************************************//** -* -* Handles the response queue ready status interrupt \ref group_i3c_intr_macros -* for slave mode of operation. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void SlaveRespReadyStsHandle(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - uint32_t respCmdPort; - uint32_t event; - - respCmdPort = I3C_CORE_RESPONSE_QUEUE_PORT(base); - - if(0 != (respCmdPort & I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_ERR_STS_Msk)) - { - uint32_t errorEvent; - - errorEvent = ResponseErrorEvent(respCmdPort); - if(NULL != context->cbEvents) - { - context->cbEvents(errorEvent); - } - return; - } - if(respCmdPort & I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_RX_RSP_Msk) - { - context->slaveRxBufferCnt = _FLD2VAL(I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_DATA_LENGTH, respCmdPort); - - if(CY_I3C_CCC_DEFSLVS != _FLD2VAL(I3C_CORE_SLAVE_RESPONSE_QUEUE_PORT_CCC_HDR_HEADER, respCmdPort)) - { - //Receive Response - master write - SlaveHandleDataReceive(base, context); - - I3C_CORE_RESET_CTRL(base) |= I3C_CORE_RESET_CTRL_RX_FIFO_RST_Msk; - - context->slaveStatus = CY_I3C_SLAVE_RD_CMPLT; - event = CY_I3C_SLAVE_RD_CMPLT_EVENT; - - context->state = CY_I3C_IDLE; - if(NULL != context->cbEvents) - { - context->cbEvents(event); - } - } - } - - else - { - //Transmit Response - master read - uint32_t size; - - size = (CY_I3C_FIFO_SIZE/4) - Cy_I3C_GetFreeEntriesInTxFifo(base); //Gets the number of entries in the Tx Fifo - - context->slaveTxBufferCnt = (context->slaveTxBufferIdx) - size; - context->slaveStatus = CY_I3C_SLAVE_WR_CMPLT; - event = CY_I3C_SLAVE_WR_CMPLT_EVENT; - - context->state = CY_I3C_IDLE; - if(NULL != context->cbEvents) - { - context->cbEvents(event); - } - } -} - - -/******************************************************************************* -* Function Name: SlaveHandleDataReceive -****************************************************************************//** -* -* Reads data from RX FIFO into the buffer provided by -* \ref Cy_I3C_SlaveConfigWriteBuf. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void SlaveHandleDataReceive(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if(context->slaveRxBufferSize > 0UL) - { - context->state = CY_I3C_SLAVE_RX; - context->slaveStatus = CY_I3C_SLAVE_RD_BUSY; - uint32_t numToCopy; - - numToCopy = ((CY_I3C_FIFO_SIZE/4) - Cy_I3C_GetFreeEntriesInRxFifo(base)); - - ReadArray(base, context->slaveRxBuffer, numToCopy); - context->slaveRxBufferIdx += numToCopy; - context->slaveRxBufferSize -= numToCopy; - - context->slaveRxBuffer = &(context->slaveRxBuffer[context->slaveRxBufferIdx]); - } -} - - -/******************************************************************************* -* Function Name: SlaveHandleDataTransmit -****************************************************************************//** -* -* Loads TX FIFO with data provided by \ref Cy_I3C_SlaveConfigReadBuf. -* -* \param base -* The pointer to the I3C instance. -* -* \param context -* The pointer to the context structure \ref cy_stc_i3c_context_t allocated -* by the user. The structure is used during the I3C operation for internal -* configuration and data retention. The user must not modify anything -* in this structure. -* -*******************************************************************************/ -static void SlaveHandleDataTransmit(I3C_CORE_Type *base, cy_stc_i3c_context_t *context) -{ - if(context->slaveTxBufferSize) - { - context->state = CY_I3C_SLAVE_TX; - context->slaveStatus = CY_I3C_SLAVE_WR_BUSY; - - uint32_t numToCopy; - - numToCopy = Cy_I3C_GetFreeEntriesInTxFifo(base)*4; - - if(numToCopy > (context->slaveTxBufferSize)) - { - numToCopy = context->slaveTxBufferSize; - } - WriteArray(base, context->slaveTxBuffer, numToCopy); - context->slaveTxBufferIdx += numToCopy; - context->slaveTxBufferSize -= numToCopy; - context->slaveTxBuffer = &context->slaveTxBuffer[context->slaveTxBufferIdx]; - } -} - -#if defined(__cplusplus) - } -#endif - -#endif /* CY_IP_MXI3C */ -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ipc_bt.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ipc_bt.c deleted file mode 100644 index 77ef54bc06..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_ipc_bt.c +++ /dev/null @@ -1,713 +0,0 @@ -/***************************************************************************//** -* \file cy_ipc_bt.c -* \version 1.0 -* -* \brief -* This driver provides the source code for BT IPC. -* -******************************************************************************** -* \copyright -* Copyright 2017-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXIPC) - -#include "cy_ipc_bt.h" - -/* Should not include this. To be removed */ -#include - -/* local functions prototype */ -cy_en_btipcdrv_status_t Cy_bt_handle_hpclong_msg(cy_stc_ipc_bt_context_t *btIpcContext, uint32_t * msgPtr); -cy_en_btipcdrv_status_t Cy_bt_handle_buf_add(cy_stc_ipc_bt_context_t *btIpcContext, uint32_t * msgPtr); -cy_en_btipc_buftype_t Cy_bt_get_buf_type(cy_en_btipc_hcipti_t pti); -uint32_t Cy_bt_getPLLegnth(cy_en_btipc_hcipti_t pti, uint8_t* bufAddr); -bool Cy_bt_isOffsetNeeded(cy_en_btipc_hcipti_t pti); - - - - -void Cy_BTIPC_IRQ_Handler(cy_stc_ipc_bt_context_t *btIpcContext) -{ - uint32_t shadowIntr; - IPC_STRUCT_Type *ipcPtr; - IPC_INTR_STRUCT_Type *ipcIntrPtr; - uint32_t mesg[2]; - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint32_t notify; - uint32_t release; - uint32_t channel; - uint8_t idx; - - if (NULL == contextPtr) - return; - - ipcIntrPtr = Cy_IPC_Drv_GetIntrBaseAddr(contextPtr->intStuctureSelf); - shadowIntr = Cy_IPC_Drv_GetInterruptStatusMasked(ipcIntrPtr); - - /* Check to make sure the interrupt was a release interrupt */ - release = Cy_IPC_Drv_ExtractReleaseMask(shadowIntr); - - /* First process the release callback */ - if (0UL != release) /* Check for a Release interrupt */ - { - /* Clear the release interrupt */ - Cy_IPC_Drv_ClearInterrupt(ipcIntrPtr, release, CY_IPC_NO_NOTIFICATION); - /* release callback can be added here. */ - if (contextPtr->ulReleaseCallbackPtr) - contextPtr->ulReleaseCallbackPtr(); - } - - /* Check to make sure the interrupt was a notify interrupt */ - notify = Cy_IPC_Drv_ExtractAcquireMask(shadowIntr); - - if (0UL != notify) - { - /* Clear the notify interrupt. */ - Cy_IPC_Drv_ClearInterrupt(ipcIntrPtr, CY_IPC_NO_NOTIFICATION, notify); - if (notify & (uint32_t)(0x1 << contextPtr->dlChannelHCI)) - channel = contextPtr->dlChannelHCI; - else - channel = contextPtr->dlChannelHPC; - - ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress(channel); - - if (!Cy_IPC_Drv_ReadMsgDWord (ipcPtr, mesg)) - { - if (channel == contextPtr->dlChannelHCI) - { - /* Channel will be released in the callback function */ - if (contextPtr->dlNotifyCallbackPtr) - contextPtr->dlNotifyCallbackPtr(mesg); - } - else - { - if (contextPtr->internal_hpc_notify_cb) - contextPtr->internal_hpc_notify_cb((void*)contextPtr, mesg); - for (idx = 0; idx < MAX_BT_IPC_HPC_CB; idx++) - { - if (contextPtr->hpcNotifyCallbackPtr[idx]) - contextPtr->hpcNotifyCallbackPtr[idx](mesg); - } - /* Release channel for HPC message only */ - Cy_BTIPC_HPC_RelChannel(contextPtr, mesg); - } - } - } -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_RelChannel(cy_stc_ipc_bt_context_t *btIpcContext, void * buf) -{ - IPC_STRUCT_Type *ipcPtr; - cy_en_ipcdrv_status_t status; - uint32_t rel_mask; - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - - if ((NULL == contextPtr) || (NULL == buf)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress (contextPtr->dlChannelHCI); - - rel_mask = (uint32_t)(1 << contextPtr->intStucturePeer); - - status = Cy_IPC_Drv_LockRelease (ipcPtr, rel_mask); - - if (status) { - return CY_BT_IPC_DRV_ERROR_LOCK_REL; - } - return CY_BT_IPC_DRV_SUCCESS; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_RelChannel(cy_stc_ipc_bt_context_t *btIpcContext, void * buf) -{ - IPC_STRUCT_Type *ipcPtr; - cy_en_ipcdrv_status_t status; - uint32_t rel_mask; - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - - if ((NULL == contextPtr) || (NULL == buf)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress (contextPtr->dlChannelHPC); - - rel_mask = (uint32_t)(1 << contextPtr->intStucturePeer); - status = Cy_IPC_Drv_LockRelease (ipcPtr, rel_mask); - if (status) { - return CY_BT_IPC_DRV_ERROR_LOCK_REL; - } - return CY_BT_IPC_DRV_SUCCESS; -} - -void Cy_BTIPC_HPC_Notify(void *btIpcContext, uint32_t * msgPtr) -{ - cy_en_btipc_hpcpti_t pti; - cy_stc_ipc_bt_context_t *contextPtr = (cy_stc_ipc_bt_context_t*) btIpcContext; - if ((NULL == contextPtr) || (NULL == msgPtr)) - return; - - pti = (cy_en_btipc_hpcpti_t)((0xFF) & msgPtr[0]); - - switch (pti) - { - case CY_BT_IPC_HPC_LONG: - Cy_bt_handle_hpclong_msg(contextPtr, msgPtr); - break; - case CY_BT_IPC_HPC_BUF_AVAIL: - Cy_bt_handle_buf_add(contextPtr, msgPtr); - break; - case CY_BT_IPC_HPC_BUF_FREE: - Cy_bt_handle_buf_add(contextPtr, msgPtr); - break; - default: - /* default invalid pti */ - break; - } -} - -cy_en_btipcdrv_status_t Cy_BTIPC_Init(cy_stc_ipc_bt_context_t *btIpcContext, cy_stc_ipc_bt_config_t * btIpcConfig) -{ - cy_en_sysint_status_t intrStatus; - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint8_t idx; - - if ((NULL == contextPtr) || (NULL == btIpcConfig)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - contextPtr->dlChannelHCI = btIpcConfig->dlChannelHCI; - contextPtr->ulChannelHCI = btIpcConfig->ulChannelHCI; - - contextPtr->dlChannelHPC = btIpcConfig->dlChannelHPC; - contextPtr->ulChannelHPC = btIpcConfig->ulChannelHPC; - - contextPtr->intStuctureSelf = btIpcConfig->intStuctureSelf; - contextPtr->intStucturePeer = btIpcConfig->intStucturePeer; - contextPtr->intPeerMask = (uint32_t) (0x1 << btIpcConfig->intStucturePeer); - - contextPtr->dlNotifyCallbackPtr = btIpcConfig->dlNotifyCallbackPtr; - contextPtr->ulReleaseCallbackPtr = btIpcConfig->ulReleaseCallbackPtr; - - contextPtr->irqHandlerPtr = btIpcConfig->irqHandlerPtr; - contextPtr->ipcIntConfig.intrSrc = btIpcConfig->ipcIntConfig.intrSrc; - contextPtr->ipcIntConfig.intrPriority = btIpcConfig->ipcIntConfig.intrPriority; - - contextPtr->internal_hpc_notify_cb = btIpcConfig->internal_hpc_notify_cb; - - contextPtr->dlNotifyMask = (uint32_t)((uint32_t)(0x1 << btIpcConfig->dlChannelHCI) | (uint32_t)(0x1 << btIpcConfig->dlChannelHPC)); - contextPtr->ulReleaseMask = (uint32_t)((uint32_t)(0x1 << btIpcConfig->ulChannelHCI) | (uint32_t)(0x1 << btIpcConfig->ulChannelHPC)); - - for (idx = 0; idx < MAX_BT_IPC_HPC_CB; idx++) - contextPtr->hpcNotifyCallbackPtr[idx] = NULL; - - for (idx = 0; idx < MAX_BUF_COUNT; idx++) - { - contextPtr->buffPool[idx].bufPtr = NULL; - contextPtr->buffPool[idx].bufType = CY_BT_IPC_HCI_INVALID_BUF; - } - - intrStatus = Cy_SysInt_Init(&contextPtr->ipcIntConfig, contextPtr->irqHandlerPtr); - if (intrStatus) - { - return CY_BT_IPC_DRV_ERROR; - } - - /* enable interrupt */ - NVIC_EnableIRQ(contextPtr->ipcIntConfig.intrSrc); - - /* Set IPC Interrupt mask */ - /* Allow only notify on DL channel and release on UL channel interrupts */ - Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(contextPtr->intStuctureSelf), contextPtr->ulReleaseMask, contextPtr->dlNotifyMask); - return CY_BT_IPC_DRV_SUCCESS; - } - -cy_en_btipcdrv_status_t Cy_BTIPC_Deinit(cy_stc_ipc_bt_context_t *btIpcContext) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint8_t idx; - - if (NULL == contextPtr) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - //Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(contextPtr->intStuctureSelf), ~contextPtr->ulReleaseMask, ~contextPtr->dlNotifyMask); - - /* enable interrupt */ - NVIC_DisableIRQ(contextPtr->ipcIntConfig.intrSrc); - - contextPtr->irqHandlerPtr = NULL; - contextPtr->internal_hpc_notify_cb = NULL; - - for (idx = 0; idx < MAX_BT_IPC_HPC_CB; idx++) - contextPtr->hpcNotifyCallbackPtr[idx] = NULL; - - for (idx = 0; idx < MAX_BUF_COUNT; idx++) - { - contextPtr->buffPool[idx].bufPtr = NULL; - contextPtr->buffPool[idx].bufType = CY_BT_IPC_HCI_INVALID_BUF; - } - - return CY_BT_IPC_DRV_SUCCESS; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_getPTI (cy_en_btipc_hcipti_t *pti, uint32_t *p_length, uint32_t *msgPtr) -{ - cy_stc_ipc_msg_buff_t *ipcMsgBuf; - uint8_t *bufAddr; - cy_en_btipc_hcipti_t mesgPti; - - if ((NULL == pti) || (NULL == msgPtr) || (NULL == p_length)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - /* Incase of long messages the PTI needs to be read from DATA0[bit 8-15] */ - mesgPti = (cy_en_btipc_hcipti_t)((0xFF) & msgPtr[0]); - if (mesgPti == CY_BT_IPC_HCI_LONG) - { - ipcMsgBuf = (cy_stc_ipc_msg_buff_t*)msgPtr; - *pti = (cy_en_btipc_hcipti_t)ipcMsgBuf->actualPti; - bufAddr = ipcMsgBuf->bufAddr; - if (Cy_bt_isOffsetNeeded(*pti)) - bufAddr++; - } - else - { - *pti = mesgPti; - bufAddr = (uint8_t*)msgPtr; - /* Skip the PTI byte read from the DATA0 register */ - bufAddr++; - } - *p_length = Cy_bt_getPLLegnth(*pti, bufAddr); - return CY_BT_IPC_DRV_SUCCESS; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_Read (cy_stc_ipc_bt_context_t *btIpcContext, cy_en_btipc_hcipti_t pti, void *data, size_t* pLength) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - cy_stc_ipc_msg_alloc_t ipcMsgAlloc; - cy_stc_ipc_msg_buff_t *ipcMsgBuf; - cy_en_btipcdrv_status_t status; - cy_stc_ipc_msg_short_t *shortMesg; - cy_en_btipc_hcipti_t actualPti; - cy_en_btipc_hcipti_t mesgPti; - uint32_t mesg[2]; - uint8_t *srcPtr; - - if ((NULL == contextPtr) || (NULL == data)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - Cy_IPC_Drv_ReadDDataValue (Cy_IPC_Drv_GetIpcBaseAddress(contextPtr->dlChannelHCI), mesg); - - mesgPti = (cy_en_btipc_hcipti_t)((0xFF) & mesg[0]); - - if (mesgPti == CY_BT_IPC_HCI_LONG) - { - ipcMsgBuf = (cy_stc_ipc_msg_buff_t*)&mesg; - actualPti = (cy_en_btipc_hcipti_t)ipcMsgBuf->actualPti; - srcPtr = ipcMsgBuf->bufAddr; - if (Cy_bt_isOffsetNeeded(actualPti)) - srcPtr++; - *pLength = Cy_bt_getPLLegnth(actualPti, srcPtr); - } - else - { - shortMesg = (cy_stc_ipc_msg_short_t*)&mesg; - srcPtr = &(shortMesg->db0); - *pLength = Cy_bt_getPLLegnth(mesgPti, srcPtr); - } - - /* To be done: memcopy needs to be removed */ - /* Need to look for better option */ - /* May be a loop or DMA */ - memcpy((uint8_t*)data, srcPtr, *pLength); - - status = Cy_BTIPC_HCI_RelChannel(contextPtr, (void *) &mesg); - - /* Send buffer back to BLE */ - /* To be done: Should this assert If Channel release fails? */ - if ((mesgPti == CY_BT_IPC_HCI_LONG) && (!status)) - { - ipcMsgAlloc.pti = (uint8_t)CY_BT_IPC_HPC_BUF_FREE; - ipcMsgAlloc.bufType = Cy_bt_get_buf_type(actualPti); - ipcMsgAlloc.bufSize = *pLength; - ipcMsgAlloc.bufAddr = ipcMsgBuf->bufAddr; - - status = Cy_BTIPC_HPC_Write(contextPtr, &ipcMsgAlloc, (size_t) 2); - } - - return status; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HCI_Write(cy_stc_ipc_bt_context_t *btIpcContext, cy_en_btipc_hcipti_t pti, void *data, size_t length) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - cy_en_btipcdrv_status_t status; - uint8_t *destBuf; - cy_stc_ipc_msg_buff_t ipcPacket; - cy_en_btipc_buftype_t bufType; - cy_stc_ipc_msg_short_t ipcShort; - uint32_t *msgPtr; - uint8_t *bPtr; - - if ((NULL == contextPtr) || (NULL == data)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - /* Check if it is short message or buffer needed */ - if (length > MAX_SHORT_MESG_LENGTH) /* Long messge */ - { - /* Get the buffer type based on the payload type indeicator */ - bufType = Cy_bt_get_buf_type(pti); - /* Pick a free buffe from the pool of buffers */ - status = Cy_BTIPC_GetBuffer (contextPtr, (void **)&destBuf, bufType); - if (status) - return status; - - /* Copy payload to BLE buffer */ - /* To be done: memcopy needs to be removed */ - /* Need to look for better option */ - /* May be a loop or DMA */ - bPtr = destBuf; - /* Skip pad byte if needed */ - if (Cy_bt_isOffsetNeeded(pti)) - bPtr++; - memcpy(bPtr, data, length); - ipcPacket.pti = (uint8_t) CY_BT_IPC_HCI_LONG; - ipcPacket.actualPti = (uint8_t)pti; - ipcPacket.bufAddr = destBuf; - /* end of buffer preperation */ - msgPtr = (uint32_t*)&ipcPacket; - } - else /* Short Message */ - { - ipcShort.pti = pti; - /* To be done: memcopy needs to be removed */ - /* Need to look for better option */ - /* Loop is fine as max 8 bytes need to be copied */ - memcpy (&(ipcShort.db0), data, length); - msgPtr = (uint32_t*)&ipcShort; - } - if (!Cy_IPC_Drv_SendMsgDWord (Cy_IPC_Drv_GetIpcBaseAddress(contextPtr->ulChannelHCI), - contextPtr->intPeerMask, msgPtr)) - return CY_BT_IPC_DRV_SUCCESS; - else - return CY_BT_IPC_DRV_ERROR_LOCK_ACQUIRE; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_Write(cy_stc_ipc_bt_context_t *btIpcContext, void *data, size_t length) -{ - uint32_t *dataPtr = (uint32_t*) data; - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - - if ((NULL == contextPtr) || (NULL == data)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - if (!Cy_IPC_Drv_SendMsgDWord (Cy_IPC_Drv_GetIpcBaseAddress(contextPtr->ulChannelHPC), - contextPtr->intPeerMask, (uint32_t*) dataPtr)) - return CY_BT_IPC_DRV_SUCCESS; - else - return CY_BT_IPC_DRV_ERROR_LOCK_ACQUIRE; - -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_RegisterCb(cy_stc_ipc_bt_context_t *btIpcContext, cy_ipc_bt_callback_ptr_t hpcNotifyCallbackPtr) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint8_t idx; - uint8_t placed; - - if ((NULL == contextPtr) || (NULL == hpcNotifyCallbackPtr)) - { - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - } - - placed = 0; - for (idx = 0; idx < MAX_BT_IPC_HPC_CB; idx++) - { - if (contextPtr->hpcNotifyCallbackPtr[idx] == NULL) - { - contextPtr->hpcNotifyCallbackPtr[idx] = hpcNotifyCallbackPtr; - placed = 1; - break; - } - } - - if (placed) - return CY_BT_IPC_DRV_SUCCESS; - else - return CY_BT_IPC_DRV_ERROR; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_HPC_UnregisterCb(cy_stc_ipc_bt_context_t *btIpcContext, cy_ipc_bt_callback_ptr_t hpcNotifyCallbackPtr) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint8_t idx; - uint8_t found; - - if ((NULL == contextPtr) || (NULL == hpcNotifyCallbackPtr)) - { - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - } - - found = 0; - for (idx = 0; idx < MAX_BT_IPC_HPC_CB; idx++) - { - if (contextPtr->hpcNotifyCallbackPtr[idx] == hpcNotifyCallbackPtr) - { - contextPtr->hpcNotifyCallbackPtr[idx] = NULL; - found = 1; - break; - } - } - - if (found) - return CY_BT_IPC_DRV_SUCCESS; - else - return CY_BT_IPC_DRV_ERROR; -} - -cy_en_btipcdrv_status_t Cy_BTIPC_GetBuffer (cy_stc_ipc_bt_context_t *btIpcContext, void **bufPtr, cy_en_btipc_buftype_t bufType) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint8_t idx; - uint8_t found; - uint32_t interruptState; - - if ((NULL == contextPtr) || (NULL == bufPtr)) - { - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - } - - interruptState = Cy_SysLib_EnterCriticalSection(); - - found = 0; - for (idx = 0; idx < MAX_BUF_COUNT; idx++) - { - if ((contextPtr->buffPool[idx].bufType == bufType) && (contextPtr->buffPool[idx].bufPtr != NULL)) - { - *bufPtr = (void*)contextPtr->buffPool[idx].bufPtr; - contextPtr->buffPool[idx].bufPtr = NULL; - contextPtr->buffPool[idx].bufType = CY_BT_IPC_HCI_INVALID_BUF; - found = 1; - break; - } - } - - Cy_SysLib_ExitCriticalSection(interruptState); - - if (found) - return CY_BT_IPC_DRV_SUCCESS; - else - { - *bufPtr = NULL; - return CY_BT_IPC_DRV_ERROR_BUF_GET; - } -} - -cy_en_btipcdrv_status_t Cy_BTIPC_PutBuffer(cy_stc_ipc_bt_context_t *btIpcContext, cy_stc_ipc_bt_buf_t *bufDecriptor) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - uint8_t idx; - uint8_t done; - uint32_t interruptState; - - if ((NULL == contextPtr) || (NULL == bufDecriptor) || (bufDecriptor->bufPtr == NULL)) - { - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - } - - interruptState = Cy_SysLib_EnterCriticalSection(); - - done = 0; - for (idx = 0; idx < MAX_BUF_COUNT; idx++) - { - if (contextPtr->buffPool[idx].bufPtr == NULL) - { - contextPtr->buffPool[idx] = *bufDecriptor; - done = 1; - break; - } - } - - Cy_SysLib_ExitCriticalSection(interruptState); - - if (done) - return CY_BT_IPC_DRV_SUCCESS; - else - return CY_BT_IPC_DRV_ERROR_BUF_FULL; -} - - -/* Local function implmentation */ -cy_en_btipcdrv_status_t Cy_bt_handle_hpclong_msg(cy_stc_ipc_bt_context_t *btIpcContext, uint32_t * msgPtr) -{ - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - cy_stc_ipc_msg_init_t *ptr; - cy_stc_ipc_bt_buf_t bufDescriptor; - cy_en_btipcdrv_status_t status; - uint8_t i; - uint8_t bufCount; - - uint8_t *bPtr; - uint16_t *sPtr; - uint32_t *uiPtr; - - if ((NULL == contextPtr) || (NULL == msgPtr)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - ptr = (cy_stc_ipc_msg_init_t*)(* (msgPtr+1)); - - if (NULL == ptr) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - - bufCount = ptr->payLoadLen/BUFFER_DESCRIPTION_LEN; - /* Add code to extract boot type from initi structure */ - //msgId - //bootType - /* point to the start of buffer pool */ - ptr++; - bPtr = (uint8_t*)ptr; - - for (i = 0; i < bufCount; i++) - { - bufDescriptor.bufType = (cy_en_btipc_buftype_t) (*bPtr++); - sPtr = (uint16_t*)bPtr; - bufDescriptor.bufLen = *(sPtr++); - uiPtr = (uint32_t*)sPtr; - bufDescriptor.bufPtr = (uint8_t*)(*uiPtr++); - status = Cy_BTIPC_PutBuffer(contextPtr, &bufDescriptor); - if (status) - { - /* Need to check if some cleaning needed for error condition */ - return status; - } - bPtr = (uint8_t*)uiPtr; - } - return CY_BT_IPC_DRV_SUCCESS; -} - -cy_en_btipcdrv_status_t Cy_bt_handle_buf_add(cy_stc_ipc_bt_context_t *btIpcContext, uint32_t * msgPtr) -{ - cy_stc_ipc_bt_buf_t bufDescriptor; - cy_stc_ipc_msg_alloc_t allocBuf; - cy_stc_ipc_bt_context_t *contextPtr = btIpcContext; - - if ((NULL == contextPtr) || (NULL == msgPtr)) - return CY_BT_IPC_DRV_ERROR_BAD_HANDLE; - allocBuf = *(cy_stc_ipc_msg_alloc_t*)(msgPtr); - bufDescriptor.bufType = (cy_en_btipc_buftype_t) allocBuf.bufType; - bufDescriptor.bufLen = allocBuf.bufSize; - bufDescriptor.bufPtr = (uint8_t*) allocBuf.bufAddr; - - return Cy_BTIPC_PutBuffer(contextPtr, &bufDescriptor); -} - -cy_en_btipc_buftype_t Cy_bt_get_buf_type(cy_en_btipc_hcipti_t pti) -{ - cy_en_btipc_buftype_t bufType; - /* To be done: Currently retruning Control buffer for all PTIs. Need to change it once we have clarity on it */ - switch (pti) - { - case CY_BT_IPC_HCI_CMD: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_ACL: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_SCO: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_EVT: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_ISO: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_DIAG: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_MPAF: - bufType = CY_BT_IPC_CTRL_BUF; - break; - case CY_BT_IPC_HCI_SLIPH5: - bufType = CY_BT_IPC_CTRL_BUF; - break; - default: - bufType = CY_BT_IPC_HCI_INVALID_BUF; - break; - } - return bufType; -} - -uint32_t Cy_bt_getPLLegnth(cy_en_btipc_hcipti_t pti, uint8_t* bufAddr) -{ - uint32_t length; - switch (pti) - { - case CY_BT_IPC_HCI_CMD: - length = (uint32_t)(((BTHCI_CMD_HDR_t*)bufAddr)->params_len); - length += sizeof(BTHCI_CMD_HDR_t); - break; - case CY_BT_IPC_HCI_ACL: - length = (uint32_t)(((BTHCI_ACL_HDR_t*)bufAddr)->data_len); - length += sizeof(BTHCI_ACL_HDR_t); - break; - case CY_BT_IPC_HCI_SCO: - length = (uint32_t)(((BTHCI_SCO_HDR_t*)bufAddr)->data_len); - length += sizeof(BTHCI_SCO_HDR_t); - break; - case CY_BT_IPC_HCI_EVT: - length = (uint32_t)(((BTHCI_EVENT_HDR_t*)bufAddr)->params_len); - length += sizeof(BTHCI_EVENT_HDR_t); - break; - case CY_BT_IPC_HCI_ISO: - length = (uint32_t)(((BTHCI_ISO_HDR_t*)bufAddr)->data_len); - length += sizeof(BTHCI_ISO_HDR_t); - break; - /* To be done: Header length for the remaining PTI needs to be updated */ - case CY_BT_IPC_HCI_DIAG: - length = 0; - break; - case CY_BT_IPC_HCI_MPAF: - length = 0; - break; - case CY_BT_IPC_HCI_SLIPH5: - length = 0; - break; - default: - length = 0; - break; - } - return length; -} - -bool Cy_bt_isOffsetNeeded(cy_en_btipc_hcipti_t pti) -{ - switch (pti) - { - case CY_BT_IPC_HCI_CMD: - case CY_BT_IPC_HCI_SCO: - return true; - case CY_BT_IPC_HCI_ACL: - case CY_BT_IPC_HCI_EVT: - case CY_BT_IPC_HCI_ISO: - case CY_BT_IPC_HCI_DIAG: - case CY_BT_IPC_HCI_MPAF: - case CY_BT_IPC_HCI_SLIPH5: - default: - return false; - } -} - -#endif - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_keyscan.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_keyscan.c deleted file mode 100644 index c8475e3f3a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_keyscan.c +++ /dev/null @@ -1,1176 +0,0 @@ -/***************************************************************************//** -* \file cy_keyscan.c -* \version 1.0 -* -* \brief -* Provides an API declaration of the KEYSCAN driver -* -******************************************************************************** -* \copyright -* Copyright 2020-2021, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ -#include "cy_device.h" -#if defined (CY_IP_MXKEYSCAN) -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include "cy_keyscan.h" -#include - -/*****************************************************************************/ -/* Local pre-processor symbols/macros ('#define') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Global variable definitions (declared in header file with 'extern') */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Local type definitions ('typedef') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local variable definitions ('static') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local function prototypes ('static') */ -/*****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_GetEventsFromHWFifo(MXKEYSCAN_Type *base, cy_stc_keyscan_context_t *context); -static cy_en_ks_status_t Cy_Keyscan_Fq_Flush(cy_stc_keyscan_context_t* context); -static cy_en_ks_status_t Cy_Keyscan_Fq_GetCurNumElements(cy_stc_keyscan_context_t* context, uint8_t *numElements); -static cy_en_ks_status_t Cy_Keyscan_Fq_PutIncludeOverflowSlot(cy_stc_keyscan_context_t* context, cy_stc_key_event *element); -static cy_en_ks_status_t Cy_Keyscan_Fq_GetCurElmPtr(cy_stc_keyscan_context_t* context, cy_stc_key_event **current_element); -static cy_en_ks_status_t Cy_Keyscan_Fq_RemoveCurElement(cy_stc_keyscan_context_t* context); -static cy_en_ks_status_t Cy_Keyscan_Fq_Put(cy_stc_keyscan_context_t* context, cy_stc_key_event *element); -static cy_en_ks_status_t Cy_Keyscan_Fq_MarkCurrentEventForRollBack (cy_stc_keyscan_context_t* context); -static cy_en_ks_status_t Cy_Keyscan_Fq_RollbackUptoMarkedEvents(cy_stc_keyscan_context_t* context); -static cy_en_ks_status_t Cy_Keyscan_PutEvent(cy_stc_keyscan_context_t* context, cy_stc_key_event *event); -static cy_en_ks_status_t Cy_Keyscan_GetEvent(cy_stc_keyscan_context_t* context, cy_stc_key_event *event); -static cy_en_ks_status_t Cy_Keyscan_Mia_FreezeClk(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context); -static cy_en_ks_status_t Cy_Keyscan_Mia_UnfreezeClk(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context); -static cy_en_ks_status_t Cy_Keyscan_HwResetOnce(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context); -static cy_en_ks_status_t Cy_Keyscan_Init_Context( cy_stc_keyscan_context_t* context); - -/*****************************************************************************/ -/* Function implementation - global ('extern') and local ('static') */ -/*****************************************************************************/ - -/** - ***************************************************************************** - ** discards elements from keyscan FW circular queue. - ** This Function Discards all elements in the queue, including any elements in the overflow slot. - ** - ** [in] context Pointer to the context. - ** - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_Flush(cy_stc_keyscan_context_t* context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == context) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - context->readIndex = context->writeIndex = context->curNumElements = 0U; - } - return status; -} - -/** - ***************************************************************************** - ** Returns no of elements in the keyscan FW circular queue. - ** This Function Discards all elements in the queue, including any elements in the overflow slot. - ** - ** [in] context Pointer to the context. - ** - ** [out] numElements Pointer to the number of elements. - ** - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_GetCurNumElements(cy_stc_keyscan_context_t* context, uint8_t *numElements) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == context) || (NULL == numElements)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - *numElements = context->curNumElements; - } - return status; -} -/** - ***************************************************************************** - ** Puts an element into the queue as long as there is room for 1 element or more, i.e. - ** this method will fill in the overflow slot if that is the - ** last slot left. Should be used if (a) overflow slots are not needed (b) - ** for queuing an overflow event - ** - ** [in] context Pointer to the context. - ** - ** [in] element pointer to the element to be placed in the queue - ** - ** [in] length length number of bytes in element. This number of bytes is copied into the - ** internal storage of the queue. This must be <= the maximum element size - ** specified when the queue was constructed, otherwise the results are undefined. - ** - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_PutIncludeOverflowSlot(cy_stc_keyscan_context_t* context, cy_stc_key_event *element) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == element) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Check if we have room including the overflow slot - if (context->curNumElements < context->maxNumElements) - { - // We can put it in. Use the local put function to add the element in - status = Cy_Keyscan_Fq_Put(context, element); - } - else - { - // We have an overflow condition. Inform the caller - status = CY_KEYSCAN_QUEUE_OVERFLOW; - } - } - return status; -} - -/** - ***************************************************************************** - ** Returns pointer to the first element in the queue. If the queue is empty returns NULL. - ** - ** [in] context Pointer to the context. - ** - ** [out] element pointer to the next element in the queue if the queue is not empty - ** NULL if the queue is empty. - ** - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_GetCurElmPtr(cy_stc_keyscan_context_t* context, cy_stc_key_event **current_element) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == current_element) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Check if the queue has an element - if (context->curNumElements) - { - // Return pointer to the element - *current_element = &(context->bufStart[context->readIndex]); - } - else - { - // If we get here, the queue doesn't have any elements. Return NULL - current_element = NULL; - status = CY_KEYSCAN_EVENT_NONE; - } - - } - return status; -} -/** - ***************************************************************************** - ** Removes the current element from the queue. Does nothing if the queue is empty. - ** - ** [in] context Pointer to the context. - ** - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_RemoveCurElement(cy_stc_keyscan_context_t* context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == context) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Check if the queue has any elements - if (context->curNumElements) - { - // Reduce the number of elements by 1 - (context->curNumElements)--; - - // Advance the read index and read pointer - (context->readIndex)++; - - // Check for wraparound - if (context->readIndex >= context->maxNumElements) - { - // We have wraparound. Move the read index to the top of the buffer - context->readIndex = 0; - } - } - } - return status; -} -/** - ***************************************************************************** - ** Puts an element into the queue. - ** This Function Puts an element into the queue. Does not perform any bound checking. - ** - ** [in] context Pointer to the context. - ** - ** [in] element pointer to the element to be placed in the queue - ** - ** [in] length length number of bytes in element. This number of bytes is copied into the - ** internal storage of the queue. This must be <= the maximum element size - ** specified when the queue was constructed, otherwise the results are undefined. - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_Put(cy_stc_keyscan_context_t* context, cy_stc_key_event *element) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == element) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Copy the element at the current write location - memcpy( &context->bufStart[context->writeIndex], element, sizeof(cy_stc_key_event)); - - // Update the number of elements in the queue - (context->curNumElements)++; - - // Next increment the write index - (context->writeIndex)++; - - // Now check for wraparound - if (context->writeIndex >= context->maxNumElements) - { - // We need to wraparound. Set the write index to zero - context->writeIndex = 0; - } - } - return status; -} - -/** - ***************************************************************************** - ** Save the current FW fifo write index. This is useful for rolling - ** back what we added in case we encounter a ghost/overflow condition. - ** - ** [in] context Pointer to the context. - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_MarkCurrentEventForRollBack (cy_stc_keyscan_context_t* context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - /// Save the current FW fifo write index. This is useful for rolling - /// back what we added in case we encounter a ghost/overflow condition - context->savedWriteIndexForRollBack = context->writeIndex; - context->savedNumElements = context->curNumElements; - - } - return status; -} - -/** - ***************************************************************************** - ** Rollback upto the marked events - ** - ** [in] context Pointer to the context. - ** - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Fq_RollbackUptoMarkedEvents(cy_stc_keyscan_context_t* context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == context) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - context->curNumElements = context->savedNumElements; - // rollback upto the marked event - context->writeIndex = context->savedWriteIndexForRollBack; - } - return status; -} - -/** - ***************************************************************************** - ** Put an event into the keyscan data fifo - ** - ** [in] context Pointer to the context. - ** - ** [in] event Pointer to the event. - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_PutEvent(cy_stc_keyscan_context_t* context, cy_stc_key_event *event) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - uint8_t numElements; - /* Check if pointers are valid */ - if ((NULL == event) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - status = Cy_Keyscan_Fq_GetCurNumElements( context, &numElements); - if(status == CY_KEYSCAN_SUCCESS) - { - // Check if the fifo has room - if(numElements == KEYSCAN_FW_FIFO_SIZE - 1) - { - // Overflow! Queue a rollover event; discard whatever was given to us - event->keyCode = KEYSCAN_KEYCODE_ROLLOVER; - } - // if not overflow the event is put into fifo - status = Cy_Keyscan_Fq_PutIncludeOverflowSlot(context, event); - } - } - return status; -} - -/** - ***************************************************************************** - ** Get the next element in the FIFO - ** - ** [in] context Pointer to the context. - ** - ** [out] event Pointer to the event. - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_GetEvent(cy_stc_keyscan_context_t* context, cy_stc_key_event *event) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - cy_stc_key_event *current_event; - uint8_t numElements; - /* Check if pointers are valid */ - if ((NULL == event) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - status = Cy_Keyscan_Fq_GetCurNumElements( context, &numElements); - if(status == CY_KEYSCAN_SUCCESS) - { - // Check if fifo is empty - if (numElements == 0) - { - event->keyCode = KEYSCAN_KEYCODE_NONE; - status = CY_KEYSCAN_EVENT_NONE; - } - else - { - status = Cy_Keyscan_Fq_GetCurElmPtr(context, ¤t_event); - if(status == CY_KEYSCAN_SUCCESS) - { - event->keyCode = current_event->keyCode; - event->upDownFlag = current_event->upDownFlag; - event->scanCycleFlag = current_event->scanCycleFlag; - - Cy_Keyscan_Fq_RemoveCurElement(context); - } - - } - - } - } - return status; -} - -/** - ***************************************************************************** - ** Freeze the MIA clock. Wait until the HW accepts the command, then - ** generate an event indicating that the MIA clock is unfrozen for anyone - ** who desires to catch it - ** - ** [in] context Pointer to the context. - ** [in] base Pointer to KeyScan instance register area - ** - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Mia_FreezeClk(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Issue the freeze command to the HW - KEYSCAN_MIA_CTL(base) |= _VAL2FLD(MXKEYSCAN_MIA_CTL_FREEZE_MIA, 1U); - - // Wait till mia_clk_freezed bit in MIA_STATUS register to go high - while (_FLD2VAL(MXKEYSCAN_MIA_STATUS_MIA_CLOCK_FREEZED_STATUS, KEYSCAN_MIA_STATUS(base)) != 1U) - { - ; - } - - // Notify application that clock is frozen. This allows workarounds for clock freeze related MIA - // bugs, specifically key event loss when clock is frozen/unfrozen without reading the key event fifo - // Poll the event fifo only if the freeze didn't come from us - if (!context->keyscan_pollingKeyscanHw) - { - // Retrieve any pending events from the HW fifo - status = Cy_Keyscan_GetEventsFromHWFifo(base, context); - } - } - return status; -} -/** - ***************************************************************************** - ** Unfreeze the MIA clock. Wait until the HW accepts the command, then - ** generate an event indicating that the MIA clock is unfrozen for anyone - ** who desires to catch it - ** - ** [in] context Pointer to the context. - ** [in] base Pointer to KeyScan instance register area - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Mia_UnfreezeClk(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Unfreeze the clock - KEYSCAN_MIA_CTL(base) &= ~MXKEYSCAN_MIA_CTL_FREEZE_MIA_Msk; - - // Wait until it is unfrozen - while (_FLD2VAL(MXKEYSCAN_MIA_STATUS_MIA_CLOCK_FREEZED_STATUS, KEYSCAN_MIA_STATUS(base)) != 0U) - { - ; - } - KEYSCAN_CTL(base) &= ~MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN_Msk; - } - return status; -} - -/** - ***************************************************************************** - ** Reset the keyscan HW once. - ** - ** [in] context Pointer to the context. - ** [in] base Pointer to KeyScan instance register area - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_HwResetOnce(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Freeze the MIA clock - status = Cy_Keyscan_Mia_FreezeClk(base, context); - - if(status == CY_KEYSCAN_SUCCESS) - { - // Set the "clear reported keys" bit. This is necessary or the HW reset will not be accepted - KEYSCAN_MIA_CTL(base) |= MXKEYSCAN_MIA_CTL_REPORTED_CLEAR_KYS_Msk; - - // Set the reset bit - KEYSCAN_CTL(base) |= MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN_Msk; - - // Unfreeze the MIA clock. This will clear the reset bit - status = Cy_Keyscan_Mia_UnfreezeClk(base, context); - - // Delay to ensure that the reset takes effect - // SOme more information on why 2550 delay to be gathered. - Cy_SysLib_DelayUs(2550U); - } - - } - return status; -} - - -/** - ***************************************************************************** - ** Flush Hardware FIFO - ** - ** [in] context Pointer to the context. - ** [in] base Pointer to KeyScan instance register area - ** - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_FlushHwEvents(MXKEYSCAN_Type *base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Freeze the MIA clock - status = Cy_Keyscan_Mia_FreezeClk(base, context); - - if(status == CY_KEYSCAN_SUCCESS) - { - // Unfreeze the MIA clock. - status = Cy_Keyscan_Mia_UnfreezeClk(base, context); - // Flush the Fw fifo - Cy_Keyscan_Fq_Flush (context); - - // no keys currently pressed - context->keysPressedCount = 0U; - } - - } - return status; -} - -/** - ***************************************************************************** - ** Initialization of the keyscan FW circular queue. - ** This Function initialises circular queue to maintain the key codes for each key event generated. - ** - ** [in] context Pointer to the context. - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_Init_Context( cy_stc_keyscan_context_t* context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == context) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - /* Save element size, max elements, and buffer */ - context->elementSize = sizeof(cy_stc_key_event); - context->maxNumElements = KEYSCAN_FW_FIFO_SIZE; - context->readIndex = context->writeIndex = context->curNumElements = 0; - } - return status; -} - -/** - ***************************************************************************** - ** Registers for callback - ** - ** [in] cbEvents Pointer to the callback function. - ** - ** [in] context Pointer to the context. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Register_Callback(cy_cb_keyscan_handle_events_t cbEvents, cy_stc_keyscan_context_t* context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == context) || (NULL == cbEvents)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - /* Save callback function in context */ - context->cbEvents = cbEvents; - } - return status; -} - - -/** - ***************************************************************************** - ** Register Context with the driver - ** This Function registers for the event callback and firmware queue buffer. - ** - ** The Application must configure corresponding keyscan pins - ** according to requirements and settings of keyscan instance. - ** - ** [in] base Pointer to KeyScan instance register area - ** [in] config KeyScan module configuration. See #cy_stc_ks_config_t. - ** [out] context Pointer to the context. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Init(MXKEYSCAN_Type* base, cy_stc_ks_config_t* config, cy_stc_keyscan_context_t *context ) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == context) || (NULL == config)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - Cy_Keyscan_Init_Context(context); - // Reset the keyscan HW to ensure we start from a known state - status = Cy_Keyscan_Reset(base, context); - - if(status == CY_KEYSCAN_SUCCESS) - { - - context->keyscan_pollingKeyscanHw = false; - context->keysPressedCount = 0U; - - KEYSCAN_DEBOUNCE(base) = (_VAL2FLD(MXKEYSCAN_DEBOUNCE_MD_DEBOUNCE, config->macroDownDebCnt) | \ - _VAL2FLD(MXKEYSCAN_DEBOUNCE_MU_DEBOUNCE, config->macroUpDebCnt) | \ - _VAL2FLD(MXKEYSCAN_DEBOUNCE_U_DEBOUNCE, config->microDebCnt)); - - // Configure the control register except for the enable bit - KEYSCAN_CTL(base) = (_VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_GHOST_EN, config->ghostEnable) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KS_INT_EN, config->hostWakeupEnable) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN, MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_RC_EXT, MXKEYSCAN_KEYSCAN_CTL_RC_EXT_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_RCTC_ROW, config->noofRows) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_RCTC_COLUMN, config->noofColumns) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_PULL_HIGH, MXKEYSCAN_KEYSCAN_CTL_PULL_HIGH_DEFAULT) | \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KSI_DRV_HIGH, MXKEYSCAN_KEYSCAN_CTL_KSI_DRV_HIGH_DEFAULT)| \ - _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KYSCLK_STAYON,config->clkStayOn)); - - // Configure the control register and enable the KS HW - KEYSCAN_CTL(base) |= _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KS_EN, MXKEYSCAN_KEYSCAN_CTL_KS_EN_Msk); - } - - } - return status; -} - -/** - ***************************************************************************** - ** Reset Keyscan. - ** - ** base [in] Pointer to KEYSCAN instance register area. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Reset(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - uint32_t savedKeyscanCtrl; - - // Save the current value of the control register - savedKeyscanCtrl = KEYSCAN_CTL(base); - - // Flag that we are polling the keyscan HW. - // Avoids potentially infinite recursion - context->keyscan_pollingKeyscanHw = true; - - // Disable keyscan HW - KEYSCAN_CTL(base) &= ~MXKEYSCAN_KEYSCAN_CTL_KS_EN_Msk; - - // Delay to ensure that the HW is actually disabled - Cy_SysLib_DelayUs(100U); - - // Reset the HW multiple times to ensure that any partial counts are cleared - status = Cy_Keyscan_HwResetOnce(base, context); - status = Cy_Keyscan_HwResetOnce(base, context); - if(status == CY_KEYSCAN_SUCCESS) - { - // Clear FW event queue after a HW reset. Doesn't seem to be any reason - // to keep events around in the FW queue - status = Cy_Keyscan_Fq_Flush(context); - - // no keys currently pressed - context->keysPressedCount = 0U; - - // Clear the polling flag - context->keyscan_pollingKeyscanHw = false; - } - - // Restore the control register and enable scans if they were enabled before this function was called - KEYSCAN_CTL(base) = savedKeyscanCtrl; - } - return status; -} - -/** - ***************************************************************************** - ** Enable Keyscan. - ** - ** base [in] Pointer to KeyScan instance register area. - ** context [in] Pointer to the context. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Enable(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - KEYSCAN_CTL(base) |= _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_KS_EN, MXKEYSCAN_KEYSCAN_CTL_KS_EN_Msk); - } - return status; -} - -/** - ***************************************************************************** - ** Disable keyscan - ** - ** base [in] Pointer to KeyScan instance register area. - ** context [in] Pointer to the context. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Disable(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - Cy_Keyscan_Reset(base, context); - // Disable keyscan HW - KEYSCAN_CTL(base) &= ~MXKEYSCAN_KEYSCAN_CTL_KS_EN_Msk; - } - return status; -} - -/** - ***************************************************************************** - ** Events pending - ** - ** base [in] Pointer to KeyScan instance register area. - ** context [in] Pointer to the context. - ** eventsPending [out] Pointer to the eventsPending. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_EventsPending(MXKEYSCAN_Type* base, cy_stc_keyscan_context_t *context, bool *eventsPending) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - uint8_t numElements; - /* Check if pointers are valid */ - if ((NULL == base) || (NULL == context) || (NULL == eventsPending)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Return whether any events are in the FW fifo or not - status = Cy_Keyscan_Fq_GetCurNumElements( context, &numElements); - if(numElements == 0) - { - *eventsPending = false; - } - else - { - *eventsPending = true; - } - } - return status; -} - -/** - ***************************************************************************** - ** Get Next event from FW Queue - ** - ** base [in] Pointer to KeyScan instance register area. - ** context [in] Pointer to the context. - ** event [out] Pointer to the next event. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetNextEvent(MXKEYSCAN_Type* base, cy_stc_key_event *event, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ((NULL == base) || (NULL == context) || (NULL == event)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // Get the next event from the FW FIFO and return it. - // The get function returns CY_KEYSCAN_EVENT_NONE if the FW fifo is empty - status = Cy_Keyscan_GetEvent(context, event); - } - return status; -} - -/** - ***************************************************************************** - ** Setup interrupt source to be accepted. - ** - ** base [in] Pointer to KeyScan instance register area. - ** mask [in] The mask with the OR of the interrupt source to be accepted. - ** See \ group_keyscan_intr_mask_macro for the set of constants. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_SetInterruptMask(MXKEYSCAN_Type* base, uint32_t mask) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == base) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - KEYSCAN_INTR_MASK(base) = mask; - } - return status; -} - -/** - ***************************************************************************** - ** Return interupt mask setting. - ** - ** base [in] Pointer to KeyScan instance register area. - ** mask [out] The mask with the OR of the interrupt source which is masked. - ** See \ group_keyscan_intr_mask_macro for the set of constants. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetInterruptMask(MXKEYSCAN_Type* base, uint32_t *mask) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == mask)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - *mask = KEYSCAN_INTR_MASK(base); - } - return status; -} - -/** - ***************************************************************************** - ** Return interupt masked status. - ** - ** base [in] Pointer to KeyScan instance register area. - ** status [out] The mask with the OR of the interrupt source which occurs. - ** See \ group_keyscan_intr_mask_macro for the set of constants. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetInterruptMaskedStatus(MXKEYSCAN_Type* base, uint32_t *status) -{ - cy_en_ks_status_t return_status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == status)) - { - return_status = CY_KEYSCAN_BAD_PARAM; - } - else - { - *status = KEYSCAN_INTR_MASKED(base); - } - return return_status; -} - -/** - ***************************************************************************** - ** Return interupt raw status. - ** - ** base [in] Pointer to Keyscan instance register area. - ** status [out] The mask with the OR of the interrupt source which occurs. - ** See \ group_keyscan_intr_mask_macro for the set of constants. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_GetInterruptStatus(MXKEYSCAN_Type* base, uint32_t *status) -{ - cy_en_ks_status_t return_status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == status)) - { - return_status = CY_KEYSCAN_BAD_PARAM; - } - else - { - *status = KEYSCAN_INTR(base) ; - } - return return_status; -} - -/** - ***************************************************************************** - ** Clear interupt status. - ** - ** base [in] Pointer to Keyscan instance register area. - ** mask [in] The mask with the OR of the interrupt source to be cleared. - ** See \ group_keyscan_intr_mask_macro for the set of constants. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_ClearInterrupt(MXKEYSCAN_Type* base, uint32_t mask) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == base) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - KEYSCAN_INTR(base) = mask; - } - return status; -} - -/** - ***************************************************************************** - ** Handler for keyscan interrupts. - ** Applications have to call this function from keyscan interrupt handler. - ** - ** base [in] Pointer to Keyscan instance register area. - ** context [in] Pointer to the context. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_Interrupt_Handler(MXKEYSCAN_Type *base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - /* internally calls Cy_Keyscan_getEventsFromHWFifo to read from the fifo. */ - Cy_Keyscan_Mia_FreezeClk(base, context); - - /* Unfreeze the clock once read from fifo is complete */ - Cy_Keyscan_Mia_UnfreezeClk(base, context); - - /* notify application to read from the sw fifo. - Application has to call Cy_Keyscan_getNextEvent() in a loop till the - the return value is CY_KEYSCAN_EVENT_NONE */ - - context->cbEvents(); - } - return status; -} - -/** - ***************************************************************************** - ** HReads from Hardware fifo. - ** called when Applications call keyscan interrupt handler. - ** - ** base [in] Pointer to Keyscan instance register area. - ** context [in] Pointer to the context. - ** - *****************************************************************************/ -static cy_en_ks_status_t Cy_Keyscan_GetEventsFromHWFifo(MXKEYSCAN_Type *base, cy_stc_keyscan_context_t *context) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if ( (NULL == base) || (NULL == context)) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - bool ghostDetected; - uint8_t keyCode; - uint8_t numEvents; - uint32_t scanCycleOfLastEvent = 0; - bool firstEvent; - cy_stc_key_event event; - - // No ghost events detected to begin with - ghostDetected = false; - - // Processing for first event is slightly different from subsequent - // events. Set the first event flag on - firstEvent = true; - - Cy_Keyscan_Fq_MarkCurrentEventForRollBack(context); - - // Get the number of events present in the event FIFO - numEvents = _FLD2VAL(MXKEYSCAN_KEYFIFO_CNT_KEYFIFO_CNT, KEYSCAN_KEYFIFO_CNT(base)); - - // Now read and copy the events into the FW fifo. - while (numEvents--) - { - // Read another event from the HW FIFO - keyCode = _FLD2VAL(MXKEYSCAN_KEYFIFO_KEYFIFO, KEYSCAN_KEYFIFO(base)); - - // HW can spit out 0xff events that don't mean anything. This happens - // after a reset when the FW and HW get out of sync. The simplest way to deal - // with them is to treat them like a ghost since we have no idea what the actual HW state - // is. The caller should then generate a reset. - - // Did we see a ghost? - if (keyCode == KEYSCAN_KEYCODE_GHOST) - { - // Yes. Set the ghost detected flag - ghostDetected = true; - } - - // If we detect a ghost we discard all events, even those belonging - // to subsequent scan cycles. - if (!ghostDetected) - { - // So we don't have a ghost - - // Check if this event belongs to a different scan cycle than the previous event - if (!firstEvent && - (_FLD2VAL(MXKEYSCAN_KEYFIFO_TRACK_SCAN_CYCLE, KEYSCAN_KEYFIFO(base)) ^ scanCycleOfLastEvent)) - { - // It does. Add an end of scan cycle event to the FW fifo - event.keyCode = KEYSCAN_KEYCODE_END_OF_SCAN_CYCLE; - Cy_Keyscan_PutEvent(context, &event); - - // Save the current fifo index for rollback to the last scan cycle - Cy_Keyscan_Fq_MarkCurrentEventForRollBack(context); - } - - // Subsequent events are not first events - firstEvent = false; - - // Save the scan cycle of the new event for later use - scanCycleOfLastEvent = (_FLD2VAL(MXKEYSCAN_KEYFIFO_TRACK_SCAN_CYCLE, KEYSCAN_KEYFIFO(base))); - - // Add new event to the FW fifo - event.keyCode = keyCode; - event.upDownFlag = _FLD2VAL(MXKEYSCAN_KEYFIFO_KEY_UP_DOWN, KEYSCAN_KEYFIFO(base)); - event.scanCycleFlag = _FLD2VAL(MXKEYSCAN_KEYFIFO_TRACK_SCAN_CYCLE, KEYSCAN_KEYFIFO(base)); - - // keep track of the number of unmatched key down events by - // incrementing every time get key down event, and decrementing - // every time get a key up event - if (event.upDownFlag) - { - // since should never get a key up event without a key - // down event, don't decrement if already 0 - if (context->keysPressedCount > 0) - { - context->keysPressedCount--; // detected key up event - } - } - else - { - context->keysPressedCount++; // detected key down event - } - - Cy_Keyscan_PutEvent(context, &event); - } - } - - // Note that we are ignoring the case where the FW scans the HW just - // as its in the middle of detecting an overflow condition. If - // an overflow is detected, we really don't know what is the current - // state of the matrix. It probably doesn't matter that we don't catch - // all the keys. Current plan is to reset the HW in case of an overflow - // to allow it to accurately capture the current state of the keyboard - // This seems adequate at this time. - - // Check if an overflow or ghost condition has been detected - if ( ghostDetected || (_FLD2VAL(MXKEYSCAN_MIA_STATUS_OVERFLOW_STATUS, KEYSCAN_MIA_STATUS(base))) ) - { - // Rollback the FW fifo to the last save point - Cy_Keyscan_Fq_RollbackUptoMarkedEvents(context); - - // Now place a rollover event into the FW fifo - event.keyCode = KEYSCAN_KEYCODE_ROLLOVER; - Cy_Keyscan_PutEvent(context, &event); - - if ((_FLD2VAL(MXKEYSCAN_KEYSCAN_CTL_GHOST_EN, KEYSCAN_CTL(base)))) - { - // Enable the HW reset bit. After the reset the HW will capture - // the current state of the system - KEYSCAN_CTL(base) |= MXKEYSCAN_KEYSCAN_CTL_KYS_RST_EN_Msk; - } - // clear the pressed key count. - context->keysPressedCount = 0; - } - else - { - // If we queued any events, add an end of scan cycle marker to the end - // We can use the first event flag; it will be cleared if we - // added any events - if (!firstEvent) - { - // Now place a rollover event into the FW fifo - event.keyCode = KEYSCAN_KEYCODE_END_OF_SCAN_CYCLE; - Cy_Keyscan_PutEvent(context, &event); - } - } - - // Set the "clear reported keys" bit. This will clear the HW when the MIA clock is unfrozen - KEYSCAN_MIA_CTL(base) |= MXKEYSCAN_MIA_CTL_REPORTED_CLEAR_KYS_Msk; - } - return status; -} - -/** - ***************************************************************************** - ** Enables Ghost detection - ** - ** base [in] Pointer to Keyscan instance register area. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_EnableGhostDetection(MXKEYSCAN_Type *base) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == base) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // enable ghost detection - KEYSCAN_CTL(base) |= _VAL2FLD(MXKEYSCAN_KEYSCAN_CTL_GHOST_EN, MXKEYSCAN_KEYSCAN_CTL_GHOST_EN_Msk); - } - return status; -} - -/** - ***************************************************************************** - ** Disables Ghost detection - ** - ** base [in] Pointer to Keyscan instance register area. - *****************************************************************************/ -cy_en_ks_status_t Cy_Keyscan_DisableGhostDetection(MXKEYSCAN_Type *base) -{ - cy_en_ks_status_t status = CY_KEYSCAN_SUCCESS; - /* Check if pointers are valid */ - if (NULL == base) - { - status = CY_KEYSCAN_BAD_PARAM; - } - else - { - // disable ghost detection - KEYSCAN_CTL(base) &= ~MXKEYSCAN_KEYSCAN_CTL_GHOST_EN_Msk; - } - return status; -} - -#endif /* CY_IP_MXKEYSCAN */ -/*****************************************************************************/ -/* EOF (not truncated) */ -/*****************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_lin.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_lin.c deleted file mode 100644 index 6c82d3f018..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_lin.c +++ /dev/null @@ -1,634 +0,0 @@ -/***************************************************************************//** -* \file cy_lin.c -* \version 1.0 -* -* \brief -* Provides an API declaration of the LIN driver -* -******************************************************************************** -* \copyright -* Copyright 2020-2021, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ -#include "cy_device.h" -#if defined (CY_IP_MXLIN) -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include "cy_lin.h" - -/*****************************************************************************/ -/* Local pre-processor symbols/macros ('#define') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Global variable definitions (declared in header file with 'extern') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local type definitions ('typedef') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local variable definitions ('static') */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Local function prototypes ('static') */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Function implementation - global ('extern') and local ('static') */ -/*****************************************************************************/ -/** - ***************************************************************************** - ** Cy_Lin_DeInit - ** DeInitialisation of a LIN module. - ** This Function deinitialises the selected LIN channel. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_DeInit( LIN_CH_Type* base ) -{ - cy_en_lin_status_t status = CY_LIN_SUCCESS; - - /* Check if pointers are valid */ - if ( NULL == base ) - { - return CY_LIN_BAD_PARAM; - } - - /* Disable the LIN Channel and set the values to default. */ - LIN_CH_CTL0(base) = LIN_CH_CTL0_DEFAULT; - - /* Clear the data registers */ - LIN_CH_DATA0(base) = 0UL; - LIN_CH_DATA0(base) = 0UL; - - /* Clear the PID filed */ - LIN_CH_PID_CHECKSUM(base) &= _VAL2FLD(LIN_CH_PID_CHECKSUM_PID, 0U); - - return status; -} - -/** - ***************************************************************************** - ** Cy_Lin_Init - ** Initialisation of a LIN module. - ** This Function initialises the LIN according the Options setup in the - ** passed Config Struct. Several Checkings are done before that and an error - ** is returned if invalid Modes are requested. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_Init( LIN_CH_Type* base, const cy_stc_lin_config_t *pstcConfig) -{ - cy_en_lin_status_t status = CY_LIN_SUCCESS; - - /* Check if pointers are valid */ - if ( ( NULL == base ) || - ( NULL == pstcConfig ) ) - { - status = CY_LIN_BAD_PARAM; - } - else if (pstcConfig->masterMode && - ((LIN_MASTER_BREAK_FILED_LENGTH_MIN > pstcConfig->breakFieldLength) || - (LIN_BREAK_WAKEUP_LENGTH_BITS_MAX < pstcConfig->breakFieldLength))) - { - status = CY_LIN_BAD_PARAM; - } - else if (LIN_BREAK_WAKEUP_LENGTH_BITS_MAX < pstcConfig->breakFieldLength) - { - status = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_CTL0(base) = (_VAL2FLD(LIN_CH_CTL0_STOP_BITS, pstcConfig->stopBit) | \ - _VAL2FLD(LIN_CH_CTL0_AUTO_EN, pstcConfig->linTransceiverAutoEnable) | \ - _VAL2FLD(LIN_CH_CTL0_BREAK_DELIMITER_LENGTH, pstcConfig->breakDelimiterLength) | \ - _VAL2FLD(LIN_CH_CTL0_BREAK_WAKEUP_LENGTH, (pstcConfig->breakFieldLength - 1U)) | \ - _VAL2FLD(LIN_CH_CTL0_MODE, LIN_CH_CTL0_MODE_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_BIT_ERROR_IGNORE, LIN_CH_CTL0_BIT_ERROR_IGNORE_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_PARITY, LIN_CH_CTL0_PARITY_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_PARITY_EN, LIN_CH_CTL0_PARITY_EN_DEFAULT) | \ - _VAL2FLD(LIN_CH_CTL0_FILTER_EN, pstcConfig->filterEnable) | \ - _VAL2FLD(LIN_CH_CTL0_ENABLED, 1U)); - - } - - return status; -} - -/** - ***************************************************************************** - ** Cy_Lin_ReadData. - ** Read response data. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_ReadData( LIN_CH_Type* base, uint8_t *data ) -{ - cy_en_lin_status_t status = CY_LIN_SUCCESS; - uint8_t cnt; - uint8_t length; - uint8_t data0[4]; - uint8_t data1[4]; - - /* Check if pointers are valid */ - if( ( NULL == base ) || - ( NULL == data )) - { - status = CY_LIN_BAD_PARAM; - } - /* Check if the response is received successfully */ - else if( ( 0U == _FLD2VAL(LIN_CH_CMD_TX_RESPONSE, LIN_CH_CMD(base))) && - ( 0u == _FLD2VAL(LIN_CH_STATUS_RX_BUSY, LIN_CH_STATUS(base)))) - { - length = _FLD2VAL(LIN_CH_CTL1_DATA_NR, LIN_CH_CTL1(base)) + 1u; - /* Copy the data in to u8Data array */ - data0[0] = _FLD2VAL(LIN_CH_DATA0_DATA1, LIN_CH_DATA0(base)); - data0[1] = _FLD2VAL(LIN_CH_DATA0_DATA2, LIN_CH_DATA0(base)); - data0[2] = _FLD2VAL(LIN_CH_DATA0_DATA3, LIN_CH_DATA0(base)); - data0[3] = _FLD2VAL(LIN_CH_DATA0_DATA4, LIN_CH_DATA0(base)); - data1[0] = _FLD2VAL(LIN_CH_DATA1_DATA5, LIN_CH_DATA1(base)); - data1[1] = _FLD2VAL(LIN_CH_DATA1_DATA6, LIN_CH_DATA1(base)); - data1[2] = _FLD2VAL(LIN_CH_DATA1_DATA7, LIN_CH_DATA1(base)); - data1[3] = _FLD2VAL(LIN_CH_DATA1_DATA8, LIN_CH_DATA1(base)); - for ( cnt = 0; cnt < length; cnt++ ) - { - if( 4U > cnt ) - { - data[cnt] = data0[cnt]; - } - else - { - data[cnt] = data1[cnt - 4U]; - } - } - } - else - { - status = CY_LIN_BUSY; - } - - return status; -} - -/** - ***************************************************************************** - ** Cy_Lin_WriteData - ** Write response data. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_WriteData( LIN_CH_Type* base, const uint8_t *data, - uint8_t dataLength ) -{ - cy_en_lin_status_t status = CY_LIN_SUCCESS; - uint8_t data0[4U] = { 0 }; - uint8_t data1[4U] = { 0 }; - uint8_t cnt; - - /* Check if NULL pointer */ - if( ( NULL == base ) || - ( NULL == data ) ) - { - status = CY_LIN_BAD_PARAM; - } - /* Check if data length is valid */ - else if( LIN_DATA_LENGTH_MAX < dataLength ) - { - status = CY_LIN_BAD_PARAM; - } - /* Check if the bus is free */ - else if( 0U == _FLD2VAL(LIN_CH_STATUS_TX_BUSY, LIN_CH_STATUS(base)) ) - { - /* Write data in to the temp variables */ - for( cnt = 0U; cnt < dataLength; cnt++ ) - { - if( 4u > cnt ) - { - data0[cnt] = data[cnt]; - } - else - { - data1[cnt - 4u] = data[cnt]; - } - } - /* Write data to HW FIFO */ - LIN_CH_DATA0(base) = (_VAL2FLD(LIN_CH_DATA0_DATA1, data0[0]) | \ - _VAL2FLD(LIN_CH_DATA0_DATA2, data0[1]) | \ - _VAL2FLD(LIN_CH_DATA0_DATA3, data0[2]) | \ - _VAL2FLD(LIN_CH_DATA0_DATA4, data0[3])); - LIN_CH_DATA1(base) = (_VAL2FLD(LIN_CH_DATA1_DATA5, data1[0]) | \ - _VAL2FLD(LIN_CH_DATA1_DATA6, data1[1]) | \ - _VAL2FLD(LIN_CH_DATA1_DATA7, data1[2]) | \ - _VAL2FLD(LIN_CH_DATA1_DATA8, data1[3])); - } - else - { - status = CY_LIN_BUSY; - /* A requested operation could not be completed */ - } - - return status; -} - -/** - ***************************************************************************** - ** Cy_Lin_Enable - ** Enable LIN channel. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_Enable(LIN_CH_Type* base) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_CTL0(base) |= _VAL2FLD(LIN_CH_CTL0_ENABLED, 1U); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_Disable - ** Disable LIN channel. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_Disable(LIN_CH_Type* base) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_CTL0(base) &= _VAL2FLD(LIN_CH_CTL0_ENABLED, 0U); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_SetBreakWakeupFieldLength - ** Setup LIN break/wakeup field length. - ** Normaly this I/F is used for detection of the wakeup pulse. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetBreakWakeupFieldLength(LIN_CH_Type* base, uint8_t length) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - else if (LIN_BREAK_WAKEUP_LENGTH_BITS_MAX < length) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_CTL0(base) |= _VAL2FLD(LIN_CH_CTL0_BREAK_WAKEUP_LENGTH, (length - 1U)); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_SetChecksumType - ** Setup LIN checksum type setting - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetChecksumType(LIN_CH_Type* base, cy_en_lin_checksum_type_t type) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_CTL1(base) |= _VAL2FLD(LIN_CH_CTL1_CHECKSUM_ENHANCED, type); - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_SetDataLength - ** Setup LIN response field data length - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetDataLength(LIN_CH_Type* base, uint8_t length) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if ((NULL == base) || - (length > LIN_DATA_LENGTH_MAX) || - (length < LIN_DATA_LENGTH_MIN)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_CTL1(base) |= _VAL2FLD(LIN_CH_CTL1_DATA_NR, (length-1U)); - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_SetCmd - ** Setup LIN operation command - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetCmd(LIN_CH_Type* base, uint32_t command) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - /* The command cannot have both TX_HEADER and RX_HEADER master set's TX_HEADER and slave sets RX_HEADER. - If the Command is a wakup command then TX_HEADER, RX_HEADER, TX_RESPONSE and RX_RESPONSE are not valid. - */ - else if (((command & (LIN_CH_CMD_TX_HEADER_Msk | LIN_CH_CMD_RX_HEADER_Msk)) - == (LIN_CH_CMD_TX_HEADER_Msk | LIN_CH_CMD_RX_HEADER_Msk)) || - (((command & LIN_CH_CMD_TX_WAKEUP_Msk) != 0) && - ((command & (LIN_CH_CMD_TX_HEADER_Msk | - LIN_CH_CMD_TX_RESPONSE_Msk | - LIN_CH_CMD_RX_HEADER_Msk | - LIN_CH_CMD_RX_RESPONSE_Msk)) != 0))) - { - ret = CY_LIN_BAD_PARAM; - } - /* If software has already set the command and it is not complete then the channel must be busy processing the command. - beofre setting the command make sure that hardware has already set the bit to 0 for the above cases. - */ - else if (((_FLD2VAL(LIN_CH_CMD_TX_HEADER, LIN_CH_CMD(base)) != 0) && (command & LIN_CH_CMD_RX_HEADER_Msk) != 0) || - ((_FLD2VAL(LIN_CH_CMD_RX_HEADER, LIN_CH_CMD(base)) != 0) && (command & LIN_CH_CMD_TX_HEADER_Msk) != 0) || - ((_FLD2VAL(LIN_CH_CMD_TX_WAKEUP, LIN_CH_CMD(base)) != 0) && - ((command & (LIN_CH_CMD_TX_HEADER_Msk | - LIN_CH_CMD_TX_RESPONSE_Msk | - LIN_CH_CMD_RX_HEADER_Msk | - LIN_CH_CMD_RX_RESPONSE_Msk)) != 0))) - { - ret = CY_LIN_BUSY; - } - else - { - LIN_CH_CMD(base) = command; - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_SetHeader - ** Setup LIN header for master tx header operation - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetHeader(LIN_CH_Type* base, uint8_t id) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - uint8_t tempPID; - uint8_t parity_P1, parity_P0; - - if ((NULL == base) || - (LIN_ID_MAX < id)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - /* Calculate the Parity bits P0 & P1 - Parity is calculated as per the formula given - - P[1] = ! (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) - - P[0] = (ID[4] ^ ID[2] ^ ID[1] ^ ID[0]) - */ - parity_P0 = ((id) ^ (id>>1u) ^ - (id>>2u) ^ (id>>4u)) & 0x01u; - parity_P1 = (~((id>>1u) ^ (id>>3u) ^ - (id>>4u) ^ (id>>5u))) & 0x01u; - /* Assign the Parity bits and the header values in to the tempPID */ - tempPID = id | ((uint8_t) parity_P0<<6u) | ((uint8_t) parity_P1<<7u); - /* Write the TempID value in to the TX_HEADER register */ - LIN_CH_PID_CHECKSUM(base) = _VAL2FLD(LIN_CH_PID_CHECKSUM_PID, tempPID); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_GetHeader - ** Return received LIN header - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetHeader(LIN_CH_Type* base, uint8_t *id, uint8_t *parity) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if ((NULL == base) || - (NULL == id) || - (NULL == parity)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - /* Store received ID and parity bits */ - uint8_t temp = _FLD2VAL(LIN_CH_PID_CHECKSUM_PID, LIN_CH_PID_CHECKSUM(base)); - *parity = (temp >> 6u); - *id = (temp & LIN_ID_MAX); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_SetInterruptMask - ** Setup interrupt source to be accepted. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_SetInterruptMask(LIN_CH_Type* base, uint32_t mask) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_INTR_MASK(base) = mask; - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_GetInterruptMask - ** Return interupt mask setting. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetInterruptMask(LIN_CH_Type* base, uint32_t *mask) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if ((NULL == base) || - (NULL == mask)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - *mask = LIN_CH_INTR_MASK(base); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_GetInterruptMaskedStatus - ** Return interupt masked status. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetInterruptMaskedStatus(LIN_CH_Type* base, uint32_t *status) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if ((NULL == base) || - (NULL == status)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - *status = LIN_CH_INTR_MASKED(base); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_GetInterruptStatus - ** Return interupt raw status. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetInterruptStatus(LIN_CH_Type* base, uint32_t *status) -{ - - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if ((NULL == base) || - (NULL == status)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - *status = LIN_CH_INTR(base) ; - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_ClearInterrupt - ** Clear interupt status. - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_ClearInterrupt(LIN_CH_Type* base, uint32_t mask) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - LIN_CH_INTR(base) = mask; - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Lin_GetStatus - ** Return LIN module status - *****************************************************************************/ -cy_en_lin_status_t Cy_Lin_GetStatus(LIN_CH_Type* base, uint32_t *status) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if ((NULL == base) || - (NULL == status)) - { - ret = CY_LIN_BAD_PARAM; - } - else - { - *status = LIN_CH_STATUS(base); - } - - return ret; -} - -/** - ***************************************************************************** - ** Cy_Status_EnOut_Enable - ** Enables LIN channel 'en' out - *****************************************************************************/ -cy_en_lin_status_t Cy_Status_EnOut_Enable(LIN_CH_Type* base) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - /* check if auto enabled is set or not */ - bool auto_enable = _FLD2VAL(LIN_CH_CTL0_AUTO_EN, LIN_CH_CTL0(base)); - if(!auto_enable) - { - /* Enable EN out */ - LIN_CH_TX_RX_STATUS(base) |= _VAL2FLD(LIN_CH_TX_RX_STATUS_EN_OUT, 1U); - } - return ret; -} - -/** - ***************************************************************************** - ** Cy_Status_EnOut_Disable - ** Disables LIN channel 'en' out - *****************************************************************************/ -cy_en_lin_status_t Cy_Status_EnOut_Disable(LIN_CH_Type* base) -{ - cy_en_lin_status_t ret = CY_LIN_SUCCESS; - - if (NULL == base) - { - ret = CY_LIN_BAD_PARAM; - } - /* check if auto enabled is set or not */ - bool auto_enable = _FLD2VAL(LIN_CH_CTL0_AUTO_EN, LIN_CH_CTL0(base)); - if(!auto_enable) - { - /* Disable EN out */ - LIN_CH_TX_RX_STATUS(base) &= ~LIN_CH_TX_RX_STATUS_EN_OUT_Msk; - } - return ret; -} - -#endif /* CY_IP_MXLIN */ -/*****************************************************************************/ -/* EOF (not truncated) */ -/*****************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mpc.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mpc.c deleted file mode 100644 index 8813396664..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mpc.c +++ /dev/null @@ -1,318 +0,0 @@ -/***************************************************************************//** -* \file cy_mpc.c -* \version 1.0 -* -* \brief -* Provides an API implementation of the secure MPC driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_M33SYSCPUSS) - -#include "cy_mpc.h" - -/******************************************************************************* -* Function Name: Cy_Mpc_ConfigRotMpcStruct -****************************************************************************//** -* -* \brief Initializes the referenced mpc by setting the PC, NS/S and RW/R/W -* permissions. This is called by ROT module. -* -* -* \param base -* Base address of mpc being configured -* -* \param rotConfig -* MPC configuration structure to be used by the ROT code -* -* \return -* Initialization status -* -*******************************************************************************/ -cy_en_mpc_status_t Cy_Mpc_ConfigRotMpcStruct(RAMC_MPC_Type* base, const cy_stc_mpc_rot_cfg_t* rotConfig) -{ - uint32_t addr; - uint32_t size; - uint32_t addrBoundary, sizeBoundary; - uint32_t totalBlocks, startNib, freeBlocks, endNib, temp1; - uint32_t newAddr, newSize; - uint32_t i, partBlocks, value, blkIdx,loopCnt; - uint32_t secure, access, mask; - uint32_t blockSize; - uint32_t pc; - - addr = rotConfig->startAddress; - size = rotConfig->size; - access = rotConfig->access; - secure = rotConfig->secure; - pc = rotConfig->pc; - //To get Block size follow expression (1<<(BLOCK_SIZE+5)) - blockSize = 1 << (rotConfig->regionSize + 5); - addrBoundary = addr%(blockSize); - sizeBoundary = size%(blockSize); - - if (addrBoundary) { - return CY_MPC_BAD_PARAM; - } - - if (sizeBoundary) { - return CY_MPC_BAD_PARAM; - } - - /* - For each nibble: - - bit[0] : NS (0 indicates secure, 1 indicates non-secure) - - bit[1] : R (0 indicates read access not allowed. 1 indicates read access allowed) - - bit[2] : W (0 indicates write access not allowed, 1 indicates write access allowed) - - bit[3] : Reseved - */ - if (access == CY_MPC_ACCESS_DISABLED) - mask = 0x00000000; - else if (access == CY_MPC_ACCESS_R) - mask = 0x00000002; - else if (access == CY_MPC_ACCESS_W) - mask = 0x00000004; - else if (access == CY_MPC_ACCESS_RW) - mask = 0x00000006; - else - { - return CY_MPC_BAD_PARAM; - } - - if (secure == CY_MPC_SECURE) - mask &= 0xFFFFFFFE; - else if (secure == CY_MPC_NON_SECURE) - mask |= 0x00000001; - else - { - return CY_MPC_BAD_PARAM; - } - - if (pc > CY_MPC_PC_2) - return CY_MPC_BAD_PARAM; - - //Set PC value - base->ROT_BLK_PC = pc; - - totalBlocks = size/blockSize; - temp1 = addr/blockSize; - startNib = temp1 % 8; - freeBlocks = 8 - startNib; - blkIdx = addr/(blockSize * 8); - value = 0; - - if (totalBlocks <= freeBlocks) - { - endNib = totalBlocks + startNib - 1; - - for (i = startNib; i <= endNib; i++) - { - value = value | (mask << 4 * i); - } - - base->ROT_BLK_IDX = blkIdx; - base->ROT_BLK_LUT = value; - return CY_MPC_SUCCESS; - } - else - { - endNib = 7; - newAddr = ((addr/(8 * blockSize)) + 1) * blockSize * 8; - newSize = size - (freeBlocks*blockSize); - - for (i = startNib; i <= endNib; i++) - { - value = value | (mask << 4 * i); - } - - base->ROT_BLK_IDX = blkIdx; - base->ROT_BLK_LUT = value; - blkIdx++; - } - - blkIdx = newAddr/(blockSize * 8); - loopCnt = newSize/(blockSize * 8); - totalBlocks = newSize/(blockSize); - partBlocks = totalBlocks%8; - - value = 0; - for (i = 0; i < loopCnt; i++) - { - int j; - for ( j = 0; j < 8; j++) - value = value | (mask << (4 * j)); - base->ROT_BLK_IDX = blkIdx; - base->ROT_BLK_LUT = value; - blkIdx++; - } - - if (partBlocks) - { - value = 0; - for (i = 0; i < partBlocks; i++) - { - value = value | (mask << 4 * i); - } - base->ROT_BLK_IDX = blkIdx; - base->ROT_BLK_LUT = value; - } - return CY_MPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_Mpc_ConfigMpcStruct -****************************************************************************//** -* -* \brief Initializes the referenced mpc by setting the NS/S -* permissions. This is called by TFM module. -* -* -* \param base -* Base address of mpc being configured -* -* \param config -* MPC configuration structure to be used by the TFM code -* -* \return -* Initialization status -* -*******************************************************************************/ -cy_en_mpc_status_t Cy_Mpc_ConfigMpcStruct(RAMC_MPC_Type* base, const cy_stc_mpc_cfg_t* config) -{ - uint32_t addr; - uint32_t size; - uint32_t addrBoundary, sizeBoundary; - uint32_t totalBlocks, startBit, freeBlocks, endBit, temp1; - uint32_t newAddr, newSize; - uint32_t i, partBlocks, value, blkIdx,loopCnt; - uint32_t blockSize, secure; - - addr = config->startAddress; - size = config->size; - secure = config->secure; - - if (config->regionSize != CY_MPC_SIZE_4KB) - return CY_MPC_BAD_PARAM; - - blockSize = 1 << (config->regionSize + 5); - - addrBoundary = addr%(blockSize); - sizeBoundary = size%(blockSize); - - if (addrBoundary) { - return CY_MPC_BAD_PARAM; - } - - if (sizeBoundary) { - return CY_MPC_BAD_PARAM; - } - - totalBlocks = size/blockSize; - temp1 = addr/blockSize; - - startBit = temp1 % 32; - freeBlocks = 32 - startBit; - - blkIdx = addr/(blockSize * 32); - - value = 0; - if (totalBlocks <= freeBlocks) - { - endBit = totalBlocks + startBit - 1; - - for (i = startBit; i <= endBit; i++) - { - value = value | (1 << i); - } - - base->BLK_IDX = blkIdx; - - if (secure == CY_MPC_SECURE) - { - value = ~value; - base->BLK_LUT = base->BLK_LUT & value; - } - else - { - base->BLK_LUT = (uint32_t)(value); - } - return CY_MPC_SUCCESS; - } - else - { - endBit = 31; - newAddr = ((addr/(32 * blockSize)) + 1) * blockSize * 32; - newSize = size - (freeBlocks * blockSize); - - for (i = startBit; i <= endBit; i++) - { - value = value | (1 << i); - } - - base->BLK_IDX = blkIdx; - base->BLK_LUT = value; - blkIdx++; - } - - blkIdx = newAddr/(blockSize * 32); - loopCnt = newSize/(blockSize * 32); - totalBlocks = newSize/(blockSize); - partBlocks = totalBlocks % 32; - - for (i = 0; i < loopCnt; i++) - { - value = 0xFFFFFFFF; - base->BLK_IDX = blkIdx; - base->BLK_LUT = value; - blkIdx++; - } - - if (partBlocks) - { - value = 0; - for (i = 0; i < partBlocks; i++) - { - value = value | (1 << i); - } - base->BLK_IDX = blkIdx; - base->BLK_LUT = value; - } - return CY_MPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_Mpc_Lock -****************************************************************************//** -* -* \brief Locks the MPC configuration -* -* -* \param base -* Base address of mpc being configured -* -*******************************************************************************/ -void Cy_Mpc_Lock(RAMC_MPC_Type* base) -{ - base->CTRL = _VAL2FLD(RAMC_MPC_CTRL_LOCK, 1); -} - -#endif -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxconnbridge.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxconnbridge.c deleted file mode 100644 index b23fdc9730..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxconnbridge.c +++ /dev/null @@ -1,96 +0,0 @@ -/***************************************************************************//** -* \file cy_mxconnbridge.c -* \version 1.0 -* -* Provides an API implementation of the MXCONNBRIDGE driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXCONNBRIDGE) - -#include "cy_mxconnbridge.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_WLANResetMux -****************************************************************************//** -* -* Configure the WLAN RESET MUX bit to determine WLAN RESET value -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param value -* value -* -* \return -* Logic level present on the signal -* 0 = WLAN reset is determined by WLAN_RESET_CTL -* 1 = WLAN reset is determined by RST_LHL_GPIO -* -* \funcusage -* -*******************************************************************************/ -void Cy_MXCONNBRIDGE_WLANResetMux(MXCONNBRIDGE_Type *base, uint32_t value) -{ - uint32_t tempReg; - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_VALUE_VALID(value)); - - - tempReg= MXCONNBRIDGE_AP_WLAN_CTL(base) & ~(MXCONNBRIDGE_SDIO_RESET_CTL_WLAN_RESET_N_MUX_Msk); - MXCONNBRIDGE_AP_WLAN_CTL(base) = tempReg | _VAL2FLD(MXCONNBRIDGE_SDIO_RESET_CTL_WLAN_RESET_N_MUX, value); -} - -/******************************************************************************* -* Function Name: Cy_MXCONNBRIDGE_SetWLANSDIOMux -****************************************************************************//** -* -* Configure to choose internal or external SDIO -* -* \param base -* Pointer to the mxconnbridge base address -* -* \param value -* 1'b0 means we use internal SDIO else 1'b1 means we use external SDIO -* -* \funcusage -* -*******************************************************************************/ -void Cy_MXCONNBRIDGE_SetWLANSDIOMux(MXCONNBRIDGE_Type *base, uint32_t value) -{ - uint32_t tempReg; - CY_ASSERT_L2(CY_MXCONNBRIDGE_IS_VALUE_VALID(value)); - - - tempReg= MXCONNBRIDGE_AP_WLAN_CTL(base) & ~(MXCONNBRIDGE_SDIO_RESET_CTL_WLAN_SDIO_MUX_Msk); - MXCONNBRIDGE_AP_WLAN_CTL(base) = tempReg | _VAL2FLD(MXCONNBRIDGE_SDIO_RESET_CTL_WLAN_SDIO_MUX, value); -} - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXCONNBRIDGE */ -/* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxotpc.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxotpc.c deleted file mode 100644 index 481c8403ec..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxotpc.c +++ /dev/null @@ -1,846 +0,0 @@ -/***************************************************************************//** -* \file cy_mxotpc.c -* \version 1.0 -* -* Provides an API implementation of the OTP driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXS28OTPC) - -#include "cy_mxotpc.h" -#include - -/* Static Functions */ -static cy_mxotpc_status_t Cy_MXOTPC_GetWriteProtectedData(uint32_t otpRowNum, uint32_t otpWriteData, uint32_t *otpWriteProtData); - -/* Static Data types */ -/** OTP Program Enable Sequence Data */ -static uint8_t otpProgramEnable[] = { 0xf, 0x4, 0x8, 0xd}; - -/** \cond PARAM_CHECK_MACROS */ -/** Parameter check macros */ - -#define CY_MXOTPC_IS_ROW_VALID(row) (row < CY_MXOTPC_MAX_OTP_ROW) -#define CY_MXOTPC_IS_BITNUM_VALID(bit) (bit < 32) -#define CY_MXOTPC_IS_DEST_ADDR_ALIGNED(addr) (!((uint32_t)addr % 4u)) -#define CY_MXOTPC_IS_ARRAY_SIZE_VALID(row, size) ((row+size) < CY_MXOTPC_MAX_OTP_ROW) -#define CY_MXOTPC_IS_SIZE_VALID(size) (size != 0) -/** \endcond */ - -/******************************************************************************* -* Function Name: Cy_MXOTPC_Init -****************************************************************************//** -* -* Initializes the MXOTP Driver: -* - Enables the MXOTPC IP. -* -* \param mxotpcConfig -* This structure contains the data that needs to be filled in OTP_CTL register. -* -* Note - Allow NULL also, meaning OTP IP will go with default Configuration -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_Init(cy_mxotpc_ctl_config_t const *mxotpcConfig) -{ - Cy_MXOTPC_IpEnable(); - - if(mxotpcConfig != NULL) - Cy_MXOTPC_OtpCtlConfig(mxotpcConfig); - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_DeInit -****************************************************************************//** -* -* DeInitializes the MXOTP Driver: -* - Disables the MXOTPC IP. -* -* Note - Allow NULL also, meaning OTP IP will go with default Configuration -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_DeInit(void) -{ - Cy_MXOTPC_IpDisable(); - - return CY_MXOTPC_SUCCESS; -} - - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteProgramSequence -****************************************************************************//** -* -* Program Sequence for Writes -* -* 1.Write Following Bit -* OTP_CTL.OTPProg_En =1 // Enable OTP programming at top level control -* 2.Check whether OTP is busy or not -* OTP_CMD.START == 0 // OTP is not busy -* 3.Check whether programming is enabled or not (PROGRAM Enable Seq) -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* If this bit is not set, perform following steps, otherwise skip. -* a.OTP commands to enable OTP Programming -* i.Write OTP_PROGDATA = 0xF -* ii.Write OTP_CMD reg (with CMD =0x02), VALUE: 0x9100_0000 -* iii.Wait for OTP_CMD.START == 0 -* iv.Repeat from point i to iii for OTP_PROGDATA 0x4, 0x8 and 0xd in sequence -* Check whether programming is enabled or not -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteProgramSequence(void) -{ - uint32_t idx; - cy_mxotpc_cmd_t otpCmd = {0, 0, 0}; - - /* Check if programming is already enabled or not */ - if(!Cy_MXOTPC_OtpGetStatus(MXOTPC_OTP_STATUS_PROGOK_Msk)) - { - /* PROGRAM Sequence */ - /* 1.Write Following Bit - * OTP_CTL.OTPProg_En =1 // Enable OTP programming at top level control */ - Cy_MXOTPC_OtpProgEnable(true); - - /* 2.Check whether OTP is busy or not - * OTP_CMD.START == 0 // OTP is not busy */ - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_TIMEOUT; - - /* 3.Check whether programming is enabled or not (PROGRAM Enable Seq) - * OTP_STATUS.ProgOK == 1 // OTP programming enabled - * If this bit is not set, perform following steps, otherwise skip. - * a.OTP commands to enable OTP Programming. - * i.Write OTP_PROGDATA = 0xF - * ii.Write OTP_CMD reg (with CMD =0x02), VALUE: 0x9100_0000 - * iii.Wait for OTP_CMD.START == 0 - * iv.Repeat from point i to iii for OTP_PROGDATA 0x4, 0x8 and 0xd in sequence - * Check whether programming is enabled or not - * OTP_STATUS.ProgOK == 1 // OTP programming enabled */ - for(idx = 0; idx < sizeof(otpProgramEnable); idx++) - { - Cy_MXOTPC_OtpSetProgData(otpProgramEnable[idx]); - - otpCmd.cmd = CY_MXOTPC_OTP_PROGENABLE_CMD; - Cy_MXOTPC_OtpCmd(&otpCmd); - - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_TIMEOUT; - } - if(!Cy_MXOTPC_OtpGetStatus(MXOTPC_OTP_STATUS_PROGOK_Msk)) - return CY_MXOTPC_WRITE_ERROR; - } - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_GetWriteProtectedData -****************************************************************************//** -* -* Write Protection for already set OTP bits -* -* \param otpRowNum -* Contains the Row Number to be written -* \param otpWriteData -* Contains the Data to be written -* \param otpFinalWriteData -* Contains the corrected Data to be Written -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -static cy_mxotpc_status_t Cy_MXOTPC_GetWriteProtectedData(uint32_t otpRowNum, uint32_t otpWriteData, uint32_t *otpWriteProtData) -{ - uint32_t otpReadData; - cy_mxotpc_status_t status; - - status = Cy_MXOTPC_ReadRow( otpRowNum, &otpReadData ); - if( !status ) - { - *otpWriteProtData = (otpWriteData ^ otpReadData) & otpWriteData; - return CY_MXOTPC_SUCCESS; - } - else - return status; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteRowReadBack -****************************************************************************//** -* -* Writes a particular row with 32-bit data with/without ECC and reads the row back. -* -* Indirect PROGRAM Sequence -* 1.Write Following Bit -* OTP_CTL.OTPProg_En =1 // Enable OTP programming at top level control -* 2.Check whether OTP is busy or not -* OTP_CMD.START == 0 // OTP is not busy -* 3.Check whether programming is enabled or not (PROGRAM Enable Seq) -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* If this bit is not set, perform following steps, otherwise skip. -* a.OTP commands to enable OTP Programming -* i.Write OTP_PROGDATA = 0xF -* ii.Write OTP_CMD reg (with CMD =0x02), VALUE: 0x9100_0000 -* iii.Wait for OTP_CMD.START == 0 -* iv.Repeat from point i to iii for OTP_PROGDATA 0x4, 0x8 and 0xd in sequence -* Check whether programming is enabled or not -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* 4.Write OTP_PROGDATA register -* Write 32-bit data value to be programmed inside OTP_PROGDATA reg -* 5.WRITE OTP_CMD Register -* Write following value in OTP_CMD reg. -* For OTP_CMD command (0x0A) at 511th row, you may use following value, -* 0x8501FF00 -* 6.check completion of access -* Read 31st bit of OTP_CMD register to check completion of programming. -* OTP_CMD.START == 0 // access completed -* 7. Check programming status -* OTP_STATUS.PROGFAIL == 1 // Program failure -* -* \param otpRowNum -* Contains the Row Number to be written -* \param otpWriteData -* Contains the Data to be written -* \param otpReadBackData -* Contains the Read back Data of the Row Number passed. -* \param enable_ecc -* Contains boolean, which tells to enable ECC for that row or not. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteRowReadBack(uint32_t otpRowNum, uint32_t otpWriteData, uint32_t *otpReadBackData, bool enable_ecc) -{ - cy_mxotpc_cmd_t otpCmd = {0, 0, 0}; - cy_mxotpc_status_t result = CY_MXOTPC_INVALID; - uint32_t otpWriteProtData, otpReadData; - - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - - /* Indirect PROGRAM Sequence */ - result = Cy_MXOTPC_WriteProgramSequence(); - if(result != CY_MXOTPC_SUCCESS) - return result; - - /* 4.Write OTP_PROGDATA register - * Write 32-bit data value to be programmed inside OTP_PROGDATA reg */ - /* Write Protection : OTP bit that is already set shouldnt be set again */ - result = Cy_MXOTPC_GetWriteProtectedData(otpRowNum, otpWriteData, &otpWriteProtData); - if(result != CY_MXOTPC_SUCCESS) - return result; - - /* otpWriteProtData = 0 means required OTP's set already, Nothing to Write */ - if(otpWriteProtData) - { - Cy_MXOTPC_OtpSetProgData(otpWriteProtData); - - /* 5.WRITE OTP_CMD Register - * Write following value in OTP_CMD reg. - * For OTP_CMD command (0x0A) at 511th row, you may use following value, - * 0x8501FF00 */ - if(enable_ecc) - otpCmd.cmd = CY_MXOTPC_PROG_ECC_CMD; - else - otpCmd.cmd = CY_MXOTPC_PROG_CMD; - - otpCmd.rowAddr = otpRowNum; - Cy_MXOTPC_OtpCmd(&otpCmd); - - /* 6.check completion of access - * Read 31st bit of OTP_CMD register to check completion of programming. - * OTP_CMD.START == 0 // access completed */ - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_TIMEOUT; - - /* 7. Check programming status - * OTP_STATUS.PROGFAIL == 1 // Program failure */ - if(Cy_MXOTPC_OtpGetStatus(MXOTPC_OTP_STATUS_PROGFAIL_Msk)) - return CY_MXOTPC_WRITE_PROG_ERROR; - - /* Read the row back and verify if the data is written successfully */ - result = Cy_MXOTPC_ReadRow( otpRowNum, &otpReadData ); - if(result != CY_MXOTPC_SUCCESS) - return result; - - if((otpReadData & otpWriteData) != otpWriteData) - return CY_MXOTPC_WRITE_ERROR; - - /* Read back the Row Data and pass it back to caller for cross check */ - if( otpReadBackData ) - *otpReadBackData = otpReadData; - } - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteRow -****************************************************************************//** -* -* Writes a particular row with 32-bit data with/without ECC. -* -* \param otpRowNum -* Contains the Row Number to be written -* \param otpWriteData -* Contains the Data to be written -* \param enable_ecc -* Contains boolean, which tells to enable ECC for that row or not. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteRow(uint32_t otpRowNum, uint32_t otpWriteData, bool enable_ecc) -{ - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - - return Cy_MXOTPC_WriteRowReadBack(otpRowNum, otpWriteData, NULL, enable_ecc); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteBitReadBack -****************************************************************************//** -* -* Writes a particular row with 32-bit data without ECC and Read the Row back -* -* Indirect PROGRAM Sequence -* 1.Write Following Bit -* OTP_CTL.OTPProg_En =1 // Enable OTP programming at top level control -* 2.Check whether OTP is busy or not -* OTP_CMD.START == 0 // OTP is not busy -* 3.Check whether programming is enabled or not (PROGRAM Enable Seq) -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* If this bit is not set, perform following steps, otherwise skip. -* a.OTP commands to enable OTP Programming -* i.Write OTP_PROGDATA = 0xF -* ii.Write OTP_CMD reg (with CMD =0x02), VALUE: 0x9100_0000 -* iii.Wait for OTP_CMD.START == 0 -* iv.Repeat from point i to iii for OTP_PROGDATA 0x4, 0x8 and 0xd in sequence -* Check whether programming is enabled or not -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* 4.Write OTP_PROGDATA register after reading back and masking the -* required bit position, Write 32-bit data value to be programmed -* inside OTP_PROGDATA reg. -* 5.WRITE OTP_CMD Register -* Write following value in OTP_CMD reg. -* For OTP_CMD command (0x0A) at 511th row, you may use following value, -* 0x8501FF00 -* 6.check completion of access -* Read 31st bit of OTP_CMD register to check completion of programming. -* OTP_CMD.START == 0 // access completed -* 7. Check programming status -* OTP_STATUS.PROGFAIL == 1 // Program failure -* -* \param otpRowNum -* Contains the Row Number to be written -* \param bitNum -* Contains the bit position to be written -* \param otpReadBackData -* Contains the Read back Data of the Row Number passed. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteBitReadBack(uint32_t otpRowNum, uint32_t bitNum, uint32_t *otpReadBackData) -{ - cy_mxotpc_cmd_t otpCmd = {0, 0, 0}; - cy_mxotpc_status_t result = CY_MXOTPC_INVALID; - uint32_t otpWriteProtData, otpReadData; - - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - CY_ASSERT_L2(CY_MXOTPC_IS_BITNUM_VALID(bitNum)); - - /* Indirect PROGRAM Sequence */ - result = Cy_MXOTPC_WriteProgramSequence(); - if(result != CY_MXOTPC_SUCCESS) - return result; - - /* 4.Write OTP_PROGDATA register after reading back and masking the - * required bit position, Write 32-bit data value to be programmed - * inside OTP_PROGDATA reg */ - /* Write Protection : OTP bit that is already set shouldnt be set again */ - result = Cy_MXOTPC_GetWriteProtectedData(otpRowNum, (1 << bitNum), &otpWriteProtData); - if(result != CY_MXOTPC_SUCCESS) - return result; - - /* otpWriteProtData = 0 means required OTP's set already, Nothing to Write */ - if(otpWriteProtData) - { - Cy_MXOTPC_OtpSetProgData(otpWriteProtData); - - /* 5.WRITE OTP_CMD Register - * Write following value in OTP_CMD reg. - * For OTP_CMD command (0x0A) at 511th row, you may use following value, - * 0x8501FF00 */ - otpCmd.cmd = CY_MXOTPC_PROG_CMD; - otpCmd.rowAddr = otpRowNum; - Cy_MXOTPC_OtpCmd(&otpCmd); - - /* 6.check completion of access - * Read 31st bit of OTP_CMD register to check completion of programming. - * OTP_CMD.START == 0 // access completed */ - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_TIMEOUT; - - /* 7. Check programming status - * OTP_STATUS.PROGFAIL == 1 // Program failure */ - if(Cy_MXOTPC_OtpGetStatus(MXOTPC_OTP_STATUS_PROGFAIL_Msk)) - return CY_MXOTPC_WRITE_ERROR; - - } - - /* Read the row back and verify if the data is written successfully */ - result = Cy_MXOTPC_ReadRow( otpRowNum, &otpReadData ); - if(result != CY_MXOTPC_SUCCESS) - return result; - - if(!(otpReadData & (1 << bitNum))) - return CY_MXOTPC_WRITE_ERROR; - - /* Read back the Row Data and pass it back to caller for cross check */ - if(otpReadBackData) - *otpReadBackData = otpReadData; - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteBit -****************************************************************************//** -* -* Writes a particular row with 32-bit data without ECC -* -* \param otpRowNum -* Contains the Row Number to be written -* \param bitNum -* Contains the bit position to be written -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteBit(uint32_t otpRowNum, uint32_t bitNum) -{ - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - CY_ASSERT_L2(CY_MXOTPC_IS_BITNUM_VALID(bitNum)); - - return Cy_MXOTPC_WriteBitReadBack(otpRowNum, bitNum, NULL); -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteEcc -****************************************************************************//** -* -* Writes a particular row with ECC. -* -* Indirect PROGRAM Sequence -* 1.Write Following Bit -* OTP_CTL.OTPProg_En =1 // Enable OTP programming at top level control -* 2.Check whether OTP is busy or not -* OTP_CMD.START == 0 // OTP is not busy -* 3.Check whether programming is enabled or not (PROGRAM Enable Seq) -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* If this bit is not set, perform following steps, otherwise skip. -* a.OTP commands to enable OTP Programming -* i.Write OTP_PROGDATA = 0xF -* ii.Write OTP_CMD reg (with CMD =0x02), VALUE: 0x9100_0000 -* iii.Wait for OTP_CMD.START == 0 -* iv.Repeat from point i to iii for OTP_PROGDATA 0x4, 0x8 and 0xd in sequence -* Check whether programming is enabled or not -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* 4.WRITE OTP_CMD Register -* Write following value in OTP_CMD reg. -* For OTP_CMD command (0x0A) at 511th row, you may use following value, -* 0x8401FF00 -* 5.check completion of access -* Read 31st bit of OTP_CMD register to check completion of programming. -* OTP_CMD.START == 0 // access completed -* 6. Check programming status -* OTP_STATUS.PROGFAIL == 1 // Program failure -* 7. Read back the Row and check the ECC_STATUS register -* Check ECC_STATUS.ECC_ENABLE bits , if set then ECC_STATUS.ECC_DBL_ERR shouldnt -* be set. -* \param otpRowNum -* Contains the Row Number to be written with ECC -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteEcc(uint32_t otpRowNum) -{ - cy_mxotpc_cmd_t otpCmd = {0, 0, 0}; - uint32_t otpTempData; - cy_mxotpc_status_t result = CY_MXOTPC_INVALID; - - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - - /* Indirect ECC PROGRAM Sequence */ - result = Cy_MXOTPC_WriteProgramSequence(); - if(result != CY_MXOTPC_SUCCESS) - return result; - - /* 4.WRITE OTP_CMD Register - * Write following value in OTP_CMD reg. - * For OTP_CMD command (0x0A) at 511th row, you may use following value, - * 0x8481FF00 */ - otpCmd.cmd = CY_MXOTPC_PROG_ECC_WREAD_CMD; - otpCmd.rowAddr = otpRowNum; - Cy_MXOTPC_OtpCmd(&otpCmd); - - /* 5.check completion of access - * Read 31st bit of OTP_CMD register to check completion of programming. - * OTP_CMD.START == 0 // access completed */ - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_TIMEOUT; - - /* 6. Check programming status - * OTP_STATUS.PROGFAIL == 1 // Program failure */ - if(Cy_MXOTPC_OtpGetStatus(MXOTPC_OTP_STATUS_PROGFAIL_Msk)) - return CY_MXOTPC_WRITE_PROG_ERROR; - - /* Read the Row to check the ECC_STATUS */ - Cy_MXOTPC_ReadRow(otpRowNum, &otpTempData); - - if(!Cy_MXOTPC_OtpGetEccStatus(MXOTPC_ECC_STATUS_ECC_ENABLE_Msk)) - return CY_MXOTPC_WRITE_ECC_ERROR; - - if(Cy_MXOTPC_OtpGetEccStatus(MXOTPC_ECC_STATUS_ECC_DBL_ERR_Msk)) - return CY_MXOTPC_WRITE_ECC_ERROR; - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_ReadRow -****************************************************************************//** -* -* Reads the 32-bit value of a particular Row -* -* \param otpRowNum -* Contains the Row Number to be read -* \param otpReadData -* Contains the Read Data of the Row Number passed. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_ReadRow(uint32_t otpRowNum, uint32_t *otpReadData) -{ - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - - *otpReadData = CY_GET_REG32((CY_MXOTPC_BASE + MXOTPC_SECTION_SIZE) + (otpRowNum * 4)); - - if(Cy_MXOTPC_OtpGetEccStatus(MXOTPC_ECC_STATUS_ECC_DBL_ERR_Msk)) - return CY_MXOTPC_READ_ECC_ERROR; - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_ReadBootRow -****************************************************************************//** -* -* Reads the 32-bit value of Boot Row -* -* \param otpReadData -* Contains the Read Data of the Boot Row. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_ReadBootRow( uint32_t *otpReadData) -{ - *otpReadData = MXOTPC_BOOTROW; - - if(Cy_MXOTPC_OtpGetFoutEccStatus(MXOTPC_BOOT_ROW_FOUT_ECC_DED_STATUS_Msk)) - return CY_MXOTPC_READ_ECC_ERROR; - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_ReadBit -****************************************************************************//** -* -* Reads a bit status of a particular OTP Row -* -* \param otpRowNum -* Contains the Row Number, whose bit status should be Read -* \param bitNum -* Contains the bit position to be Read -* \param otpReadBit -* Contains the Read bit of bitNum position from the Row Number passed. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_ReadBit(uint32_t otpRowNum, uint32_t bitNum, uint32_t *otpReadBit) -{ - - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - CY_ASSERT_L2(CY_MXOTPC_IS_BITNUM_VALID(bitNum)); - - *otpReadBit = CY_GET_REG32((CY_MXOTPC_BASE + MXOTPC_SECTION_SIZE) + (otpRowNum * 4)); - /* Get the value of position:bitNum */ - *otpReadBit = (*otpReadBit & (1 << bitNum)? 1 : 0) ; - - if(Cy_MXOTPC_OtpGetEccStatus(MXOTPC_ECC_STATUS_ECC_DBL_ERR_Msk)) - return CY_MXOTPC_READ_ECC_ERROR; - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_DirectWriteRow -****************************************************************************//** -* -* Writes a particular row with 32-bit data without ECC. -* -* Direct PROGRAM Sequence -* 1.Write Following Bit -* OTP_CTL.OTPProg_En =1 // Enable OTP programming at top level control -* 2.Check whether OTP is busy or not -* OTP_CMD.START == 0 // OTP is not busy -* 3.Check whether programming is enabled or not (PROGRAM Enable Seq) -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* If this bit is not set, perform following steps, otherwise skip. -* a.OTP commands to enable OTP Programming -* i.Write OTP_PROGDATA = 0xF -* ii.Write OTP_CMD reg (with CMD =0x02), VALUE: 0x9100_0000 -* iii.Wait for OTP_CMD.START == 0 -* iv.Repeat from point i to iii for OTP_PROGDATA 0x4, 0x8 and 0xd in sequence -* Check whether programming is enabled or not -* OTP_STATUS.ProgOK == 1 // OTP programming enabled -* 4.Write CPU_PROG_CMD register -* Write command (0x0A) for Direct write -* Write command (0x08) for Direct write with ECC -* 5.Directly write to the memory mapped OTP address -* -* \param otpRowNum -* Contains the Row Number to be written -* \param otpWriteData -* Contains the Data to be written -* \param otpReadBackData -* Contains the Read back Data of the Row Number passed. -* \param otpProgEccEnable -* Contains the data whether we have to enable ECC or not. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_DirectWriteRow(uint32_t otpRowNum, uint32_t otpWriteData, uint32_t *otpReadBackData, bool otpProgEccEnable) -{ - cy_mxotpc_status_t result = CY_MXOTPC_INVALID; - uint32_t otpWriteProtData; - - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - - /* Indirect PROGRAM Sequence */ - result = Cy_MXOTPC_WriteProgramSequence(); - if(result != CY_MXOTPC_SUCCESS) - return result; - - /* 4.Write CPU_PROG_CMD register - * Write command (0x0A) for Direct write */ - if(otpProgEccEnable) - Cy_MXOTPC_OtpCpuProgCmd(CY_MXOTPC_PROG_ECC_CMD); - else - Cy_MXOTPC_OtpCpuProgCmd(CY_MXOTPC_PROG_CMD); - - /* 5.Directly write to the memory mapped OTP address */ - /* Write Protection : OTP bit that is already set shouldnt be set again */ - result = Cy_MXOTPC_GetWriteProtectedData(otpRowNum, otpWriteData, &otpWriteProtData); - if( result != CY_MXOTPC_SUCCESS ) - return result; - - /* otpWriteProtData = 0 means required OTP's set already, Nothing to Write */ - if(otpWriteProtData) - { - CY_SET_REG32((CY_MXOTPC_BASE + MXOTPC_SECTION_SIZE) + (otpRowNum * 4), otpWriteProtData); - } - - /* Read back the Row Data and pass it back to caller for cross check */ - if(otpReadBackData) - return Cy_MXOTPC_ReadRow(otpRowNum, otpReadBackData); - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_IndirectReadBit -****************************************************************************//** -* -* Reads a bit status of a particular OTP Row using Indirect access -* -* Indirect READ Sequence -* 1. Check whether OTP is busy or not -* OTP_CMD.START == 0 // OTP is not busy -* 2. WRITE OTP_CMD Register -* Write following value in OTP_CMD reg. -* For READ command (0x00) at 15th row and 3rd bit, and clearing previous read error if exist, you may use following value, -* 0X9000_0F03 -* 3. check completion of access -* Read 31st bit of OTP_CMD register to check completion of programming. -* OTP_CMD.START == 0 // access completed -* 4. Check Read status & Read bit -* OTP_CMD.ReadVal // Read value from specified bit. -* OTP_CMD.RD_ERR == 1 // Error in bit reading -* Read ECC_STATUS register for ECC status of the row. More details on ECC refer to register description. -* -* \param otpRowNum -* Contains the Row Number, whose bit status should be Read -* \param bitNum -* Contains the bit position to be Read -* \param otpReadBit -* Contains the Read bit of bitNum position from the Row Number passed. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_IndirectReadBit(uint32_t otpRowNum, uint32_t bitNum, uint32_t *otpReadBit) -{ - cy_mxotpc_cmd_t otpCmd = {0, 0, 0}; - - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - CY_ASSERT_L2(CY_MXOTPC_IS_BITNUM_VALID(bitNum)); - - /* Indirect READ Sequence */ - /* 1. Check whether OTP is busy or not - * OTP_CMD.START == 0 // OTP is not busy */ - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_READ_ERROR; - - /* 2. WRITE OTP_CMD Register - * Write following value in OTP_CMD reg. - * For READ command (0x00) at 15th row and 3rd bit, and clearing previous read error if exist, you may use following value, - * 0X9000_0F03 */ - otpCmd.cmd = CY_MXOTPC_READ_CMD; - otpCmd.rowAddr = otpRowNum; - otpCmd.colAddr = bitNum; - Cy_MXOTPC_OtpCmd(&otpCmd); - - /* 3. check completion of access - * Read 31st bit of OTP_CMD register to check completion of programming. - * OTP_CMD.START == 0 // access completed */ - if(Cy_MXOTPC_OtpCheckStartStatus(CY_START_STATUS_CHECK_TIMEOUT) == CY_MXOTPC_TIMEOUT) - return CY_MXOTPC_READ_ERROR; - - /* 4. Check Read status & Read bit - * OTP_CMD.ReadVal // Read value from specified bit. - * OTP_CMD.RD_ERR == 1 // Error in bit reading - * Read ECC_STATUS register for ECC status of the row. More details on ECC refer to register description.*/ - if(Cy_MXOTPC_OtpGetReadBitStatus()) - return CY_MXOTPC_READ_ERROR; - - *otpReadBit = Cy_MXOTPC_OtpIndirectReadBit(); - - if(Cy_MXOTPC_OtpGetEccStatus(MXOTPC_ECC_STATUS_ECC_DBL_ERR_Msk)) - return CY_MXOTPC_READ_ECC_ERROR; - - return CY_MXOTPC_SUCCESS; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_ReadRowArray -****************************************************************************//** -* -* Reads Array of Rows -* -* \param otpRowNum -* Contains the starting Row Number to be read -* \param otpDstPointer -* Contains the Destination Address where the data read has to be written back. -* \param size -* Contains the number of rows to be read from otpRowNum. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_ReadRowArray(uint32_t otpRowNum, uint32_t *otpDstPointer, uint32_t size) -{ - cy_mxotpc_status_t status = CY_MXOTPC_READ_ERROR; - CY_ASSERT_L2(CY_MXOTPC_IS_SIZE_VALID(size)); - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - CY_ASSERT_L2(CY_MXOTPC_IS_DEST_ADDR_ALIGNED(otpDstPointer)); - CY_ASSERT_L2(CY_MXOTPC_IS_ARRAY_SIZE_VALID(otpRowNum, size)); - - while(size != 0) - { - status = Cy_MXOTPC_ReadRow( otpRowNum, otpDstPointer); - if(status != CY_MXOTPC_SUCCESS) - break; - - otpRowNum++; - otpDstPointer++; - size--; - } - - return status; -} - -/******************************************************************************* -* Function Name: Cy_MXOTPC_WriteRowArray -****************************************************************************//** -* -* Writes Array of Rows -* -* \param otpRowNum -* Contains the starting Row Number to be written -* \param otpSrcPointer -* Contains the Destination Address where the data has to be read has to be written to rows. -* \param size -* Contains the number of rows to be written from otpRowNum. -* \param enable_ecc -* Contains boolean, which tells to enable ECC for that row or not. -* -* \return the MXOTPC API status \ref cy_mxotpc_status_t. -* -*******************************************************************************/ -cy_mxotpc_status_t Cy_MXOTPC_WriteRowArray(uint32_t otpRowNum, uint32_t *otpSrcPointer, uint32_t size, bool enable_ecc) -{ - cy_mxotpc_status_t status = CY_MXOTPC_WRITE_ERROR; - CY_ASSERT_L2(CY_MXOTPC_IS_SIZE_VALID(size)); - CY_ASSERT_L2(CY_MXOTPC_IS_ROW_VALID(otpRowNum)); - CY_ASSERT_L2(CY_MXOTPC_IS_DEST_ADDR_ALIGNED(otpSrcPointer)); - CY_ASSERT_L2(CY_MXOTPC_IS_ARRAY_SIZE_VALID(otpRowNum, size)); - - while(size != 0) - { - status = Cy_MXOTPC_WriteRow( otpRowNum, *otpSrcPointer, enable_ecc); - if(status != CY_MXOTPC_SUCCESS) - break; - - otpRowNum++; - otpSrcPointer++; - size--; - } - - return status; -} - -#endif /* CY_IP_MXS28OTPC */ -/* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxsdiodev.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxsdiodev.c deleted file mode 100644 index ec0d03d417..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_mxsdiodev.c +++ /dev/null @@ -1,581 +0,0 @@ -/***************************************************************************//** -* \file cy_mxsdiodev.c -* \version 1.0 -* -* Provides an API implementation of the MXSDIODEV driver -* -******************************************************************************** -* \copyright -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXSDIODEV) - -#include "cy_mxsdiodev.h" -#include - -#if defined(__cplusplus) -extern "C" { -#endif - -/** \cond internal */ -#define CY_SDIO_DEV_IS_SPEED_MODE_VALID(speedMode) ((CY_SDIO_DEV_SDR12 == (speedMode)) || \ - (CY_SDIO_DEV_SDR25 == (speedMode)) || \ - (CY_SDIO_DEV_SDR50 == (speedMode)) || \ - (CY_SDIO_DEV_SDR104 == (speedMode)) || \ - (CY_SDIO_DEV_DDR50 == (speedMode))) - -#define CY_SDIO_DEV_IS_BLOCK_SIZE_VALID(blockSize) ((CY_SDIO_DEV_BLK_SIZE_64 == (blockSize)) || \ - (CY_SDIO_DEV_BLK_SIZE_128 == (blockSize)) || \ - (CY_SDIO_DEV_BLK_SIZE_256 == (blockSize)) || \ - (CY_SDIO_DEV_BLK_SIZE_512 == (blockSize))) - -#define CY_SDIO_DEV_IS_SDIO_VERSION_VALID(version) ((CY_SDIO_DEV_VERSION_3_0 == (version)) || \ - (CY_SDIO_DEV_VERSION_2_0 == (version))) - -#define CY_SDIO_DEV_IS_MANF_ID_CONFIG_VALID(manf_id) ((CY_SDIO_DEV_USE_DEFAULT_MANF_ID == (manf_id)) || \ - (CY_SDIO_DEV_USER_PROVIDED_MANF_ID == (manf_id))) - -#define MIN(a,b) (((a)<(b))?(a):(b)) - -/** \endcond */ -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Init(MXSDIO_Type *base, - cy_stc_sdio_dev_config_t const *config, - cy_stc_sdio_dev_context_t *context) -{ - cy_en_sdio_dev_status_t ret = CY_SDIO_DEV_SUCCESS; - - /* Check for the NULL pointer. */ - if ((NULL != base) && (NULL != config) && (NULL != context)) - { - /* Check input values */ - CY_ASSERT_L2(CY_SDIO_DEV_IS_SPEED_MODE_VALID(config->max_speed_config)); - CY_ASSERT_L2(CY_SDIO_DEV_IS_BLOCK_SIZE_VALID(config->blk_size)); - CY_ASSERT_L2(CY_SDIO_DEV_IS_SDIO_VERSION_VALID(config->version)); - CY_ASSERT_L2(CY_SDIO_DEV_IS_MANF_ID_CONFIG_VALID(config->use_default_manfid)); - - context->current_speed_config = config->max_speed_config; - context->current_blk_size = config->blk_size; - - /* The driver assumes that the device has been reset and waiting for - * OTP Shadow registers to be configurated - */ - MXSDIO_OTPSHADOWREG1(base) = _VAL2FLD(MXSDIO_OTPSHADOWREG1_SDIOVERSION, config->version) | - _VAL2FLD(MXSDIO_OTPSHADOWREG1_PID, config->use_default_manfid) | - _VAL2FLD(MXSDIO_OTPSHADOWREG1_F2BLOCKSIZE, config->blk_size) | - _VAL2FLD(MXSDIO_OTPSHADOWREG1_MAXSPEEDCODING, config->max_speed_config); - - - - if (config->use_default_manfid == CY_SDIO_DEV_USER_PROVIDED_MANF_ID) - { - MXSDIO_OTPSHADOWREG2(base) = _VAL2FLD(MXSDIO_OTPSHADOWREG2_MANFID0, (uint16_t) config->manfid[0]); - MXSDIO_OTPSHADOWREG3(base) = _VAL2FLD(MXSDIO_OTPSHADOWREG3_MANFID1, (uint16_t) config->manfid[1]) | - _VAL2FLD(MXSDIO_OTPSHADOWREG3_MANFID2, (uint16_t) config->manfid[2]); - } - } - else - { - ret = CY_SDIO_DEV_ERROR_INVALID_PARAMETER; - } - return ret; -} - -void Cy_SDIO_DEV_DeInit(MXSDIO_Type *base) -{ - /* Reset OTP Shadow Registers */ - MXSDIO_OTPSHADOWREG1(base) = 0; - MXSDIO_OTPSHADOWREG2(base) = 0; - MXSDIO_OTPSHADOWREG3(base) = 0; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Enable(MXSDIO_Type *base) -{ - cy_en_sdio_dev_status_t ret = CY_SDIO_DEV_SUCCESS; - - /* Check for the NULL pointer. */ - if (NULL != base) - { - /* Take SDIO Device out of reset */ - MXSDIO_CLOCKCTRLSTATUS(base) |= _VAL2FLD(MXSDIO_CLOCKCTRLSTATUS_FORCEHTPREQUEST, 1u); - - /* Configure Receive interrupt for each frame received */ - /* TBD : What if user doesn't want to subscribe for interrupts */ - MXSDIO_INTRCVLAZY(base) = _VAL2FLD(MXSDIO_INTRCVLAZY_FRAMECOUNT, 1u); - - /* Mark F2 is ready */ - MXSDIO_CORECONTROL(base) |= _VAL2FLD(MXSDIO_CORECONTROL_F2READY, 1u); - } - else - { - ret = CY_SDIO_DEV_ERROR_INVALID_PARAMETER; - } - return ret; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Disable(MXSDIO_Type *base) -{ - /* Disable Frame based receive interrupt */ - MXSDIO_INTRCVLAZY(base) = 0; - - /* Disable host interrupts */ - MXSDIO_INTHOSTMASK(base) = 0; - - /* Stop the Clock */ - MXSDIO_CLOCKCTRLSTATUS(base) = 0; - - /* Diable Core - Mark F2 not ready */ - MXSDIO_CORECONTROL(base) = 0; - - return CY_SDIO_DEV_SUCCESS; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_GetStatus(MXSDIO_Type const *base, bool *sdStatus) -{ - /* Check for the NULL pointer. */ - if ((NULL != base) && (NULL != sdStatus)) - { - *sdStatus = (bool)(MXSDIO_CORESTATUS(base) & MXSDIO_CORESTATUS_SDIOIOE2_Msk); - } - else - { - return CY_SDIO_DEV_ERROR_INVALID_PARAMETER; - } - return CY_SDIO_DEV_SUCCESS; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_ConfigReadBuf(MXSDIO_Type const *base, uint8_t *buffer, uint32_t size, cy_stc_sdio_dev_context_t *context) -{ - /* Check for the NULL pointer. */ - if ((NULL != base) && (NULL != context)) - { - context->rx_buffer = buffer; - context->max_rx_buf_len = size; - } - else - { - return CY_SDIO_DEV_ERROR_INVALID_PARAMETER; - } - return CY_SDIO_DEV_SUCCESS; -} - -/* Returns length of the packet if the packet is valid */ -static uint32_t Is_packet_valid(uint8_t *buffer) -{ - cy_stc_sdio_dev_rx_header_t *rxh = NULL; - - /* First 4 bytes indicate hardware tag */ - rxh = (cy_stc_sdio_dev_rx_header_t *) buffer; - - /* Check if any of the discard flag set */ - if (rxh->flags & RXF_DISCARD) - { - return 0; - } - /* Packet too short */ - if(rxh->len < CY_SDIO_DEV_FRAMETAG_LEN) - { - return 0; - } - return rxh->len; -} -static bool dma_tx_reset(MXSDIO_Type *base) -{ - uint32_t retry = CY_SDIO_DEV_RETRY_TIME; - uint32_t status = 0; - - /* If DMA is already in reset, do not reset. */ - if (_FLD2VAL(MXSDIO_XMTSTATUS0_XMTSTATE, MXSDIO_XMTSTATUS0(base)) == - CY_SDIO_DEV_XS_DISABLED) - return true; - - /* suspend tx DMA first */ - MXSDIO_XMTCONTROL(base) |= MXSDIO_XMTCONTROL_SUSPEN_Msk; - - status = _FLD2VAL(MXSDIO_XMTSTATUS0_XMTSTATE, MXSDIO_XMTSTATUS0(base)); - - while ( (retry > 0UL) && - (status != CY_SDIO_DEV_XS_DISABLED) && - (status != CY_SDIO_DEV_XS_IDLE) && - (status != CY_SDIO_DEV_XS_STOPPED) ) - { - status = _FLD2VAL(MXSDIO_XMTSTATUS0_XMTSTATE, MXSDIO_XMTSTATUS0(base)); - Cy_SysLib_Delay(1); - retry--; - } - - MXSDIO_XMTCONTROL(base) = 0; - - retry = CY_SDIO_DEV_RETRY_TIME; - status = _FLD2VAL(MXSDIO_XMTSTATUS0_XMTSTATE, MXSDIO_XMTSTATUS0(base)); - - while ( (retry > 0UL) && - (status != CY_SDIO_DEV_XS_DISABLED)) - { - status = _FLD2VAL(MXSDIO_XMTSTATUS0_XMTSTATE, MXSDIO_XMTSTATUS0(base)); - Cy_SysLib_Delay(1); - retry--; - } - - /* We should be disabled at this point */ - return (status == CY_SDIO_DEV_XS_DISABLED); -} - -static bool dma_rx_reset(MXSDIO_Type *base) -{ - uint32_t retry = CY_SDIO_DEV_RETRY_TIME; - uint32_t status = 0; - - MXSDIO_RCVCONTROL(base) = 0; - - retry = CY_SDIO_DEV_RETRY_TIME; - status = _FLD2VAL(MXSDIO_RCVSTATUS0_RCVSTATE, MXSDIO_RCVSTATUS0(base)); - while ( (retry > 0UL) && - (status != CY_SDIO_DEV_RS_DISABLED)) - { - status = _FLD2VAL(MXSDIO_RCVSTATUS0_RCVSTATE, MXSDIO_RCVSTATUS0(base)); - Cy_SysLib_Delay(1); - retry--; - } - - return (status == CY_SDIO_DEV_RS_DISABLED); -} - -void Cy_SDIO_DEV_Interrupt(MXSDIO_Type *base, cy_stc_sdio_dev_context_t *context) -{ - uint32 intstatus; - - /* Read interrupt status register */ - intstatus = MXSDIO_INTSTATUS(base); - - /* Transmit Complete Event */ - if (intstatus & MXSDIO_INTSTATUS_XMTINT_Msk) - { - context->tx_buffer = NULL; - context->tx_buf_len = 0; - - if (context->cbEvents) - context->cbEvents(CY_SDIO_DEV_TRANSMIT_CMPLT_EVENT); - } - - /* Receive Complete Event */ - if (intstatus & MXSDIO_INTSTATUS_RCVINT_Msk) - { - if (context->cbEvents) - { - if (Is_packet_valid(context->rx_buffer)) - { - context->cbEvents(CY_SDIO_DEV_RECEIVE_CMPLT_EVENT); - } - else - { - context->cbEvents(CY_SDIO_DEV_RECEIVE_PKT_ERROR); - } - } - context->rx_buffer = NULL; - context->max_rx_buf_len = 0; - } - /* Receive Packet - Underflow */ - if (intstatus & MXSDIO_INTSTATUS_RCVDESCUF_Msk) - { - /* Try receiving packet if user has configured receive buufer */ - (void) Cy_SDIO_DEV_Receive_Buffer(base, context); - } - - /* Descriptor protocol error */ - if (intstatus & MXSDIO_INTSTATUS_DESCPROTERR_Msk) - { - /* Reset DMA engine and retransmit */ - /* Check if TX operation stopped or RX operation stopped */ - if (CY_SDIO_DEV_XS_STOPPED == _FLD2VAL(MXSDIO_XMTSTATUS0_XMTSTATE, MXSDIO_XMTSTATUS0(base))) - { - if (dma_tx_reset(base)) - { - (void) Cy_SDIO_DEV_Transmit_Buffer(base, context->tx_buffer, context->tx_buf_len, context); - } - else - { - /* Do nothing: Dropping the frame */ - } - } - if (CY_SDIO_DEV_RS_STOPPED == _FLD2VAL(MXSDIO_RCVSTATUS0_RCVSTATE, MXSDIO_RCVSTATUS0(base))) - { - if (dma_rx_reset(base)) - { - (void) Cy_SDIO_DEV_Receive_Buffer(base, context); - } - { - /* Do nothing: Dropping the frame */ - } - } - } - - /* Clear the interrupt status after processing */ - MXSDIO_INTSTATUS(base) = intstatus; - - return; -} - -void Cy_SDIO_DEV_RegisterEventCallback(MXSDIO_Type const *base, cy_cb_sdio_dev_handle_events_t callback, cy_stc_sdio_dev_context_t *context) -{ - /* Suppress a compiler warning about unused variables */ - (void) base; - - if (NULL != context) - { - context->cbEvents = callback; - } - - return; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Transmit_Buffer(MXSDIO_Type const *base, uint8_t *buffer, uint16_t buf_len, cy_stc_sdio_dev_context_t *context) -{ - if ((NULL != context) && (buffer != NULL) && (buf_len > 0)) - { - cy_stc_sdio_dev_dma_descr_t tx_descriptor; - uint16_t inv_buf_len = ~(buf_len); - - memcpy(buffer, &buf_len, 2); - memcpy(&buffer[2], &inv_buf_len, 2); - - context->tx_buffer = buffer; - context->tx_buf_len = buf_len; - - /* Setup descriptors */ - tx_descriptor.ctrl1 = D64_CTRL1_EOF | D64_CTRL1_SOF; - - /* Setup DMA channel transmitter */ - MXSDIO_XMTADDRESSHI(base) = 0; - MXSDIO_XMTADDRESSLOW(base) = ((uint32_t)&tx_descriptor); // Transmit descriptor table address - MXSDIO_XMTPTR(base) = ((uint32_t)&tx_descriptor + sizeof(cy_stc_sdio_dev_dma_descr_t)) & 0xffff; // needs to be lower 16 bits of descriptor address - - MXSDIO_XMTCONTROL(base) = ( _BOOL2FLD(MXSDIO_XMTCONTROL_PTYCHKDISABLE, 1u) | - _VAL2FLD(MXSDIO_XMTCONTROL_BURSTLEN, 2u) | - _VAL2FLD(MXSDIO_XMTCONTROL_PREFETCHCTL, (1U)) ); - - tx_descriptor.addrlow = (uint32_t) buffer; - tx_descriptor.ctrl2 = D64_CTRL2_BC_USABLE_MASK & buf_len; - - /* Fire off the DMA */ - MXSDIO_XMTCONTROL(base) |= MXSDIO_XMTCONTROL_XMTEN_Msk; - } - else - { - return CY_SDIO_DEV_ERROR_INVALID_PARAMETER; - } - return CY_SDIO_DEV_SUCCESS; -} - -__STATIC_INLINE cy_en_sdio_dev_status_t Cy_SDIO_DEV_Poll_Transmit_Complete(MXSDIO_Type const *base) -{ - cy_en_sdio_dev_status_t ret = CY_SDIO_DEV_ERROR_TIMEOUT; - uint32_t retry = CY_SDIO_DEV_RETRY_TIME; - bool transmitComplete; - - while (retry > 0UL) - { - transmitComplete = _FLD2BOOL(MXSDIO_INTSTATUS_XMTINT, - MXSDIO_INTSTATUS(base)); - - if (false == transmitComplete) - { - ret = CY_SDIO_DEV_SUCCESS; - break; - } - - Cy_SysLib_Delay(1); - retry--; - } - - return ret; -} - -__STATIC_INLINE cy_en_sdio_dev_status_t Cy_SDIO_DEV_Poll_Receive_Complete(MXSDIO_Type const *base) -{ - cy_en_sdio_dev_status_t ret = CY_SDIO_DEV_ERROR_TIMEOUT; - uint32_t retry = CY_SDIO_DEV_RETRY_TIME; - bool receiveComplete; - - while (retry > 0UL) - { - receiveComplete = _FLD2BOOL(MXSDIO_INTSTATUS_RCVINT, - MXSDIO_INTSTATUS(base)); - - if (false == receiveComplete) - { - ret = CY_SDIO_DEV_SUCCESS; - break; - } - - Cy_SysLib_Delay(1); - retry--; - } - - return ret; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Transmit_Buffer_Blocking(MXSDIO_Type const *base, uint8_t *buffer, uint16_t buf_len) -{ - cy_en_sdio_dev_status_t ret = CY_SDIO_DEV_SUCCESS; - cy_stc_sdio_dev_dma_descr_t tx_descriptor; - uint32_t interrupt_mask; - - /* Setup descriptors */ - tx_descriptor.ctrl1 = D64_CTRL1_EOF | D64_CTRL1_SOF; - - /* Setup DMA channel transmitter */ - MXSDIO_XMTADDRESSHI(base) = 0; - MXSDIO_XMTADDRESSLOW(base) = ((uint32_t)&tx_descriptor); // Transmit descriptor table address - MXSDIO_XMTPTR(base) = ((uint32_t)&tx_descriptor + sizeof(cy_stc_sdio_dev_dma_descr_t)) & 0xffff; // needs to be lower 16 bits of descriptor address - MXSDIO_XMTCONTROL(base) = ( _BOOL2FLD(MXSDIO_XMTCONTROL_PTYCHKDISABLE, 1u) | - _VAL2FLD(MXSDIO_XMTCONTROL_BURSTLEN, 2u) | - _VAL2FLD(MXSDIO_XMTCONTROL_PREFETCHCTL, (1U)) ); - - if ( buf_len > 0 ) - { - uint16_t inv_buf_len = ~(buf_len); - - memcpy(buffer, &buf_len, 2); - memcpy(&buffer[2], &inv_buf_len, 2); - - tx_descriptor.addrlow = (uint32_t) buffer; - tx_descriptor.ctrl2 = buf_len; - - /* Disable interrupts */ - interrupt_mask = MXSDIO_INTHOSTMASK(base); - MXSDIO_INTHOSTMASK(base) = 0; - - /* Fire off the DMA */ - MXSDIO_XMTCONTROL(base) |= MXSDIO_XMTCONTROL_XMTEN_Msk; - - ret = Cy_SDIO_DEV_Poll_Transmit_Complete(base); - - MXSDIO_XMTCONTROL(base) &= (~MXSDIO_XMTCONTROL_XMTEN_Msk); - - /* Enable interrupts */ - MXSDIO_INTHOSTMASK(base) = interrupt_mask; - } - - return ret; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Receive_Buffer(MXSDIO_Type const *base, cy_stc_sdio_dev_context_t *context) -{ - if ((context->rx_buffer != NULL) && (context->max_rx_buf_len > 0)) - { - cy_stc_sdio_dev_dma_descr_t rx_descriptor; - /* Setup descriptors */ - rx_descriptor.ctrl1 = D64_CTRL1_EOF | D64_CTRL1_SOF; - - /* Setup DMA channel transmitter */ - MXSDIO_RCVADDRESSHI(base) = 0; - MXSDIO_RCVADDRESSLOW(base) = ((uint32_t)&rx_descriptor); // Transmit descriptor table address - MXSDIO_RCVPTR(base) = ((uint32_t)&rx_descriptor + sizeof(cy_stc_sdio_dev_dma_descr_t)) & 0xffff; // needs to be lower 16 bits of descriptor address - MXSDIO_RCVCONTROL(base) = ( _BOOL2FLD(MXSDIO_RCVCONTROL_PTYCHKDISABLE, 1u) | - _VAL2FLD(MXSDIO_RCVCONTROL_BURSTLEN, 2u) | - _VAL2FLD(MXSDIO_RCVCONTROL_PREFETCHCTL, 0u) ); - - rx_descriptor.addrlow = (uint32_t) context->rx_buffer; - rx_descriptor.ctrl2 = D64_CTRL2_BC_USABLE_MASK & context->max_rx_buf_len; - - /* Fire off the DMA */ - MXSDIO_RCVCONTROL(base) |= MXSDIO_RCVCONTROL_RCVEN_Msk; - } - else - { - return CY_SDIO_DEV_ERROR_INVALID_PARAMETER; - } - - return CY_SDIO_DEV_SUCCESS; -} - -cy_en_sdio_dev_status_t Cy_SDIO_DEV_Receive_Buffer_Blocking(MXSDIO_Type const *base, char **buffer, uint32_t *buf_len) -{ - cy_en_sdio_dev_status_t ret = CY_SDIO_DEV_SUCCESS; - cy_stc_sdio_dev_dma_descr_t rx_descriptor; - uint32_t interrupt_mask; - - /* Setup descriptors */ - rx_descriptor.ctrl1 = D64_CTRL1_EOF | D64_CTRL1_SOF; - - /* Setup DMA channel transmitter */ - MXSDIO_RCVADDRESSHI(base) = 0; - MXSDIO_RCVADDRESSLOW(base) = ((uint32_t)&rx_descriptor); // Transmit descriptor table address - MXSDIO_RCVPTR(base) = ((uint32_t)&rx_descriptor + sizeof(cy_stc_sdio_dev_dma_descr_t)) & 0xffff; // needs to be lower 16 bits of descriptor address - MXSDIO_RCVCONTROL(base) = ( _BOOL2FLD(MXSDIO_RCVCONTROL_PTYCHKDISABLE, 1u) | - _VAL2FLD(MXSDIO_RCVCONTROL_BURSTLEN, 2u) | - _VAL2FLD(MXSDIO_RCVCONTROL_PREFETCHCTL, 1u) ); - - while ( *buf_len > 0 ) - { - uint32_t read_size = MIN( *buf_len, D64_CTRL2_BC_USABLE_MASK ); - - rx_descriptor.addrlow = (uint32_t) *buffer; - rx_descriptor.ctrl2 = D64_CTRL2_BC_USABLE_MASK & read_size; - - /* Disable interrupts */ - interrupt_mask = MXSDIO_INTHOSTMASK(base); - MXSDIO_INTHOSTMASK(base) = 0; - - /* Fire off the DMA */ - MXSDIO_RCVCONTROL(base) |= MXSDIO_RCVCONTROL_RCVEN_Msk; - - /* Update variables */ - *buf_len -= read_size; - *buffer += read_size; - - ret = Cy_SDIO_DEV_Poll_Receive_Complete(base); - - MXSDIO_RCVCONTROL(base) &= (~MXSDIO_RCVCONTROL_RCVEN_Msk); - - /* Enable interrupts */ - MXSDIO_INTHOSTMASK(base) = interrupt_mask; - } - - return ret; -} - -uint32_t Cy_SDIO_DEV_GetInterruptStatus(MXSDIO_Type const *base) -{ - return MXSDIO_INTSTATUS(base); -} - -void Cy_SDIO_DEV_ClearInterruptStatus(MXSDIO_Type const *base, uint32_t status) -{ - MXSDIO_INTSTATUS(base) = status; - (void) MXSDIO_INTSTATUS(base); -} - -uint32_t Cy_SDIO_DEV_GetInterruptMask(MXSDIO_Type const *base) -{ - return (MXSDIO_INTHOSTMASK(base)); -} - -void Cy_SDIO_DEV_SetInterruptMask(MXSDIO_Type const *base, uint32_t interruptMask) -{ - MXSDIO_INTHOSTMASK(base) = interruptMask; -} - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXSDIODEV */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_pd_ppu.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_pd_ppu.c deleted file mode 100644 index 2242eb7e86..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_pd_ppu.c +++ /dev/null @@ -1,469 +0,0 @@ -/***************************************************************************//** -* \file cy_pd_ppu.c -* \version 1.0 -* -* This file provides the source code for ARM PPU Platform PD specific driver -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXS28SRSS) - -#include -#include -#include -#include "cy_syslib.h" - -/* Static Functions */ -static cy_pd_ppu_status_t cy_pd_ppu_enable_irq(struct ppu_v1_reg *ppu); -static cy_pd_ppu_status_t cy_pd_ramc_ppu0_irq_enable(); -static cy_pd_ppu_status_t cy_pd_ramc_ppu1_irq_enable(); -static cy_pd_ppu_status_t cy_pd_ramc_ppu2_irq_enable(); -static cy_pd_ppu_status_t cy_pd_ppu_main_irq_enable(void); -static void cy_pd_ramc_ppu0_isr(void); -static void cy_pd_ramc_ppu1_isr(void); -static void cy_pd_ramc_ppu2_isr(void); -static void cy_pd_ppu_main_isr(void); -static void cy_pd_ppu_interrupt_handler(struct ppu_v1_reg *ppu); - -/** -* \addtogroup group_pd_ppu_functions -* \{ -*/ - -/******************************************************************************* -* Function Name: cy_pd_ppu_init -****************************************************************************//** -* -* Initializes the PD PPU Driver: -* -* \param ppu -* This Parameter contains PPU base pointer for which the intialization has -* to be done, it will point to one of the below PPU's -* Main PPU -* RAMC_PPU0 -* RAMC_PPU1 -* RAMC_PPU2 -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -cy_pd_ppu_status_t cy_pd_ppu_init(struct ppu_v1_reg *ppu) -{ - cy_pd_ppu_status_t status; - uint32_t state; - CY_ASSERT(ppu != NULL); - - ppu_v1_init(ppu); - - cy_pd_ppu_enable_irq(ppu); - - status = cy_pd_ppu_get_power_mode(ppu, &state); - if (status != CY_PD_PPU_SUCCESS) - return status; - - if (state == PPU_V1_MODE_ON) { - ppu_v1_interrupt_unmask(ppu, PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK); - ppu_v1_dynamic_enable(ppu, PPU_V1_MODE_OFF); - } - - return CY_PD_PPU_SUCCESS; -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_get_power_mode -****************************************************************************//** -* -* Gets the current power mode of the particular PPU -* -* \param ppu -* This Parameter contains PPU base pointer for which the intialization has -* to be done, it will point to one of the below PPU's -* Main PPU -* RAMC_PPU0 -* RAMC_PPU1 -* RAMC_PPU2 -* -* \param mode -* Contains the current mode of the PPU. -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -cy_pd_ppu_status_t cy_pd_ppu_get_power_mode(struct ppu_v1_reg *ppu, uint32_t *mode) -{ - CY_ASSERT(ppu != NULL); - *mode = ppu_v1_get_power_mode(ppu); - CY_ASSERT(*mode < PPU_V1_MODE_COUNT); - - return CY_PD_PPU_SUCCESS; -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_set_power_mode -****************************************************************************//** -* -* Sets the required power mode of the particular PPU -* -* \param ppu -* This Parameter contains PPU base pointer for which the intialization has -* to be done, it will point to one of the below PPU's -* Main PPU -* RAMC_PPU0 -* RAMC_PPU1 -* RAMC_PPU2 -* -* \param mode -* Contains the future power mode to be set for the PPU. -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -cy_pd_ppu_status_t cy_pd_ppu_set_power_mode(struct ppu_v1_reg *ppu, uint32_t mode) -{ - cy_pd_ppu_status_t status = CY_PD_PPU_INVALID_STATE; - CY_ASSERT(ppu != NULL); - CY_ASSERT(mode < PPU_V1_MODE_COUNT); - - switch (mode) { - case PPU_V1_MODE_OFF: - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_MASKED); - ppu_v1_interrupt_mask(ppu, PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK); - status = (cy_pd_ppu_status_t)ppu_v1_set_power_mode(ppu, PPU_V1_MODE_OFF); - ppu_v1_lock_off_disable(ppu); - ppu_v1_off_unlock(ppu); - - CY_ASSERT(status == CY_PD_PPU_SUCCESS); - break; - - case PPU_V1_MODE_ON: - ppu_v1_interrupt_unmask(ppu, PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK); - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_MASKED); - status = (cy_pd_ppu_status_t)ppu_v1_set_power_mode(ppu, PPU_V1_MODE_ON); - ppu_v1_dynamic_enable(ppu, PPU_V1_MODE_OFF); - - CY_ASSERT(status == CY_PD_PPU_SUCCESS); - break; - - case PPU_V1_MODE_MEM_RET: - status = (cy_pd_ppu_status_t)ppu_v1_set_power_mode(ppu, PPU_V1_MODE_MEM_RET); - CY_ASSERT(status == CY_PD_PPU_SUCCESS); - break; - - case PPU_V1_MODE_FULL_RET: - status = (cy_pd_ppu_status_t)ppu_v1_set_power_mode(ppu, PPU_V1_MODE_FULL_RET); - CY_ASSERT(status == CY_PD_PPU_SUCCESS); - break; - - default: - return CY_PD_PPU_BAD_PARAM; - } - - return status; -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_reset -****************************************************************************//** -* -* Resets the PD using PPU -* -* \param ppu -* This Parameter contains PPU base pointer for which the intialization has -* to be done, it will point to one of the below PPU's -* Main PPU -* RAMC_PPU0 -* RAMC_PPU1 -* RAMC_PPU2 -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -cy_pd_ppu_status_t cy_pd_ppu_reset(struct ppu_v1_reg *ppu) -{ - cy_pd_ppu_status_t status; - CY_ASSERT(ppu != NULL); - - status = cy_pd_ppu_set_power_mode(ppu, PPU_V1_MODE_OFF); - if (status == CY_PD_PPU_SUCCESS) - status = cy_pd_ppu_set_power_mode(ppu, PPU_V1_MODE_ON); - - return status; -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_enable_irq -****************************************************************************//** -* -* High level API , which will call the PD specific PPU IRQ enables -* -* \param ppu -* This Parameter contains PPU base pointer for which the intialization has -* to be done, it will point to one of the below PPU's -* Main PPU -* RAMC_PPU0 -* RAMC_PPU1 -* RAMC_PPU2 -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -static cy_pd_ppu_status_t cy_pd_ppu_enable_irq(struct ppu_v1_reg *ppu) -{ - if((uint32_t)ppu == (uint32_t)CY_PPU_MAIN_BASE) - return cy_pd_ppu_main_irq_enable(); - else if((uint32_t)ppu == (uint32_t)CY_RAMC_PPU0_BASE) - return cy_pd_ramc_ppu0_irq_enable(); - else if((uint32_t)ppu == (uint32_t)CY_RAMC_PPU1_BASE) - return cy_pd_ramc_ppu1_irq_enable(); - else if((uint32_t)ppu == (uint32_t)CY_RAMC_PPU2_BASE) - return cy_pd_ramc_ppu2_irq_enable(); - - return CY_PD_PPU_ERROR; -} - -/******************************************************************************* -* Function Name: cy_pd_ramc_ppu0_irq_enable -****************************************************************************//** -* -* Enables the IRQ for RAMC_PPU0 -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -static cy_pd_ppu_status_t cy_pd_ramc_ppu0_irq_enable(void) -{ - cy_stc_sysint_t ramc_ppu0_irq_cfg = - { - .intrSrc = cpuss_interrupt_ppu_sramc0_IRQn, - .intrPriority = 7UL - }; - - /* Hook interrupt service routine. */ - if(Cy_SysInt_Init(&ramc_ppu0_irq_cfg, &cy_pd_ramc_ppu0_isr)) - return CY_PD_PPU_ERROR; - - /* Enable interrupt in NVIC. */ - NVIC_EnableIRQ((IRQn_Type) ramc_ppu0_irq_cfg.intrSrc); - - return CY_PD_PPU_SUCCESS; -} - -/******************************************************************************* -* Function Name: cy_pd_ramc_ppu1_irq_enable -****************************************************************************//** -* -* Enables the IRQ for RAMC_PPU1 -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -static cy_pd_ppu_status_t cy_pd_ramc_ppu1_irq_enable(void) -{ - cy_stc_sysint_t ramc_ppu1_irq_cfg = - { - .intrSrc = cpuss_interrupt_ppu_sramc1_IRQn, - .intrPriority = 7UL - }; - - /* Hook interrupt service routine. */ - if(Cy_SysInt_Init(&ramc_ppu1_irq_cfg, &cy_pd_ramc_ppu1_isr)) - return CY_PD_PPU_ERROR; - - /* Enable interrupt in NVIC. */ - NVIC_EnableIRQ((IRQn_Type) ramc_ppu1_irq_cfg.intrSrc); - - return CY_PD_PPU_SUCCESS; -} - -/******************************************************************************* -* Function Name: cy_pd_ramc_ppu2_irq_enable -****************************************************************************//** -* -* Enables the IRQ for RAMC_PPU2 -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -static cy_pd_ppu_status_t cy_pd_ramc_ppu2_irq_enable(void) -{ - cy_stc_sysint_t ramc_ppu2_irq_cfg = - { - .intrSrc = cpuss_interrupt_ppu_sramc2_IRQn, - .intrPriority = 7UL - }; - - /* Hook interrupt service routine. */ - if(Cy_SysInt_Init(&ramc_ppu2_irq_cfg, &cy_pd_ramc_ppu2_isr)) - return CY_PD_PPU_ERROR; - - /* Enable interrupt in NVIC. */ - NVIC_EnableIRQ((IRQn_Type) ramc_ppu2_irq_cfg.intrSrc); - - return CY_PD_PPU_SUCCESS; -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_main_irq_enable -****************************************************************************//** -* -* Enables the IRQ for MAIN PPU -* -* \return the PD PPU API status \ref cy_pd_ppu_status_t. -* -*******************************************************************************/ - -static cy_pd_ppu_status_t cy_pd_ppu_main_irq_enable(void) -{ - cy_stc_sysint_t ppu_main_irq_cfg = - { - .intrSrc = srss_interrupt_main_ppu_IRQn, - .intrPriority = 7UL - }; - - /* Hook interrupt service routine. */ - if(Cy_SysInt_Init(&ppu_main_irq_cfg, &cy_pd_ppu_main_isr)) - return CY_PD_PPU_ERROR; - - /* Enable interrupt in NVIC. */ - NVIC_EnableIRQ((IRQn_Type) ppu_main_irq_cfg.intrSrc); - - return CY_PD_PPU_SUCCESS; -} - -/******************************************************************************* -* Function Name: cy_pd_ramc_ppu0_isr -****************************************************************************//** -* -* ISR Handler for RAMC_PPU0 IRQ -* -*******************************************************************************/ - -static void cy_pd_ramc_ppu0_isr(void) -{ - cy_pd_ppu_interrupt_handler((struct ppu_v1_reg *)RAMC_PPU0_BASE); -} - -/******************************************************************************* -* Function Name: cy_pd_ramc_ppu1_isr -****************************************************************************//** -* -* ISR Handler for RAMC_PPU1 IRQ -* -*******************************************************************************/ - -static void cy_pd_ramc_ppu1_isr(void) -{ - cy_pd_ppu_interrupt_handler((struct ppu_v1_reg *)RAMC_PPU1_BASE); -} - -/******************************************************************************* -* Function Name: cy_pd_ramc_ppu2_isr -****************************************************************************//** -* -* ISR Handler for RAMC_PPU2 IRQ -* -*******************************************************************************/ - -static void cy_pd_ramc_ppu2_isr(void) -{ - cy_pd_ppu_interrupt_handler((struct ppu_v1_reg *)RAMC_PPU2_BASE); -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_main_isr -****************************************************************************//** -* -* ISR Handler for MAIN PPU IRQ -* -*******************************************************************************/ - -static void cy_pd_ppu_main_isr(void) -{ - cy_pd_ppu_interrupt_handler((struct ppu_v1_reg *)PWRMODE_PPU_MAIN); -} - -/******************************************************************************* -* Function Name: cy_pd_ppu_interrupt_handler -****************************************************************************//** -* -* Common IR Handler for all the PPU IRQ's -* -* \param ppu -* This Parameter contains PPU base pointer for which the intialization has -* to be done, it will point to one of the below PPU's -* Main PPU -* RAMC_PPU0 -* RAMC_PPU1 -* RAMC_PPU2 -* -*******************************************************************************/ - -static void cy_pd_ppu_interrupt_handler(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - /* ON request interrupt */ - if (ppu_v1_is_power_active_edge_interrupt(ppu, PPU_V1_MODE_ON)) { - ppu_v1_ack_power_active_edge_interrupt(ppu, PPU_V1_MODE_ON); - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_MASKED); - ppu_v1_interrupt_unmask(ppu, PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK); - - /* Minimum policy reached interrupt */ - } else if (ppu_v1_is_dyn_policy_min_interrupt(ppu)) { - ppu_v1_ack_interrupt(ppu, PPU_V1_ISR_DYN_POLICY_MIN_IRQ); - ppu_v1_interrupt_mask(ppu, PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK); - - /* - * Enable the core PACTIVE ON signal rising edge interrupt then check if - * the PACTIVE ON signal is high. If it is high, we may have missed the - * transition from low to high. In that case, just disable the interrupt - * and acknowledge it in case it is pending. There is no need to send an - * update request as one has already been queued. - */ - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_RISING_EDGE); - if (ppu_v1_is_power_devactive_high(ppu, PPU_V1_MODE_ON)) { - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_MASKED); - ppu_v1_ack_power_active_edge_interrupt(ppu, PPU_V1_MODE_ON); - ppu_v1_interrupt_unmask(ppu, PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK); - } - } -} -/** \} group_pd_ppu_functions */ - -#endif /* CY_IP_MXS28SRSS */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_pdm_pcm_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_pdm_pcm_v2.c deleted file mode 100644 index 8bbaa79a7f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_pdm_pcm_v2.c +++ /dev/null @@ -1,293 +0,0 @@ -/***************************************************************************//** -* \file cy_pdm_pcm_v2.c -* \version 2.20 -* -* The source code file for the PDM_PCM driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXPDM) - -#include "cy_pdm_pcm_v2.h" - -/** -* \addtogroup group_pdm_pcm_functions_v2 -* \{ -*/ - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Channel_Init -***************************************************************************//** -* -* Initialize the PDM-PCM Channel -* -* \pre If the PDM-PCM module is initialized previously, the -* -* \param base The pointer to the PDM-PCM instance address -* \param chan_config The pointer to a configuration structure. -* \param channel_num The channel number to be initialized. -* \return error / status code. See \ref cy_en_pdm_pcm_status_t. -* -*******************************************************************************/ -cy_en_pdm_pcm_status_t Cy_PDM_PCM_Channel_Init(PDM_Type * base, cy_stc_pdm_pcm_channel_config_t const * chan_config, uint8_t channel_num) -{ - cy_en_pdm_pcm_status_t ret = CY_PDM_PCM_BAD_PARAM; - - if((NULL != base) && (NULL != chan_config)) - { - CY_ASSERT_L2(CY_PDM_PCM_IS_WORD_SIZE_VALID(chan_config->wordSize)); - CY_ASSERT_L2(CY_PDM_PCM_IS_SIGNEXTENSION_VALID(chan_config->signExtension)); - CY_ASSERT_L2(CY_PDM_PCM_IS_TRIG_LEVEL(chan_config->rxFifoTriggerLevel)); - CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(chan_config->fir0_scale)); - CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(chan_config->fir1_scale)); - - - ret = CY_PDM_PCM_SUCCESS; - - - PDM_PCM_RX_FIFO_CTL(base, channel_num) = _VAL2FLD(PDM_CH_RX_FIFO_CTL_TRIGGER_LEVEL, chan_config->rxFifoTriggerLevel); - - - PDM_PCM_CH_CTL(base, channel_num) = _VAL2FLD(PDM_CH_CTL_WORD_SIZE, chan_config->wordSize) | - _BOOL2FLD(PDM_CH_CTL_WORD_SIGN_EXTEND, chan_config->signExtension) | - _BOOL2FLD(PDM_CH_CTL_ENABLED, CY_PDM_PCM_ENABLE); - - PDM_PCM_CH_IF_CTL(base, channel_num) = _VAL2FLD(PDM_CH_IF_CTL_SAMPLE_DELAY, chan_config->sampledelay); - - - PDM_PCM_CH_CIC_CTL(base, channel_num) = chan_config->cic_decim_code; - - PDM_PCM_CH_FIR0_CTL(base, channel_num) = _VAL2FLD(PDM_CH_FIR0_CTL_DECIM3, chan_config->fir0_decim_code) | - _VAL2FLD(PDM_CH_FIR0_CTL_SCALE, chan_config->fir0_scale) | - _VAL2FLD(PDM_CH_FIR0_CTL_ENABLED, chan_config->fir0_enable); - - PDM_PCM_CH_FIR1_CTL(base, channel_num) = _VAL2FLD(PDM_CH_FIR1_CTL_DECIM2, chan_config->fir1_decim_code) | - _VAL2FLD(PDM_CH_FIR1_CTL_SCALE, chan_config->fir1_scale) | - _VAL2FLD(PDM_CH_FIR1_CTL_ENABLED, CY_PDM_PCM_ENABLE); - - PDM_PCM_CH_DC_BLOCK_CTL(base, channel_num) = _VAL2FLD(PDM_CH_DC_BLOCK_CTL_CODE, chan_config->dc_block_code) | - _VAL2FLD(PDM_CH_DC_BLOCK_CTL_ENABLED, CY_PDM_PCM_ENABLE); - - } - return ret; -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_Init -***************************************************************************//** -* -* Initialize the PDM-PCM module -* -* \pre If the PDM-PCM module is initialized previously, the -* -* \param base The pointer to the PDM-PCM instance address -* \param config The pointer to a configuration structure. -* \return error / status code. See \ref cy_en_pdm_pcm_status_t. -* -*******************************************************************************/ -cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config) -{ - cy_en_pdm_pcm_status_t ret = CY_PDM_PCM_BAD_PARAM; - - if((NULL != base) && (NULL != config)) - { - CY_ASSERT_L2(CY_PDM_PCM_IS_CLK_SEL_VALID(config->clksel)); - CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(config->halverate)); - CY_ASSERT_L2(CY_PDM_PCM_IS_ROUTE_VALID(config->route)); - - ret = CY_PDM_PCM_SUCCESS; - - /* The clock setting */ - PDM_PCM_CLOCK_CTL(base) = _VAL2FLD(PDM_CLOCK_CTL_CLOCK_DIV, config->clkDiv) | - _VAL2FLD(PDM_CLOCK_CTL_CLOCK_SEL, config->clksel) | - _VAL2FLD(PDM_CLOCK_CTL_HALVE, config->halverate); - - /* PDM-PCM ROUTE setting */ - PDM_PCM_ROUTE_CTL(base) = _VAL2FLD(PDM_ROUTE_CTL_DATA_SEL, config->route); - - if(config->fir0_coeff_user_value) - { - PDM_PCM_FIR0_COEFF0(base) = _VAL2FLD(PDM_FIR0_COEFF0_DATA0, config->fir0_coeff[0].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF0_DATA1, config->fir0_coeff[0].coeff_data1); - - PDM_PCM_FIR0_COEFF1(base) = _VAL2FLD(PDM_FIR0_COEFF1_DATA0, config->fir0_coeff[1].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF1_DATA1, config->fir0_coeff[1].coeff_data1); - - PDM_PCM_FIR0_COEFF2(base) = _VAL2FLD(PDM_FIR0_COEFF2_DATA0, config->fir0_coeff[2].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF2_DATA1, config->fir0_coeff[2].coeff_data1); - - PDM_PCM_FIR0_COEFF3(base) = _VAL2FLD(PDM_FIR0_COEFF3_DATA0, config->fir0_coeff[3].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF3_DATA1, config->fir0_coeff[3].coeff_data1); - - PDM_PCM_FIR0_COEFF4(base) = _VAL2FLD(PDM_FIR0_COEFF4_DATA0, config->fir0_coeff[4].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF4_DATA1, config->fir0_coeff[4].coeff_data1); - - PDM_PCM_FIR0_COEFF5(base) = _VAL2FLD(PDM_FIR0_COEFF5_DATA0, config->fir0_coeff[5].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF5_DATA1, config->fir0_coeff[5].coeff_data1); - - PDM_PCM_FIR0_COEFF6(base) = _VAL2FLD(PDM_FIR0_COEFF6_DATA0, config->fir0_coeff[6].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF6_DATA1, config->fir0_coeff[6].coeff_data1); - - PDM_PCM_FIR0_COEFF7(base) = _VAL2FLD(PDM_FIR0_COEFF7_DATA0, config->fir0_coeff[7].coeff_data0) | - _VAL2FLD(PDM_FIR0_COEFF7_DATA1, config->fir0_coeff[7].coeff_data1); - } - - if(config->fir1_coeff_user_value) - { - PDM_PCM_FIR1_COEFF0(base) = _VAL2FLD(PDM_FIR1_COEFF0_DATA0, config->fir1_coeff[0].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF0_DATA1, config->fir1_coeff[0].coeff_data1); - - PDM_PCM_FIR1_COEFF1(base) = _VAL2FLD(PDM_FIR1_COEFF1_DATA0, config->fir1_coeff[1].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF1_DATA1, config->fir1_coeff[1].coeff_data1); - - PDM_PCM_FIR1_COEFF2(base) = _VAL2FLD(PDM_FIR1_COEFF2_DATA0, config->fir1_coeff[2].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF2_DATA1, config->fir1_coeff[2].coeff_data1); - - PDM_PCM_FIR1_COEFF3(base) = _VAL2FLD(PDM_FIR1_COEFF3_DATA0, config->fir1_coeff[3].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF3_DATA1, config->fir1_coeff[3].coeff_data1); - - PDM_PCM_FIR1_COEFF4(base) = _VAL2FLD(PDM_FIR1_COEFF4_DATA0, config->fir1_coeff[4].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF4_DATA1, config->fir1_coeff[4].coeff_data1); - - PDM_PCM_FIR1_COEFF5(base) = _VAL2FLD(PDM_FIR1_COEFF5_DATA0, config->fir1_coeff[5].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF5_DATA1, config->fir1_coeff[5].coeff_data1); - - PDM_PCM_FIR1_COEFF6(base) = _VAL2FLD(PDM_FIR1_COEFF6_DATA0, config->fir1_coeff[6].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF6_DATA1, config->fir1_coeff[6].coeff_data1); - - PDM_PCM_FIR1_COEFF7(base) = _VAL2FLD(PDM_FIR1_COEFF7_DATA0, config->fir1_coeff[7].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF7_DATA1, config->fir1_coeff[7].coeff_data1); - - PDM_PCM_FIR1_COEFF8(base) = _VAL2FLD(PDM_FIR1_COEFF8_DATA0, config->fir1_coeff[8].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF8_DATA1, config->fir1_coeff[8].coeff_data1); - - PDM_PCM_FIR1_COEFF9(base) = _VAL2FLD(PDM_FIR1_COEFF9_DATA0, config->fir1_coeff[9].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF9_DATA1, config->fir1_coeff[9].coeff_data1); - - PDM_PCM_FIR1_COEFF10(base) = _VAL2FLD(PDM_FIR1_COEFF10_DATA0, config->fir1_coeff[10].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF10_DATA1, config->fir1_coeff[10].coeff_data1); - - PDM_PCM_FIR1_COEFF11(base) = _VAL2FLD(PDM_FIR1_COEFF11_DATA0, config->fir1_coeff[11].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF11_DATA1, config->fir1_coeff[11].coeff_data1); - - PDM_PCM_FIR1_COEFF12(base) = _VAL2FLD(PDM_FIR1_COEFF12_DATA0, config->fir1_coeff[12].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF12_DATA1, config->fir1_coeff[12].coeff_data1); - - PDM_PCM_FIR1_COEFF13(base) = _VAL2FLD(PDM_FIR1_COEFF13_DATA0, config->fir1_coeff[13].coeff_data0) | - _VAL2FLD(PDM_FIR1_COEFF13_DATA1, config->fir1_coeff[13].coeff_data1); - - } - - } - - return (ret); -} - -/****************************************************************************** -* Function Name: Cy_PDM_PCM_test_Init -***************************************************************************//** -* -* Initialize the PDM-PCM module -* -* \pre If the PDM-PCM module is initialized previously, the -* -* \param base The pointer to the PDM-PCM instance address -* \param config The pointer to a configuration structure. -* \param test_config test_config -* \return error / status code. See \ref cy_en_pdm_pcm_status_t. -* -*******************************************************************************/ -cy_en_pdm_pcm_status_t Cy_PDM_PCM_test_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config, cy_stc_test_config_t const * test_config) -{ - cy_en_pdm_pcm_status_t ret = CY_PDM_PCM_BAD_PARAM; - - if((NULL != base) && (NULL != config) && (NULL != test_config) ) - { - if(!test_config->enable) - { - return ret; - } - CY_ASSERT_L2(CY_PDM_PCM_IS_CLK_SEL_VALID(config->clksel)); - CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(config->halverate)); - CY_ASSERT_L2(CY_PDM_PCM_IS_ROUTE_VALID(config->route)); - - ret = CY_PDM_PCM_SUCCESS; - - PDM_PCM_TEST_CTL(base) = _VAL2FLD(PDM_TEST_CTL_DRIVE_DELAY_HI, test_config->drive_delay_hi) | - _VAL2FLD(PDM_TEST_CTL_DRIVE_DELAY_LO, test_config->drive_delay_lo); - PDM_PCM_TEST_CTL(base) |= _VAL2FLD(PDM_TEST_CTL_MODE_HI, test_config->mode_hi) | - _VAL2FLD(PDM_TEST_CTL_MODE_LO, test_config->mode_lo); - PDM_PCM_TEST_CTL(base) |= _VAL2FLD(PDM_TEST_CTL_AUDIO_FREQ_DIV, test_config->audio_freq_div) | - _BOOL2FLD(PDM_TEST_CTL_CH_ENABLED, test_config->enable); - - } - - return (ret); -} - - -/******************************************************************************* -* Function Name: Cy_PDM_PCM_Channel_DeInit -****************************************************************************//** -* -* Uninitializes the PDM-PCM channel. -* -* \param base The pointer to the PDM-PCM instance address. -* \param channel_num channel number to be de initialized. -* -*******************************************************************************/ -void Cy_PDM_PCM_Channel_DeInit(PDM_Type * base, uint8_t channel_num) -{ - PDM_PCM_CH_IF_CTL(base, channel_num) = CY_PDM_PCM_CH_IF_CTL_DEFAULT;/* Channel interface control default value */ - PDM_PCM_CH_CTL(base, channel_num) = CY_PDM_PCM_CH_CTL_DEFAULT; /* Channel control default values */ - PDM_PCM_CH_CIC_CTL(base, channel_num) = CY_PDM_PCM_CH_CIC_DECIM_CODE_DEFAULT; - PDM_PCM_CH_FIR1_CTL(base, channel_num) = CY_PDM_PCM_CH_FIR1_DEFAULT; - PDM_PCM_CH_DC_BLOCK_CTL(base, channel_num) = CY_PDM_PCM_CH_DCBLOCK_DEFAULT; - PDM_PCM_CH_FIR0_CTL(base, channel_num) = 0UL; - PDM_PCM_INTR_RX_MASK(base, channel_num) = 0UL; /* Disable interrupts */ - PDM_PCM_RX_FIFO_CTL(base, channel_num) = 0UL; - PDM_PCM_CTL_CLR(base) = (1 << channel_num); - -} - - -/******************************************************************************* -* Function Name: Cy_PDM_PCM_DeInit -****************************************************************************//** -* -* Uninitializes the PDM-PCM module. -* -* \param base The pointer to the PDM-PCM instance address. -* -*******************************************************************************/ -void Cy_PDM_PCM_DeInit(PDM_Type * base) -{ - PDM_PCM_ROUTE_CTL(base) = 0UL; /* Default Route settings */ - PDM_PCM_TEST_CTL(base) = CY_PDM_PCM_TEST_CTL_DEFAULT; /* Default Test settings */ - PDM_PCM_CTL(base) = 0UL; /* Disable the PDM_PCM IP block */ - PDM_PCM_CLOCK_CTL(base) = CY_PDM_PCM_CLK_CTL_DEFAULT; /* The default clock settings */ -} - -/** \} group_pdm_pcm_functions_v2 */ - -#endif /* CY_IP_MXPDM */ - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_sysclk_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_sysclk_v2.c deleted file mode 100644 index 0e9ba79a7a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_sysclk_v2.c +++ /dev/null @@ -1,2091 +0,0 @@ -/***************************************************************************//** -* \file cy_sysclk.c -* \version 1.40 -* -* Provides an API implementation of the sysclk driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) - -#include "cy_sysclk.h" -#include "cy_syslib.h" -#include - - -cy_en_sysclk_status_t - Cy_SysClk_PeriPclkSetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, - uint32_t dividerNum, uint32_t dividerValue) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - if (dividerType == CY_SYSCLK_DIV_8_BIT) - { - if ((dividerNum < PERI_DIV_8_NR) && - (dividerValue <= (PERI_DIV_8_CTL_INT8_DIV_Msk >> PERI_DIV_8_CTL_INT8_DIV_Pos))) - { - CY_REG32_CLR_SET(PERI_DIV_8_CTL(grpNum, dividerNum), PERI_DIV_8_CTL_INT8_DIV, dividerValue); - retVal = CY_SYSCLK_SUCCESS; - } - } - else if (dividerType == CY_SYSCLK_DIV_16_BIT) - { - if ((dividerNum < PERI_DIV_16_NR) && - (dividerValue <= (PERI_DIV_16_CTL_INT16_DIV_Msk >> PERI_DIV_16_CTL_INT16_DIV_Pos))) - { - CY_REG32_CLR_SET(PERI_DIV_16_CTL(grpNum, dividerNum), PERI_DIV_16_CTL_INT16_DIV, dividerValue); - retVal = CY_SYSCLK_SUCCESS; - } - } - else - { /* return bad parameter */ - } - return (retVal); -} - - -uint32_t Cy_SysClk_PeriPclkGetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - uint32_t retVal; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - CY_ASSERT_L1(dividerType <= CY_SYSCLK_DIV_16_BIT); - - if (dividerType == CY_SYSCLK_DIV_8_BIT) - { - CY_ASSERT_L1(dividerNum < PERI_DIV_8_NR); - retVal = _FLD2VAL(PERI_DIV_8_CTL_INT8_DIV, PERI_DIV_8_CTL(grpNum, dividerNum)); - } - else - { /* 16-bit divider */ - CY_ASSERT_L1(dividerNum < PERI_DIV_16_NR); - retVal = _FLD2VAL(PERI_DIV_16_CTL_INT16_DIV, PERI_DIV_16_CTL(grpNum, dividerNum)); - } - return (retVal); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriPclkSetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, - uint32_t dividerIntValue, uint32_t dividerFracValue) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - if (dividerType == CY_SYSCLK_DIV_16_5_BIT) - { - if ((dividerNum < PERI_DIV_16_5_NR) && - (dividerIntValue <= (PERI_DIV_16_5_CTL_INT16_DIV_Msk >> PERI_DIV_16_5_CTL_INT16_DIV_Pos)) && - (dividerFracValue <= (PERI_DIV_16_5_CTL_FRAC5_DIV_Msk >> PERI_DIV_16_5_CTL_FRAC5_DIV_Pos))) - { - CY_REG32_CLR_SET(PERI_DIV_16_5_CTL(grpNum, dividerNum), PERI_DIV_16_5_CTL_INT16_DIV, dividerIntValue); - CY_REG32_CLR_SET(PERI_DIV_16_5_CTL(grpNum, dividerNum), PERI_DIV_16_5_CTL_FRAC5_DIV, dividerFracValue); - retVal = CY_SYSCLK_SUCCESS; - } - } - else if (dividerType == CY_SYSCLK_DIV_24_5_BIT) - { - if ((dividerNum < PERI_DIV_24_5_NR) && - (dividerIntValue <= (PERI_DIV_24_5_CTL_INT24_DIV_Msk >> PERI_DIV_24_5_CTL_INT24_DIV_Pos)) && - (dividerFracValue <= (PERI_DIV_24_5_CTL_FRAC5_DIV_Msk >> PERI_DIV_24_5_CTL_FRAC5_DIV_Pos))) - { - CY_REG32_CLR_SET(PERI_DIV_24_5_CTL(grpNum, dividerNum), PERI_DIV_24_5_CTL_INT24_DIV, dividerIntValue); - CY_REG32_CLR_SET(PERI_DIV_24_5_CTL(grpNum, dividerNum), PERI_DIV_24_5_CTL_FRAC5_DIV, dividerFracValue); - retVal = CY_SYSCLK_SUCCESS; - } - } - else - { /* return bad parameter */ - } - return (retVal); -} - - -void Cy_SysClk_PeriPclkGetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, - uint32_t *dividerIntValue, uint32_t *dividerFracValue) -{ - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_16_5_BIT) || (dividerType == CY_SYSCLK_DIV_24_5_BIT)) && - (dividerIntValue != NULL) && (dividerFracValue != NULL)); - - if (dividerType == CY_SYSCLK_DIV_16_5_BIT) - { - CY_ASSERT_L1(dividerNum < PERI_DIV_16_5_NR); - *dividerIntValue = _FLD2VAL(PERI_DIV_16_5_CTL_INT16_DIV, PERI_DIV_16_5_CTL(grpNum, dividerNum)); - *dividerFracValue = _FLD2VAL(PERI_DIV_16_5_CTL_FRAC5_DIV, PERI_DIV_16_5_CTL(grpNum, dividerNum)); - } - else - { /* 24.5-bit divider */ - CY_ASSERT_L1(dividerNum < PERI_DIV_24_5_NR); - *dividerIntValue = _FLD2VAL(PERI_DIV_24_5_CTL_INT24_DIV, PERI_DIV_24_5_CTL(grpNum, dividerNum)); - *dividerFracValue = _FLD2VAL(PERI_DIV_24_5_CTL_FRAC5_DIV, PERI_DIV_24_5_CTL(grpNum, dividerNum)); - } -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriPclkAssignDivider(en_clk_dst_t ipBlock, - cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - uint8_t periNum = (ipBlock & PERI_PCLK_PERI_NUM_Msk ); - - if ((CY_PERI_CLOCK_NR > periNum) && - (CY_SYSCLK_DIV_24_5_BIT >= dividerType)) - - { - if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) || - ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR))) - { - PERI_CLOCK_CTL(grpNum, periNum) = _VAL2FLD(CY_PERI_CLOCK_CTL_TYPE_SEL, dividerType) | - _VAL2FLD(CY_PERI_CLOCK_CTL_DIV_SEL, dividerNum); - - retVal = CY_SYSCLK_SUCCESS; - } - } - return (retVal); -} - - -uint32_t Cy_SysClk_PeriPclkGetAssignedDivider(en_clk_dst_t ipBlock) -{ - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - uint8_t periNum = (ipBlock & PERI_PCLK_PERI_NUM_Msk ); - - CY_ASSERT_L1(CY_PERI_CLOCK_NR > periNum); - - return (PERI_CLOCK_CTL(grpNum, periNum) & (CY_PERI_CLOCK_CTL_DIV_SEL_Msk | CY_PERI_CLOCK_CTL_TYPE_SEL_Msk)); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriPclkEnableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - if (dividerType <= CY_SYSCLK_DIV_24_5_BIT) - { - if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) || - ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR))) - { - /* specify the divider, make the reference = clk_peri, and enable the divider */ - PERI_DIV_CMD(grpNum) = PERI_DIV_CMD_ENABLE_Msk | - CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk | - CY_PERI_DIV_CMD_PA_DIV_SEL_Msk | - _VAL2FLD(CY_PERI_DIV_CMD_TYPE_SEL, dividerType) | - _VAL2FLD(CY_PERI_DIV_CMD_DIV_SEL, dividerNum); - (void)PERI_DIV_CMD(grpNum); /* dummy read to handle buffered writes */ - retVal = CY_SYSCLK_SUCCESS; - } - } - return (retVal); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriPclkDisableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - if (dividerType <= CY_SYSCLK_DIV_24_5_BIT) - { - if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) || - ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR))) - { - /* specify the divider and disable it */ - PERI_DIV_CMD(grpNum) = PERI_DIV_CMD_DISABLE_Msk | - _VAL2FLD(CY_PERI_DIV_CMD_TYPE_SEL, dividerType) | - _VAL2FLD(CY_PERI_DIV_CMD_DIV_SEL, dividerNum); - retVal = CY_SYSCLK_SUCCESS; - } - } - return (retVal); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriPclkEnablePhaseAlignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, - cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - if (dividerTypePA <= CY_SYSCLK_DIV_24_5_BIT) - { - if (((dividerTypePA == CY_SYSCLK_DIV_8_BIT) && (dividerNumPA < PERI_DIV_8_NR)) || - ((dividerTypePA == CY_SYSCLK_DIV_16_BIT) && (dividerNumPA < PERI_DIV_16_NR)) || - ((dividerTypePA == CY_SYSCLK_DIV_16_5_BIT) && (dividerNumPA < PERI_DIV_16_5_NR)) || - ((dividerTypePA == CY_SYSCLK_DIV_24_5_BIT) && ((dividerNumPA < PERI_DIV_24_5_NR) || (dividerNumPA == 63u)))) - { - /* First, disable the divider that is to be phase-aligned. - The other two parameters are checked in that function; - if they're not valid, the divider is not disabled. */ - retVal = Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum); - if (retVal == CY_SYSCLK_SUCCESS) - { - /* Then, specify the reference divider, and the divider, and enable the divider */ - PERI_DIV_CMD(grpNum) = PERI_DIV_CMD_ENABLE_Msk | - _VAL2FLD(CY_PERI_DIV_CMD_PA_TYPE_SEL, dividerTypePA) | - _VAL2FLD(CY_PERI_DIV_CMD_PA_DIV_SEL, dividerNumPA) | - _VAL2FLD(CY_PERI_DIV_CMD_TYPE_SEL, dividerType) | - _VAL2FLD(CY_PERI_DIV_CMD_DIV_SEL, dividerNum); - } - } - } - return (retVal); -} - - -bool Cy_SysClk_PeriPclkGetDividerEnabled(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - bool retVal = false; - uint8_t grpNum = (ipBlock & PERI_PCLK_GR_NUM_Msk )>>PERI_PCLK_GR_NUM_Pos; - - CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) || - ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) || - ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR))); - - switch(dividerType) - { - case CY_SYSCLK_DIV_8_BIT: - retVal = _FLD2BOOL(PERI_DIV_8_CTL_EN, PERI_DIV_8_CTL(grpNum, dividerNum)); - break; - case CY_SYSCLK_DIV_16_BIT: - retVal = _FLD2BOOL(PERI_DIV_16_CTL_EN, PERI_DIV_16_CTL(grpNum, dividerNum)); - break; - case CY_SYSCLK_DIV_16_5_BIT: - retVal = _FLD2BOOL(PERI_DIV_16_5_CTL_EN, PERI_DIV_16_5_CTL(grpNum, dividerNum)); - break; - case CY_SYSCLK_DIV_24_5_BIT: - retVal = _FLD2BOOL(PERI_DIV_24_5_CTL_EN, PERI_DIV_24_5_CTL(grpNum, dividerNum)); - break; - default: - /* Unknown Divider */ - break; - } - return (retVal); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, - uint32_t dividerNum, uint32_t dividerValue) -{ - return Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum, dividerValue); -} - - -uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - return Cy_SysClk_PeriPclkGetDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, - uint32_t dividerIntValue, uint32_t dividerFracValue) -{ - return Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum, dividerIntValue, dividerFracValue); -} - - -void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, - uint32_t *dividerIntValue, uint32_t *dividerFracValue) -{ - Cy_SysClk_PeriPclkGetFracDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum, dividerIntValue, dividerFracValue); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, - cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - return Cy_SysClk_PeriPclkAssignDivider(ipBlock, dividerType, dividerNum); -} - - -uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock) -{ - return Cy_SysClk_PeriPclkGetAssignedDivider(ipBlock); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - return Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - return Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum); -} - - -cy_en_sysclk_status_t - Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, - cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA) -{ - return Cy_SysClk_PeriPclkEnablePhaseAlignDivider((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum, dividerTypePA, dividerNumPA); -} - - -bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - return Cy_SysClk_PeriPclkGetDividerEnabled((en_clk_dst_t)PERI_PCLK_PERIPHERAL_GROUP_NUM, dividerType, dividerNum); -} - - -/* ========================================================================== */ -/* ========================= clk_slow SECTION ========================= */ -/* ========================================================================== */ - - -uint32_t Cy_SysClk_ClkSlowGetFrequency(void) -{ - return 0; -} - - -void Cy_SysClk_ClkSlowSetDivider(uint8_t divider) -{ - -} - - -uint8_t Cy_SysClk_ClkSlowGetDivider(void) -{ - - return 0; -} - -/* ========================================================================== */ -/* ========================= clk_pump SECTION ========================= */ -/* ========================================================================== */ - -void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source) -{ -} - - -cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void) -{ - return CY_SYSCLK_PUMP_IN_CLKPATH0; -} - - -void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider) -{ -} - - -cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void) -{ - return CY_SYSCLK_PUMP_NO_DIV; -} - - -void Cy_SysClk_ClkPumpEnable(void) -{ -} - - -void Cy_SysClk_ClkPumpDisable(void) -{ -} - -/* ========================================================================== */ -/* ========================== clk_bak SECTION ========================= */ -/* ========================================================================== */ - -void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source) -{ - CY_ASSERT_L3(source <= CY_SYSCLK_BAK_IN_PILO); - CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_CLK_SEL, source); -} - - -cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void) -{ - return ((cy_en_clkbak_in_sources_t)_FLD2VAL(BACKUP_CTL_CLK_SEL, BACKUP_CTL)); -} - -/* ========================================================================== */ -/* ======================== clk_timer SECTION ========================= */ -/* ========================================================================== */ - -void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source) -{ - -} - -cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void) -{ - return (cy_en_clktimer_in_sources_t)0; -} - -void Cy_SysClk_ClkTimerSetDivider(uint8_t divider) -{ - -} - -uint8_t Cy_SysClk_ClkTimerGetDivider(void) -{ - return 0; -} - -void Cy_SysClk_ClkTimerEnable(void) -{ - -} - -void Cy_SysClk_ClkTimerDisable(void) -{ - -} - -/* ========================================================================== */ -/* =========================== clkLf SECTION ========================== */ -/* ========================================================================== */ - -void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source) -{ - CY_ASSERT_L3(source <= CY_SYSCLK_CLKLF_IN_PILO); - CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_LFCLK_SEL, source); -} - - -cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void) -{ - return ((cy_en_clklf_in_sources_t)(_FLD2VAL(SRSS_CLK_SELECT_LFCLK_SEL, SRSS_CLK_SELECT))); -} - -/* ========================================================================== */ -/* ======================== clk_peri SECTION ========================== */ -/* ========================================================================== */ - -uint32_t Cy_SysClk_ClkPeriGetFrequency(void) -{ - return 0; -} - - -void Cy_SysClk_ClkPeriSetDivider(uint8_t divider) -{ -} - - -uint8_t Cy_SysClk_ClkPeriGetDivider(void) -{ - return 0; -} - - -/* ========================================================================== */ -/* ======================== PERI SECTION ========================== */ -/* ========================================================================== */ - - -cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetDivider(uint8_t groupNum, int8_t divider) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - - if (groupNum < CY_PERI_GROUP_NR) - { - if ((divider <= (PERI_GR_CLOCK_CTL_INT8_DIV_Msk >> PERI_GR_CLOCK_CTL_INT8_DIV_Pos))) - { - CY_REG32_CLR_SET(PERI_GR_CLOCK_CTL(groupNum), PERI_GR_CLOCK_CTL_INT8_DIV, divider); - retVal = CY_SYSCLK_SUCCESS; - } - } - - return retVal; -} - - -int8_t Cy_SysClk_PeriGroupGetDivider(uint8_t groupNum) -{ - int8_t retVal = 0; - - if (groupNum < CY_PERI_GROUP_NR) - { - return(_FLD2VAL(PERI_GR_CLOCK_CTL_INT8_DIV, PERI_GR_CLOCK_CTL(groupNum))); - - } - - return retVal; -} - - -cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetSlaveCtl(uint8_t groupNum, uint32_t slaveCtl) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - - if (groupNum < CY_PERI_GROUP_NR) - { - CY_REG32_CLR_SET(PERI_GR_SL_CTL(groupNum), PERI_GR_SL_CTL_ENABLED, slaveCtl); - retVal = CY_SYSCLK_SUCCESS; - } - - return retVal; -} - - -uint32_t Cy_SysClk_PeriGroupGetSlaveCtl(uint8_t groupNum) -{ - uint32_t retVal = 0; - - if (groupNum < CY_PERI_GROUP_NR) - { - retVal = _FLD2VAL(PERI_GR_SL_CTL_ENABLED, PERI_GR_SL_CTL(groupNum)); - - } - - return retVal; -} - - -/* ========================================================================== */ -/* ========================= clk_fast SECTION ========================= */ -/* ========================================================================== */ - - -uint32_t Cy_SysClk_ClkFastGetFrequency(void) -{ - return 0; -} - - -void Cy_SysClk_ClkFastSetDivider(uint8_t divider) -{ - -} - - -uint8_t Cy_SysClk_ClkFastGetDivider(void) -{ - return 0; -} - -/* ========================================================================== */ -/* ========================= clkHf[n] SECTION ========================= */ -/* ========================================================================== */ - -cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - if (clkHf < CY_SRSS_NUM_HFROOT) - { - SRSS_CLK_ROOT_SELECT[clkHf] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk; - retVal = CY_SYSCLK_SUCCESS; - } - return (retVal); -} - - -bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) -{ - bool retVal = false; - if (clkHf < CY_SRSS_NUM_HFROOT) - { - retVal = _FLD2BOOL(SRSS_CLK_ROOT_SELECT_ENABLE, SRSS_CLK_ROOT_SELECT[clkHf]); - } - return (retVal); -} - -cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - if ((0UL < clkHf) /* prevent CLK_HF0 disabling */ - && (clkHf < CY_SRSS_NUM_HFROOT)) - { - SRSS_CLK_ROOT_SELECT[clkHf] &= ~SRSS_CLK_ROOT_SELECT_ENABLE_Msk; - retVal = CY_SYSCLK_SUCCESS; - } - return (retVal); -} - - -cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - if ((clkHf < CY_SRSS_NUM_HFROOT) && (source <= CY_SYSCLK_CLKHF_IN_CLKPATH15)) - { - CY_REG32_CLR_SET(SRSS_CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_MUX, source); - retVal = CY_SYSCLK_SUCCESS; - } - return (retVal); -} - - -cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf) -{ - CY_ASSERT_L1(clkHf < CY_SRSS_NUM_HFROOT); - return ((cy_en_clkhf_in_sources_t)((uint32_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS_CLK_ROOT_SELECT[clkHf])))); -} - - -cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - if ((clkHf < CY_SRSS_NUM_HFROOT) && (divider <= CY_SYSCLK_CLKHF_DIVIDE_BY_8)) - { - CY_REG32_CLR_SET(SRSS_CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_DIV, divider); - retVal = CY_SYSCLK_SUCCESS; - } - return (retVal); -} - - -cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf) -{ - CY_ASSERT_L1(clkHf < CY_SRSS_NUM_HFROOT); - return ((cy_en_clkhf_dividers_t)(((uint32_t)_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS_CLK_ROOT_SELECT[clkHf])))); -} - - -/* ========================================================================== */ -/* ============================ MFO SECTION ============================ */ -/* ========================================================================== */ - - -void Cy_SysClk_MfoEnable(bool deepSleepEnable) -{ -#if (CY_SRSS_MFO_PRESENT) -#if defined (CY_IP_MXS28SRSS) - SRSS_CLK_MFO_CONFIG = SRSS_CLK_MFO_CONFIG_ENABLE_Msk; -#else - SRSS_CLK_MFO_CONFIG = SRSS_CLK_MFO_CONFIG_ENABLE_Msk | (deepSleepEnable ? SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk : 0UL); -#endif -#endif -} - -bool Cy_SysClk_MfoIsEnabled(void) -{ -#if (CY_SRSS_MFO_PRESENT) - return (CY_SRSS_MFO_PRESENT && (0UL != (SRSS_CLK_MFO_CONFIG & SRSS_CLK_MFO_CONFIG_ENABLE_Msk))); -#else - return false; -#endif - -} - -void Cy_SysClk_MfoDisable(void) -{ -#if (CY_SRSS_MFO_PRESENT) - SRSS_CLK_MFO_CONFIG = 0UL; -#endif -} - - -/* ========================================================================== */ -/* ============================ CLK_MF SECTION ============================ */ -/* ========================================================================== */ - - -void Cy_SysClk_ClkMfEnable(void) -{ -#if (CY_SRSS_MFO_PRESENT) - SRSS_CLK_MF_SELECT |= SRSS_CLK_MF_SELECT_ENABLE_Msk; -#endif -} - - -bool Cy_SysClk_ClkMfIsEnabled(void) -{ -#if (CY_SRSS_MFO_PRESENT) - return ((0UL != (SRSS_CLK_MF_SELECT & SRSS_CLK_MF_SELECT_ENABLE_Msk))); -#else - return false; -#endif -} - - -void Cy_SysClk_ClkMfDisable(void) -{ -#if (CY_SRSS_MFO_PRESENT) - SRSS_CLK_MF_SELECT &= ~SRSS_CLK_MF_SELECT_ENABLE_Msk; -#endif -} - - -void Cy_SysClk_ClkMfSetDivider(uint32_t divider) -{ -#if (CY_SRSS_MFO_PRESENT) - if ((CY_SRSS_MFO_PRESENT) && CY_SYSCLK_IS_MF_DIVIDER_VALID(divider)) - { - if (!Cy_SysClk_ClkMfIsEnabled()) - { - CY_REG32_CLR_SET(SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); - } - } -#endif -} - - -uint32_t Cy_SysClk_ClkMfGetDivider(void) -{ -#if (CY_SRSS_MFO_PRESENT) - return ((CY_SRSS_MFO_PRESENT) ? (1UL + _FLD2VAL(SRSS_CLK_MF_SELECT_MFCLK_DIV, SRSS_CLK_MF_SELECT)) : 1UL); -#else - return 0; -#endif -} - - -uint32_t Cy_SysClk_ClkMfGetFrequency(void) -{ -#if (CY_SRSS_MFO_PRESENT) - uint32_t locFreq = (Cy_SysClk_MfoIsEnabled()) ? CY_SYSCLK_MFO_FREQ : 0UL; /* Get root frequency */ - uint32_t locDiv = Cy_SysClk_ClkMfGetDivider(); /* clkMf prescaler (1-256) */ - - /* Divide the path input frequency down and return the result */ - return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); -#else - return 0; -#endif -} - -/* ========================================================================== */ -/* =========================== WCO SECTION =========================== */ -/* ========================================================================== */ - -cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_TIMEOUT; - - /* Enable WCO */ -#if defined (CY_IP_MXS28SRSS) - BACKUP_WCO_CTL |= BACKUP_WCO_CTL_WCO_EN_Msk; -#else - BACKUP_CTL |= BACKUP_CTL_WCO_EN_Msk; -#endif - - /* now do the timeout wait for STATUS, bit WCO_OK */ - for (; (Cy_SysClk_WcoOkay() == false) && (0UL != timeoutus); timeoutus--) - { - Cy_SysLib_DelayUs(1U); - } - - if (0UL != timeoutus) - { - retVal = CY_SYSCLK_SUCCESS; - } - - return (retVal); -} - -bool Cy_SysClk_WcoOkay(void) -{ - return (_FLD2BOOL(BACKUP_WCO_STATUS_WCO_OK, BACKUP_WCO_STATUS)); -} - -void Cy_SysClk_WcoDisable(void) -{ -#if defined (CY_IP_MXS28SRSS) - BACKUP_WCO_CTL &= (uint32_t)~BACKUP_WCO_CTL_WCO_EN_Msk; -#else - BACKUP_CTL &= (uint32_t)~BACKUP_CTL_WCO_EN_Msk; -#endif -} - -#if defined (CY_IP_MXS28SRSS) -void Cy_SysClk_WcoGainControl(cy_en_wco_gain_ctrl_modes_t gmMode) -{ - CY_REG32_CLR_SET(BACKUP_WCO_CTL, BACKUP_WCO_CTL_GM, gmMode); -} -#endif - -void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass) -{ -#if defined (CY_IP_MXS28SRSS) - CY_REG32_CLR_SET(BACKUP_WCO_CTL, BACKUP_WCO_CTL_WCO_BYP_EN, bypass); -#else - CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_WCO_BYPASS, bypass); -#endif -} - -/* ========================================================================== */ -/* =========================== PILO SECTION =========================== */ -/* ========================================================================== */ - -void Cy_SysClk_PiloEnable(void) -{ -#if (CY_SRSS_PILO_PRESENT) - SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_EN_Msk; /* 1 = enable */ - Cy_SysLib_Delay(1U/*msec */); - /* release the reset and enable clock output */ - SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | - SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk; -#endif -} - -bool Cy_SysClk_PiloIsEnabled(void) -{ -#if (CY_SRSS_PILO_PRESENT) - return (_FLD2BOOL(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, SRSS_CLK_PILO_CONFIG)); -#else - return false; -#endif -} - -void Cy_SysClk_PiloDisable(void) -{ -#if (CY_SRSS_PILO_PRESENT) - /* Clear PILO_EN, PILO_RESET_N, and PILO_CLK_EN bitfields. This disables the - PILO and holds the PILO in a reset state. */ - SRSS_CLK_PILO_CONFIG &= (uint32_t)~(SRSS_CLK_PILO_CONFIG_PILO_EN_Msk | - SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | - SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk); -#endif -} - - -void Cy_SysClk_PiloSetTrim(uint32_t trimVal) -{ -#if (CY_SRSS_PILO_PRESENT) - CY_REG32_CLR_SET(SRSS_CLK_PILO_CONFIG, SRSS_CLK_PILO_CONFIG_PILO_FFREQ, trimVal); -#endif -} - - -uint32_t Cy_SysClk_PiloGetTrim(void) -{ -#if (CY_SRSS_PILO_PRESENT) - return (_FLD2VAL(SRSS_CLK_PILO_CONFIG_PILO_FFREQ, SRSS_CLK_PILO_CONFIG)); -#else - return 0; -#endif -} - -/* ========================================================================== */ -/* ========================== ALTHF SECTION =========================== */ -/* ========================================================================== */ - -uint32_t Cy_SysClk_AltHfGetFrequency(void) -{ - #if defined (CY_IP_MXBLESS) - return (cy_BleEcoClockFreqHz); - #else /* CY_IP_MXBLESS */ - return (0UL); - #endif /* CY_IP_MXBLESS */ -} - -/* ========================================================================== */ -/* ========================== ALTLF SECTION =========================== */ -/* ========================================================================== */ - - -uint32_t Cy_SysClk_AltLfGetFrequency(void) -{ - return (0UL); -} - - -bool Cy_SysClk_AltLfIsEnabled(void) -{ - return (false); -} - - -/* ========================================================================== */ -/* =========================== ILO SECTION ============================ */ -/* ========================================================================== */ - - -void Cy_SysClk_IloEnable(void) -{ - SRSS_CLK_ILO_CONFIG |= SRSS_CLK_ILO_CONFIG_ENABLE_Msk; -} - - -cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; - if (!_FLD2BOOL(SRSS_WDT_CTL_WDT_EN, SRSS_WDT_CTL)) /* if disabled */ - { - SRSS_CLK_ILO_CONFIG &= ~SRSS_CLK_ILO_CONFIG_ENABLE_Msk; - retVal = CY_SYSCLK_SUCCESS; - } - return (retVal); -} - - -void Cy_SysClk_IloHibernateOn(bool on) -{ - CY_REG32_CLR_SET(SRSS_CLK_ILO_CONFIG, SRSS_CLK_ILO_CONFIG_ILO_BACKUP, ((on) ? 1UL : 0UL)); -} - - -/* ========================================================================== */ -/* ========================= EXTCLK SECTION =========================== */ -/* ========================================================================== */ - - - static uint32_t cySysClkExtFreq = 0UL; - - -#define CY_SYSCLK_EXTCLK_MAX_FREQ (100000000UL) /* 100 MHz */ - - -void Cy_SysClk_ExtClkSetFrequency(uint32_t freq) -{ - if (freq <= CY_SYSCLK_EXTCLK_MAX_FREQ) - { - cySysClkExtFreq = freq; - } -} - -/******************************************************************************* -* Function Name: Cy_SysClk_ExtClkGetFrequency -****************************************************************************//** -* -* Returns the frequency of the External Clock Source (EXTCLK) from the -* internal storage. -* -* \return The frequency of the External Clock Source. -* -* \funcusage -* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency -* -*******************************************************************************/ -uint32_t Cy_SysClk_ExtClkGetFrequency(void) -{ - return (cySysClkExtFreq); -} - -/* ========================================================================== */ -/* =========================== ECO SECTION ============================ */ -/* ========================================================================== */ -#if (CY_SRSS_ECO_PRESENT) -static uint32_t ecoFreq = 0UL; /* Internal storage for ECO frequency user setting */ -#endif - -void Cy_SysClk_EcoDisable(void) -{ -#if (CY_SRSS_ECO_PRESENT) - SRSS_CLK_ECO_CONFIG &= ~SRSS_CLK_ECO_CONFIG_ECO_EN_Msk; -#endif -} - - -uint32_t Cy_SysClk_EcoGetStatus(void) -{ -#if (CY_SRSS_ECO_PRESENT) - uint32_t eco_status = SRSS_CLK_ECO_STATUS; - uint32_t eco_status_mask = SRSS_CLK_ECO_AMP_OK_Msk | SRSS_CLK_ECO_READY_Msk; - - /* if ECO is not ready, just report the ECO_OK bit. Otherwise report 2 = ECO ready */ - return ((eco_status_mask == (eco_status_mask & eco_status)) ? - CY_SYSCLK_ECOSTAT_STABLE : (SRSS_CLK_ECO_AMP_OK_Msk & eco_status)); -#else - return 0; -#endif -} - - -uint32_t Cy_SysClk_EcoBleGetStatus(void) -{ -#if (CY_SRSS_ECO_PRESENT) - /* if ECO for BLE is Enabled, report 1. Otherwise report 0 */ - return ((SRSS_CLK_ECO_STATUS_ECO_BLE_ENABLED_Msk == (SRSS_CLK_ECO_STATUS_ECO_BLE_ENABLED_Msk & SRSS_CLK_ECO_STATUS)) ? - CY_SYSCLK_ECOSTAT_BLE_ENABLED : CY_SYSCLK_ECOSTAT_BLE_DISABLED); -#else - return 0; -#endif -} - - -cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint32_t esr, uint32_t driveLevel) -{ - /* Legacy */ - return CY_SYSCLK_INVALID_STATE; -} - - -cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) -{ -#if (CY_SRSS_ECO_PRESENT) - cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; - bool zeroTimeout = (0UL == timeoutus); - - /* Invalid state error if ECO is already enabled */ - if (0UL == (SRSS_CLK_ECO_CONFIG_ECO_EN_Msk & SRSS_CLK_ECO_CONFIG)) - { - /* Set ECO enable */ - SRSS_CLK_ECO_CONFIG |= SRSS_CLK_ECO_CONFIG_ECO_EN_Msk; - - /* Wait for CY_SYSCLK_ECOSTAT_STABLE */ - for (; (CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (0UL != timeoutus); timeoutus--) - { - Cy_SysLib_DelayUs(1U); - } - - if (zeroTimeout || (0UL != timeoutus)) - { - retVal = CY_SYSCLK_SUCCESS; - } - else - { - /* If ECO doesn't start, then disable it */ - SRSS_CLK_ECO_CONFIG &= ~SRSS_CLK_ECO_CONFIG_ECO_EN_Msk; - retVal = CY_SYSCLK_TIMEOUT; - } - } - - return (retVal); - -#else - return CY_SYSCLK_INVALID_STATE; -#endif -} - -/******************************************************************************* -* Function Name: Cy_SysClk_EcoGetFrequency -****************************************************************************//** -* -* Returns the frequency of the external crystal oscillator (ECO). -* -* \return The frequency of the ECO. -* -* \note If the ECO is not enabled or stable - a zero is returned. -* -* \funcusage -* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable -* -*******************************************************************************/ -uint32_t Cy_SysClk_EcoGetFrequency(void) -{ -#if (CY_SRSS_ECO_PRESENT) - return ((CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL); -#else - return 0; -#endif -} - -#if defined (CY_IP_MXS28SRSS) -cy_en_sysclk_status_t Cy_SysClk_EcoBleControl(cy_en_eco_for_ble_t control, uint32_t timeoutus) -{ -#if (CY_SRSS_ECO_PRESENT) - cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; - bool zeroTimeout = (0UL == timeoutus); - - CY_ASSERT_L1(control < sizeof(cy_en_eco_for_ble_t)); - - /* Set ECO for BLE with control value */ - SRSS_CLK_ECO_CONFIG |= (control << SRSS_CLK_ECO_CONFIG_ECO_BLE_EN_Pos); - - /* Wait for CY_SYSCLK_ECOSTAT_STABLE */ - for (; (CY_SYSCLK_ECOSTAT_BLE_ENABLED != Cy_SysClk_EcoBleGetStatus()) && (0UL != timeoutus); timeoutus--) - { - Cy_SysLib_DelayUs(1U); - } - - retVal = (zeroTimeout || (0UL != timeoutus)) ? CY_SYSCLK_SUCCESS : CY_SYSCLK_TIMEOUT; - - return (retVal); -#else - return CY_SYSCLK_INVALID_STATE; -#endif -} -#endif - -cy_en_sysclk_status_t Cy_SysClk_EcoPrescaleConfigure(uint32_t enable, uint32_t frac_div, uint32_t int_div) -{ -#if (CY_SRSS_ECO_PRESENT) - cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; - - if(enable) { - /* Invalid state error if CO_DIV_ENABLED is already enabled */ - if (0UL == (SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk & SRSS_CLK_ECO_PRESCALE)) - { - SRSS_CLK_ECO_PRESCALE |= SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk; - SRSS_CLK_ECO_PRESCALE = _VAL2FLD(SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV, frac_div); - SRSS_CLK_ECO_PRESCALE = _VAL2FLD(SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV, int_div); - retVal = CY_SYSCLK_SUCCESS; - } - } - else { - /* Invalid state error if CO_DIV_ENABLED is already disabled */ - if (1UL == (SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk & SRSS_CLK_ECO_PRESCALE)) - { - SRSS_CLK_ECO_PRESCALE &= ~(SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk); - retVal = CY_SYSCLK_SUCCESS; - } - } - return retVal; -#else - return CY_SYSCLK_INVALID_STATE; -#endif -} - - -/* ========================================================================== */ -/* ==================== INPUT MULTIPLEXER SECTION ===================== */ -/* ========================================================================== */ - - -cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - if ((clkPath < CY_SRSS_NUM_CLKPATH) && - ((source <= CY_SYSCLK_CLKPATH_IN_DSIMUX) || - ((CY_SYSCLK_CLKPATH_IN_DSI <= source) && (source <= CY_SYSCLK_CLKPATH_IN_PILO)))) - { - if (source >= CY_SYSCLK_CLKPATH_IN_DSI) - { - SRSS_CLK_DSI_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_DSI_SELECT_DSI_MUX, (uint32_t)source); - SRSS_CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)CY_SYSCLK_CLKPATH_IN_DSIMUX); - } - else - { - SRSS_CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)source); - } - retVal = CY_SYSCLK_SUCCESS; - } - return (retVal); -} - -cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) -{ - CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); - cy_en_clkpath_in_sources_t retVal = - (cy_en_clkpath_in_sources_t )((uint32_t)_FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS_CLK_PATH_SELECT[clkPath])); - if (retVal == CY_SYSCLK_CLKPATH_IN_DSIMUX) - { - retVal = (cy_en_clkpath_in_sources_t)((uint32_t)(((uint32_t)CY_SYSCLK_CLKPATH_IN_DSI) | - ((uint32_t)(_FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS_CLK_DSI_SELECT[clkPath]))))); - } - return (retVal); -} - -uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) -{ - CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); - - uint32_t freq = 0UL; /* The path mux output frequency in Hz, 0 = an unknown frequency */ - - /* Get the frequency of the source, i.e., the path mux input */ - switch(Cy_SysClk_ClkPathGetSource(clkPath)) - { - case CY_SYSCLK_CLKPATH_IN_IMO: /* The IMO frequency is fixed at 8 MHz */ - freq = CY_SYSCLK_IMO_FREQ; - break; - - case CY_SYSCLK_CLKPATH_IN_EXT: - freq = Cy_SysClk_ExtClkGetFrequency(); - break; - - case CY_SYSCLK_CLKPATH_IN_ECO: - freq = Cy_SysClk_EcoGetFrequency(); - break; - - case CY_SYSCLK_CLKPATH_IN_ALTHF: - freq = Cy_SysClk_AltHfGetFrequency(); - break; - - case CY_SYSCLK_CLKPATH_IN_ILO: - freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_WCO: - freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_PILO: - freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_ALTLF: - freq = Cy_SysClk_AltLfGetFrequency(); - break; - - default: - /* Don't know the frequency of dsi_out, leave freq = 0UL */ - break; - } - - return (freq); -} - -/******************************************************************************* -* Function Name: Cy_SysClk_ClkPathGetFrequency -****************************************************************************//** -* -* Returns the output frequency of the clock path mux. -* -* \return The output frequency of the path mux. -* -* \note If the return value equals zero, that means either: -* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or -* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). -* -* \funcusage -* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable -* -*******************************************************************************/ -uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) -{ - CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); - - uint32_t freq = Cy_SysClk_ClkPathMuxGetFrequency(clkPath); - uint32_t fDiv = 1UL; /* FLL/PLL multiplier/feedback divider */ - uint32_t rDiv = 1UL; /* FLL/PLL reference divider */ - uint32_t oDiv = 1UL; /* FLL/PLL output divider */ - bool enabled = false; /* FLL or PLL enable status; n/a for direct */ - - if (clkPath == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ - { - cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; - Cy_SysClk_FllGetConfiguration(&fllCfg); - enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); - fDiv = fllCfg.fllMult; - rDiv = fllCfg.refDiv; - oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; - } - else if (clkPath <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ - { - cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; - (void)Cy_SysClk_PllGetConfiguration(clkPath, &pllcfg); - enabled = (Cy_SysClk_PllIsEnabled(clkPath)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); - fDiv = pllcfg.feedbackDiv; - rDiv = pllcfg.referenceDiv; - oDiv = pllcfg.outputDiv; - } - else - { - /* Do nothing with the path mux frequency */ - } - - if (enabled && /* If FLL or PLL is enabled and not bypassed */ - (0UL != rDiv) && (0UL != oDiv)) /* to avoid division by zero */ - { - freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), - ((uint64_t)rDiv * (uint64_t)oDiv)); - } - - return (freq); -} - -/* ========================================================================== */ -/* =========================== FLL SECTION ============================ */ -/* ========================================================================== */ - -/* min and max FLL output frequencies, in Hz */ -#define CY_SYSCLK_FLL_MIN_CCO_OUTPUT_FREQ (48000000UL) -#define CY_SYSCLK_FLL_MIN_OUTPUT_FREQ (CY_SYSCLK_FLL_MIN_CCO_OUTPUT_FREQ / 2U) -#define CY_SYSCLK_FLL_MAX_OUTPUT_FREQ (100000000UL) - -#define CY_SYSCLK_FLL_IS_CCO_RANGE_VALID(range) (((range) == CY_SYSCLK_FLL_CCO_RANGE0) || \ - ((range) == CY_SYSCLK_FLL_CCO_RANGE1) || \ - ((range) == CY_SYSCLK_FLL_CCO_RANGE2) || \ - ((range) == CY_SYSCLK_FLL_CCO_RANGE3) || \ - ((range) == CY_SYSCLK_FLL_CCO_RANGE4)) -/** \cond INTERNAL */ -#define CY_SYSCLK_FLL_INT_COEF (327680000UL) -#define CY_SYSCLK_FLL_GAIN_IDX (11U) -#define CY_SYSCLK_FLL_GAIN_VAL (8UL * CY_SYSCLK_FLL_INT_COEF) - -#define TRIM_STEPS_SCALE (100000000ULL) /* 10 ^ 8 */ -#define MARGIN_SCALE (100000ULL) /* 10 ^ 5 */ -/** \endcond */ - -bool Cy_SysClk_FllIsEnabled(void) -{ -#if (CY_SRSS_FLL_PRESENT) - return (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)); -#else - return false; -#endif -} - - -bool Cy_SysClk_FllLocked(void) -{ -#if (CY_SRSS_FLL_PRESENT) - return (_FLD2BOOL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS_CLK_FLL_STATUS)); -#else - return false; -#endif -} - -cy_en_sysclk_status_t Cy_SysClk_FllDisable(void) -{ -#if (CY_SRSS_FLL_PRESENT) - CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); - SRSS_CLK_FLL_CONFIG &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS_CLK_FLL_CONFIG4 &= ~SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; - return (CY_SYSCLK_SUCCESS); -#else - return (CY_SYSCLK_INVALID_STATE); -#endif -} - -void Cy_SysClk_FllOutputDividerEnable(bool enable) -{ -#if (CY_SRSS_FLL_PRESENT) - SRSS_CLK_FLL_CONFIG = _BOOL2FLD(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, enable); -#endif -} - - -cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode) -{ -#if (CY_SRSS_FLL_PRESENT) - cy_en_sysclk_status_t retVal = CY_SYSCLK_SUCCESS; - - /* check for errors */ - if ((outputFreq < CY_SYSCLK_FLL_MIN_OUTPUT_FREQ) || (CY_SYSCLK_FLL_MAX_OUTPUT_FREQ < outputFreq) || /* invalid output frequency */ - (((outputFreq * 5UL) / inputFreq) < 11UL)) /* check output/input frequency ratio */ - { - retVal = CY_SYSCLK_BAD_PARAM; - } - else /* no errors */ - { - /* If output mode is bypass (input routed directly to output), then done. - The output frequency equals the input frequency regardless of the - frequency parameters. */ - if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) - { - cy_stc_fll_manual_config_t config; - uint32_t ccoFreq; - bool wcoSource = (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(0UL/*FLL*/)) ? true : false; - - config.outputMode = outputMode; - /* 1. Output division by 2 is always required */ - config.enableOutputDiv = true; - /* 2. Compute the target CCO frequency from the target output frequency and output division */ - ccoFreq = outputFreq * 2UL; - /* 3. Compute the CCO range value from the CCO frequency */ - config.ccoRange = ((ccoFreq >= 150339200UL) ? CY_SYSCLK_FLL_CCO_RANGE4 : - ((ccoFreq >= 113009380UL) ? CY_SYSCLK_FLL_CCO_RANGE3 : - ((ccoFreq >= 84948700UL) ? CY_SYSCLK_FLL_CCO_RANGE2 : - ((ccoFreq >= 63855600UL) ? CY_SYSCLK_FLL_CCO_RANGE1 : CY_SYSCLK_FLL_CCO_RANGE0)))); - - /* 4. Compute the FLL reference divider value. - refDiv is a constant if the WCO is the FLL source, otherwise the formula is - refDiv = ROUNDUP((inputFreq / outputFreq) * 250) */ - config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (uint64_t)outputFreq); - - /* 5. Compute the FLL multiplier value. - Formula is fllMult = ccoFreq / (inputFreq / refDiv) */ - config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uint64_t)inputFreq); - /* 6. Compute the lock tolerance. - Formula is lock tolerance = 1.5 * fllMult * (((1 + CCO accuracy) / (1 - source clock accuracy)) - 1) - We assume CCO accuracy is 0.25%. - We assume the source clock accuracy = 1%. This is the accuracy of the IMO. - Therefore the formula is lock tolerance = 1.5 * fllMult * 0.012626 = 0.018939 * fllMult */ - config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); - - { - /* constants indexed by ccoRange */ - const uint32_t trimSteps[] = {110340UL, 110200UL, 110000UL, 110000UL, 117062UL}; /* Scaled by 10^8 */ - const uint32_t margin[] = {436UL, 581UL, 772UL, 1030UL, 1320UL}; /* Scaled by 10^5 */ - /* 7. Compute the CCO igain and pgain */ - { - /* intermediate parameters */ - uint32_t kcco = (trimSteps[config.ccoRange] * margin[config.ccoRange]); - uint32_t ki_p = (uint32_t)CY_SYSLIB_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv); - - /* find the largest IGAIN value that is less than or equal to ki_p */ - uint32_t locigain = CY_SYSCLK_FLL_GAIN_VAL; - uint32_t locpgain = CY_SYSCLK_FLL_GAIN_VAL; - - /* find the largest IGAIN value that is less than or equal to ki_p */ - for(config.igain = CY_SYSCLK_FLL_GAIN_IDX; config.igain != 0UL; config.igain--) - { - if(locigain <= ki_p) - { - break; - } - locigain >>= 1U; - } - /* decrement igain if the WCO is the FLL source */ - if (wcoSource && (config.igain > 0U)) - { - config.igain--; - locigain >>= 1U; - } - - /* then find the largest PGAIN value that is less than or equal to ki_p - igain */ - for(config.pgain = CY_SYSCLK_FLL_GAIN_IDX; config.pgain != 0UL; config.pgain--) - { - if(locpgain <= (ki_p - locigain)) - { - break; - } - locpgain >>= 1U; - } - - /* decrement pgain if the WCO is the FLL source */ - if (wcoSource && (config.pgain > 0U)) - { - config.pgain--; - } - } - - /* 8. Compute the CCO_FREQ bits in CLK_FLL_CONFIG4 register */ - { - uint64_t cmp = CY_SYSLIB_DIV_ROUND(((TRIM_STEPS_SCALE / MARGIN_SCALE) * (uint64_t)ccoFreq), (uint64_t)margin[config.ccoRange]); - uint64_t mlt = TRIM_STEPS_SCALE + (uint64_t)trimSteps[config.ccoRange]; - uint64_t res = mlt; - - config.cco_Freq = 0U; - - while(res < cmp) - { - res *= mlt; - res /= TRIM_STEPS_SCALE; - config.cco_Freq++; - } - } - } - - /* 9. Compute the settling count, using a 1 usec settling time. Use a constant if the WCO is the FLL source */ - { - uint64_t fref = CY_SYSLIB_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv); - uint32_t divval = CY_SYSLIB_DIV_ROUNDUP(inputFreq, 1000000UL); - uint32_t altval = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)divval * fref, 6000000ULL) + 1UL; - - config.settlingCount = wcoSource ? 200U : (uint16_t) - ((outputFreq < fref) ? divval : - ((divval > altval) ? divval : altval)); - } - /* Configure FLL based on calculated values */ - retVal = Cy_SysClk_FllManualConfigure(&config); - } - else /* if not, bypass output mode */ - { - CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); - } - } - - return (retVal); -#else - return CY_SYSCLK_INVALID_STATE; -#endif -} - - -cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config) -{ -#if (CY_SRSS_FLL_PRESENT) - cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; - - /* Check for errors */ - CY_ASSERT_L1(config != NULL); - - if (!Cy_SysClk_FllIsEnabled()) /* If disabled */ - { - /* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */ - /* asserts just check for bitfield overflow */ - CY_ASSERT_L1(config->fllMult <= (SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk >> SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos)); - - SRSS_CLK_FLL_CONFIG = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult) | - _BOOL2FLD(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, config->enableOutputDiv); - - /* update CLK_FLL_CONFIG2 register with 2 parameters */ - /* asserts just check for bitfield overflow */ - CY_ASSERT_L1(config->refDiv <= (SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk >> SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos)); - CY_ASSERT_L1(config->lockTolerance <= (SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk >> SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos)); - - SRSS_CLK_FLL_CONFIG2 = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv) | - _VAL2FLD(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, config->lockTolerance); - - /* update CLK_FLL_CONFIG3 register with 4 parameters */ - /* asserts just check for bitfield overflow */ - CY_ASSERT_L1(config->igain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos)); - CY_ASSERT_L1(config->pgain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos)); - CY_ASSERT_L1(config->settlingCount <= (SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk >> SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos)); - - SRSS_CLK_FLL_CONFIG3 = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain) | - _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, config->pgain) | - _VAL2FLD(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, config->settlingCount) | - _VAL2FLD(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, config->outputMode); - - /* update CLK_FLL_CONFIG4 register with 1 parameter; preserve other bits */ - /* asserts just check for bitfield overflow */ - CY_ASSERT_L1(CY_SYSCLK_FLL_IS_CCO_RANGE_VALID(config->ccoRange)); - CY_ASSERT_L1(config->cco_Freq <= (SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos)); - - CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange)); - CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq)); - - retVal = CY_SYSCLK_SUCCESS; - } - - return (retVal); -#else - return CY_SYSCLK_INVALID_STATE; -#endif -} - - -void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config) -{ -#if (CY_SRSS_FLL_PRESENT) - CY_ASSERT_L1(config != NULL); - /* read 2 parameters from CLK_FLL_CONFIG register */ - uint32_t tempReg = SRSS_CLK_FLL_CONFIG; - config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg); - config->enableOutputDiv = _FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, tempReg); - /* read 2 parameters from CLK_FLL_CONFIG2 register */ - tempReg = SRSS_CLK_FLL_CONFIG2; - config->refDiv = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg); - config->lockTolerance = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, tempReg); - /* read 4 parameters from CLK_FLL_CONFIG3 register */ - tempReg = SRSS_CLK_FLL_CONFIG3; - config->igain = (uint8_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, tempReg); - config->pgain = (uint8_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, tempReg); - config->settlingCount = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, tempReg); - config->outputMode = (cy_en_fll_pll_output_mode_t)((uint32_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, tempReg)); - /* read 2 parameters from CLK_FLL_CONFIG4 register */ - tempReg = SRSS_CLK_FLL_CONFIG4; - config->ccoRange = (cy_en_fll_cco_ranges_t)((uint32_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_RANGE, tempReg)); - config->cco_Freq = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_FREQ, tempReg); -#endif -} - - -cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) -{ -#if (CY_SRSS_FLL_PRESENT) - bool zeroTimeout = (0UL == timeoutus); - - /* first set the CCO enable bit */ - SRSS_CLK_FLL_CONFIG4 |= SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; - - /* Wait until CCO is ready */ - for (; (!_FLD2BOOL(SRSS_CLK_FLL_STATUS_CCO_READY, SRSS_CLK_FLL_STATUS)) && /* if cco_ready == 0 */ - (0UL != timeoutus); - timeoutus--) - { - Cy_SysLib_DelayUs(1U); - } - - /* Set the FLL bypass mode to FLL_REF */ - CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); - - /* Set the FLL enable bit, if CCO is ready */ - if (zeroTimeout || (0UL != timeoutus)) - { - SRSS_CLK_FLL_CONFIG |= SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - } - - /* now do the timeout wait for FLL_STATUS, bit LOCKED */ - for (; (!Cy_SysClk_FllLocked()) && /* if locked == 0 */ - (0UL != timeoutus); - timeoutus--) - { - Cy_SysLib_DelayUs(1U); - } - - if (zeroTimeout || (0UL != timeoutus)) - { - /* Set the FLL bypass mode to FLL_OUT (ignoring lock indicator) */ - CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT); - } - else - { - /* If lock doesn't occur, FLL is stopped */ - (void)Cy_SysClk_FllDisable(); - } - - return ((zeroTimeout || (0UL != timeoutus)) ? CY_SYSCLK_SUCCESS : CY_SYSCLK_TIMEOUT); -#else - return CY_SYSCLK_INVALID_STATE; -#endif -} - - -/* ========================================================================== */ -/* =========================== PLL SECTION ============================ */ -/* ========================================================================== */ - -/* PLL OUTPUT_DIV bitfield allowable range */ -#define CY_SYSCLK_PLL_MIN_OUTPUT_DIV (2UL) -#define CY_SYSCLK_PLL_MAX_OUTPUT_DIV (16UL) - -/* PLL REFERENCE_DIV bitfield allowable range */ -#define CY_SYSCLK_PLL_MIN_REF_DIV (1UL) -#define CY_SYSCLK_PLL_MAX_REF_DIV (18UL) - -/* PLL FEEDBACK_DIV bitfield allowable ranges, LF and normal modes */ -#define CY_SYSCLK_PLL_MIN_FB_DIV_LF (19UL) -#define CY_SYSCLK_PLL_MAX_FB_DIV_LF (56UL) -#define CY_SYSCLK_PLL_MIN_FB_DIV_NORM (22UL) -#define CY_SYSCLK_PLL_MAX_FB_DIV_NORM (112UL) - -/* PLL FEEDBACK_DIV bitfield allowable range selection */ -#define CY_SYSCLK_PLL_MIN_FB_DIV ((config->lfMode) ? CY_SYSCLK_PLL_MIN_FB_DIV_LF : CY_SYSCLK_PLL_MIN_FB_DIV_NORM) -#define CY_SYSCLK_PLL_MAX_FB_DIV ((config->lfMode) ? CY_SYSCLK_PLL_MAX_FB_DIV_LF : CY_SYSCLK_PLL_MAX_FB_DIV_NORM) - -/* PLL Fvco range allowable ranges, LF and normal modes */ -#define CY_SYSCLK_PLL_MIN_FVCO_LF (170000000UL) -#define CY_SYSCLK_PLL_MAX_FVCO_LF (200000000UL) -#define CY_SYSCLK_PLL_MIN_FVCO_NORM (200000000UL) -#define CY_SYSCLK_PLL_MAX_FVCO_NORM (400000000UL) -/* PLL Fvco range selection */ -#define CY_SYSCLK_PLL_MIN_FVCO ((config->lfMode) ? CY_SYSCLK_PLL_MIN_FVCO_LF : CY_SYSCLK_PLL_MIN_FVCO_NORM) -#define CY_SYSCLK_PLL_MAX_FVCO ((config->lfMode) ? CY_SYSCLK_PLL_MAX_FVCO_LF : CY_SYSCLK_PLL_MAX_FVCO_NORM) - -/* PLL input and output frequency limits */ -#define CY_SYSCLK_PLL_MIN_IN_FREQ (4000000UL) -#define CY_SYSCLK_PLL_MAX_IN_FREQ (64000000UL) -#define CY_SYSCLK_PLL_MIN_OUT_FREQ (CY_SYSCLK_PLL_MIN_FVCO / CY_SYSCLK_PLL_MAX_OUTPUT_DIV) -#define CY_SYSCLK_PLL_MAX_OUT_FREQ (150000000UL) - - -bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) -{ -#if (CY_IP_MXS28SRSS) - CY_ASSERT_L1(clkPath < CY_SRSS_NUM_PLL); - return (_FLD2BOOL(CLK_LP_PLL_PLL28LP_STRUCT_CONFIG_PLL_ENABLE, SRSS_CLK_LP_PLL_CONFIG(clkPath))); -#else - return false; -#endif -} - - -bool Cy_SysClk_PllLocked(uint32_t clkPath) -{ - return false; -} - - -bool Cy_SysClk_PllLostLock(uint32_t clkPath) -{ - return false; -} - - -cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) -{ - return CY_SYSCLK_INVALID_STATE; -} - - -cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config) -{ - return CY_SYSCLK_INVALID_STATE; -} - - -cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config) -{ - return CY_SYSCLK_INVALID_STATE; -} - - -cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config) -{ - return CY_SYSCLK_INVALID_STATE; -} - - -cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) -{ -#if (CY_IP_MXS28SRSS) - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - bool nonZeroTimeout = (timeoutus != 0UL); - - if (clkPath < CY_SRSS_NUM_PLL) - { - /* Set the PLL BYPASS_SEL bits to PLL_OUT(0x3)*/ - SRSS_CLK_LP_PLL_CONFIG(clkPath) |= CLK_LP_PLL_PLL28LP_STRUCT_CONFIG_BYPASS_SEL_Msk; - - /* Set the PLL enable bit */ - SRSS_CLK_LP_PLL_CONFIG(clkPath) |= CLK_LP_PLL_PLL28LP_STRUCT_CONFIG_PLL_ENABLE_Msk; - - /* Set the OUTPU_DIV to 1, Need to be relooked */ - SRSS_CLK_LP_PLL_CONFIG4(clkPath) = _VAL2FLD(CLK_LP_PLL_PLL28LP_STRUCT_CONFIG4_OUTPUT_DIV, 1); - - /* now do the timeout wait for PLL_STATUS, bit LOCKED */ - for (; (0UL == (CLK_LP_PLL_PLL28LP_STRUCT_STATUS_LOCKED_Msk & SRSS_CLK_LP_PLL_CONFIG2(clkPath))) && - (0UL != timeoutus); - timeoutus--) - { - Cy_SysLib_DelayUs(1U); - } - retVal = ((nonZeroTimeout && (timeoutus == 0UL)) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); - } - return (retVal); -#else - return CY_SYSCLK_INVALID_STATE; -#endif - -} - -/* ========================================================================== */ -/* =========================== IHO SECTION ============================ */ -/* ========================================================================== */ - -#if defined (CY_IP_MXS40SSRSS) - -bool Cy_SysClk_IhoIsEnabled(void) -{ -#if (CY_SRSS_IHO_PRESENT) - return (_FLD2BOOL(SRSS_CLK_IHO_CONFIG_ENABLE, SRSS_CLK_IHO_CONFIG)); -#else - return false; -#endif -} - -void Cy_SysClk_IhoDisable(void) -{ -#if (CY_SRSS_IHO_PRESENT) - SRSS_CLK_IHO_CONFIG = 0UL; -#endif -} - -void Cy_SysClk_IhoEnable(void) -{ -#if (CY_SRSS_IHO_PRESENT) - SRSS_CLK_IHO_CONFIG |= SRSS_CLK_IHO_CONFIG_ENABLE_Msk; -#endif - -} -#endif -/* ========================================================================== */ -/* ==================== Clock Measurement section ===================== */ -/* ========================================================================== */ -/* Slow control register default value */ -#define TST_DDFT_SLOW_CTL_DEFAULT_VAL (0x00001F1FUL) - -/* Fast control register */ -#define TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40260104U) - -/* Slow control register default value */ -#define TST_DDFT_FAST_CTL_DEFAULT_VAL (0x00003D3DUL) - -/* Define for select signal outputs in slow clock */ -#define SRSS_CLK_OUTPUT_SLOW_MASK ((uint32_t) SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk | \ - SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk) - -/* Define for select signal outputs in fast clock */ -#define SRSS_CLK_OUTPUT_FAST_MASK ((uint32_t) SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk | \ - SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk | \ - SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk | \ - SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk | \ - SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk | \ - SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk) - -/* Cy_SysClk_StartClkMeasurementCounters() input parameter saved for use later in other functions */ -static uint32_t clk1Count1; - -/* These variables act as locks to prevent collisions between clock measurement and entry into - Deep Sleep mode. See Cy_SysClk_DeepSleep(). */ -static bool preventCounting = false; - - -bool Cy_SysClk_ClkMeasurementCountersDone(void) -{ - return (_FLD2BOOL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1)); -} - -cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2) -{ - cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; - - uint32_t clkOutputSlowVal = 0UL; - uint32_t clkOutputFastVal = 0UL; - - uint32_t clkOutputSlowMask = 0UL; - uint32_t clkOutputFastMask = 0UL; - - /* Prepare values for measurement control registers */ - - /* Connect the indicated clocks to the respective counters: - - if clock1 is a slow clock, - select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL0, and SRSS_CLK_OUTPUT_FAST.FAST_SEL0 = SLOW_SEL0 - else if clock1 is a fast clock, - select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL0, - else error, do nothing and return. - - if clock2 is a slow clock, - select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL1, and SRSS_CLK_OUTPUT_FAST.FAST_SEL1 = SLOW_SEL1 - else if clock2 is a fast clock, - select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL1, - else error, do nothing and return. - */ - if ((clock1 < CY_SYSCLK_MEAS_CLK_LAST_CLK) && (clock2 < CY_SYSCLK_MEAS_CLK_LAST_CLK) && - (count1 <= (SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk >> SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos))) - { - if (clock1 < CY_SYSCLK_MEAS_CLK_FAST_CLKS) - { /* slow clock */ - clkOutputSlowVal |= _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, (uint32_t)clock1); - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL0, 7UL/*slow_sel0 output*/); - - clkOutputSlowMask |= SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk; - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk; - } - else - { /* fast clock */ - if (clock1 < CY_SYSCLK_MEAS_CLK_PATH_CLKS) - { /* ECO, EXT, ALTHF */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL0, (uint32_t)clock1); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk; - } - else - { /* PATH or CLKHF */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL0, (((uint32_t)clock1 >> 8) & 0xFUL) /*use enum bits [11:8]*/); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk; - - if (clock1 < CY_SYSCLK_MEAS_CLK_CLKHFS) - { /* PATH select */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_PATH_SEL0, ((uint32_t)clock1 & 0xFUL) /*use enum bits [3:0]*/); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk; - } - else - { /* CLKHF select */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0, ((uint32_t)clock1 & 0xFUL) /*use enum bits [3:0]*/); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk; - } - } - } /* clock1 fast clock */ - - if (clock2 < CY_SYSCLK_MEAS_CLK_FAST_CLKS) - { /* slow clock */ - clkOutputSlowVal |= _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, (uint32_t)clock2); - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL1, 7UL/*slow_sel1 output*/); - - clkOutputSlowMask |= SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk; - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk; - } - else - { /* fast clock */ - if (clock2 < CY_SYSCLK_MEAS_CLK_PATH_CLKS) - { /* ECO, EXT, ALTHF */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL1, (uint32_t)clock2); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk; - } - else - { /* PATH or CLKHF */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_FAST_SEL1, (((uint32_t)clock2 >> 8) & 0xFUL) /*use enum bits [11:8]*/); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk; - - if (clock2 < CY_SYSCLK_MEAS_CLK_CLKHFS) - { /* PATH select */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_PATH_SEL1, ((uint32_t)clock2 & 0xFUL) /*use enum bits [3:0]*/); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk; - } - else - { /* CLKHF select */ - clkOutputFastVal |= _VAL2FLD(SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1, ((uint32_t)clock2 & 0xFUL) /*use enum bits [3:0]*/); - clkOutputFastMask |= SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk; - } - } - } /* clock2 fast clock */ - - if ((!preventCounting) /* don't start a measurement if about to enter Deep Sleep mode */ || - (_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1) != 0UL/*1 = done */)) - { - /* Set default values for counters measurement control registers */ - SRSS_TST_DDFT_SLOW_CTL_REG = TST_DDFT_SLOW_CTL_DEFAULT_VAL; - SRSS_TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_DEFAULT_VAL; - - SRSS_CLK_OUTPUT_SLOW = ((SRSS_CLK_OUTPUT_SLOW & ((uint32_t) ~clkOutputSlowMask)) | clkOutputSlowVal); - SRSS_CLK_OUTPUT_FAST = ((SRSS_CLK_OUTPUT_FAST & ((uint32_t) ~clkOutputFastMask)) | clkOutputFastVal); - - /* Save this input parameter for use later, in other functions. - No error checking is done on this parameter */ - clk1Count1 = count1; - - /* Counting starts when counter1 is written with a nonzero value */ - SRSS_CLK_CAL_CNT1 = clk1Count1; - - retVal = CY_SYSCLK_SUCCESS; - } - } - - return (retVal); -} - - -uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq) -{ - uint32_t retVal = 0UL; - bool isMeasurementValid = false; - - /* Check whether the device was in the Deep Sleep mode or the flash partially blocked while the - * operation was done - */ - if(SRSS_TST_DDFT_SLOW_CTL_REG == TST_DDFT_SLOW_CTL_DEFAULT_VAL) - { - if(SRSS_TST_DDFT_FAST_CTL_REG == TST_DDFT_FAST_CTL_DEFAULT_VAL) - { - isMeasurementValid = true; - } - } - - retVal = _FLD2VAL(SRSS_CLK_CAL_CNT2_CAL_COUNTER2, SRSS_CLK_CAL_CNT2); - - if (isMeasurementValid && (0UL != retVal)) - { - if (!measuredClock) - { /* clock1 is the measured clock */ - retVal = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)clk1Count1 * (uint64_t)refClkFreq, (uint64_t)retVal); - } - else - { /* clock2 is the measured clock */ - retVal = (uint32_t)CY_SYSLIB_DIV_ROUND((uint64_t)retVal * (uint64_t)refClkFreq, (uint64_t)clk1Count1); - } - } - else - { - /* Return zero value to indicate invalid measurement */ - retVal = 0UL; - } - - return (retVal); -} - - -/* ========================================================================== */ -/* ========================== TRIM SECTION ============================ */ -/* ========================================================================== */ - - -/** \cond INTERNAL */ -/* target frequency */ -#define CY_SYSCLK_ILO_TARGET_FREQ (32768UL) -/* Nominal trim step size is 1.5% of "the frequency". Using the target frequency */ -#define CY_SYSCLK_ILO_TRIM_STEP (CY_SYSLIB_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ * 15UL, 1000UL))//tbd -/** \endcond */ - -int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) -{ - return 0; -} - -/** \cond INTERNAL */ -#define CY_SYSCLK_PILO_TARGET_FREQ (32768UL) -/* nominal trim step size */ -#define CY_SYSCLK_PILO_TRIM_STEP (5UL)//tbd -/** \endcond */ - -int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) -{ - return 0; -} - -/* ========================================================================== */ -/* ====================== POWER MANAGEMENT SECTION ==================== */ -/* ========================================================================== */ - - -/** \cond INTERNAL */ -/* Timeout count for use in function Cy_SysClk_DeepSleepCallback() is sufficiently large for ~1 second */ -#define TIMEOUT (1000000UL) -/** \endcond */ - -cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode) -{ - cy_en_syspm_status_t retVal = CY_SYSPM_FAIL; - - return (retVal); -} - - -/* ========================================================================== */ -/* ========================= clkHf[n] SECTION ========================= */ -/* ========================================================================== */ - -/** \cond INTERNAL */ -uint32_t altHfFreq = 0UL; /* Internal storage for BLE ECO frequency user setting */ -/** \endcond */ - - -uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) -{ - /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */ - uint32_t pDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(clkHf); /* root prescaler (1/2/4/8) */ - uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */ - uint32_t freq = Cy_SysClk_ClkPathGetFrequency(path); - - /* Divide the path input frequency down and return the result */ - return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); -} - - -/* ========================================================================== */ -/* ===================== clk_peripherals SECTION ====================== */ -/* ========================================================================== */ - - -uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum) -{ - uint32_t integer = 0UL; /* Integer part of peripheral divider */ - uint32_t freq = Cy_SysClk_ClkPeriGetFrequency(); /* Get Peri frequency */ - - CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) || \ - ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) || \ - ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) || \ - ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR))); - - /* get the divider value for clk_peri to the selected peripheral clock */ - switch(dividerType) - { - case CY_SYSCLK_DIV_8_BIT: - case CY_SYSCLK_DIV_16_BIT: - integer = 1UL + Cy_SysClk_PeriphGetDivider(dividerType, dividerNum); - freq = CY_SYSLIB_DIV_ROUND(freq, integer); - break; - - case CY_SYSCLK_DIV_16_5_BIT: - case CY_SYSCLK_DIV_24_5_BIT: - { - uint32_t locFrac; - uint32_t locDiv; - uint64_t locFreq = freq * 32ULL; - Cy_SysClk_PeriphGetFracDivider(dividerType, dividerNum, &integer, &locFrac); - /* For fractional dividers, the divider is (int + 1) + frac/32 */ - locDiv = ((1UL + integer) * 32UL) + locFrac; - freq = (uint32_t) CY_SYSLIB_DIV_ROUND(locFreq, (uint64_t)locDiv); - } - break; - - default: - /* Unknown Divider */ - break; - } - - return (freq); -} - - -#endif -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_sysint_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_sysint_v2.c deleted file mode 100644 index fe81d2a718..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_sysint_v2.c +++ /dev/null @@ -1,160 +0,0 @@ -/***************************************************************************//** -* \file cy_sysint.c -* \version 1.0 -* -* \brief -* Provides an API implementation of the SysInt driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_M33SYSCPUSS) - -#include "cy_sysint.h" - -#if defined(__GNUC__) -typedef void(* __attribute__((interrupt)) exec_func_ptr)(void) ; /* typedef for the function pointers in the vector table */ -#elif (__CC_ARM) -typedef void(* exec_func_ptr)(void) __attribute__((interrupt)); /* typedef for the function pointers in the vector table */ -#else -typedef __irq void(* exec_func_ptr)(void); /* typedef for the function pointers in the vector table */ -#endif - -#ifdef CY_SECURE_WORLD -uint32_t *__s_vector_table_rw_ptr = (uint32_t*)&__s_vector_table_rw; -extern exec_func_ptr __s_vector_table[] ; /**< secure vector table in secure SRAM */ -#else -uint32_t *__ns_vector_table_rw_ptr = (uint32_t*)&__ns_vector_table_rw; -extern exec_func_ptr __ns_vector_table[] ; /**< Non-secure vector table in non-secure SRAM */ -#endif - - -void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc) - -{ - CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); - - MXCM33_CM33_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc; -} - - -IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum) - -{ - CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); - - return ((IRQn_Type)(MXCM33_CM33_NMI_CTL((uint32_t)nmiNum - 1UL))); -} - - -cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr) -{ - cy_en_sysint_status_t status = CY_SYSINT_SUCCESS; - - if(NULL != config) - { - CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); - - NVIC_SetPriority(config->intrSrc, config->intrPriority); -#ifdef CY_SECURE_WORLD - if (SCB->VTOR == (uint32_t)__s_vector_table) -#else - if (SCB->VTOR == (uint32_t)__ns_vector_table_rw_ptr) -#endif - { - (void)Cy_SysInt_SetVector(config->intrSrc, userIsr); - } - } - else - { - status = CY_SYSINT_BAD_PARAM; - } - - return(status); -} - - -cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) -{ - cy_israddress prevIsr; -#ifdef CY_SECURE_WORLD - uint32_t *ptr; - if (SCB->VTOR == (uint32_t)__s_vector_table) - { - CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr)); - prevIsr = (cy_israddress)__s_vector_table[CY_INT_IRQ_BASE + IRQn]; - ptr = (uint32_t*)&__s_vector_table[CY_INT_IRQ_BASE + IRQn]; - *ptr = (uint32_t) userIsr; - } -#else - if (SCB->VTOR == (uint32_t)__ns_vector_table_rw_ptr) - { - CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr)); - prevIsr = (cy_israddress)__ns_vector_table_rw_ptr[CY_INT_IRQ_BASE + IRQn]; - __ns_vector_table_rw_ptr[CY_INT_IRQ_BASE + IRQn] = (uint32_t)userIsr; - } -#endif - else - { - /* vector table is always loaded to non secure SRAM, so there is no need to return - the non-secure ROM vector */ - prevIsr = NULL; - } - - return (prevIsr); -} - - -cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn) -{ - cy_israddress currIsr; - -#ifdef CY_SECURE_WORLD - /* Return the SRAM ISR address only if it was moved to __ramVectors */ - if (SCB->VTOR == (uint32_t)__s_vector_table) - { - currIsr = (cy_israddress)__s_vector_table[CY_INT_IRQ_BASE + IRQn]; - } -#else - if (SCB->VTOR == (uint32_t)__ns_vector_table_rw_ptr) - { - currIsr = (cy_israddress)__ns_vector_table_rw_ptr[CY_INT_IRQ_BASE + IRQn]; - } -#endif - else - { - /* vector table is always loaded to non-secure SRAM, so there is no need to return - the non-secure ROM vector */ - currIsr = NULL; - } - - return (currIsr); -} - - -void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn) -{ - NVIC->STIR = (uint32_t)IRQn & CY_SYSINT_STIR_MASK; -} - - -#endif - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_syspm_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_syspm_v2.c deleted file mode 100644 index a2ebcdaa49..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_syspm_v2.c +++ /dev/null @@ -1,2463 +0,0 @@ -/***************************************************************************//** -* \file cy_syspm.c -* \version 4.20 -* -* This driver provides the source code for API power management. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXS28SRSS) - -#include "cy_syspm.h" - -//#include "cy_ipc_drv.h" -//#include "cy_ipc_sema.h" -//#include "cy_ipc_pipe.h" -//#include "cy_prot.h" - -/******************************************************************************* -* Internal Functions -*******************************************************************************/ -static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor); - -static void SetReadMarginTrimUlp(void); -static void SetReadMarginTrimLp(void); -static void SetWriteAssistTrimUlp(void); -static void SetWriteAssistTrimLp(void); -static bool IsVoltageChangePossible(void); - - -/******************************************************************************* -* Internal Defines -*******************************************************************************/ -#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - - /** The internal define for clock divider */ - #define SYSPM_CLK_DIVIDER (9U) - - /* Mask for the fast clock divider value */ - #define SYSPM_FAST_CLK_DIV_Msk (0xFF000000UL) - - /* Position for the fast clock divider value */ - #define SYSPM_FAST_CLK_DIV_Pos (24UL) - - /* Mask for the slow clock divider value */ - #define SYSPM_SLOW_CLK_DIV_Msk (0x00FF0000UL) - - /* Position for the slow clock divider value */ - #define SYSPM_SLOW_CLK_DIV_Pos (16UL) - - /* Mask for both slow and fast mask clock dividers */ - #define SYSPM_CLK_DIV_MASK (SYSPM_FAST_CLK_DIV_Msk | SYSPM_SLOW_CLK_DIV_Msk) - - #if (CY_CPU_CORTEX_M4) - #define CUR_CORE_DP_MASK (0x01UL) - #define OTHER_CORE_DP_MASK (0x02UL) - #else - #define CUR_CORE_DP_MASK (0x02UL) - #define OTHER_CORE_DP_MASK (0x01UL) - #endif - -#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ - -/* The define for the current active bus master */ -#if (CY_CPU_CORTEX_M0P) - #define ACTIVE_BUS_MASTER CPUSS_MS_ID_CM0 -#else - #define ACTIVE_BUS_MASTER CPUSS_MS_ID_CM4 -#endif /* (CY_CPU_CORTEX_M0P) */ - -#if 0 //TBD -/* Define of MMIO group where UDB is located */ -#define MMIO_UDB_GROUP_NR (4U) - -/* Define of MMIO group where UDB is located */ -#define MMIO_UDB_SLAVE_NR (3U) - -/* The UDB placement on MMIO slave level */ -#define PERI_UDB_SLAVE_ENABLED ((uint32_t) 1UL << MMIO_UDB_GROUP_NR) -#endif - -/* The definition for the delay of the LDO after its output -* voltage is changed -*/ -#define LDO_STABILIZATION_DELAY_US (9U) - -/* Define to indicate that a 10 us delay is needed */ -#define NEED_DELAY (0x0U) - -/* Slow output register */ -#define CLK_OUTPUT_SLOW_MASK (0x06U) - -/* Slow control register */ -#define TST_DDFT_FAST_CTL_MASK (62U) - -/* Load value for the timer to count delay after exiting Deep Sleep */ -#define IMO_10US_DELAY (68U) - -/* Define to indicate that a 10 us delay was done after exiting Deep Sleep */ -#define DELAY_DONE (0xAAAAAAAAU) - -/* Define for transitional 0.95 V for the LDO regulator */ -#define LDO_OUT_VOLTAGE_0_95V (0x0BU) - -/* Define for transitional 1.1 V for the LDO regulator */ -#define LDO_OUT_VOLTAGE_1_1V (0x17U) - -/* Define for transitional 1.15 V for the LDO regulator */ -#define LDO_OUT_VOLTAGE_1_15V (0x1BU) - -/* The definition for the delay of the Buck supply regulator -* stabilization after it is configured with enabled Buck output 1 */ -#define BUCK_INIT_STABILIZATION_US (900U) - -/* The definition for the delay of the Buck supply regulator -* stabilization after it is configured with enabled Buck -* output 2 only -*/ -#define BUCK_OUT2_INIT_DELAY_US (600U) - -/* The definition for the delay of the Buck regulator after its output -* voltage is changed -*/ -#define BUCK_OUT2_STABILIZATION_DELAY_US (200U) - -/* Define for transitional 0.95 V for buck regulator */ -#define BUCK_OUT1_VOLTAGE_0_95V (3U) - -/* Define for a Buck regulator stabilization delay from 0.9 V to 0.95 V */ -#define BUCK_OUT1_0_9V_TO_0_95V_DELAY_US (52U) - -/* Define for a Buck regulator stabilization delay from 0.95 V to 1.1 V */ -#define BUCK_OUT1_0_95V_TO_1_1V_DELAY_US (145U) - -/* Define for an LDO stabilization delay from 0.9 V to 0.95 V */ -#define LDO_0_9V_TO_0_95V_DELAY_US (3U) - -/* Define for an LDO regulator stabilization delay from 0.95 V to 1.1 V */ -#define LDO_0_95V_TO_1_1V_DELAY_US (7U) - -/* Define for ROM trim in LP mode */ -#define CPUSS_TRIM_ROM_LP (0x00000013U) - -/* Define for RAM trim in LP mode */ -#define CPUSS_TRIM_RAM_LP (0x00004013U) - -/* Define for ROM trim in ULP mode */ -#define CPUSS_TRIM_ROM_ULP (0x00000012U) - -/* Define for trim RAM in ULP mode */ -#define CPUSS_TRIM_RAM_ULP (0x00006012U) - -/* Define for IPC0 notification */ -//#define SYSPM_IPC_NOTIFY_STRUCT0 ((uint32_t) 0x1UL << CY_IPC_INTR_SYSCALL1) //TBD - -/* The define of bit positions of the syscall return status */ -#define SYSCALL_STATUS_MASK (0xFF000000U) - -/* The define for the success return status of the syscall */ -#define SYSCALL_STATUS_SUCCESS (0xA0000000U) - -/* The define for device TO *B Revision ID */ -#define SYSPM_DEVICE_PSOC6ABLE2_REV_0B (0x22U) - -/* The pointer to the Cy_EnterDeepSleep() function in the ROM */ -#define ROM_ENTER_DEEP_SLEEP_ADDR (*(uint32_t *) 0x00000D30UL) - -/* The define to call the ROM Cy_EnterDeepSleep() function. -* The ROM Cy_EnterDeepSleep() function prepares the system for the Deep Sleep -* and restores the system after wakeup from the Deep Sleep. */ -typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wasEventSent); - -#define EnterDeepSleepSrom(waitFor, wasEventSent) \ - ((cy_cb_syspm_deep_sleep_t) ROM_ENTER_DEEP_SLEEP_ADDR)((waitFor), &(wasEventSent)) - -/* Mask for the RAM read assist bits */ -#define CPUSS_TRIM_RAM_CTL_RA_MASK ((uint32_t) 0x3U << 8U) - -/* The define for SROM opcode to set the flash voltage bit */ -#define FLASH_VOLTAGE_BIT_ULP_OPCODE (0x0C000003U) - -/* The define for SROM opcode to clear the flash voltage bit */ -#define FLASH_VOLTAGE_BIT_LP_OPCODE (0x0C000001U) - -/* The define for SROM opcode to set the flash voltage bit */ -#define FLASH_VOLTAGE_BIT_ULP_PSOC6ABLE2_OPCODE (0x30000101U) - -/* The define for SROM to clear the flash voltage bit */ -#define FLASH_VOLTAGE_BIT_LP_PSOC6ABLE2_OPCODE (0x30000001U) - -/* The wait time for transition into the minimum regulator current mode -*/ -#define SET_MIN_CURRENT_MODE_DELAY_US (1U) - -/* The wait delay time that occurs before the active reference is settled. -* Intermediate delay is used in transition into the normal regulator current -* mode -*/ -#define ACT_REF_SETTLE_DELAY_US (8U) - -/* The wait delay time that occurs after the active reference is settled. -* Final delay is used in transition into the normal regulator current mode -*/ -#define SET_NORMAL_CURRENT_MODE_DELAY_US (1U) - -/* The internal define of the tries number in the -* Cy_SysPm_SystemSetMinRegulatorCurrent() function -*/ -#define WAIT_DELAY_TRYES (100U) - -/* The define of retained power mode of the CM4 */ -#define CM4_PWR_STS_RETAINED (2UL) - -/* The define for number of callback roots */ -#define CALLBACK_ROOT_NR (5U) - -/* Mask for checking the CM4 Deep Sleep status */ -#define CM4_DEEPSLEEP_MASK (CPUSS_CM4_STATUS_SLEEPING_Msk | CPUSS_CM4_STATUS_SLEEPDEEP_Msk) - -/* Mask for checking the CM0P Deep Sleep status */ -#define CM0_DEEPSLEEP_MASK (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk) - -/* The mask to unlock the Hibernate power mode */ -#define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos) - -/* The mask to set the Hibernate power mode */ -#define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\ - SRSS_PWR_HIBERNATE_FREEZE_Msk |\ - SRSS_PWR_HIBERNATE_HIBERNATE_Msk)) - -/* The mask to retain the Hibernate power mode status */ -#define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\ - SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\ - SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\ - SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\ - SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk)) - -/** The mask for the Hibernate wakeup sources */ -#define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\ - SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\ - SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\ - SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk)) - -/** The define to update the token to indicate the transition into Hibernate */ -#define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos) - - -/* The mask for low power modes the power circuits (POR/BOD, Bandgap reference, -* Reference buffer, Current reference) when active core regulator is LDO -*/ -//#define PWR_CIRCUITS_SET_LPMODE_LDO_MASK (SRSS_PWR_CTL_LINREG_LPMODE_Msk | PWR_CIRCUITS_SET_LPMODE_BUCK_MASK) //TBD - -/* The mask for low power modes the power circuits (POR/BOD, Bandgap reference, -* Reference buffer, Current reference) when active core regulator is Buck -*/ -#if 0 //TBD -#define PWR_CIRCUITS_SET_LPMODE_BUCK_MASK (SRSS_PWR_CTL_PORBOD_LPMODE_Msk |\ - SRSS_PWR_CTL_BGREF_LPMODE_Msk |\ - SRSS_PWR_CTL_VREFBUF_LPMODE_Msk |\ - SRSS_PWR_CTL_IREF_LPMODE_Msk) -#endif -/******************************************************************************* -* Internal Variables -*******************************************************************************/ - -/* Array of the callback roots */ -static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL}; - -/* The array of the pointers to failed callback */ -static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {NULL, NULL, NULL, NULL, NULL}; - -/* Structure for registers that should retain while Deep Sleep mode */ -//static cy_stc_syspm_backup_regs_t bkpRegs;//TBD - -#if (CY_CPU_CORTEX_M4) - /* Global boolean variable used to clear the Event Register of the CM4 core */ - static bool wasEventSent = false; -#endif /* (CY_CPU_CORTEX_M4) */ - - -uint32_t Cy_SysPm_ReadStatus(void) -{ - uint32_t pmStatus = 0UL; -#if 0 //TBD - /* Check whether CM4 is in Deep Sleep mode */ - if ((CPUSS_CM4_STATUS & CM4_DEEPSLEEP_MASK) == CM4_DEEPSLEEP_MASK) - { - pmStatus |= CY_SYSPM_STATUS_CM4_DEEPSLEEP; - } - /* Check whether CM4 is in Sleep mode */ - else if(0U != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS_CM4_STATUS)) - { - pmStatus |= CY_SYSPM_STATUS_CM4_SLEEP; - } - else - { - pmStatus |= CY_SYSPM_STATUS_CM4_ACTIVE; - } - - /* Check whether CM0p is in Deep Sleep mode */ - if ((CPUSS_CM0_STATUS & CM0_DEEPSLEEP_MASK) == CM0_DEEPSLEEP_MASK) - { - pmStatus |= CY_SYSPM_STATUS_CM0_DEEPSLEEP; - } - /* Check whether CM0p is in Sleep mode */ - else if (0U != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS_CM0_STATUS)) - { - pmStatus |= CY_SYSPM_STATUS_CM0_SLEEP; - } - else - { - pmStatus |= CY_SYSPM_STATUS_CM0_ACTIVE; - } -#endif - /* Check whether the device is in LP mode by reading - * the core voltage: - * - 0.9V (nominal) - System ULP mode - * - 1.1V (nominal) - System LP mode - */ - - /* Read current active regulator */ - if (Cy_SysPm_LdoIsEnabled()) - { - /* Current active regulator is LDO */ - if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_ULP) - { - pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP; - } - else - { - pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP; - } - } - else - { - /* Current active regulator is Buck */ - if (Cy_SysPm_BuckGetVoltage1() != CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP) - { - pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP; - } - else - { - pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP; - } - } - - return pmStatus; -} - - -cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) -{ - uint32_t interruptState; - uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP; - cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - - CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); - - /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ - if (pmCallbackRoot[cbSleepRootIdx] != NULL) - { - retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY); - } - - /* The CPU can switch into the Sleep power mode only when - * all executed registered callback functions with the CY_SYSPM_CHECK_READY - * parameter return CY_SYSPM_SUCCESS. - */ - if(retVal == CY_SYSPM_SUCCESS) - { - /* Call the registered callback functions with - * CY_SYSPM_BEFORE_TRANSITION parameter - */ - interruptState = Cy_SysLib_EnterCriticalSection(); - if (pmCallbackRoot[cbSleepRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION); - } - - /* The CPU enters the Sleep power mode upon execution of WFI/WFE */ - SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk; - - if(waitFor != CY_SYSPM_WAIT_FOR_EVENT) - { - __WFI(); - } - else - { - __WFE(); - #if 0 //TBD - #if (CY_CPU_CORTEX_M4) - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - /* For the CM4 CPU, the WFE instruction is called twice. - * The second WFE call clears the Event Register of CM4 CPU. - * Cypress ID #279077. - */ - if(wasEventSent) - { - __WFE(); - } - - wasEventSent = true; - } - #endif /* (CY_CPU_CORTEX_M4) */ - #endif - } - Cy_SysLib_ExitCriticalSection(interruptState); - - /* Call the registered callback functions with the - * CY_SYSPM_AFTER_TRANSITION parameter - */ - if (pmCallbackRoot[cbSleepRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION); - } - } - else - { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY - * parameter - */ - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL); - retVal = CY_SYSPM_FAIL; - } - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) -{ - uint32_t interruptState; - uint32_t cbDeepSleepRootIdx = (uint32_t) CY_SYSPM_DEEPSLEEP; - cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - - CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); - - /* Call the registered callback functions with the CY_SYSPM_CHECK_READY - * parameter - */ - if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) - { - retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_READY); - } - - /* The CPU can switch into the Deep Sleep power mode only when - * all executed registered callback functions with the CY_SYSPM_CHECK_READY - * parameter return CY_SYSPM_SUCCESS - */ - if (retVal == CY_SYSPM_SUCCESS) - { - /* System Deep Sleep indicator */ - bool wasSystemDeepSleep = false; - CY_UNUSED_PARAM(wasSystemDeepSleep); - - /* Call the registered callback functions with the - * CY_SYSPM_BEFORE_TRANSITION parameter - */ - interruptState = Cy_SysLib_EnterCriticalSection(); - if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_BEFORE_TRANSITION); - } -#if 0 //TBD - if (0U != cy_device->udbPresent) - { - /* Check whether the UDB disabled on MMIO level */ - if (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED)) - { - /* Save non-retained registers */ - Cy_SysPm_SaveRegisters(&bkpRegs); - } - } -#endif - /* Different device families and revisions have a different Deep Sleep entries */ - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) //TBD - { - /* The CPU enters Deep Sleep and wakes up in the RAM */ - wasSystemDeepSleep = EnterDeepSleepRam(waitFor); - } - else - { - #if 0 //TBD - #if (CY_CPU_CORTEX_M0P) - - /* Check if there is a pending syscall */ - if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false) - { - /* Do not put the CPU into Deep Sleep and return pending status */ - retVal = CY_SYSPM_SYSCALL_PENDING; - } - else - #endif /* (CY_CPU_CORTEX_M0P) */ - #endif - { - #if 0 //TBD - #if (CY_CPU_CORTEX_M4) - /* Repeat the WFI/WFE instruction if a wake up was not intended. - * Cypress ID #272909 - */ - do - { - #endif /* (CY_CPU_CORTEX_M4) */ - #endif - - /* The CPU enters Deep Sleep mode upon execution of WFI/WFE */ - SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk; - - if(waitFor != CY_SYSPM_WAIT_FOR_EVENT) - { - __WFI(); - } - else - { - __WFE(); - } - #if 0 //TBD - #if (CY_CPU_CORTEX_M4) - } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, CPUSS_CM4_PWR_CTL) == CM4_PWR_STS_RETAINED); - #endif /* (CY_CPU_CORTEX_M4) */ - #endif - } - } - -#if 0 //TBD - if (0U != cy_device->udbPresent) - { - /* Do not restore the UDBs if there was no system Deep Sleep mode or - * UDBs are disabled on MMIO level - */ - if (wasSystemDeepSleep && (0UL != (PERI_GR_SL_CTL(MMIO_UDB_SLAVE_NR) & PERI_UDB_SLAVE_ENABLED))) - { - cy_stc_syspm_backup_regs_t *ptrRegs; - - #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A) - { - ptrRegs = &bkpRegs; - } - else - #endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ - { - //ptrRegs = (cy_stc_syspm_backup_regs_t *) REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT));//TBD - } - - /* Restore non-retained registers */ - Cy_SysPm_RestoreRegisters(ptrRegs); - } - } -#endif - Cy_SysLib_ExitCriticalSection(interruptState); - } - - if (retVal == CY_SYSPM_SUCCESS) - { - /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION - * parameter - */ - if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_AFTER_TRANSITION); - } - } - else - { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY - * parameter - */ - if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_FAIL); - } - - /* Rewrite return value to indicate fail */ - if (retVal != CY_SYSPM_SYSCALL_PENDING) - { - retVal = CY_SYSPM_FAIL; - } - } - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) -{ - cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE; - /* Call the registered callback functions with the - * CY_SYSPM_CHECK_READY parameter - */ - if (pmCallbackRoot[cbHibernateRootIdx] != NULL) - { - retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY); - } - - /* The system can switch into Hibernate power mode only when - * all executed registered callback functions with CY_SYSPM_CHECK_READY - * parameter return CY_SYSPM_SUCCESS. - */ - if(retVal == CY_SYSPM_SUCCESS) - { - /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION - * parameter - */ - (void) Cy_SysLib_EnterCriticalSection(); - if (pmCallbackRoot[cbHibernateRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION); - } - - /* Preserve the token that will be retained through a wakeup sequence. - * This could be used by Cy_SysLib_GetResetReason() to differentiate - * Wakeup from a general reset event. - * Preserve the wakeup source(s) configuration. - */ - SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_WAKEUP_MASK) | HIBERNATE_TOKEN; - - /* Disable overriding by the peripherals the next pin-freeze command */ - SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; - - /* The second write causes freezing of I/O cells to save the I/O-cell state */ - SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; - - /* Third write cause system to enter Hibernate */ - SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; - - /* Read register to make sure it is settled */ - (void) SRSS_PWR_HIBERNATE; - - /* Wait for transition */ - __WFI(); - - /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION - * parameter in the Hibernate power mode are not applicable as system - * wake-up was made on system reboot. - */ - - /* A wakeup from Hibernate is performed by toggling of the wakeup - * pins, or WDT matches, or Backup domain alarm expires. This depends on - * what item is configured in the Hibernate register. After a wakeup - * event, a normal Boot procedure occurs. - * There is no need to exit from the critical section. - */ - } - else - { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY - * parameter. The return value should be CY_SYSPM_SUCCESS. - */ - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL); - retVal = CY_SYSPM_FAIL; - } - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) -{ - uint32_t interruptState; - uint32_t cbLpRootIdx = (uint32_t) CY_SYSPM_LP; - cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - - /* Call the registered callback functions with the - * CY_SYSPM_CHECK_READY parameter - */ - if (pmCallbackRoot[cbLpRootIdx] != NULL) - { - retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_READY); - } - - /* The system can switch into LP only when - * all executed registered callback functions with the - * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS - */ - if (retVal == CY_SYSPM_SUCCESS) - { - - /* Call the registered callback functions with the - * CY_SYSPM_BEFORE_TRANSITION parameter - */ - interruptState = Cy_SysLib_EnterCriticalSection(); - if (pmCallbackRoot[cbLpRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_BEFORE_TRANSITION); - } - - /* Read current active regulator and set LP voltage */ - if (Cy_SysPm_LdoIsEnabled()) - { - /* Current active regulator is LDO */ - if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_LP) - { - retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - } - } - else - { - /* Current active regulator is Buck */ - if (Cy_SysPm_BuckGetVoltage1() != CY_SYSPM_BUCK_OUT1_VOLTAGE_LP) - { - retVal = Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - } - } - - Cy_SysLib_ExitCriticalSection(interruptState); - - /* Call the registered callback functions with the - * CY_SYSPM_AFTER_TRANSITION parameter - */ - if (pmCallbackRoot[cbLpRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_AFTER_TRANSITION); - } - } - else - { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY - * parameter - */ - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_FAIL); - retVal = CY_SYSPM_FAIL; - } - - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) -{ - uint32_t interruptState; - cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_ULP; - - /* Call the registered callback functions with the - * CY_SYSPM_CHECK_READY parameter - */ - if (pmCallbackRoot[cbUlpRootIdx] != NULL) - { - retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_READY); - } - - /* The system can switch into the ULP only when - * all executed registered callback functions with the - * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS - */ - if (retVal == CY_SYSPM_SUCCESS) - { - /* Call the registered callback functions with the - * CY_SYSPM_BEFORE_TRANSITION parameter - */ - interruptState = Cy_SysLib_EnterCriticalSection(); - if (pmCallbackRoot[cbUlpRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_BEFORE_TRANSITION); - } - - /* Read current active regulator and set ULP voltage */ - if (Cy_SysPm_LdoIsEnabled()) - { - /* Current active regulator is LDO */ - if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_ULP) - { - retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_ULP); - } - } - else - { - /* Current active regulator is Buck */ - if (Cy_SysPm_BuckGetVoltage1() != CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP) - { - retVal = Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP); - } - } - - Cy_SysLib_ExitCriticalSection(interruptState); - - /* Call the registered callback functions with the - * CY_SYSPM_AFTER_TRANSITION parameter - */ - if (pmCallbackRoot[cbUlpRootIdx] != NULL) - { - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_AFTER_TRANSITION); - } - } - else - { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY - * parameter - */ - (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_FAIL); - retVal = CY_SYSPM_FAIL; - } - - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) -{ - cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED; - - /* Check are the power circuits are ready to enter into regulator minimum - * current mode - */ - if (0U != _FLD2VAL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)) - { - /* Configure the minimum current mode for LDO regulator */ - if(Cy_SysPm_LdoIsEnabled()) - { - //SRSS_PWR_CTL |= PWR_CIRCUITS_SET_LPMODE_LDO_MASK; //TBD - } - else - { - /* Configure the minimum current mode for Buck regulator */ - //SRSS_PWR_CTL |= PWR_CIRCUITS_SET_LPMODE_BUCK_MASK; //TBD - } - - /* This wait time allows the circuits to remove their dependence on - * the Active mode circuits, such as active Reference - */ - Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US); - - /* Disable active reference */ - // SRSS_PWR_CTL |= SRSS_PWR_CTL_ACT_REF_DIS_Msk; //TBD - - retVal = CY_SYSPM_SUCCESS; - } - - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void) -{ - uint32_t timeOut = WAIT_DELAY_TRYES; - cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT; - - /* Configure the regulator normal current mode for the POR/BOD circuits - * and for the Bandgap Voltage and Current References - */ - if (Cy_SysPm_LdoIsEnabled()) - { - //SRSS_PWR_CTL &= (uint32_t) ~CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK;//TBD - } - else - { - // SRSS_PWR_CTL &= (uint32_t) ~CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK; //TBD - } - - /* This wait time allows setting active Reference */ - Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US); -#if 0 //TBD - while ((0U == _FLD2VAL(SRSS_PWR_CTL_ACT_REF_OK, SRSS_PWR_CTL)) && (0U != timeOut)) - { - timeOut--; - } -#endif - if (0U != timeOut) - { - /* Disable the low-power for Bandgap reference circuit */ - //SRSS_PWR_CTL &= (uint32_t) ~SRSS_PWR_CTL_BGREF_LPMODE_Msk;//TBD - - /* Delay to finally set the normal current mode */ - Cy_SysLib_DelayUs(SET_NORMAL_CURRENT_MODE_DELAY_US); - - retVal= CY_SYSPM_SUCCESS; - } - - return retVal; -} - - -void Cy_SysPm_CpuSleepOnExit(bool enable) -{ - if(enable) - { - /* Enable sleep-on-exit feature */ - SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk; - } - else - { - /* Disable sleep-on-exit feature */ - SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk); - } -} - - -void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) -{ - CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); - - uint32_t polarityMask = 0U; - - if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource)) - { - /* Reconfigure the wakeup pins and LPComp polarity based on the input */ - if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK)) - { - polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK; - } - - if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK)) - { - polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK; - } - - if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN0_MASK)) - { - polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK; - } - - if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN1_MASK)) - { - polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK; - } - } - - SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) | wakeupSource; - - /* Read register to make sure it is settled */ - (void) SRSS_PWR_HIBERNATE; -} - - -void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) -{ - CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); - - uint32_t clearWakeupSourceMask = wakeupSource & (uint32_t) ~SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk; - - if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource)) - { - /* Clear the high active level of the requested sources */ - if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)) - { - clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK; - } - - if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)) - { - clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK; - } - - if ((uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH)) - { - clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK; - } - - if ((uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH)) - { - clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK; - } - } - - SRSS_PWR_HIBERNATE &= (uint32_t) ~clearWakeupSourceMask; - - /* Read register to make sure it is settled */ - (void) SRSS_PWR_HIBERNATE; -} - - -cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) -{ - CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage)); - - cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE; - - /* Enable the Buck regulator only if it was not enabled previously. - * If the LDO is disabled, the device is sourced by the Buck regulator - */ - if (Cy_SysPm_LdoIsEnabled()) - { - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - - /* Update the RAM and ROM trim values when final target Buck 0.9 V */ - if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage) - { - if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_0_9V) - { - retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_0_9V); - } - else - { - retVal = CY_SYSPM_SUCCESS; - } - - if (CY_SYSPM_SUCCESS == retVal) - { - #if 0 //TBD - /* Increase LDO output voltage to 0.95 V nominal */ - SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), - SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V); - #endif - } - } - - /* Update the RAM and ROM trim values when the final target Buck 1.1 V */ - if (CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V == voltage) - { - if (Cy_SysPm_LdoGetVoltage() != CY_SYSPM_LDO_VOLTAGE_1_1V) - { - retVal = Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_1_1V); - } - else - { - retVal = CY_SYSPM_SUCCESS; - } - - if (CY_SYSPM_SUCCESS == retVal) - { - #if 0 //TBD - /* Set the LDO 1.15 V as final Buck output is 1.1 V */ - SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), - SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_1_15V); - #endif - } - } - - /* Proceed only if previous settings were done successfully */ - if (CY_SYSPM_SUCCESS == retVal) - { - /* A delay for the supply to stabilize at the new voltage */ - Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US); -#if 0 //TBD - /* Disable the Deep Sleep, nWell, and Retention regulators */ - SRSS_PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) | - _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1U) | - _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1U)); -#endif -#if 0 //TBD - /* Configure the Buck regulator */ - SRSS_PWR_BUCK_CTL = - _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); - - SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U); - - SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, 1U); -#endif - - /* Wait until Buck output 1 is stable */ - Cy_SysLib_DelayUs(BUCK_INIT_STABILIZATION_US); -#if 0 //TBD - /* Disable the LDO, because Vbuckout1 and LDO are shorted */ - SRSS_PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U); -#endif - } - - Cy_SysLib_ExitCriticalSection(interruptState); - } - else - { - /* The Buck is already enabled, so just update the Buck voltage */ - cy_en_syspm_buck_voltage1_t curBuckVoltage = Cy_SysPm_BuckGetVoltage1(); - - if (voltage != curBuckVoltage) - { - retVal = Cy_SysPm_BuckSetVoltage1(voltage); - } - else - { - retVal = CY_SYSPM_SUCCESS; - } - } - - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage) -{ - CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage)); - - cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE; - - - /* Change the voltage only if protection context is set to zero (PC = 0) - * or the device revision supports modifying registers via syscall - */ - if (IsVoltageChangePossible()) - { - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - - if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage) - { - /* Set bit of the flash voltage control register before ULP mode is set */ - retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_ULP); - - if (CY_SYSPM_SUCCESS == retVal) - { - /* Update read-write margin value for the ULP mode */ - SetReadMarginTrimUlp(); - } - } - else - { -#if 0 //TBD - /* Increase Buck output voltage to 0.95 V nominal */ - SRSS_PWR_BUCK_CTL = - _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V); -#endif - /* Wait until regulator is stable on higher intermediate voltage */ - Cy_SysLib_DelayUs(BUCK_OUT1_0_9V_TO_0_95V_DELAY_US); - - /* Update write assist value for the LP mode */ - SetWriteAssistTrimLp(); - - retVal = CY_SYSPM_SUCCESS; - } - - /* Proceed only if previous settings were done successfully */ - if (CY_SYSPM_SUCCESS == retVal) - { - /* The system may continue operating while the voltage on Vccd - * discharges to the new voltage. The time it takes to reach the - * new voltage depends on the conditions, including the load current - * on Vccd and the external capacitor size. - */ -#if 0 //TBD - SRSS_PWR_BUCK_CTL = - _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); -#endif - - if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage) - { - /* Update write assist value for the ULP mode */ - SetWriteAssistTrimUlp(); - } - else - { - /* Delay stabilizing at the new voltage is required only - * when changing from a lower voltage to a higher voltage - */ - Cy_SysLib_DelayUs(BUCK_OUT1_0_95V_TO_1_1V_DELAY_US); - - /* Update read-write margin value for the LP mode */ - SetReadMarginTrimLp(); - - /* Clear bit of the flash voltage control register after - * the LP mode is set - */ - retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_LP); - } - } - - Cy_SysLib_ExitCriticalSection(interruptState); - } - - return retVal; -} - - -bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) -{ - CY_ASSERT_L3(CY_SYSPM_IS_BUCK_OUTPUT_VALID(output)); - - bool retVal = false; - - if (output == CY_SYSPM_BUCK_VBUCK_1) - { - #if 0 //TBD - retVal = (_FLD2BOOL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, SRSS_PWR_BUCK_CTL)); - #endif - } - - /* Return false if device does not have the second Buck output (SIMO) */ -#if 0 //TBD - if (0U != cy_device->sysPmSimoPresent) //TBD - { - if(output == CY_SYSPM_BUCK_VRF) - { - #if 0 //TBD - retVal = ((0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS_PWR_BUCK_CTL2)) || - (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, SRSS_PWR_BUCK_CTL2))); - #endif - } - } -#endif - return(retVal); -} - - -void Cy_SysPm_BuckEnableVoltage2(void) -{ - /* Do nothing if device does not have the second Buck output (SIMO) */ -#if 0 //TBD - if (0U != cy_device->sysPmSimoPresent) - { - if (!Cy_SysPm_BuckIsEnabled()) - { - #if 0 //TBD - /* Enable the SIMO Buck regulator */ - SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U); - #endif - } - - /* Enable the SIMO Buck output 2 */ - //SRSS_PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U); //TBD - - /* Wait until the output is stable */ - Cy_SysLib_DelayUs(BUCK_OUT2_INIT_DELAY_US); - } -#endif -} - - -void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle) -{ -#if 0 //TBD - /* Do nothing if device does not have the second Buck output (SIMO) */ - if (0U != cy_device->sysPmSimoPresent) - { - uint32_t curVoltage; - - CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage)); - - /* Get the current voltage */ - curVoltage = (uint32_t) Cy_SysPm_BuckGetVoltage2(); - - if ((uint32_t) voltage != curVoltage) - { - #if 0 //TBD - SRSS_PWR_BUCK_CTL2 = - _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL2), SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, (uint32_t) voltage); - #endif - - /* Delay stabilizing at the new voltage is required only - * when changing from a lower voltage to a higher voltage. - */ - if(waitToSettle && ((uint32_t) voltage > curVoltage)) - { - Cy_SysLib_DelayUs(BUCK_OUT2_STABILIZATION_DELAY_US); - } - } - } -#endif -} - - -cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) -{ - CY_ASSERT_L3(CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage)); - - cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE; - - /* Change the voltage only if protection context is set to zero (PC = 0), - * or the device revision supports modifying registers via syscall - */ - if (IsVoltageChangePossible()) - { - uint32_t interruptState; - //uint32_t trimVoltage; //TBD - - interruptState = Cy_SysLib_EnterCriticalSection(); - - if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage) - { - /* Remove additional wakeup delay from Deep Sleep - * for 1.1 V LDO. Cypress ID #290172 - */ - //SRSS_PWR_TRIM_WAKE_CTL = 0UL; //TBD - - // trimVoltage = SFLASH_LDO_0P9V_TRIM;//TBD - - /* Set bit of the flash voltage control register before the ULP is set */ - retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_ULP); - - if (CY_SYSPM_SUCCESS == retVal) - { - /* Update read-write margin value for the ULP mode */ - SetReadMarginTrimUlp(); - } - } - else - { - /* Configure additional wakeup delay from Deep Sleep - * for 1.1 V LDO. Cypress ID #290172 - */ - //SRSS_PWR_TRIM_WAKE_CTL = SFLASH_PWR_TRIM_WAKE_CTL; //TBD - - // trimVoltage = SFLASH_LDO_1P1V_TRIM;//TBD -#if 0 //TBD - SRSS_PWR_TRIM_PWRSYS_CTL = - _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V); -#endif - /* A delay for the supply to stabilize at the new higher voltage */ - Cy_SysLib_DelayUs(LDO_0_9V_TO_0_95V_DELAY_US); - - /* Update write assist value for the LP mode */ - SetWriteAssistTrimLp(); - - retVal = CY_SYSPM_SUCCESS; - } - - if (CY_SYSPM_SUCCESS == retVal) - { - /* The system may continue operating while the voltage on Vccd - * discharges to the new voltage. The time it takes to reach the - * new voltage depends on the conditions, including the load current - * on Vccd and the external capacitor size. - */ - #if 0 //TBD - SRSS_PWR_TRIM_PWRSYS_CTL = - _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, trimVoltage); - #endif - - if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage) - { - /* Update write assist value for the ULP mode */ - SetWriteAssistTrimUlp(); - } - else - { - /* A delay for the supply to stabilize at the new intermediate voltage */ - Cy_SysLib_DelayUs(LDO_0_95V_TO_1_1V_DELAY_US); - - /* Update read-write margin value for the LP mode */ - SetReadMarginTrimLp(); - - /* Clear bit of the flash voltage control register after - * the LP mode is set - */ - retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_LP); - } - } - - Cy_SysLib_ExitCriticalSection(interruptState); - } - - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode) -{ - CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode)); - - cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED; - - switch (mode) - { - case CY_SYSPM_LDO_MODE_NORMAL: - { - retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent(); - } - break; - - case CY_SYSPM_LDO_MODE_MIN: - { - retVal = Cy_SysPm_SystemSetMinRegulatorCurrent(); - } - break; - - case CY_SYSPM_LDO_MODE_DISABLED: - { - #if 0 //TBD - /* Disable the LDO, Deep Sleep, nWell, and Retention regulators */ - SRSS_PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) | - _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1U) | - _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1U) | - _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U)); - #endif - - retVal = CY_SYSPM_SUCCESS; - } - break; - - default: - retVal = CY_SYSPM_FAIL; - break; - } - - return retVal; -} - - -cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void) -{ - cy_en_syspm_ldo_mode_t retVal; - - if (!Cy_SysPm_LdoIsEnabled()) - { - retVal = CY_SYSPM_LDO_MODE_DISABLED; - } - else if (Cy_SysPm_SystemIsMinRegulatorCurrentSet()) - { - retVal = CY_SYSPM_LDO_MODE_MIN; - } - else - { - retVal = CY_SYSPM_LDO_MODE_NORMAL; - } - - return retVal; -} - - -bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler) -{ - bool retVal = false; - - /* Verify the input parameters. */ - if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL)) - { - uint32_t callbackRootIdx = (uint32_t) handler->type; - - /* If the callback list is not empty. */ - if (pmCallbackRoot[callbackRootIdx] != NULL) - { - cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx]; - cy_stc_syspm_callback_t* insertPos = curCallback; - - /* Find the callback after which the new callback is to be - * inserted. Ensure the given callback has not been registered. - */ - while ((NULL != curCallback->nextItm) && (curCallback != handler)) - { - curCallback = curCallback->nextItm; - /* Callbacks with the same order value are stored in the order - * they are registered. - */ - if (curCallback->order <= handler->order) - { - insertPos = curCallback; - } - } - /* If the callback has not been registered. */ - if (curCallback != handler) - { - /* If the callback is to be inserted at the beginning of the list. */ - if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order)) - { - handler->nextItm = insertPos; - handler->prevItm = NULL; - handler->nextItm->prevItm = handler; - pmCallbackRoot[callbackRootIdx] = handler; - } - else - { - handler->nextItm = insertPos->nextItm; - handler->prevItm = insertPos; - - /* If the callback is not inserted at the end of the list. */ - if (handler->nextItm != NULL) - { - handler->nextItm->prevItm = handler; - } - insertPos->nextItm = handler; - } - retVal = true; - } - } - else - { - /* The callback list is empty. */ - pmCallbackRoot[callbackRootIdx] = handler; - handler->nextItm = NULL; - handler->prevItm = NULL; - retVal = true; - } - } - return retVal; -} - - -bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) -{ - bool retVal = false; - - if (handler != NULL) - { - uint32_t callbackRootIdx = (uint32_t) handler->type; - cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx]; - - /* Search requested callback item in the linked list */ - while (curCallback != NULL) - { - /* Requested callback is found */ - if (curCallback == handler) - { - retVal = true; - break; - } - - /* Go to next callback item in the linked list */ - curCallback = curCallback->nextItm; - } - - if (retVal) - { - /* Requested callback is first in the list */ - if (pmCallbackRoot[callbackRootIdx] == handler) - { - /* Check whether this the only callback registered */ - if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL) - { - pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm; - pmCallbackRoot[callbackRootIdx]->prevItm = NULL; - } - else - { - /* We had only one callback */ - pmCallbackRoot[callbackRootIdx] = NULL; - } - } - else - { - /* Update links of related to unregistered callback items */ - curCallback->prevItm->nextItm = curCallback->nextItm; - - if (curCallback->nextItm != NULL) - { - curCallback->nextItm->prevItm = curCallback->prevItm; - } - } - } - } - - return retVal; -} - - -cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode) -{ - CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type)); - CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode)); - - static cy_stc_syspm_callback_t* lastExecutedCallback = NULL; - cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type]; - cy_stc_syspm_callback_params_t curParams; - - if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY)) - { - /* Execute registered callbacks with order from first registered to the - * last registered. Stop executing if CY_SYSPM_FAIL was returned in - * CY_SYSPM_CHECK_READY mode - */ - while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY))) - { - /* The modes defined in the .skipMode element are not executed */ - if (0UL == ((uint32_t) mode & curCallback->skipMode)) - { - /* Update elements for local callback parameter values */ - curParams.base = curCallback->callbackParams->base; - curParams.context = curCallback->callbackParams->context; - - retVal = curCallback->callback(&curParams, mode); - - /* Update callback pointer with value of executed callback. - * Such update is required to execute further callbacks in - * backward order after exit from LP mode or to undo - * configuration after callback returned fail: from last called - * to first registered. - */ - lastExecutedCallback = curCallback; - } - curCallback = curCallback->nextItm; - } - - if (mode == CY_SYSPM_CHECK_READY) - { - /* Update the pointer to the failed callback with the result of the callback execution. - * If the callback fails, the value of the pointer will be updated - * with the address of the callback which returned CY_SYSPM_FAIL, else, - * it will be updated with NULL. - */ - if(retVal == CY_SYSPM_FAIL) - { - failedCallback[(uint32_t) type] = lastExecutedCallback; - } - else - { - failedCallback[(uint32_t) type] = NULL; - } - } - } - else - { - /* Execute registered callbacks with order from lastCallback or last - * executed to the first registered callback. Such a flow is required if - * a previous callback function returned CY_SYSPM_FAIL or a previous - * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is - * required to undo configurations in correct backward order. - */ - if (mode != CY_SYSPM_CHECK_FAIL) - { - while (curCallback->nextItm != NULL) - { - curCallback = curCallback->nextItm; - } - } - else - { - /* Skip last executed callback that returns CY_SYSPM_FAIL, as this - * callback already knows that it failed. - */ - curCallback = lastExecutedCallback; - - if (curCallback != NULL) - { - curCallback = curCallback->prevItm; - } - } - - /* Execute callback functions with required type and mode */ - while (curCallback != NULL) - { - /* The modes defined in the .skipMode element are not executed */ - if (0UL == ((uint32_t) mode & curCallback->skipMode)) - { - /* Update elements for local callback parameter values */ - curParams.base = curCallback->callbackParams->base; - curParams.context = curCallback->callbackParams->context; - - retVal = curCallback->callback(&curParams, mode); - } - curCallback = curCallback->prevItm; - } - } - - return retVal; -} - - -cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type) -{ - return failedCallback[(uint32_t) type]; -} - - -void Cy_SysPm_IoUnfreeze(void) -{ - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - - /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O: - * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0 - */ - SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL; - - /* Lock the Hibernate mode: - * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0 - */ - SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK; - - /* Read register to make sure it is settled */ - (void) SRSS_PWR_HIBERNATE; - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_bit_t value) -{ - CY_ASSERT_L3(CY_SYSPM_IS_BIT_FOR_FLASH_VALID(value)); - - cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED; - - uint16_t curDeviceRevision = Cy_SysLib_GetDeviceRevision(); - uint16_t curDevice = Cy_SysLib_GetDevice(); -#if 0 //TBD - /* Check the current protection context value. We can have a direct register - * update if protection context is = 0 */ - if ((Cy_Prot_GetActivePC(ACTIVE_BUS_MASTER) == 0U) && (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) && - (curDeviceRevision <= SYSPM_DEVICE_PSOC6ABLE2_REV_0B)) - { - FLASHC_FM_CTL_ANA_CTL0 = - _CLR_SET_FLD32U((FLASHC_FM_CTL_ANA_CTL0), FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, value); - - retVal = CY_SYSPM_SUCCESS; - } -#endif - /* Update the flash voltage bit using a syscall. This can be done on devices - * that support modifying registers via syscall. - */ - if (((curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) && (curDeviceRevision > SYSPM_DEVICE_PSOC6ABLE2_REV_0B)) || - (curDevice != CY_SYSLIB_DEVICE_PSOC6ABLE2)) - { - // uint32_t syscallCode; //TBD - //IPC_STRUCT_Type *ipcSyscallBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL);//TBD - - /* Set required syscall code */ - if (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - #if 0 //TBD - syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ? - FLASH_VOLTAGE_BIT_ULP_PSOC6ABLE2_OPCODE : FLASH_VOLTAGE_BIT_LP_PSOC6ABLE2_OPCODE; - #endif - } - else - { - #if 0 //TBD - syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ? - FLASH_VOLTAGE_BIT_ULP_OPCODE : FLASH_VOLTAGE_BIT_LP_OPCODE; - #endif - } - #if 0 //TBD - /* Tries to acquire the IPC structure and pass the arguments to SROM API */ - if (Cy_IPC_Drv_SendMsgWord(ipcSyscallBase, SYSPM_IPC_NOTIFY_STRUCT0, syscallCode) == CY_IPC_DRV_SUCCESS) - { - /* Checks whether the IPC structure is not locked */ - while (Cy_IPC_Drv_IsLockAcquired(ipcSyscallBase)) - { - /* Polls whether the IPC is released */ - } - - /* Check the return status of a syscall */ - uint32_t syscallStatus = Cy_IPC_Drv_ReadDataValue(ipcSyscallBase); - - if (SYSCALL_STATUS_SUCCESS == (syscallStatus & SYSCALL_STATUS_MASK)) - { - retVal = CY_SYSPM_SUCCESS; - } - } - #endif - } - - return retVal; -} - - -void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) -{ - CY_ASSERT_L1(NULL != regs); -#if 0 //TBD - /* Save the registers before Deep Sleep */ - regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG = UDB_UDBIF_BANK_CTL; - - regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG = UDB_BCTL_MDCLK_EN; - regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG = UDB_BCTL_MBCLK_EN; - regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG = UDB_BCTL_BOTSEL_L; - regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG = UDB_BCTL_BOTSEL_U; - regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG = UDB_BCTL_QCLK_EN_0; - regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG = UDB_BCTL_QCLK_EN_1; - regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG = UDB_BCTL_QCLK_EN_2; -#endif -} - - -void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) -{ - CY_ASSERT_L1(NULL != regs); -#if 0 //TBD - /* Restore the registers after Deep Sleep */ - UDB_BCTL_MDCLK_EN = regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG; - UDB_BCTL_MBCLK_EN = regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG; - UDB_BCTL_BOTSEL_L = regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG; - UDB_BCTL_BOTSEL_U = regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG; - UDB_BCTL_QCLK_EN_0 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG; - UDB_BCTL_QCLK_EN_1 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN1_REG; - UDB_BCTL_QCLK_EN_2 = regs->CY_SYSPM_UDB_BCTL_QCLK_EN2_REG; - - UDB_UDBIF_BANK_CTL = regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG; -#endif -} - - -/******************************************************************************* -* Function Name: EnterDeepSleepRam -****************************************************************************//** -* -* The internal function that prepares the system for Deep Sleep and -* restores the system after a wakeup from Deep Sleep. -* -* \param waitFor -* Selects wait for action. See \ref cy_en_syspm_waitfor_t. -* -* \return -* - true - System Deep Sleep was occurred. -* - false - System Deep Sleep was not occurred. -* -*******************************************************************************/ -#if defined (__ICCARM__) - #pragma diag_suppress=Ta023 - __ramfunc -#else - CY_SECTION(".cy_ramfunc") CY_NOINLINE -#endif -static bool EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) -{ - /* Store the address of the Deep Sleep indicator into the RAM */ - //volatile uint32_t *delayDoneFlag = &FLASHC_BIST_DATA_0; - - /* Indicator of System Deep Sleep mode */ - bool retVal = false; - #if 0 //TBD - /* Acquire the IPC to prevent changing of the shared resources at the same time */ - while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) - { - /* Wait until the IPC structure is released by another CPU */ - } - #endif -#if 0 //TBD -#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A) - { - /* Set the flag that the current CPU entered Deep Sleep */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) |= CUR_CORE_DP_MASK; - - /* Change the slow and fast clock dividers only under the condition that - * the other CPU is already in Deep Sleep. Cypress ID #284516 - */ - if (0U != (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & OTHER_CORE_DP_MASK)) - { - /* Get the divider values of the slow and high clocks and store them into - * the IPC data register - */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = - (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & ((uint32_t) ~(SYSPM_CLK_DIV_MASK))) | - (((uint32_t)(_FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS_CM0_CLOCK_CTL) << SYSPM_SLOW_CLK_DIV_Pos)) | - ((uint32_t)(_FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS_CM4_CLOCK_CTL) << SYSPM_FAST_CLK_DIV_Pos))); - - /* Increase the clock divider for the slow and fast clocks to SYSPM_CLK_DIVIDER */ - CPUSS_CM0_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, SYSPM_CLK_DIVIDER); - - CPUSS_CM4_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, SYSPM_CLK_DIVIDER); - - /* Read the divider value to make sure it is set */ - (void) CPUSS_CM0_CLOCK_CTL; - (void) CPUSS_CM4_CLOCK_CTL; - } - } - else -#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ -#endif - { - /* Update pointer to the latest saved UDB structure */ - //REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (uint32_t) &bkpRegs; //TBD - } -#if 0 //TBD - /* Release the IPC */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; -#endif - -#if 0 //TBD -#if (CY_CPU_CORTEX_M4) - - /* Store the address of the CM4 power status register */ - volatile uint32_t *cpussCm4PwrCtlAddr = &CPUSS_CM4_PWR_CTL; - - /* Repeat the WFI/WFE instruction if a wake up was not intended. - * Cypress ID #272909 - */ - do - { -#endif /* (CY_CPU_CORTEX_M4) */ -#endif - /* The CPU enters Deep Sleep mode upon execution of WFI/WFE */ - SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk; - - if(waitFor != CY_SYSPM_WAIT_FOR_EVENT) - { - __WFI(); - } - else - { - __WFE(); - #if 0 //TBD - #if (CY_CPU_CORTEX_M4) - /* Call the WFE instruction twice to clear the Event register - * of the CM4 CPU. Cypress ID #279077 - */ - if(wasEventSent) - { - __WFE(); - } - wasEventSent = true; - #endif /* (CY_CPU_CORTEX_M4) */ - #endif - } -#if 0 //TBD -#if (CY_CPU_CORTEX_M4) - } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, (*cpussCm4PwrCtlAddr)) == CM4_PWR_STS_RETAINED); -#endif /* (CY_CPU_CORTEX_M4) */ -#endif - -#if 0 //TBD - /* Acquire the IPC to prevent changing of the shared resources at the same time */ - while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) - { - /* Wait until the IPC structure is released by another CPU */ - } -#endif -#if 0 //TBD -#ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE - if (Cy_SysLib_GetDeviceRevision() == CY_SYSLIB_DEVICE_REV_0A) - { - /* Read and change the slow and fast clock dividers only under the condition - * that the other CPU is already in Deep Sleep. Cypress ID #284516 - */ - if (0U != (REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) & OTHER_CORE_DP_MASK)) - { - /* Restore the clock dividers for the slow and fast clocks */ - CPUSS_CM0_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, - (_FLD2VAL(SYSPM_SLOW_CLK_DIV, REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))); - - CPUSS_CM4_CLOCK_CTL = - _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, - (_FLD2VAL(SYSPM_FAST_CLK_DIV, REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT))))); - - retVal = true; - } - - /* Indicate that the current CPU is out of Deep Sleep */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) &= ((uint32_t) ~CUR_CORE_DP_MASK); - } - else -#endif /* #ifndef CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE */ -#endif - { -#if 0 //TBD - /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is - * cleared. Cypress ID #288510 - */ - if (*delayDoneFlag == NEED_DELAY) - { - uint32_t ddftSlowCtl; - uint32_t clkOutputSlow; - uint32_t ddftFastCtl; - - /* Save timer configuration */ - ddftSlowCtl = SRSS_TST_DDFT_SLOW_CTL_REG; - clkOutputSlow = SRSS_CLK_OUTPUT_SLOW; - ddftFastCtl = SRSS_TST_DDFT_FAST_CTL_REG; - - /* Configure the counter to be sourced by IMO */ - SRSS_TST_DDFT_SLOW_CTL_REG = SRSS_TST_DDFT_SLOW_CTL_MASK; - SRSS_CLK_OUTPUT_SLOW = CLK_OUTPUT_SLOW_MASK; - SRSS_TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_MASK; - - /* Load the down-counter to count the 10 us */ - SRSS_CLK_CAL_CNT1 = IMO_10US_DELAY; - - while (0U == (SRSS_CLK_CAL_CNT1 & SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk)) - { - /* Wait until the counter stops counting */ - } - - /* Indicate that delay was done */ - *delayDoneFlag = DELAY_DONE; - - /* Restore timer configuration */ - SRSS_TST_DDFT_SLOW_CTL_REG = ddftSlowCtl; - SRSS_CLK_OUTPUT_SLOW = clkOutputSlow; - SRSS_TST_DDFT_FAST_CTL_REG = ddftFastCtl; - - retVal = true; - } -#endif - } -#if 0 //TBD - /* Release the IPC */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; -#endif - return retVal; -} -#if defined (__ICCARM__) - #pragma diag_default=Ta023 -#endif - - -/******************************************************************************* -* Function Name: SetReadMarginTrimUlp -****************************************************************************//** -* -* This is the internal function that updates the read-margin trim values for the -* RAM and ROM. The trim update is done during transition of regulator voltage -* from higher to a lower one. -* -*******************************************************************************/ -static void SetReadMarginTrimUlp(void) -{ - /* Update read-write margin value for the ULP mode. Cypress ID#297292 */ - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_TRIM_Msk)) | - (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_TRIM_Msk); - - CPUSS_TRIM_ROM_CTL = (CPUSS_TRIM_ROM_CTL & ((uint32_t) ~CPUSS_TRIM_ROM_CTL_TRIM_Msk)) | - (CPUSS_TRIM_ROM_ULP & CPUSS_TRIM_ROM_CTL_TRIM_Msk); - #endif - } - else - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); - - CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP; - #endif - } -} - - -/******************************************************************************* -* Function Name: SetReadMarginTrimLp -****************************************************************************//** -* -* The internal function that updates the read-margin trim values for the -* RAM and ROM. The trim update is done during transition of regulator voltage -* from a lower to a higher one. -* -*******************************************************************************/ -static void SetReadMarginTrimLp(void) -{ - /* Update read-write margin value for the LP mode. Cypress ID#297292 */ - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RM_Msk)) | - (CPUSS_TRIM_RAM_LP & CPUSS_TRIM_RAM_CTL_RM_Msk); - - CPUSS_TRIM_ROM_CTL = (CPUSS_TRIM_ROM_CTL & ((uint32_t) ~CPUSS_TRIM_ROM_CTL_RM_Msk)) | - (CPUSS_TRIM_ROM_LP & CPUSS_TRIM_ROM_CTL_RM_Msk); - #endif - } - else - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_ROM_CTL_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); - - CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP; - #endif - } -} - - -/******************************************************************************* -* Function Name: SetWriteAssistTrimUlp -****************************************************************************//** -* -* The internal function that updates the write assistant trim value for the -* RAM. The trim update is done during transition of regulator voltage -* from higher to a lower. -* -*******************************************************************************/ -static void SetWriteAssistTrimUlp(void) -{ - /* Update write assist value for the LP mode. Cypress ID#297292 */ - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_WA_Msk)) | - (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_WA_Msk); - #endif - } - else - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_ROM_CTL_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); - #endif - } -} - - -/******************************************************************************* -* Function Name: SetWriteAssistTrimLp -****************************************************************************//** -* -* The internal function that updates the write assistant trim value for the -* RAM. The trim update is done during transition of regulator voltage -* from lower to a higher one. -* -*******************************************************************************/ -static void SetWriteAssistTrimLp(void) -{ - /* Update write assist value for the LP mode. Cypress ID#297292 */ - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (CPUSS_TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_WA_Msk)) | - (CPUSS_TRIM_RAM_LP & CPUSS_TRIM_RAM_CTL_WA_Msk); - #endif - } - else - { - #if 0 //TBD - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); - - CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP; - #endif - } -} - - -/******************************************************************************* -* Function Name: IsVoltageChangePossible -****************************************************************************//** -* -* The internal function that checks wherever it is possible to change the core -* voltage. The voltage change is possible only when the protection context is -* set to zero (PC = 0), or the device supports modifying registers via syscall. -* -*******************************************************************************/ -static bool IsVoltageChangePossible(void) -{ -#if 0 //TBD - bool retVal = true; - - if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) - { - uint32_t curProtContext = Cy_Prot_GetActivePC(ACTIVE_BUS_MASTER); - - retVal = ((Cy_SysLib_GetDeviceRevision() > SYSPM_DEVICE_PSOC6ABLE2_REV_0B) || (curProtContext == 0U)); - } - - return retVal; -#endif - return false; - -} - -bool Cy_SysPm_Cm4IsActive(void) -{ - return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_ACTIVE) != 0U); -} - - -bool Cy_SysPm_Cm4IsSleep(void) -{ - return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_SLEEP) != 0U); -} - - -bool Cy_SysPm_Cm4IsDeepSleep(void) -{ - return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_DEEPSLEEP) != 0U); -} - - -bool Cy_SysPm_Cm0IsActive(void) -{ - return ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_ACTIVE) != 0U); -} - - -bool Cy_SysPm_Cm0IsSleep(void) -{ - return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_SLEEP) != 0U); -} - - -bool Cy_SysPm_Cm0IsDeepSleep(void) -{ - return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_DEEPSLEEP) != 0U); -} - - -bool Cy_SysPm_IsSystemLp(void) -{ - return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LP) != 0U); -} - - -bool Cy_SysPm_IsSystemUlp(void) -{ - return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_ULP) != 0U); -} - - -void Cy_SysPm_CpuSendWakeupEvent(void) -{ - __SEV(); -} - - -bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void) -{ - return false; -} - - -bool Cy_SysPm_BuckIsEnabled(void) -{ -//TBD -// return (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_EN, SRSS_PWR_BUCK_CTL)); - return false; -} - - -cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void) -{ - uint32_t retVal = 0; - - return ((cy_en_syspm_buck_voltage1_t) retVal); -} - - -cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) -{ - - uint32_t retVal = 0UL; -#if 0 //TBD - - if (0U != cy_device->sysPmSimoPresent) - { - retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, SRSS_PWR_BUCK_CTL2); - } -#endif - - return ((cy_en_syspm_buck_voltage2_t) retVal); - - -} - - -void Cy_SysPm_BuckDisableVoltage2(void) -{ -#if 0 //TBD - - if (0U != cy_device->sysPmSimoPresent) - { - /* Disable the Vbuck2 output */ - SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U); - } -#endif -} - - -void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) -{ -#if 0 //TBD - - bool isBuckEnabled = Cy_SysPm_BuckIsEnabled(); - - if ((0U != cy_device->sysPmSimoPresent) && isBuckEnabled) - { - if(hwControl) - { - SRSS_PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U); - } - else - { - SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U); - } - } -#endif -} - - -bool Cy_SysPm_BuckIsVoltage2HwControlled(void) -{ - bool retVal = false; -#if 0 //TBD - - if (0U != cy_device->sysPmSimoPresent) - { - retVal = (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS_PWR_BUCK_CTL2)); - } -#endif - return retVal; -} - - -cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void) -{ - return (cy_en_syspm_ldo_voltage_t)0;//TBD -} - - -bool Cy_SysPm_LdoIsEnabled(void) -{ - return false; -} - - -bool Cy_SysPm_IoIsFrozen(void) -{ - return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE)); -} - - -void Cy_SysPm_PmicEnable(void) -{ -#if 0 //TBD - if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL)) - { - BACKUP_PMIC_CTL = - _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | - _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U) | - _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U); - } -#endif -} - - -void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity) -{ -#if 0 //TBD - CY_ASSERT_L3(CY_SYSPM_IS_POLARITY_VALID(polarity)); - - if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL)) - { - BACKUP_PMIC_CTL = - (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | - _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, (uint32_t) polarity)) & - ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U)); - } -#endif -} - - -void Cy_SysPm_PmicAlwaysEnable(void) -{ -#if 0 //TBD - BACKUP_PMIC_CTL |= _VAL2FLD(BACKUP_PMIC_CTL_PMIC_ALWAYSEN, 1U); -#endif -} - - -void Cy_SysPm_PmicEnableOutput(void) -{ -#if 0 //TBD - if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL)) - { - BACKUP_PMIC_CTL |= - _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U); - } -#endif -} - - -void Cy_SysPm_PmicDisableOutput(void) -{ -#if 0 //TBD - if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL)) - { - BACKUP_PMIC_CTL = - (BACKUP_PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) & - ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U)); - } -#endif -} - - -void Cy_SysPm_PmicLock(void) -{ -#if 0 //TBD - BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0U); -#endif -} - - -void Cy_SysPm_PmicUnlock(void) -{ -#if 0 //TBD - BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY); -#endif -} - - -bool Cy_SysPm_PmicIsEnabled(void) -{ -#if 0 //TBD - return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN, BACKUP_PMIC_CTL)); -#endif - return false; -} - - -bool Cy_SysPm_PmicIsOutputEnabled(void) -{ -#if 0 //TBD - return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, BACKUP_PMIC_CTL)); -#endif - return false; -} - - -bool Cy_SysPm_PmicIsLocked(void) -{ -#if 0 //TBD - return ((_FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL) == CY_SYSPM_PMIC_UNLOCK_KEY) ? false : true); -#endif - return false; -} - - -void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl) -{ -#if 0 //TBD - CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl)); - - BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl); -#endif -} - - -cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void) -{ - uint32_t retVal = 0; -#if 0 //TBD - retVal = _FLD2VAL(BACKUP_CTL_VDDBAK_CTL, BACKUP_CTL); -#endif - return ((cy_en_syspm_vddbackup_control_t) retVal); -} - - -void Cy_SysPm_BackupEnableVoltageMeasurement(void) -{ -#if 0 //TBD - BACKUP_CTL |= BACKUP_CTL_VBACKUP_MEAS_Msk; -#endif -} - - -void Cy_SysPm_BackupDisableVoltageMeasurement(void) -{ -#if 0 //TBD - BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_VBACKUP_MEAS_Msk); -#endif -} - - -void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key) -{ -#if 0 //TBD - CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key)); - - if(key == CY_SYSPM_SC_CHARGE_ENABLE) - { - BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE); - } - else - { - BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_EN_CHARGE_KEY_Msk); - } -#endif -} - -#endif -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_systick_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_systick_v2.c deleted file mode 100644 index 1c4737bee1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/cy_systick_v2.c +++ /dev/null @@ -1,224 +0,0 @@ -/***************************************************************************//** -* \file cy_systick.c -* \version 1.30 -* -* Provides the API definitions of the SisTick driver. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_M33SYSCPUSS) - -#include /* for NULL */ -#include "cy_systick.h" -#include "cy_sysint.h" - -extern cy_israddress __ramVectors[]; - -static Cy_SysTick_Callback Cy_SysTick_Callbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; -static void Cy_SysTick_ServiceCallbacks(void); - -void Cy_SysTick_EnableInterrupt(void) -{ - SYSTICK_CTRL = SYSTICK_CTRL | SysTick_CTRL_TICKINT_Msk; -} - -void Cy_SysTick_DisableInterrupt(void) -{ - SYSTICK_CTRL = SYSTICK_CTRL & ~SysTick_CTRL_TICKINT_Msk; -} - -void Cy_SysTick_SetReload(uint32_t value) -{ - CY_ASSERT_L1(CY_SYSTICK_IS_RELOAD_VALID(value)); - - SYSTICK_LOAD = (value & SysTick_LOAD_RELOAD_Msk); -} - -uint32_t Cy_SysTick_GetReload(void) -{ - return (SYSTICK_LOAD); -} - -uint32_t Cy_SysTick_GetValue(void) -{ - return (SYSTICK_VAL); -} - -void Cy_SysTick_Clear(void) -{ - SYSTICK_VAL = 0u; -} - -uint32_t Cy_SysTick_GetCountFlag(void) -{ - return (SYSTICK_CTRL & SysTick_CTRL_COUNTFLAG_Msk); -} - -void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval) -{ - CY_ASSERT_L1(CY_SYSTICK_IS_RELOAD_VALID(interval)); - - uint32_t i; - - for (i = 0u; i - -#if defined(__cplusplus) -extern "C" { - -#endif /* __cplusplus */ - - -cy_en_tdm_status_t Cy_AudioTDM_TX_Init( TDM_TX_STRUCT_Type * base, cy_stc_tdm_config_tx_t const * config); -void Cy_AudioTDM_TX_DeInit( TDM_TX_STRUCT_Type * base); - -cy_en_tdm_status_t Cy_AudioTDM_RX_Init( TDM_RX_STRUCT_Type * base, cy_stc_tdm_config_rx_t const * config); -void Cy_AudioTDM_RX_DeInit( TDM_RX_STRUCT_Type * base); - -/** -* \addtogroup group_tdm_functions -* \{ -*/ - -/******************************************************************************* -* Function Name: Cy_AudioTDM_Init -****************************************************************************//** -* -* Initializes the TDM module in accordance with a configuration structure. -* -* \pre If the TDM module is initialized previously, the \ref Cy_AudioTDM_DeInit() -* must be called before calling this function. -* -* \param base The pointer to the TDM instance address. -* -* \param config The pointer to a configuration structure. -* -* \return error / status code. See \ref cy_en_tdm_status_t. -* -* \funcusage -* \ -* -*******************************************************************************/ -cy_en_tdm_status_t Cy_AudioTDM_Init( TDM_STRUCT_Type * base, cy_stc_tdm_config_t const * config) -{ - cy_en_tdm_status_t ret = CY_TDM_BAD_PARAM; - - if((NULL != base) && (NULL != config)) - { - if(config->tx_config.enable) - { - ret = Cy_AudioTDM_TX_Init(&(base->TDM_TX_STRUCT),&(config->tx_config)); - if(ret == CY_TDM_BAD_PARAM) - { - return(ret); - } - } - if(config->rx_config.enable) - { - ret = Cy_AudioTDM_RX_Init(&(base->TDM_RX_STRUCT),&(config->rx_config)); - } - } - return (ret); -} - -/** \} group_tdm_functions */ - -/**************************************************************************/ -/* Function Name: Cy_AudioTDM_TX_Init */ -/**************************************************************************/ -/* -* Initializes the TDM Transmitter module in accordance with a configuration structure. -* -* \pre If the TDM TX module is initialized previously, the \ref Cy_AudioTX_Tx_DeInit() -* must be called before calling this function. -* -* \param base The pointer to the TDM->TX instance address. -* -* \param config The pointer to a configuration structure. -* -* \return error / status code. See \ref cy_en_tdm_status_t. -* -* \funcusage -* -****************************************************************************/ -cy_en_tdm_status_t Cy_AudioTDM_TX_Init( TDM_TX_STRUCT_Type * base, cy_stc_tdm_config_tx_t const * config) -{ - - cy_en_tdm_status_t ret = CY_TDM_SUCCESS; - uint8_t clockDiv = config->clkDiv -1U; - uint8_t channelNum = config->channelNUM - 1U; - uint8_t channelSIZE = config->channelSize - 1U; - CY_ASSERT_L2(base); - CY_ASSERT_L2(config); - CY_ASSERT_L2(CY_TDM_IS_CHANNELS_VALID(channelNum)); - CY_ASSERT_L2(CY_TDM_IS_CHANNEL_SIZE_VALID(channelSIZE)); - CY_ASSERT_L2(CY_I2S_TDM_IS_INPUT_SIGNAL_MODE_VALID(config->signalInput)); - - /* Channnel Default */ - if((TDM_STRUCT_TX_CTL(base) & TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_ENABLED_Msk)) - { - ret = CY_TDM_BAD_PARAM; - return(ret); - } - - /* The TX interface setting */ - TDM_STRUCT_TX_IF_CTL(base) = - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV, clockDiv) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL, config->clkSel) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_SCK_POLARITY, config->sckPolarity) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_FSYNC_POLARITY, config->fsyncPolarity) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_FSYNC_FORMAT, config->fsyncFormat) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_NR, channelNum) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_SIZE, channelSIZE) | - _BOOL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_I2S_MODE, config->i2sMode); - - if(!config->masterMode) - { - TDM_STRUCT_TX_ROUTE_CTL(base) = _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_ROUTE_CTL_MODE, config->signalInput); - } - - /* Chanel Enable */ - TDM_STRUCT_TX_CH_CTL(base) = config->chEN; - /* The FIFO setting */ - TDM_STRUCT_TX_FIFO_CTL(base) = _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_TRIGGER_LEVEL,config->fifoTriggerLevel); - /* The TC Interface setting */ - TDM_STRUCT_TX_CTL(base) = - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_WORD_SIZE, config->wordSize) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_FORMAT, config->format) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS, config->masterMode); - - return (ret); -} - -/**************************************************************************/ -/* Function Name: Cy_AudioTDM_RX_Init */ -/**************************************************************************/ -cy_en_tdm_status_t Cy_AudioTDM_RX_Init( TDM_RX_STRUCT_Type * base, cy_stc_tdm_config_rx_t const * config) -{ - cy_en_tdm_status_t ret = CY_TDM_SUCCESS; - uint16_t clockDiv = (uint32_t)config->clkDiv - 1U; - uint8_t channelSIZE = config->channelSize - 1U; - uint8_t channelNum = config->channelNUM - 1U; - CY_ASSERT_L2(base); - CY_ASSERT_L2(config); - CY_ASSERT_L2(CY_TDM_IS_CLK_DIV_VALID(clockDiv)); - CY_ASSERT_L2(CY_TDM_IS_CHANNELS_VALID(channelNum)); - CY_ASSERT_L2(CY_TDM_IS_CHANNEL_SIZE_VALID(channelSIZE)); - CY_ASSERT_L2(CY_I2S_TDM_IS_INPUT_SIGNAL_MODE_VALID(config->signalInput)); - - /* The RX interface setting */ - TDM_STRUCT_RX_IF_CTL(base) = - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV, clockDiv) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL, config->clkSel) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_SCK_POLARITY, config->sckPolarity) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_FSYNC_POLARITY, config->fsyncPolarity) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_LATE_SAMPLE, config->lateSample) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_FSYNC_FORMAT, config->fsyncFormat) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_NR, channelNum) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_SIZE, channelSIZE) | - _BOOL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_I2S_MODE, config->i2sMode); - - if(!config->masterMode) - { - TDM_STRUCT_RX_ROUTE_CTL(base) = _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_ROUTE_CTL_MODE, config->signalInput); - } - - /* Chanel Enable */ - TDM_STRUCT_RX_CH_CTL(base) = config->chEN; - /* The FIFO setting */ - TDM_STRUCT_RX_FIFO_CTL(base) = _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_TRIGGER_LEVEL,config->fifoTriggerLevel); - /* The TC Interface setting */ - TDM_STRUCT_RX_CTL(base) = - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIZE, config->wordSize) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIGN_EXTEND, config->signExtend) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_FORMAT, config->format) | - _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS, config->masterMode); - - return (ret); -} - -/** -* \addtogroup group_tdm_functions -* \{ -*/ - - -/******************************************************************************* -* Function Name: Cy_AudioTDM_DeInit -****************************************************************************//** -* -* -* \param base base -* -*******************************************************************************/ -void Cy_AudioTDM_DeInit( TDM_STRUCT_Type * base) -{ - Cy_AudioTDM_TX_DeInit(&(base->TDM_TX_STRUCT)); - Cy_AudioTDM_RX_DeInit(&(base->TDM_RX_STRUCT)); -} - -/** \} group_tdm_functions */ - -/**************************************************************************/ -/* Function Name: Cy_AudioTDM_TX_DeInit */ -/**************************************************************************/ -void Cy_AudioTDM_TX_DeInit( TDM_TX_STRUCT_Type * base) -{ - TDM_STRUCT_TX_INTR_TX_MASK(base) = 0UL; - TDM_STRUCT_TX_FIFO_CTL(base) = 0UL; - TDM_STRUCT_TX_IF_CTL(base) = CY_TDM_TX_IF_CTL_DEFAULT; - TDM_STRUCT_TX_CTL(base) = CY_TDM_TX_CTL_DEFAULT; -} - -/**************************************************************************/ -/* Function Name: Cy_AudioTDM_RX_DeInit */ -/**************************************************************************/ -void Cy_AudioTDM_RX_DeInit( TDM_RX_STRUCT_Type * base) -{ - TDM_STRUCT_RX_INTR_RX_MASK(base) = 0UL; - TDM_STRUCT_RX_FIFO_CTL(base) = 0UL; - TDM_STRUCT_RX_IF_CTL(base) = CY_TDM_RX_IF_CTL_DEFAULT; - TDM_STRUCT_RX_CTL(base) = CY_TDM_RX_CTL_DEFAULT; -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - - -#endif /* CY_IP_MXTDM */ -/******************************************************************************/ -/* [] END OF FILE */ -/******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd.c deleted file mode 100644 index 268f1b331a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd.c +++ /dev/null @@ -1,5012 +0,0 @@ -/****************************************************************************** - * copyright (C) 2014-2015 Cadence Design Systems - * All rights reserved. - ****************************************************************************** - * edd.c - * Ethernet DMA MAC Driver, - * for GEM GXL core part no. IP7014, from rev 1p05 up - * for GEM XL core part no. IP7012, from rev 1p01 up - * and XGM GXL core part no. IP716, from rev 1p01 up - * - * Main source file - *****************************************************************************/ - -#include "cy_device.h" - -#if defined(CY_IP_MXETH) - -#include "cdn_stdint.h" -#include "cdn_errno.h" -#include "log.h" -#include "cps_v2.h" -#include "emac_regs.h" -#include "cedi.h" -#include "edd_int.h" - -#ifdef __cplusplus - extern "C" { -#endif - -/****************************************************************************** - * Private Driver functions - *****************************************************************************/ - -uint32_t CPS_UncachedRead32(volatile uint32_t* address) { - return (*((volatile uint32_t *)(address))); -} - -void CPS_UncachedWrite32(volatile uint32_t* address, uint32_t value) { - (*((volatile uint32_t *)(address)) = (value)); - return; -} - -void CPS_WritePhysAddress32(volatile uint32_t* address, uint32_t value) { - (*((volatile uint32_t *)(address)) = (value)); - return; -} -/* Calculate the descriptor sizes (in bytes) for a given DMA config */ -static void calcDescriptorSizes(const CEDI_Config *config, - uint16_t *txDescSize, - uint16_t *rxDescSize) { - - /* use 1 contiguous block for Tx descriptor lists - * and another contiguous block for Rx descriptor lists */ - *txDescSize = CEDI_TWO_BD_WORD_SIZE; - *rxDescSize = CEDI_TWO_BD_WORD_SIZE; - - if (config->dmaAddrBusWidth) // DMA address bus width. 0 =32b , 1=64b - { - *txDescSize += CEDI_TWO_BD_WORD_SIZE; - *rxDescSize += CEDI_TWO_BD_WORD_SIZE; - } - - if (config->enTxExtBD){ - *txDescSize += CEDI_TWO_BD_WORD_SIZE; - } - - if (config->enRxExtBD){ - *rxDescSize += CEDI_TWO_BD_WORD_SIZE; - } -} - -static uint32_t numTxDescriptors(CEDI_Config *config) -{ - uint16_t i; - uint16_t sumTxDesc = 0; - - for (i=0; itxQs; i++) - /* allow 1 extra for "endstop" descriptor */ - sumTxDesc += ((uint32_t)((config->txQLen)[i]+CEDI_MIN_TXBD)); - return sumTxDesc; -} - -static uint32_t numRxDescriptors(CEDI_Config *config) -{ - uint16_t i; - uint16_t sumRxDesc = 0; - - for (i=0; irxQs; i++) - /* allow 1 extra for "endstop" descriptor */ - sumRxDesc += ((uint32_t)((config->rxQLen)[i]+CEDI_MIN_RXBD)); - return sumRxDesc; -} - -static uint32_t initTxDescLists(void *pD) -{ - uint8_t q; - - /* set start of Tx vAddr lists - place in pD block after - * privateData struct */ - CEDI_PdVar(txQueue[0]).vAddrList = - (uintptr_t *)((uint8_t *)pD + sizeof(CEDI_PrivateData)); - for (q=0; qnumRxDesc = CEDI_PdVar(cfg).rxQLen[q] + CEDI_MIN_RXBD; - - emacFindQBaseAddr(pD, q, rxQ, &pAddr, &vAddr); - rxQ->rxDescStart = (rxDesc *)vAddr; - - /* initialise the descriptors */ - descPtr = rxQ->rxDescStart; - for (i = 0; inumRxDesc; i++) { - CPS_UncachedWrite32((uint32_t *) - &(descPtr->word[0]), i?0:CEDI_RXD_WRAP|CEDI_RXD_USED); - CPS_UncachedWrite32((uint32_t *) - &(descPtr->word[1]), CEDI_RXD_EMPTY); - descPtr = (rxDesc*) (((uintptr_t)(descPtr)) + - (CEDI_PdVar(rxDescriptorSize))); - } - - if (0!=emacResetRxQ(pD, q, 0)) - return EINVAL; - } - - return 0; -} - - -/* return the number of priority queues available in the h/w config */ -static uint8_t maxHwQs(uintptr_t regBase) { - uint8_t qCount = 1; - uint32_t reg = CPS_UncachedRead32( - (&(((struct emac_regs *)(regBase))->designcfg_debug6))); - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__READ(reg)) qCount++; - if (EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__READ(reg)) qCount++; - return qCount; -} - -static void disableAllInterrupts(void *pD) -{ -#define CEDI_DISABLE_ALL_INT(Q) if (CEDI_PdVar(numQs)>Q) \ - CPS_UncachedWrite32(CEDI_RegAddr(int_q##Q##_disable), 0xFFFFFFFF); - - CPS_UncachedWrite32(CEDI_RegAddr(int_disable), 0xFFFFFFFF); - - CEDI_DISABLE_ALL_INT(1); - CEDI_DISABLE_ALL_INT(2); -/* // Only Three Queues are supported - CEDI_DISABLE_ALL_INT(3); - CEDI_DISABLE_ALL_INT(4); - CEDI_DISABLE_ALL_INT(5); - CEDI_DISABLE_ALL_INT(6); - CEDI_DISABLE_ALL_INT(7); - CEDI_DISABLE_ALL_INT(8); - CEDI_DISABLE_ALL_INT(9); - CEDI_DISABLE_ALL_INT(10); - CEDI_DISABLE_ALL_INT(11); - CEDI_DISABLE_ALL_INT(12); - CEDI_DISABLE_ALL_INT(13); - CEDI_DISABLE_ALL_INT(14); - CEDI_DISABLE_ALL_INT(15); -*/ -} - -static void clearAllInterrupts(void *pD) -{ - -#define CEDI_CLEAR_ALL_WRCLR_INT(Q) if (CEDI_PdVar(numQs)>Q) \ - CPS_UncachedWrite32(CEDI_RegAddr(int_q##Q##_status), 0xFFFFFFFF); - -#define CEDI_CLEAR_ALL_RDCLR_INT(Q) if (CEDI_PdVar(numQs)>Q) \ - CPS_UncachedRead32(CEDI_RegAddr(int_q##Q##_status)); - - if (0==CEDI_PdVar(hwCfg).irq_read_clear) { - CPS_UncachedWrite32(CEDI_RegAddr(int_status), 0xFFFFFFFF); - CEDI_CLEAR_ALL_RDCLR_INT(1); - CEDI_CLEAR_ALL_RDCLR_INT(2); -/* // Only Three Queues are supported - CEDI_CLEAR_ALL_RDCLR_INT(3); - CEDI_CLEAR_ALL_RDCLR_INT(4); - CEDI_CLEAR_ALL_RDCLR_INT(5); - CEDI_CLEAR_ALL_RDCLR_INT(6); - CEDI_CLEAR_ALL_RDCLR_INT(7); - CEDI_CLEAR_ALL_RDCLR_INT(8); - CEDI_CLEAR_ALL_RDCLR_INT(9); - CEDI_CLEAR_ALL_RDCLR_INT(10); - CEDI_CLEAR_ALL_RDCLR_INT(11); - CEDI_CLEAR_ALL_RDCLR_INT(12); - CEDI_CLEAR_ALL_RDCLR_INT(13); - CEDI_CLEAR_ALL_RDCLR_INT(14); - CEDI_CLEAR_ALL_RDCLR_INT(15); -*/ - } - else { - CPS_UncachedRead32(CEDI_RegAddr(int_status)); - CEDI_CLEAR_ALL_WRCLR_INT(1); - CEDI_CLEAR_ALL_WRCLR_INT(2); -/* // Only Three Queues are supported - CEDI_CLEAR_ALL_WRCLR_INT(3); - CEDI_CLEAR_ALL_WRCLR_INT(4); - CEDI_CLEAR_ALL_WRCLR_INT(5); - CEDI_CLEAR_ALL_WRCLR_INT(6); - CEDI_CLEAR_ALL_WRCLR_INT(7); - CEDI_CLEAR_ALL_WRCLR_INT(8); - CEDI_CLEAR_ALL_WRCLR_INT(9); - CEDI_CLEAR_ALL_WRCLR_INT(10); - CEDI_CLEAR_ALL_WRCLR_INT(11); - CEDI_CLEAR_ALL_WRCLR_INT(12); - CEDI_CLEAR_ALL_WRCLR_INT(13); - CEDI_CLEAR_ALL_WRCLR_INT(14); - CEDI_CLEAR_ALL_WRCLR_INT(15); -*/ - } -} - -/* Return all registers to reset values */ -static void initAllRegs(void *pD) -{ - CPS_UncachedWrite32(CEDI_RegAddr(network_control), 0); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), 0); -// CPS_UncachedWrite32(CEDI_RegAddr(user_io_register), 0); /* not present in player */ - CPS_UncachedWrite32(CEDI_RegAddr(transmit_status), 0); - CPS_UncachedWrite32(CEDI_RegAddr(receive_q_ptr), 0); - CPS_UncachedWrite32(CEDI_RegAddr(transmit_q_ptr), 0); - CPS_UncachedWrite32(CEDI_RegAddr(receive_status), 0); - CPS_UncachedWrite32(CEDI_RegAddr(int_disable), 0xFFFFFFFF); - CPS_UncachedWrite32(CEDI_RegAddr(phy_management), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum), 0xFFFFFFFF); - CPS_UncachedWrite32(CEDI_RegAddr(pbuf_txcutthru), 0x00003FFF); - CPS_UncachedWrite32(CEDI_RegAddr(pbuf_rxcutthru), 0x000007FF); - CPS_UncachedWrite32(CEDI_RegAddr(jumbo_max_length), 0x00002800); -// CPS_UncachedWrite32(CEDI_RegAddr(external_fifo_interface), 0); -// CPS_UncachedWrite32(CEDI_RegAddr(axi_max_pipeline), 0x00000101); -// CPS_UncachedWrite32(CEDI_RegAddr(rsc_control), 0); - CPS_UncachedWrite32(CEDI_RegAddr(int_moderation), 0); - CPS_UncachedWrite32(CEDI_RegAddr(sys_wake_time), 0); - CPS_UncachedWrite32(CEDI_RegAddr(hash_bottom), 0); - CPS_UncachedWrite32(CEDI_RegAddr(hash_top), 0); - CPS_UncachedWrite32(CEDI_RegAddr(wol_register), 0); - CPS_UncachedWrite32(CEDI_RegAddr(stretch_ratio), 0); - CPS_UncachedWrite32(CEDI_RegAddr(stacked_vlan), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pfc_pause), 0); - CPS_UncachedWrite32(CEDI_RegAddr(mask_add1_bottom), 0); - CPS_UncachedWrite32(CEDI_RegAddr(mask_add1_top), 0); - CPS_UncachedWrite32(CEDI_RegAddr(dma_addr_or_mask), 0); - CPS_UncachedWrite32(CEDI_RegAddr(rx_ptp_unicast), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_ptp_unicast), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_nsec_cmp), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_sec_cmp), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_msb_sec_cmp), 0); - CPS_UncachedWrite32(CEDI_RegAddr(dpram_fill_dbg), 0); -// CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), 0); -// CPS_UncachedWrite32(CEDI_RegAddr(pcs_an_adv), 0); -// CPS_UncachedWrite32(CEDI_RegAddr(pcs_an_np_tx), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum1), 0xFFFFFFFF); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum2), 0xFFFFFFFF); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum3), 0xFFFFFFFF); - CPS_UncachedWrite32(CEDI_RegAddr(rx_lpi), 0); - CPS_UncachedWrite32(CEDI_RegAddr(rx_lpi_time), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_lpi), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_lpi_time), 0); - CPS_UncachedWrite32(CEDI_RegAddr(dpram_fill_dbg), 0); - CPS_UncachedWrite32(CEDI_RegAddr(cbs_control), 0); - CPS_UncachedWrite32(CEDI_RegAddr(cbs_idleslope_q_a), 0); - CPS_UncachedWrite32(CEDI_RegAddr(cbs_idleslope_q_b), 0); - CPS_UncachedWrite32(CEDI_RegAddr(upper_tx_q_base_addr), 0); - CPS_UncachedWrite32(CEDI_RegAddr(upper_rx_q_base_addr), 0); - CPS_UncachedWrite32(CEDI_RegAddr(tx_bd_control), 0); - CPS_UncachedWrite32(CEDI_RegAddr(rx_bd_control), 0); -} - -/* Check the selected callback(s) have non-NULL call addresses. - * Test all events selected, returning any with NULL callbacks. - * @param selection - bit-flags defining callback selection - * @return 0 if all OK (not NULL) - * @return OR'd combination of events whose cb function pointers are NULL - */ -static uint32_t callbacksNullCheck(void *pD, uint32_t selection) -{ - uint32_t nullCbEvents = 0; - - if (!selection) - return 0; - - if ((selection & (CEDI_EV_TX_COMPLETE | CEDI_EV_TX_USED_READ)) - && ((CEDI_PdVar(cb).txEvent)==NULL)) - { - nullCbEvents |= - (selection & (CEDI_EV_TX_COMPLETE | CEDI_EV_TX_USED_READ)); - selection &= ~(CEDI_EV_TX_COMPLETE | CEDI_EV_TX_USED_READ); - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_RX_COMPLETE) && - ((CEDI_PdVar(cb).rxFrame)==NULL)) - { - nullCbEvents |= (selection & CEDI_EV_RX_COMPLETE); - selection ^= ~selection & CEDI_EV_RX_COMPLETE; - if (!selection) - return nullCbEvents; - } - if ((selection & (CEDI_EV_TX_UNDERRUN | CEDI_EV_TX_RETRY_EX_LATE_COLL - | CEDI_EV_TX_FR_CORRUPT )) && - ((CEDI_PdVar(cb).txError)==NULL)) - { - nullCbEvents |= (selection & (CEDI_EV_TX_UNDERRUN | - CEDI_EV_TX_RETRY_EX_LATE_COLL | CEDI_EV_TX_FR_CORRUPT)); - selection &= ~(CEDI_EV_TX_UNDERRUN | - CEDI_EV_TX_RETRY_EX_LATE_COLL | CEDI_EV_TX_FR_CORRUPT); - if (!selection) - return nullCbEvents; - } - - if ((selection & (CEDI_EV_RX_USED_READ | CEDI_EV_RX_OVERRUN)) && - ((((CEDI_PrivateData *)pD)->cb.rxError)==NULL)) - { - nullCbEvents |= (selection & (CEDI_EV_RX_USED_READ | CEDI_EV_RX_OVERRUN)); - selection &= ~(CEDI_EV_RX_USED_READ | CEDI_EV_RX_OVERRUN); - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_MAN_FRAME) && - ((CEDI_PdVar(cb).phyManComplete)==NULL)) - { - nullCbEvents |= CEDI_EV_MAN_FRAME; - selection &= ~CEDI_EV_MAN_FRAME; - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_HRESP_NOT_OK) && - ((CEDI_PdVar(cb).hrespError)==NULL)) - { - nullCbEvents |= CEDI_EV_HRESP_NOT_OK; - selection &= ~CEDI_EV_HRESP_NOT_OK; - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_PCS_LP_PAGE_RX) && - ((CEDI_PdVar(cb).lpPageRx)==NULL)) - { - nullCbEvents |= CEDI_EV_PCS_LP_PAGE_RX; - selection &= ~CEDI_EV_PCS_LP_PAGE_RX; - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_PCS_AN_COMPLETE) && - ((CEDI_PdVar(cb).anComplete)==NULL)) - { - nullCbEvents |= CEDI_EV_PCS_AN_COMPLETE; - selection &= ~CEDI_EV_PCS_AN_COMPLETE; - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_PCS_LINK_CHANGE_DET) && - ((CEDI_PdVar(cb).linkChange)==NULL)) - { - nullCbEvents |= CEDI_EV_PCS_LINK_CHANGE_DET; - selection &= ~CEDI_EV_PCS_LINK_CHANGE_DET; - if (!selection) - return nullCbEvents; - } - - if ((selection & (CEDI_EV_TSU_SEC_INC | CEDI_EV_TSU_TIME_MATCH)) && - ((CEDI_PdVar(cb).tsuEvent)==NULL)) - { - nullCbEvents |= (selection & - (CEDI_EV_TSU_SEC_INC | CEDI_EV_TSU_TIME_MATCH)); - selection &= ~(CEDI_EV_TSU_SEC_INC | CEDI_EV_TSU_TIME_MATCH); - if (!selection) - return nullCbEvents; - } - - if ((selection & (CEDI_EV_PAUSE_FRAME_TX | CEDI_EV_PAUSE_TIME_ZERO | - CEDI_EV_PAUSE_NZ_QU_RX)) && - ((CEDI_PdVar(cb).pauseEvent)==NULL)) - { - nullCbEvents |= (selection & (CEDI_EV_PAUSE_FRAME_TX | - CEDI_EV_PAUSE_TIME_ZERO | CEDI_EV_PAUSE_NZ_QU_RX)); - selection &= ~(CEDI_EV_PAUSE_FRAME_TX | CEDI_EV_PAUSE_TIME_ZERO | - CEDI_EV_PAUSE_NZ_QU_RX); - if (!selection) - return nullCbEvents; - } - - if ((selection & (CEDI_EV_PTP_TX_DLY_REQ | CEDI_EV_PTP_TX_SYNC)) && - ((CEDI_PdVar(cb).ptpPriFrameTx)==NULL)) - { - nullCbEvents |= (selection & - (CEDI_EV_PTP_TX_DLY_REQ | CEDI_EV_PTP_TX_SYNC)); - selection &= ~(CEDI_EV_PTP_TX_DLY_REQ | CEDI_EV_PTP_TX_SYNC); - if (!selection) - return nullCbEvents; - } - - - if ((selection & (CEDI_EV_PTP_TX_PDLY_REQ | CEDI_EV_PTP_TX_PDLY_RSP)) && - ((CEDI_PdVar(cb).ptpPeerFrameTx)==NULL)) - { - nullCbEvents |= (selection & - (CEDI_EV_PTP_TX_PDLY_REQ | CEDI_EV_PTP_TX_PDLY_RSP )); - selection &= ~(CEDI_EV_PTP_TX_PDLY_REQ | CEDI_EV_PTP_TX_PDLY_RSP ); - if (!selection) - return nullCbEvents; - } - - if ((selection & (CEDI_EV_PTP_RX_DLY_REQ | CEDI_EV_PTP_RX_SYNC)) && - ((CEDI_PdVar(cb).ptpPriFrameRx)==NULL)) - { - nullCbEvents |= (selection & - (CEDI_EV_PTP_RX_DLY_REQ | CEDI_EV_PTP_RX_SYNC)); - selection &= ~(CEDI_EV_PTP_RX_DLY_REQ | CEDI_EV_PTP_RX_SYNC); - if (!selection) - return nullCbEvents; - } - - if ((selection & (CEDI_EV_PTP_RX_PDLY_REQ | CEDI_EV_PTP_RX_PDLY_RSP)) && - ((CEDI_PdVar(cb).ptpPeerFrameRx)==NULL)) - { - nullCbEvents |= (selection & - (CEDI_EV_PTP_RX_PDLY_REQ | CEDI_EV_PTP_RX_PDLY_RSP)); - selection &= ~(CEDI_EV_PTP_RX_PDLY_REQ | CEDI_EV_PTP_RX_PDLY_RSP); - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_LPI_CH_RX) && ((CEDI_PdVar(cb).lpiStatus)==NULL)) - { - nullCbEvents |= CEDI_EV_LPI_CH_RX; - selection &= ~CEDI_EV_LPI_CH_RX; - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_WOL_RX) && ((CEDI_PdVar(cb).wolEvent)==NULL)) - { - nullCbEvents |= CEDI_EV_WOL_RX; - selection &= ~CEDI_EV_WOL_RX; - if (!selection) - return nullCbEvents; - } - - if ((selection & CEDI_EV_EXT_INTR) && ((CEDI_PdVar(cb).extInpIntr)==NULL)) - { - nullCbEvents |= CEDI_EV_EXT_INTR; - selection &= ~CEDI_EV_EXT_INTR; - } - - - return nullCbEvents; -} - -/* initializing the upper 32 bit buffer queue base addresses from config */ -static void initUpper32BuffQAddr(void *pD) -{ - uint32_t regData; - - regData = 0; - -#ifdef EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MODIFY - EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MODIFY( - regData, CEDI_PdVar(cfg).upper32BuffTxQAddr); - - CPS_UncachedWrite32(CEDI_RegAddr(upper_tx_q_base_addr), regData); - - regData = 0; - EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MODIFY( - regData, CEDI_PdVar(cfg).upper32BuffRxQAddr); - - CPS_UncachedWrite32(CEDI_RegAddr(upper_rx_q_base_addr), regData); -#else - EMAC_REGS__MSB_BUFF_Q_BASE_ADDR_REG__MSB_BUFF_Q_BASE_ADDR__MODIFY( - regData, CEDI_PdVar(cfg).upper32BuffTxQAddr); - - CPS_UncachedWrite32(CEDI_RegAddr(msb_buff_q_base_addr_reg), regData); -#endif -} - -/* Initialise axi_max_pipeline register from config struct */ -static void initAxiMaxPipelineReg(void *pD) -{ - CEDI_Config *config = &CEDI_PdVar(cfg); - uint32_t regData, axiPipelineFifoDepth; - - regData = CPS_UncachedRead32(CEDI_RegAddr(axi_max_pipeline)); - axiPipelineFifoDepth = 1<<(CEDI_PdVar(hwCfg).axi_access_pipeline_bits); - - /* value of max pipeline must be >0 and not greater than fifo depth - * (2^axi_access_pipeline) */ - if ((CEDI_PdVar(hwCfg).axi) && (config->aw2wMaxPipeline==0)) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "*** Warning: aw2wMaxPipeline requested value = 0, increasing to 1"); - config->aw2wMaxPipeline = 1; - } else if ((config->aw2wMaxPipeline) > axiPipelineFifoDepth) { - vDbgMsg(DBG_GEN_MSG, 5, "*** Warning: aw2wMaxPipeline requested"\ - "value (%u) greater than fifo depth (%u), reducing to %u\n", - config->aw2wMaxPipeline, axiPipelineFifoDepth, axiPipelineFifoDepth); - config->aw2wMaxPipeline = axiPipelineFifoDepth; - } - EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MODIFY( - regData, config->aw2wMaxPipeline); - - if ((CEDI_PdVar(hwCfg).axi) && (config->ar2rMaxPipeline==0)) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "*** Warning: ar2rMaxPipeline requested value = 0, increasing to 1"); - config->ar2rMaxPipeline = 1; - } - else if ((config->ar2rMaxPipeline) > axiPipelineFifoDepth) { - vDbgMsg(DBG_GEN_MSG, 5, "*** Warning: ar2rMaxPipeline requested"\ - "value (%u) greater than fifo depth (%u), reducing to %u\n", - config->ar2rMaxPipeline, axiPipelineFifoDepth, axiPipelineFifoDepth); - config->ar2rMaxPipeline = axiPipelineFifoDepth; - } - EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MODIFY( - regData, config->ar2rMaxPipeline); - - CPS_UncachedWrite32(CEDI_RegAddr(axi_max_pipeline), regData); -} - -/* Initialise Network Control register from config struct */ -static void initNetControlReg(void *pD) -{ - CEDI_Config *config = &CEDI_PdVar(cfg); - uint32_t regTmp; - - /* Disable everything first to be safe */ - regTmp = 0; - CPS_UncachedWrite32(CEDI_RegAddr(network_control), regTmp); - - if (config->enableMdio) - EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SET(regTmp); - - if (config->altSgmiiEn) - EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SET(regTmp); - - if (config->storeUdpTcpOffset) - EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SET(regTmp); - - /* for ext. TSU require tsu configured */ - if ((config->enExtTsuPort) && CEDI_PdVar(hwCfg).tsu) - EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SET(regTmp); - /* pfc multi quantum functionality */ - if(config->pfcMultiQuantum) - EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SET(regTmp); - /* clear stats */ - EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SET(regTmp); - - CPS_UncachedWrite32(CEDI_RegAddr(network_control), regTmp); -} - -/* Initialise DMA Config register from config struct */ -static void initDmaConfigReg(void *pD) -{ - CEDI_Config *config = &CEDI_PdVar(cfg); - uint32_t regTmp = 0, tmp1; - - switch(config->dmaDataBurstLen) { - case CEDI_DMA_DBUR_LEN_1: - tmp1 = CEDI_AMBD_BURST_LEN_1; - break; - case CEDI_DMA_DBUR_LEN_4: - tmp1 = CEDI_AMBD_BURST_LEN_4; - break; - case CEDI_DMA_DBUR_LEN_8: - tmp1 = CEDI_AMBD_BURST_LEN_8; - break; - case CEDI_DMA_DBUR_LEN_16: - tmp1 = CEDI_AMBD_BURST_LEN_16; - break; - default: - tmp1 = CEDI_AMBD_BURST_LEN_4; - break; - } - EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MODIFY(regTmp, tmp1); - - if (config->dmaEndianism & CEDI_END_SWAP_DESC) - EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SET(regTmp); - if (config->dmaEndianism & CEDI_END_SWAP_DATA) - EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SET(regTmp); - - EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MODIFY(regTmp, config->rxPktBufSize); - EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MODIFY(regTmp, config->txPktBufSize); - - if (config->chkSumOffEn & CEDI_CFG_CHK_OFF_TX) - EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SET(regTmp); - - EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MODIFY(regTmp, config->rxBufLength[0]); - - if (config->dmaCfgFlags & CEDI_CFG_DMA_DISC_RXP) - EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SET(regTmp); - - if (config->dmaCfgFlags & CEDI_CFG_DMA_FRCE_RX_BRST) - EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SET(regTmp); - - if (config->dmaCfgFlags & CEDI_CFG_DMA_FRCE_TX_BRST) - EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SET(regTmp); - - if (config->dmaAddrBusWidth) - EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SET(regTmp); - - if (config->enTxExtBD) - EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SET(regTmp); - - if (config->enRxExtBD) - EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SET(regTmp); - - CPS_UncachedWrite32(CEDI_RegAddr(dma_config), regTmp); -} - -/* Initialise Network Config register from config struct */ -static void initNetConfigReg(void *pD) -{ - CEDI_Config *config = &CEDI_PdVar(cfg); - uint32_t regTmp = 0; - - if ((config->ifTypeSel==CEDI_IFSP_1000M_GMII) || - (config->ifTypeSel==CEDI_IFSP_1000M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_1000BASE_X)) - EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SET(regTmp); - - if ((config->ifTypeSel==CEDI_IFSP_10M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_100M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_1000M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_1000BASE_X)) - EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SET(regTmp); - - if ((config->ifTypeSel==CEDI_IFSP_10M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_100M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_1000M_SGMII)) - EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SET(regTmp); - - if (config->uniDirEnable) - EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SET(regTmp); - - if ((config->ifTypeSel != CEDI_IFSP_10M_MII) && - (config->ifTypeSel != CEDI_IFSP_10M_SGMII)) - EMAC_REGS__NETWORK_CONFIG__SPEED__SET(regTmp); - - if (config->fullDuplex) - EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SET(regTmp); - - if (config->enRxHalfDupTx) - EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SET(regTmp); - - if (config->ignoreIpgRxEr) - EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SET(regTmp); - - if (config->enRxBadPreamble) - EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__SET(regTmp); - - if (config->rxJumboFrEn) - EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SET(regTmp); - - if (config->rx1536ByteEn) - EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SET(regTmp); - - if (config->extAddrMatch) - EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SET(regTmp); - - EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MODIFY(regTmp, - config->rxBufOffset); - - if (config->rxLenErrDisc) - EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SET( - regTmp); - - EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MODIFY(regTmp, - config->mdcPclkDiv); - - EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MODIFY(regTmp, - config->dmaBusWidth); - - if (config->disCopyPause) - EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SET(regTmp); - - if (config->chkSumOffEn & CEDI_CFG_CHK_OFF_RX) - EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SET(regTmp); - - CPS_UncachedWrite32(CEDI_RegAddr(network_config), regTmp); -} - - -/* set Rx buffer sizes for Q>0 */ -static void setRxQBufferSizes(void *pD, const CEDI_Config *config) -{ -#define CEDI_WR_RXQB_SIZE_N_CASE(Q) \ - case Q: CPS_UncachedWrite32(CEDI_RegAddr(dma_rxbuf_size_q##Q), reg);\ - break; - - uint32_t reg, q; - if (CEDI_PdVar(cfg).rxQs>1) - for (q=1; q<=CEDI_PdVar(cfg).rxQs; q++) { - reg = 0; - EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MODIFY( - reg, config->rxBufLength[q]); - switch(q) { - CEDI_WR_RXQB_SIZE_N_CASE(1); - CEDI_WR_RXQB_SIZE_N_CASE(2); -/* // Three queues are supported - CEDI_WR_RXQB_SIZE_N_CASE(3); - CEDI_WR_RXQB_SIZE_N_CASE(4); - CEDI_WR_RXQB_SIZE_N_CASE(5); - CEDI_WR_RXQB_SIZE_N_CASE(6); - CEDI_WR_RXQB_SIZE_N_CASE(7); - CEDI_WR_RXQB_SIZE_N_CASE(8); - CEDI_WR_RXQB_SIZE_N_CASE(9); - CEDI_WR_RXQB_SIZE_N_CASE(10); - CEDI_WR_RXQB_SIZE_N_CASE(11); - CEDI_WR_RXQB_SIZE_N_CASE(12); - CEDI_WR_RXQB_SIZE_N_CASE(13); - CEDI_WR_RXQB_SIZE_N_CASE(14); - CEDI_WR_RXQB_SIZE_N_CASE(15); -*/ - } - } -} - -/***************** Hardware Revision Compatibility Tests *******************/ - -/* Return non-zero if h/w includes stateless offloads */ -uint32_t offloadsSupport(void *pD) -{ - if (pD==NULL) - return 0; - else - return (((CEDI_PdVar(hwCfg).moduleId==GEM_GXL_MODULE_ID_V0) - || (CEDI_PdVar(hwCfg).moduleId==GEM_GXL_MODULE_ID_V1)) - && (CEDI_PdVar(hwCfg).moduleRev>=OFFLOADS_GEM_GXL_REV)); -} - -/* Return non-zero if h/w includes 24bit sub-ns timer increment resolution */ -uint32_t subNsTsuInc24bSupport(void *pD) -{ - if (pD==NULL) - return 0; - else - /* resolution increase came in at r1p06f2 */ - return (((CEDI_PdVar(hwCfg).moduleId==GEM_GXL_MODULE_ID_V0) - && (CEDI_PdVar(hwCfg).moduleRev==0x0106) - && (CEDI_PdVar(hwCfg).fixNumber>=2)) - || ((CEDI_PdVar(hwCfg).moduleId==GEM_GXL_MODULE_ID_V0) - && (CEDI_PdVar(hwCfg).moduleRev>0x0106)) - || (CEDI_PdVar(hwCfg).moduleId>=GEM_GXL_MODULE_ID_V1)); -} - -/* Read DesignConfig Debug registers into privateData for faster access. - * pD must point to a privateData struct with cfg.regBase set */ -uint32_t readDesignConfig(void *pD) -{ - uint32_t reg; - - if (pD==NULL) - return EINVAL; - - /* read in revision & number of queues, which are also set by defs file */ - CEDI_PdVar(hwCfg).numQueues = maxHwQs(CEDI_PdVar(cfg).regBase); - - reg = CPS_UncachedRead32(CEDI_RegAddr(revision_reg)); - - CEDI_PdVar(hwCfg).moduleId = - EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__READ(reg); - CEDI_PdVar(hwCfg).moduleRev = - EMAC_REGS__REVISION_REG__MODULE_REVISION__READ(reg); - CEDI_PdVar(hwCfg).fixNumber = -#ifdef EMAC_REGS__REVISION_REG__FIX_NUMBER__READ - EMAC_REGS__REVISION_REG__FIX_NUMBER__READ(reg); -#else - 0; -#endif - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug1)); - CEDI_PdVar(hwCfg).no_pcs = - EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__READ(reg); -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__SERDES__READ - CEDI_PdVar(hwCfg).serdes = - EMAC_REGS__DESIGNCFG_DEBUG1__SERDES__READ(reg); -#endif -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__RDC_50__READ - CEDI_PdVar(hwCfg).RDC_50 = - EMAC_REGS__DESIGNCFG_DEBUG1__RDC_50__READ(reg); -#endif -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__TDC_50__READ - CEDI_PdVar(hwCfg).TDC_50 = - EMAC_REGS__DESIGNCFG_DEBUG1__TDC_50__READ(reg); -#endif - CEDI_PdVar(hwCfg).int_loopback = - EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__READ(reg); -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__NO_INT_LOOPBACK__READ - CEDI_PdVar(hwCfg).no_int_loopback = - EMAC_REGS__DESIGNCFG_DEBUG1__NO_INT_LOOPBACK__READ(reg); -#else - CEDI_PdVar(hwCfg).no_int_loopback = !CEDI_PdVar(hwCfg).int_loopback; -#endif - CEDI_PdVar(hwCfg).ext_fifo_interface = - EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__READ(reg); - -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__APB_REV1__READ - CEDI_PdVar(hwCfg).apb_rev1 = - EMAC_REGS__DESIGNCFG_DEBUG1__APB_REV1__READ(reg); -#endif -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__APB_REV2__READ - CEDI_PdVar(hwCfg).apb_rev2 = - EMAC_REGS__DESIGNCFG_DEBUG1__APB_REV2__READ(reg); -#endif - CEDI_PdVar(hwCfg).user_io = - EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__READ(reg); - CEDI_PdVar(hwCfg).user_out_width = - EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__READ(reg); - CEDI_PdVar(hwCfg).user_in_width = - EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__READ(reg); -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__NO_SCAN_PINS__READ - CEDI_PdVar(hwCfg).no_scan_pins = - EMAC_REGS__DESIGNCFG_DEBUG1__NO_SCAN_PINS__READ(reg); -#endif - CEDI_PdVar(hwCfg).no_stats = - EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__READ(reg); - CEDI_PdVar(hwCfg).no_snapshot = - EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__READ(reg); - CEDI_PdVar(hwCfg).irq_read_clear = - EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__READ(reg); -#ifdef EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__READ - /* need both compile-time test for macro and runtime test for feature - support, to allow regression against older h/w */ - if (offloadsSupport(pD)) - CEDI_PdVar(hwCfg).exclude_cbs = - EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__READ(reg); -#else - CEDI_PdVar(hwCfg).exclude_cbs = 0; -#endif - CEDI_PdVar(hwCfg).dma_bus_width = - EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__READ(reg); - CEDI_PdVar(hwCfg).axi_cache_value = - EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug2)); - CEDI_PdVar(hwCfg).jumbo_max_length = - EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__READ(reg); - CEDI_PdVar(hwCfg).hprot_value = - EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__READ(reg); - CEDI_PdVar(hwCfg).rx_pkt_buffer = - EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__READ(reg); - CEDI_PdVar(hwCfg).tx_pkt_buffer = - EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__READ(reg); - CEDI_PdVar(hwCfg).rx_pbuf_addr = - EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_addr = - EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__READ(reg); - CEDI_PdVar(hwCfg).axi = - EMAC_REGS__DESIGNCFG_DEBUG2__AXI__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug3)); - CEDI_PdVar(hwCfg).num_spec_add_filters = - EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug5)); - CEDI_PdVar(hwCfg).rx_fifo_cnt_width = - EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__READ(reg); - CEDI_PdVar(hwCfg).tx_fifo_cnt_width = - EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__READ(reg); - CEDI_PdVar(hwCfg).tsu = - EMAC_REGS__DESIGNCFG_DEBUG5__TSU__READ(reg); - CEDI_PdVar(hwCfg).phy_ident = - EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__READ(reg); - CEDI_PdVar(hwCfg).dma_bus_width_def = - EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__READ(reg); - CEDI_PdVar(hwCfg).mdc_clock_div = - EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__READ(reg); - CEDI_PdVar(hwCfg).endian_swap_def = - EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__READ(reg); - CEDI_PdVar(hwCfg).rx_pbuf_size_def = - EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_size_def = - EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__READ(reg); - CEDI_PdVar(hwCfg).rx_buffer_length_def = - EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__READ(reg); - CEDI_PdVar(hwCfg).tsu_clk = - EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__READ(reg); - CEDI_PdVar(hwCfg).axi_prot_value = - EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug6)); - CEDI_PdVar(hwCfg).tx_pbuf_queue_segment_size = - EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__READ(reg); - CEDI_PdVar(hwCfg).ext_tsu_timer = - EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__READ(reg); - CEDI_PdVar(hwCfg).tx_add_fifo_if = - EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__READ(reg); - CEDI_PdVar(hwCfg).host_if_soft_select = - EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__READ(reg); - CEDI_PdVar(hwCfg).dma_addr_width = - EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__READ(reg); - CEDI_PdVar(hwCfg).pfc_multi_quantum = - EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__READ(reg); - /* Offloads features: first available in GEM_GXL rev 1p07- */ - if (offloadsSupport(pD)) { -#ifdef EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__READ - CEDI_PdVar(hwCfg).pbuf_lso = - EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__READ(reg); -#else - CEDI_PdVar(hwCfg).pbuf_lso = 0; -#endif -#ifdef EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__READ - CEDI_PdVar(hwCfg).pbuf_rsc = - EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__READ(reg); -#else - CEDI_PdVar(hwCfg).pbuf_rsc = 0; -#endif - CEDI_PdVar(hwCfg).intrpt_mod = 1; - CEDI_PdVar(hwCfg).hdr_split = 1; - } else { - CEDI_PdVar(hwCfg).pbuf_lso = 0; - CEDI_PdVar(hwCfg).pbuf_rsc = 0; - CEDI_PdVar(hwCfg).intrpt_mod = 0; - CEDI_PdVar(hwCfg).hdr_split = 0; - } - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug7)); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q0 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q1 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q2 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q3 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q4 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q5 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q6 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q7 = - EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug8)); - CEDI_PdVar(hwCfg).num_type1_screeners = - EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__READ(reg); - CEDI_PdVar(hwCfg).num_type2_screeners = - EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__READ(reg); - CEDI_PdVar(hwCfg).num_scr2_ethtype_regs = - EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__READ(reg); - CEDI_PdVar(hwCfg).num_scr2_compare_regs = - EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug9)); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q8 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q9 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q10 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q11 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q12 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q13 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q14 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_num_segments_q15 = - EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__READ(reg); - - reg = CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug10)); - CEDI_PdVar(hwCfg).axi_access_pipeline_bits = - EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__READ(reg); - CEDI_PdVar(hwCfg).rx_pbuf_data = - EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__READ(reg); - CEDI_PdVar(hwCfg).tx_pbuf_data = - EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__READ(reg); - - return 0; -} - -/****************************************************************************** - * Public Driver functions - * ***************************************************************************/ - -uint32_t emacProbe(CEDI_Config *config, CEDI_SysReq *sysReq) -{ - uint32_t regTmp, regVal; - uint16_t txDescSize, rxDescSize, sumTxDesc, sumRxDesc; - struct emac_regs *regAddr; - uint8_t paramErr = 0, numQs; - uint16_t i; - - if ((config==NULL) || (sysReq==NULL)) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: NULL parameter supplied"); - return EINVAL; - } - - vDbgMsg(DBG_GEN_MSG, 10, "%s entered (regBase %p)\n", __func__, - (void *)config->regBase); - - if (config->regBase % sizeof(uint32_t)) { - vDbgMsg(DBG_GEN_MSG, 5, - "%s\n", "Error: regBase address not 32-bit aligned"); - return EINVAL; - } - - /* Module ID check */ - regAddr = ((struct emac_regs *)(config->regBase)); - regVal = CPS_UncachedRead32(&(regAddr->revision_reg)); - regTmp = EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__READ( - regVal); - if ((regTmp!=GEM_GXL_MODULE_ID_V0) && - (regTmp!=GEM_GXL_MODULE_ID_V1) && - (regTmp!=GEM_XL_MODULE_ID)) { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: Module ID check failed - 0x%04X read, IP type not supported\n", - regTmp); -#ifndef SANITY_CHECK_TESTS - return EINVAL; -#endif //SANITY_CHECK_TESTS - } - else -#ifdef EMAC_REGS__REVISION_REG__FIX_NUMBER__READ - vDbgMsg(DBG_GEN_MSG, 10, - "Module ID = 0x%03X, design rev = 0x%04X, fix no. = %u\n", - regTmp, - EMAC_REGS__REVISION_REG__MODULE_REVISION__READ(regVal), - EMAC_REGS__REVISION_REG__FIX_NUMBER__READ(regVal) - ); -#else - vDbgMsg(DBG_GEN_MSG, 10, "Module ID = 0x%04X, design rev = 0x%04X\n", regTmp, - EMAC_REGS__REVISION_REG__MODULE_REVISION__READ(regVal)); -#endif - - /* required config parameters range checking */ - paramErr = ((config->rxQs==0) || (config->txQs==0)); - - /* limit numbers of queues to what is available */ - numQs = maxHwQs(config->regBase); - if (config->rxQs>numQs) { - vDbgMsg(DBG_GEN_MSG, 10, - "Warning: Too many Rx queues requested (%u), only %u in h/w config\n", - config->rxQs, numQs); - config->rxQs = numQs; - } - if (config->txQs>numQs) { - vDbgMsg(DBG_GEN_MSG, 10, - "Warning: Too many Tx queues requested (%u), only %u in h/w config\n", - config->txQs, numQs); - config->txQs = numQs; - } - - regTmp = EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__READ( - CPS_UncachedRead32(&(regAddr->designcfg_debug6))); - - // DMA address bus width. 0 =32b , 1=64b - if ((config->dmaAddrBusWidth) && (!regTmp)) - { - vDbgMsg(DBG_GEN_MSG, 10, "%s\n", - "Warning: 64-bit DMA addressing not supported in h/w config"); - config->dmaAddrBusWidth = 0; - } - - for (i=0; irxQs; i++) - { - if (config->rxQLen[i]>CEDI_MAX_RBQ_LENGTH) - { - vDbgMsg(DBG_GEN_MSG, 10, - "config->rxQLen(%u) (=%u) greater than maximum limit (%u)\n", - i, config->rxQLen[i], CEDI_MAX_RBQ_LENGTH); - paramErr = 1; - break; - } - } - if (!paramErr) - for (i=0; itxQs; i++) - { - if (config->txQLen[i]>CEDI_MAX_TBQ_LENGTH) - { - vDbgMsg(DBG_GEN_MSG, 10, - "config->txQLen(%u) (=%u) greater than maximum limit (%u)\n", - i, config->txQLen[i], CEDI_MAX_TBQ_LENGTH); - paramErr = 1; - break; - } - } - - if (paramErr) - { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: parameter out of range"); - return EINVAL; - } - - /* required memory allocations */ - - /* descriptor list sizes */ - calcDescriptorSizes(config, &txDescSize, &rxDescSize); - - sumTxDesc = numTxDescriptors(config); - sysReq->txDescListSize = sumTxDesc * txDescSize; - vDbgMsg(DBG_GEN_MSG, 10, "txQSize = %u\n", sysReq->txDescListSize); - vDbgMsg(DBG_GEN_MSG, 10, "txDescSize = %u bytes\n", txDescSize); - - sumRxDesc = numRxDescriptors(config); - sysReq->rxDescListSize = sumRxDesc * rxDescSize; - vDbgMsg(DBG_GEN_MSG, 10, "rxQSize = %u\n", sysReq->rxDescListSize); - vDbgMsg(DBG_GEN_MSG, 10, "rxDescSize = %u bytes\n", rxDescSize); - - /* privateData including vAddr lists */ - sysReq->privDataSize = sizeof(CEDI_PrivateData) - + sizeof(uintptr_t)*(sumTxDesc+sumRxDesc); - vDbgMsg(DBG_GEN_MSG, 10, "privDataSize = %u bytes\n", - sysReq->privDataSize); - sysReq->statsSize = sizeof(CEDI_Statistics); - vDbgMsg(DBG_GEN_MSG, 10, "statsSize = %u bytes\n", - sysReq->statsSize); - - return 0; -} - -uint32_t emacInit(void *pD, const CEDI_Config *config, - CEDI_Callbacks *callbacks) -{ -#define CEDI_ADD_TX_PBUF_SEGS(Q) if (CEDI_PdVar(numQs)>Q)\ - numQSegs += 1<regBase); - - /* parameter validation */ - if ((pD==NULL) || (config==NULL) || (callbacks==NULL)) - { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: NULL main parameter"); - return EINVAL; - } - - if (!paramErr) - { - /* Copy config & callbacks into private data */ - ((CEDI_PrivateData *)pD)->cfg = *config; - ((CEDI_PrivateData *)pD)->cb = *callbacks; - - paramErr = callbacksNullCheck(pD, config->intrEnable); - - if (paramErr) - vDbgMsg(DBG_GEN_MSG, 5, - "Error: Callback =NULL for event(s) 0x%08X\n", paramErr); - - readDesignConfig(pD); - - initAllRegs(pD); - } - - if (!paramErr) { - CEDI_PdVar(numQs) = CEDI_PdVar(hwCfg).numQueues; - if ((config->rxQs==0) || (config->rxQs>CEDI_PdVar(numQs)) || - (config->txQs==0) || (config->txQs>CEDI_PdVar(numQs))) - { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: out-of-range numQs parameter"); - paramErr = 1; - } - } - - if (!paramErr) - for (i=0; irxQs; i++) - { - if (config->rxQLen[i]>CEDI_MAX_RBQ_LENGTH) - { - paramErr = 1; - vDbgMsg(DBG_GEN_MSG, 5, - "Error: out-of-range rxQLen(%u) parameter\n", i); - break; - } - } - - if (!paramErr) { - if ((config->txQAddr==(uintptr_t)NULL) || - (config->txQPhyAddr==0) || - (config->rxQAddr==(uintptr_t)NULL) || - (config->rxQPhyAddr==0)) - { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: NULL Tx or Rx descriptor address parameter"); - paramErr = 1; - } - } - - if (!paramErr) - for (i=0; itxQs; i++) - { - if (config->txQLen[i]>CEDI_MAX_TBQ_LENGTH) - { - paramErr = 1; - vDbgMsg(DBG_GEN_MSG, 5, - "Error: out-of-range txQLen(%u) parameter\n", i); - break; - } - } - - if (!paramErr) { - if ((config->dmaAddrBusWidth) && - (!((CEDI_PrivateData *)pD)->hwCfg.dma_addr_width)) - { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: 64-bit DMA addressing not supported in h/w config"); - paramErr = 1; - } - } - - if (!paramErr) { - paramErr = ((config->txPktBufSize>1) || (config->rxPktBufSize>3)); - if (!paramErr) - for (i=0; irxQs; i++) { - paramErr = paramErr || (config->rxBufLength[i]==0); - } - if (paramErr) - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: Invalid Packet buffer size or Rx buffer length"); - } - - if (!paramErr) { - if (config->dmaDataBurstLen>CEDI_DMA_DBUR_LEN_16) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: Requested DMA burst length value out of range"); - paramErr = 1; - } - } - - if (!paramErr) { - vDbgMsg(DBG_GEN_MSG, 10, "1 << config->dmaBusWidth = %u, "\ - "CEDI_PdVar(hwCfg).dma_bus_width = %u\n", - 1 << config->dmaBusWidth, CEDI_PdVar(hwCfg).dma_bus_width); - if ((1 << config->dmaBusWidth)>CEDI_PdVar(hwCfg).dma_bus_width) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: Requested DMA bus width greater than h/w allows"); - paramErr = 1; - } - } - - if (!paramErr) { - // enforce 32- or 64-bit alignment for RX buffers only - if (config->dmaBusWidth==CEDI_DMA_BUS_WIDTH_32) - paramErr = ((config->rxQPhyAddr) % 4); - else /* expect 64-bit word alignment for 64/128-bit bus */ - paramErr = ((config->rxQPhyAddr) % 8); - - if (paramErr) - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", - "Error: bad alignment of descriptor list memory"); - } - - if (!paramErr) { - if (0!=(paramErr = config->ifTypeSel>CEDI_IFSP_1000BASE_X)) - { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: ifTypeSel out of range 0-CEDI_IFSP_1000BASE_X (%u)\n", - CEDI_PdVar(cfg).ifTypeSel); - } - } - - if (!paramErr) { - if (0!=(paramErr = CEDI_PdVar(cfg).rxBufOffset>3)) - { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: rxBufOffset out of range 0-3 bytes (%u)\n", - CEDI_PdVar(cfg).rxBufOffset); - } - } - - if (!paramErr) { - if (0!=(paramErr = config->mdcPclkDiv>CEDI_MDC_DIV_BY_224)) - { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: mdcPclkDiv out of range (%u)\n", - config->mdcPclkDiv); - } - } - - if (!paramErr && (0==CEDI_PdVar(hwCfg).no_stats)) { - paramErr = (config->statsRegs==(uintptr_t)NULL); - if (paramErr) - vDbgMsg(DBG_GEN_MSG, 5, "%s", - "Error: NULL statistics struct address\n"); - } - - if (!paramErr && (0==CEDI_PdVar(hwCfg).pfc_multi_quantum)) { - paramErr = (config->pfcMultiQuantum == 1); - if (paramErr) - vDbgMsg(DBG_GEN_MSG, 5, "%s", - "Error: pfc Multiple quantum not supported by h/w\n"); - } - - /* sanity-check multi-queue packet buffer segments and distribution */ - if ((CEDI_PdVar(numQs)>1) && (CEDI_PdVar(hwCfg).tx_pkt_buffer)) - { - if (CEDI_PdVar(hwCfg).tx_pbuf_queue_segment_size>= - CEDI_PdVar(hwCfg).tx_pbuf_addr) { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: H/w configuration specifies Tx segment size %u, "\ - "must be less than Tx pbuf addr (%u)\n", - CEDI_PdVar(hwCfg).tx_pbuf_queue_segment_size, - CEDI_PdVar(hwCfg).tx_pbuf_addr); - hwConfigErr = 1; - } - - numTxSegs = 1<numTxSegs) { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: H/w configuration allocates %u Tx packet buffer"\ - " segments to queues out of %u total\n", numQSegs, numTxSegs); - hwConfigErr = 1; - } - } - - - /* Need PCS present for these interface types */ - if (((config->ifTypeSel==CEDI_IFSP_10M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_100M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_1000M_SGMII) || - (config->ifTypeSel==CEDI_IFSP_1000BASE_X)) - && (EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__READ( - CPS_UncachedRead32(CEDI_RegAddr(designcfg_debug1))))) { - - vDbgMsg(DBG_GEN_MSG, 5, - "Error: config struct specifies interface type (%u) which requires"\ - " PCS but this is not present in EMAC h/w\n", config->ifTypeSel); - hwConfigErr = 1; - } - - if (hwConfigErr) - return ENOTSUP; - else if (paramErr) - return EINVAL; - - /****************** Initialise driver internal data ************************/ - - ((CEDI_PrivateData *)pD)->anLinkStat = 0; - ((CEDI_PrivateData *)pD)->anRemFault = 0; - ((CEDI_PrivateData *)pD)->autoNegActive = 0; - ((CEDI_PrivateData *)pD)->basePageExp = 1; - - /* ensure all interrupt sources disabled */ - disableAllInterrupts(pD); - /* ensure ISRs are cleared */ - clearAllInterrupts(pD); - - /****************** Initialise Tx & Rx descriptor lists ********************/ - - calcDescriptorSizes(config, &CEDI_PdVar(txDescriptorSize), - &CEDI_PdVar(rxDescriptorSize)); - - /* DMA config register */ - initDmaConfigReg(pD); - - /* writing the upper 32 bit buffer queue base address from config */ - initUpper32BuffQAddr(pD); - - if (0!=initTxDescLists(pD)) - return EINVAL; - if (0!=initRxDescLists(pD)) - return EINVAL; - - /****************************** Initialise hardware ************************/ - - /* Network control register */ - initNetControlReg(pD); - - /* Network config register */ - initNetConfigReg(pD); - - /* AXI Max pipeline register */ - if(ETH_AXI_MASTER_PRESENT == 1) - { - initAxiMaxPipelineReg(pD); - } - - setRxQBufferSizes(pD, config); - - /* Ensure specific address registers disabled */ - for (i=1; i<=CEDI_PdVar(hwCfg).num_spec_add_filters; i++) - emacDisableSpecAddr(pD, i); - - /* and screener registers */ - for (i=0; icfg).regBase, - EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__READ(regVal), - EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__READ(regVal), - cond1?"read":"write", - dat16); - - (*(CEDI_PdVar(cb).phyManComplete))(pD, cond1, dat16); - } - - /****************************** TxEvent ****************************/ - cond1 = 0; - cond2 = 0; - - if (qNum==0) { - cond1 = EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__READ(isrReg); - cond2 = EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__READ(isrReg); - } - else { - cond1 = 0; - cond2 = EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__READ(isrReg); - } - if (cond1 || cond2) - { - events = cond1?CEDI_EV_TX_USED_READ:0; - events |= cond2?CEDI_EV_TX_COMPLETE:0; - - /* report both events in one callback call */ - /*vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) Tx Event:0x%08X queue:%u\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events, qNum);*/ - - (*(CEDI_PdVar(cb).txEvent))(pD, events, qNum); - } - - /****************************** TxError ****************************/ - cond1 = 0; - cond2 = 0; - cond3 = 0; - - if (qNum==0) { - cond1 = EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__READ(isrReg); - cond2 = - EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ( - isrReg); - cond3 = EMAC_REGS__INT_STATUS__AMBA_ERROR__READ(isrReg); - } - else { - cond2 = - EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ( - isrReg); - cond3 = EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__READ(isrReg); - } - if (cond1 || cond2 || cond3) - { - events = cond1?CEDI_EV_TX_UNDERRUN:0; - events |= cond2?CEDI_EV_TX_RETRY_EX_LATE_COLL:0; - events |= cond3?CEDI_EV_TX_FR_CORRUPT:0; - -#ifdef DEBUG - /* read Q ptr for debug */ - switch(qNum) { - default: /* default */ - case 0: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q_ptr)); break; - case 1: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q1_ptr)); break; - case 2: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q2_ptr)); break; - case 3: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q3_ptr)); break; - case 4: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q4_ptr)); break; - case 5: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q5_ptr)); break; - case 6: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q6_ptr)); break; - case 7: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q7_ptr)); break; - case 8: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q8_ptr)); break; - case 9: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q9_ptr)); break; - case 10: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q10_ptr)); break; - case 11: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q11_ptr)); break; - case 12: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q12_ptr)); break; - case 13: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q13_ptr)); break; - case 14: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q14_ptr)); break; - case 15: regVal = CPS_UncachedRead32(CEDI_RegAddr(transmit_q15_ptr)); break; - } - - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) Tx Error:0x%08X queue:%u tx_q_ptr:"\ - "0x%08X isr0=%08X\n", (uint32_t)CEDI_PdVar(cfg).regBase, - events, qNum, regVal, isrReg); -#endif - - (*(CEDI_PdVar(cb).txError))(pD, events, qNum); - } - - /*************************** RxFrame *******************************/ - if (((qNum==0) && - (EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__READ(isrReg))) - || - ((qNum>0) && - (EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__READ(isrReg)))) - { - /*vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) Rx Frame Complete, queue:%u\n", - (uint32_t)CEDI_PdVar(cfg).regBase, qNum);*/ - (*(CEDI_PdVar(cb).rxFrame))(pD, qNum); - } - - /*************************** RxError *******************************/ - cond1 = 0; - cond2 = 0; - - if (qNum==0) { - cond1 = EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__READ(isrReg); - cond2 = EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__READ(isrReg); - } - else { - cond1 = EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__READ(isrReg); - cond2 = EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__READ(isrReg); - } - if (cond1 || cond2) - { - events = cond1?CEDI_EV_RX_USED_READ:0; - events |= cond2?CEDI_EV_RX_OVERRUN:0; - - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) Rx Error:0x%08X queue:%u\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events, qNum); - (*(CEDI_PdVar(cb).rxError))(pD, events, qNum); - } - - /************************ HResp not OK Event ***********************/ - if (((qNum==0) && - (EMAC_REGS__INT_STATUS__RESP_NOT_OK__READ(isrReg))) - || - ((qNum>0) && - (EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__READ(isrReg)))) - { - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) HResp not OK, queue:%u\n", - (uint32_t)CEDI_PdVar(cfg).regBase, qNum); - - (*(CEDI_PdVar(cb).hrespError))(pD, qNum); - } - - /************************* AN LP Page Rx ***************************/ - if ((qNum==0) && - EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__READ(isrReg)) - { - if (CEDI_PdVar(basePageExp)) { - CEDI_PdVar(lpPageRx).nextPage = 0; - /* Read base page data */ - emacGetLpAbilityPage(pD, &CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage); - } - else { - CEDI_PdVar(lpPageRx).nextPage = 1; - /* Read next page data */ - emacGetLpNextPage(pD, &CEDI_PdVar(lpPageRx).lpPageDat.lpNextPage); - } - - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) AN Link Partner %s Page Rx\n", - (uint32_t)CEDI_PdVar(cfg).regBase, - CEDI_PdVar(basePageExp)?"Base":"Next"); - if (CEDI_PdVar(basePageExp)) - vDbgMsg(DBG_GEN_MSG, 10, "LpNextPage: %u LpAck: %u FullDuplex: %u HalfDuplex: %u Pause Capability: %u RemoteFault: %u\n", - CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage.ablInfo.defLpAbl.lpNextPage, - CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage.ablInfo.defLpAbl.lpAck, - CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage.ablInfo.defLpAbl.fullDuplex, - CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage.ablInfo.defLpAbl.halfDuplex, - CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage.ablInfo.defLpAbl.pauseCap, - CEDI_PdVar(lpPageRx).lpPageDat.lpBasePage.ablInfo.defLpAbl.remFlt); - - /* write Null message next page as default, can be overridden in callback or later */ - nullNp.ack2 = 0; - nullNp.message = 0x001; - nullNp.msgPage = 1; - nullNp.np = 0; - emacSetNextPageTx(pD, &nullNp); - - (*(CEDI_PdVar(cb).lpPageRx))(pD, &CEDI_PdVar(lpPageRx)); - - CEDI_PdVar(basePageExp) = 0; - } - - /************************* AN Complete *****************************/ - if ((qNum==0) && - EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__READ(isrReg)) - { - CEDI_PdVar(basePageExp) = 1; - CEDI_PdVar(autoNegActive) = 0; - - regVal = CPS_UncachedRead32(CEDI_RegAddr(network_status)); - CEDI_PdVar(anStatus).duplexRes = - EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__READ(regVal); - CEDI_PdVar(anStatus).linkState = - EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__READ(regVal); - CEDI_PdVar(anStatus).pauseRxRes = - EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__READ(regVal); - CEDI_PdVar(anStatus).pauseTxRes = - EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__READ(regVal); - - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) Auto-negotiation Complete\n", - (uint32_t)CEDI_PdVar(cfg).regBase); - - (*(CEDI_PdVar(cb).anComplete))(pD, &CEDI_PdVar(anStatus)); - } - - /*********************** Link State Change *************************/ - if ((qNum==0) && EMAC_REGS__INT_STATUS__LINK_CHANGE__READ(isrReg)) - { - if (CEDI_PdVar(autoNegActive)) { - emacGetLinkStatus(pD, &linkState); - } - else { - linkState = EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_status))); - } - - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) Link State changed - state = %u\n", - (uint32_t)CEDI_PdVar(cfg).regBase, linkState); - - (*(CEDI_PdVar(cb).linkChange))(pD, linkState); - } - - /************************ Pause Event ******************************/ - if (qNum==0) { - cond1 = - EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__READ(isrReg); - cond2 = EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__READ(isrReg); - cond3 = - EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__READ(isrReg); - - if (cond1 || cond2 || cond3) - { - events = cond1?CEDI_EV_PAUSE_FRAME_TX:0; - events |= cond2?CEDI_EV_PAUSE_TIME_ZERO:0; - events |= cond3?CEDI_EV_PAUSE_NZ_QU_RX:0; - - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) Pause Event, type:0x%08X\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events); - - (*(CEDI_PdVar(cb).pauseEvent))(pD, events); - } - } - - /***************** PTP Primary Frame Tx Event **********************/ - if (qNum==0) { - cond1 = - EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__READ( - isrReg); - cond2 = EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__READ( - isrReg); - - if (cond1 || cond2) - { - events = cond1?CEDI_EV_PTP_TX_DLY_REQ:0; - events |= cond2?CEDI_EV_PTP_TX_SYNC:0; - - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) PTP Primary Frame Tx, type:0x%08X\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events); - - if (0!=emacGetPtpFrameTxTime(pD, &CEDI_PdVar(ptpTime))) { - CEDI_PdVar(ptpTime).secsUpper = 0; - CEDI_PdVar(ptpTime).secsLower = 0; - CEDI_PdVar(ptpTime).nanosecs = 0; - } - (*(CEDI_PdVar(cb).ptpPriFrameTx))(pD, events, &CEDI_PdVar(ptpTime)); - } - } - - /******************* PTP Peer Frame Tx Event ***********************/ - if (qNum==0) { - cond1 = - EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__READ( - isrReg); - cond2 = - EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__READ( - isrReg); - - if (cond1 || cond2) - { - events = cond1?CEDI_EV_PTP_TX_PDLY_REQ:0; - events |= cond2?CEDI_EV_PTP_TX_PDLY_RSP:0; - - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) PTP Peer Frame Tx, type:0x%08X\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events); - - if (0!=emacGetPtpPeerFrameTxTime(pD, &CEDI_PdVar(ptpTime))) { - CEDI_PdVar(ptpTime).secsUpper = 0; - CEDI_PdVar(ptpTime).secsLower = 0; - CEDI_PdVar(ptpTime).nanosecs = 0; - } - (*(CEDI_PdVar(cb).ptpPeerFrameTx))(pD, events, &CEDI_PdVar(ptpTime)); - } - } - - /***************** PTP Primary Frame Rx Event **********************/ - if (qNum==0) { - cond1 = - EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__READ( - isrReg); - cond2 = EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__READ( - isrReg); - - if (cond1 || cond2) - { - events = cond1?CEDI_EV_PTP_RX_DLY_REQ:0; - events |= cond2?CEDI_EV_PTP_RX_SYNC:0; - - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) PTP Primary Frame Rx, type:0x%08X\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events); - - if (0!=emacGetPtpFrameRxTime(pD, &CEDI_PdVar(ptpTime))) { - CEDI_PdVar(ptpTime).secsUpper = 0; - CEDI_PdVar(ptpTime).secsLower = 0; - CEDI_PdVar(ptpTime).nanosecs = 0; - } - (*(CEDI_PdVar(cb).ptpPriFrameRx))(pD, events, &CEDI_PdVar(ptpTime)); - } - } - - /******************* PTP Peer Frame Rx Event ***********************/ - if (qNum==0) { - cond1 = - EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__READ( - isrReg); - cond2 = - EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__READ( - isrReg); - - if (cond1 || cond2) - { - events = cond1?CEDI_EV_PTP_RX_PDLY_REQ:0; - events |= cond2?CEDI_EV_PTP_RX_PDLY_RSP:0; - - vDbgMsg(DBG_GEN_MSG, 10, - "EMAC (0x%08X) PTP Peer Frame Rx, type:0x%08X\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events); - - if (0!=emacGetPtpPeerFrameRxTime(pD, &CEDI_PdVar(ptpTime))) { - CEDI_PdVar(ptpTime).secsUpper = 0; - CEDI_PdVar(ptpTime).secsLower = 0; - CEDI_PdVar(ptpTime).nanosecs = 0; - } - (*(CEDI_PdVar(cb).ptpPeerFrameRx))(pD, events, &CEDI_PdVar(ptpTime)); - } - } - - /************************* TSU Event *******************************/ - if (qNum==0) { - cond1 = - EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__READ( - isrReg); - cond2 = - EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__READ( - isrReg); - - if (cond1 || cond2) - { - events = cond1?CEDI_EV_TSU_SEC_INC:0; - events |= cond2?CEDI_EV_TSU_TIME_MATCH:0; - - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) TSU Event, type:0x%08X\n", - (uint32_t)CEDI_PdVar(cfg).regBase, events); - - (*(CEDI_PdVar(cb).tsuEvent))(pD, events); - } - } - - /************************* LPI Status Change ***********************/ - if ((qNum==0) && - EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__READ(isrReg)) - { - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) LPI Status change Event\n", - - (uint32_t)CEDI_PdVar(cfg).regBase); - - (*(CEDI_PdVar(cb).lpiStatus))(pD); - } - - /************************* Wake On LAN Event ***********************/ - if ((qNum==0) && EMAC_REGS__INT_STATUS__WOL_INTERRUPT__READ(isrReg)) - { - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) Wake on LAN Event\n", - (uint32_t)CEDI_PdVar(cfg).regBase); - - (*(CEDI_PdVar(cb).wolEvent))(pD); - } - - /****************** External Input Interrupt Event *****************/ - if ((qNum==0) && EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__READ(isrReg)) - { - vDbgMsg(DBG_GEN_MSG, 10, "EMAC (0x%08X) External Input Interrupt\n", - (uint32_t)CEDI_PdVar(cfg).regBase); - - (*(CEDI_PdVar(cb).extInpIntr))(pD); - } - - } /* for qNum */ - } - - if (handled) - return 0; - else - return ECANCELED; -} - -/** - * Enable or disable the specified interrupts. - * @param[in] pD driver private state info specific to this instance - * @param[in] events - * OR'd combination of bit-flags selecting the events to - * be enabled or disabled - * @param[in] enable if equal 1 enable the events, if 0 then disable - * @param[in] queueNum between 0 and config->rxQs-1, or =CEDI_ALL_QUEUES - - * number of Tx or Rx priority queue, relevant to some of - * Tx and Rx events: - * CEDI_EV_TX_COMPLETE, CEDI_EV_TX_FR_CORRUPT, - * CEDI_EV_RX_COMPLETE, CEDI_EV_RX_USED_READ, CEDI_EV_RX_OVERRUN, - * CEDI_EV_HRESP_NOT_OK - * Must be =0 or CEDI_ALL_QUEUES for other events. - * To dis/enable on all available Qs, set queueNum to CEDI_ALL_QUEUES and - * set events to CEDI_EVSET_ALL_Q0_EVENTS. - * @return EINVAL for invalid pD pointer or enable - * @return EINVAL for invalid queueNum - * @return EINVAL for invalid event, - * e.g. CEDI_EV_PAUSE_FRAME_TX when queueNum = 2 - * @return EINVAL for NULL callback for event to be enabled - * @return 0 for success - */ - -uint32_t emacSetEventEnable(void *pD, uint32_t events, uint8_t enable, - uint8_t queueNum) -{ -#define CEDI_ENABLE_INT(Q) if ((queueNum==Q) || (queueNum==CEDI_ALL_QUEUES)) \ - CPS_UncachedWrite32(CEDI_RegAddr(int_q##Q##_enable), regVal); - -#define CEDI_DISABLE_INT(Q) if ((queueNum==Q) || (queueNum==CEDI_ALL_QUEUES))\ - CPS_UncachedWrite32(CEDI_RegAddr(int_q##Q##_disable), regVal); - - uint32_t regVal, paramErr; - - if (pD==NULL) { - vDbgMsg(DBG_GEN_MSG, 5, "%s", "*** Error: NULL pD parameter\n"); - return EINVAL; - } - if ((queueNum>=CEDI_PdVar(numQs)) && (queueNum!=CEDI_ALL_QUEUES)) { - vDbgMsg(DBG_GEN_MSG, 5, - "*** Error: Invalid parameter, queueNum: %u\n", queueNum); - return EINVAL; - } - if (enable>1) { - vDbgMsg(DBG_GEN_MSG, 5, - "*** Error: Invalid parameter, enable: %u\n", enable); - return EINVAL; - } - /* test for invalid events */ - if ((events &(~(((queueNum==0)||(queueNum==CEDI_ALL_QUEUES)) - ?CEDI_EVSET_ALL_Q0_EVENTS:CEDI_EVSET_ALL_QN_EVENTS)))!=0) { - vDbgMsg(DBG_GEN_MSG, 5, - "*** Error: Invalid parameter, events: 0x%08X (queueNum=%u)\n", - events, queueNum); - return EINVAL; - } - - regVal = 0; - - if (events) - { - if (enable) { - paramErr=callbacksNullCheck(pD, events); - if (0 != paramErr) { - vDbgMsg(DBG_GEN_MSG, 5, - "*** Error: Callback =NULL for event(s) 0x%08X\n", paramErr); - return EINVAL; - } - - if ((queueNum==0) || (queueNum==CEDI_ALL_QUEUES)) { - regVal = 0; - if (events & CEDI_EV_MAN_FRAME) - EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_COMPLETE) - EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_USED_READ) - EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_USED_READ) - EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_UNDERRUN) - EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_RETRY_EX_LATE_COLL) - EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_PCS_LINK_CHANGE_DET) - EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PCS_AN_COMPLETE) - EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_PCS_LP_PAGE_RX) - EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(regVal); - - if (events & CEDI_EV_TSU_SEC_INC) - EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(regVal); - - if (events & CEDI_EV_TSU_TIME_MATCH) - EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_FR_CORRUPT) - EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_COMPLETE) - EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_OVERRUN) - EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_HRESP_NOT_OK) - EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PAUSE_NZ_QU_RX) - EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_PAUSE_TIME_ZERO) - EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PAUSE_FRAME_TX) - EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_EXT_INTR) - EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PTP_RX_DLY_REQ) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_RX_SYNC) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_DLY_REQ) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_SYNC) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_PTP_RX_PDLY_REQ) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_RX_PDLY_RSP) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_PDLY_REQ) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_PDLY_RSP) - EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_LPI_CH_RX) - EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_WOL_RX) - EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(regVal); - - CPS_UncachedWrite32(CEDI_RegAddr(int_enable), regVal); - } - if (queueNum>0) { - regVal = 0; - if (events & CEDI_EV_RX_COMPLETE) - EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_USED_READ) - EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_RETRY_EX_LATE_COLL) - EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_FR_CORRUPT) - EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_COMPLETE) - EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_HRESP_NOT_OK) - EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(regVal); - - - /* write to interrupt enable register */ - CEDI_ENABLE_INT(1); - CEDI_ENABLE_INT(2); -/* // Three queues are supported - CEDI_ENABLE_INT(3); - CEDI_ENABLE_INT(4); - CEDI_ENABLE_INT(5); - CEDI_ENABLE_INT(6); - CEDI_ENABLE_INT(7); - CEDI_ENABLE_INT(8); - CEDI_ENABLE_INT(9); - CEDI_ENABLE_INT(10); - CEDI_ENABLE_INT(11); - CEDI_ENABLE_INT(12); - CEDI_ENABLE_INT(13); - CEDI_ENABLE_INT(14); - CEDI_ENABLE_INT(15); -*/ - } - } - else /* enable==0, i.e. disabling specified events */ - { - if ((queueNum==0) || (queueNum==CEDI_ALL_QUEUES)) { - regVal = 0; - if (events & CEDI_EV_MAN_FRAME) - EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_COMPLETE) - EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_USED_READ) - EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_USED_READ) - EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_UNDERRUN) - EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_RETRY_EX_LATE_COLL) - EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_PCS_LINK_CHANGE_DET) - EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PCS_AN_COMPLETE) - EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_PCS_LP_PAGE_RX) - EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(regVal); - - if (events & CEDI_EV_TSU_SEC_INC) - EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(regVal); - - if (events & CEDI_EV_TSU_TIME_MATCH) - EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_FR_CORRUPT) - EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_COMPLETE) - EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_OVERRUN) - EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_HRESP_NOT_OK) - EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PAUSE_NZ_QU_RX) - EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_PAUSE_TIME_ZERO) - EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PAUSE_FRAME_TX) - EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_EXT_INTR) - EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_PTP_RX_DLY_REQ) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_RX_SYNC) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_DLY_REQ) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_SYNC) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_PTP_RX_PDLY_REQ) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_RX_PDLY_RSP) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_PDLY_REQ) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_PTP_TX_PDLY_RSP) - EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(regVal); - - if (events & CEDI_EV_LPI_CH_RX) - EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_WOL_RX) - EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(regVal); - - CPS_UncachedWrite32(CEDI_RegAddr(int_disable), regVal); - } - if (queueNum>0) { - regVal = 0; - if (events & CEDI_EV_RX_COMPLETE) - EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_RX_USED_READ) - EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_TX_RETRY_EX_LATE_COLL) - EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_FR_CORRUPT) - EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET - (regVal); - - if (events & CEDI_EV_TX_COMPLETE) - EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(regVal); - - if (events & CEDI_EV_HRESP_NOT_OK) - EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(regVal); - - - /* write to interrupt disable register */ - CEDI_DISABLE_INT(1); - CEDI_DISABLE_INT(2); -/* // Three queues are supported - CEDI_DISABLE_INT(3); - CEDI_DISABLE_INT(4); - CEDI_DISABLE_INT(5); - CEDI_DISABLE_INT(6); - CEDI_DISABLE_INT(7); - CEDI_DISABLE_INT(8); - CEDI_DISABLE_INT(9); - CEDI_DISABLE_INT(10); - CEDI_DISABLE_INT(11); - CEDI_DISABLE_INT(12); - CEDI_DISABLE_INT(13); - CEDI_DISABLE_INT(14); - CEDI_DISABLE_INT(15); -*/ - } - } - } - return 0; -} - -uint32_t emacGetEventEnable(void *pD, uint8_t queueNum, uint32_t *event) -{ -#define CEDI_READ_INT_MASK_CASE(Q) case Q:\ - regVal = ~CPS_UncachedRead32(CEDI_RegAddr(int_q##Q##_mask)); break; - - uint32_t ret = 0; - uint32_t regVal = 0; - - if ((pD==NULL)||(event==NULL)) - return EINVAL; - - if (queueNum>=CEDI_PdVar(numQs)) - return EINVAL; - - if (queueNum==0) { - regVal = ~CPS_UncachedRead32(CEDI_RegAddr(int_mask)); - if (regVal) { - if (EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_MAN_FRAME; - - if (EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_RX_COMPLETE; - - if (EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_RX_USED_READ; - - if (EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_TX_USED_READ; - - if (EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_TX_UNDERRUN; - - if (EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__READ( - regVal)) - ret |= CEDI_EV_TX_RETRY_EX_LATE_COLL; - - if (EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_PCS_LINK_CHANGE_DET; - - if (EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_PCS_AN_COMPLETE; - - if (EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__READ(regVal)) - ret |= CEDI_EV_PCS_LP_PAGE_RX; - - if (EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__READ( - regVal)) - ret |= CEDI_EV_TSU_SEC_INC; - - if (EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__READ(regVal)) - ret |= CEDI_EV_TSU_TIME_MATCH; - - if (EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_TX_FR_CORRUPT; - - if (EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_TX_COMPLETE; - - if (EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_RX_OVERRUN; - - if (EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_HRESP_NOT_OK; - - if (EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_PAUSE_NZ_QU_RX; - - if (EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_PAUSE_TIME_ZERO; - - if (EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_PAUSE_FRAME_TX; - - if (EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_EXT_INTR; - - if (EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__READ(regVal)) - ret |= CEDI_EV_PTP_RX_DLY_REQ; - - if (EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__READ(regVal)) - ret |= CEDI_EV_PTP_RX_SYNC; - - if (EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__READ( - regVal)) - ret |= CEDI_EV_PTP_TX_DLY_REQ; - - if (EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__READ(regVal)) - ret |= CEDI_EV_PTP_TX_SYNC; - - if (EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__READ( - regVal)) - ret |= CEDI_EV_PTP_RX_PDLY_REQ; - - if (EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__READ( - regVal)) - ret |= CEDI_EV_PTP_RX_PDLY_RSP; - - if (EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__READ( - regVal)) - ret |= CEDI_EV_PTP_TX_PDLY_REQ; - - if (EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__READ( - regVal)) - ret |= CEDI_EV_PTP_TX_PDLY_RSP; - - if (EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__READ(regVal)) - ret |= CEDI_EV_LPI_CH_RX; - - if (EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__READ(regVal)) - ret |= CEDI_EV_WOL_RX; - } - } - else - { - switch(queueNum) { - CEDI_READ_INT_MASK_CASE(1); - CEDI_READ_INT_MASK_CASE(2); -/* // Three queues are supported - CEDI_READ_INT_MASK_CASE(3); - CEDI_READ_INT_MASK_CASE(4); - CEDI_READ_INT_MASK_CASE(5); - CEDI_READ_INT_MASK_CASE(6); - CEDI_READ_INT_MASK_CASE(7); - CEDI_READ_INT_MASK_CASE(8); - CEDI_READ_INT_MASK_CASE(9); - CEDI_READ_INT_MASK_CASE(10); - CEDI_READ_INT_MASK_CASE(11); - CEDI_READ_INT_MASK_CASE(12); - CEDI_READ_INT_MASK_CASE(13); - CEDI_READ_INT_MASK_CASE(14); - CEDI_READ_INT_MASK_CASE(15); -*/ - } - - if (regVal) { - if (EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_RX_COMPLETE; - - if (EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_RX_USED_READ; - - if (EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_TX_RETRY_EX_LATE_COLL; - - if (EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_TX_FR_CORRUPT; - - if (EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ( - regVal)) - ret |= CEDI_EV_TX_COMPLETE; - - if (EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(regVal)) - ret |= CEDI_EV_HRESP_NOT_OK; - } - } - - (*event) = ret; - return 0; -} - -uint32_t emacSetIntrptModerate(void *pD, uint8_t txIntDelay, - uint8_t rxIntDelay) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if ((CEDI_PdVar(hwCfg).intrpt_mod==0) && (txIntDelay || rxIntDelay)) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(int_moderation)); - EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MODIFY(reg, txIntDelay); - EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MODIFY(reg, rxIntDelay); - CPS_UncachedWrite32(CEDI_RegAddr(int_moderation), reg); - return 0; -} - -uint32_t emacGetIntrptModerate(void *pD, uint8_t *txIntDelay, - uint8_t *rxIntDelay) -{ - uint32_t reg; - if ((pD==NULL) || (txIntDelay==NULL) || (rxIntDelay==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).intrpt_mod==0) { - *txIntDelay = 0; - *rxIntDelay = 0; - } else { - reg = CPS_UncachedRead32(CEDI_RegAddr(int_moderation)); - *txIntDelay=EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__READ(reg); - *rxIntDelay=EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__READ(reg); - } - return 0; -} - -uint32_t emacSetIfSpeed(void *pD, CEDI_IfSpeed speedSel) -{ - uint32_t reg; - -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered: speedSel = %u\n", -// __func__, speedSel); - - if (pD==NULL) return EINVAL; -//yots if ((speedSelCEDI_SPEED_1000M)) -//yots return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - switch (speedSel) { - case CEDI_SPEED_10M: - EMAC_REGS__NETWORK_CONFIG__SPEED__CLR(reg); - EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__CLR(reg); - break; - case CEDI_SPEED_100M: - EMAC_REGS__NETWORK_CONFIG__SPEED__SET(reg); - EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__CLR(reg); - break; - case CEDI_SPEED_1000M: - EMAC_REGS__NETWORK_CONFIG__SPEED__CLR(reg); - EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SET(reg); - break; - } - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); - return 0; -} - -uint32_t emacGetIfSpeed(void *pD, CEDI_IfSpeed *speedSel) -{ - uint32_t reg; - - if ((pD==NULL)||(speedSel==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__READ(reg)) - *speedSel = CEDI_SPEED_1000M; - else if (EMAC_REGS__NETWORK_CONFIG__SPEED__READ(reg)) - *speedSel = CEDI_SPEED_100M; - else - *speedSel = CEDI_SPEED_10M; - - return 0; -} - -void emacSetJumboFramesRx(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetJumboFramesRx(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - *enable=EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -uint32_t emacSetJumboFrameRxMaxLen(void *pD, uint16_t length) -{ - uint32_t reg; - uint8_t enabled; - if (pD==NULL) return EINVAL; - if (length>MAX_JUMBO_FRAME_LENGTH) - return EINVAL; - - emacGetJumboFramesRx(pD, &enabled); - reg = CPS_UncachedRead32(CEDI_RegAddr(jumbo_max_length)); - if (enabled) - emacSetJumboFramesRx(pD, 0); - EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MODIFY(reg, length); - CPS_UncachedWrite32(CEDI_RegAddr(jumbo_max_length), reg); - if (enabled) - emacSetJumboFramesRx(pD, 1); - return 0; -} - -uint32_t emacGetJumboFrameRxMaxLen(void *pD, uint16_t *length) -{ - if ((pD==NULL)||(length==NULL)) - return EINVAL; - - *length=EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__READ( - CPS_UncachedRead32(CEDI_RegAddr(jumbo_max_length))); - - return 0; -} - -void emacSetUniDirEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetUniDirEnable(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -uint32_t emacSetTxChecksumOffload(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (!CEDI_PdVar(hwCfg).tx_pkt_buffer) - return EINVAL; - vDbgMsg(DBG_GEN_MSG, 10, "%s entered: enable = %u\n", - __func__, enable); - - reg = CPS_UncachedRead32(CEDI_RegAddr(dma_config)); - if (enable) - EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SET(reg); - else - EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(dma_config), reg); - return 0; -} - -uint32_t emacGetTxChecksumOffload(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__READ( - CPS_UncachedRead32(CEDI_RegAddr(dma_config))); - - return 0; -} - -uint32_t emacSetRxBufOffset(void *pD, uint8_t offset) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (offset>3) return EINVAL; - EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MODIFY(reg, offset); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); - return 0; -} - -uint32_t emacGetRxBufOffset(void *pD, uint8_t *offset) -{ - if ((pD==NULL)||(offset==NULL)) - return EINVAL; - *offset= EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSet1536ByteFramesRx(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGet1536ByteFramesRx(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSetRxChecksumOffload(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - vDbgMsg(DBG_GEN_MSG, 10, "%s entered: enable = %u\n", - __func__, enable); - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetRxChecksumOffload(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSetFcsRemove(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetFcsRemove(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -uint32_t emacSetRxDmaDataAddrMask(void *pD, uint8_t enableBit, - uint8_t bitValues) -{ - uint32_t reg = 0; - if (pD==NULL) return EINVAL; - if ((enableBit>0xf) || (bitValues>0xf)) return EINVAL; - - EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MODIFY(reg, enableBit); - EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MODIFY(reg, bitValues); - CPS_UncachedWrite32(CEDI_RegAddr(dma_addr_or_mask), reg); - return 0; -} - -uint32_t emacGetRxDmaDataAddrMask(void *pD, uint8_t *enableBit, - uint8_t *bitValues) -{ - uint32_t reg; - if (pD==NULL || !enableBit || !bitValues) return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(dma_addr_or_mask)); - *enableBit = EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__READ(reg); - *bitValues = EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__READ(reg); - return 0; -} - -void emacSetRxBadPreamble(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetRxBadPreamble(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSetFullDuplex(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - vDbgMsg(DBG_GEN_MSG, 10, "%s entered: set to %s duplex\n", - __func__, enable?"full":"half"); - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetFullDuplex(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - *enable=EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSetIgnoreFcsRx(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetIgnoreFcsRx(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSetRxHalfDuplexInTx(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetRxHalfDuplexInTx(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - *enable= EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - - -uint32_t emacGetIfCapabilities(void *pD, uint32_t *cap) -{ - if ((pD==NULL)||(cap==NULL)) - return EINVAL; - - *cap = 0; - -// TODO: temporary detection based on header-data splitting until get LSO-related define -#ifdef EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__READ - *cap |= CEDI_CAP_LSO; -#endif -// TODO: RSC, RSS,... - - return EOK; -} - -/******************************** Pause Control ******************************/ - -void emacSetPauseEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetPauseEnable(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacTxPauseFrame(void *pD) -{ - uint32_t reg; - if (pD==NULL) return; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return; -} - -void emacTxZeroQPause(void *pD) -{ - uint32_t reg; - if (pD==NULL) return; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return; -} - -uint32_t emacGetRxPauseQuantum(void *pD, uint16_t *value) -{ - if ((pD==NULL)||(value==NULL)) - return EINVAL; - - *value = EMAC_REGS__PAUSE_TIME__QUANTUM__READ( - CPS_UncachedRead32(CEDI_RegAddr(pause_time))); - return 0; -} - -uint32_t emacSetTxPauseQuantum(void *pD, uint16_t value, uint8_t qpriority) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if (qpriority >= CEDI_QUANTA_PRIORITY_MAX) return EINVAL; - if ((CEDI_PdVar(hwCfg).pfc_multi_quantum==0) - && (qpriority>0)) { - return ENOTSUP; - } - - switch (qpriority) { - default: /* default */ - case 0: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum)); - EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum), reg); - break; - case 1: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum)); - EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum), reg); - break; - case 2: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum1)); - EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum1), reg); - break; - case 3: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum1)); - EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum1), reg); - break; - case 4: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum2)); - EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum2), reg); - break; - case 5: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum2)); - EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum2), reg); - break; - case 6: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum3)); - EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum3), reg); - break; - case 7: - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum3)); - EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MODIFY(reg, value); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pause_quantum3), reg); - break; - } - return EOK; -} - -uint32_t emacGetTxPauseQuantum(void *pD, uint16_t *value, uint8_t qpriority) -{ - if ((pD==NULL)||(value==NULL)) - return EINVAL; - if ((CEDI_PdVar(hwCfg).pfc_multi_quantum==0) - && (qpriority>0)) { - return ENOTSUP; - } - if (qpriority >= CEDI_QUANTA_PRIORITY_MAX) - return EINVAL; - - switch(qpriority){ - default: /* default */ - case 0: - *value= EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum))); - break; - case 1: - *value= EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum))); - break; - case 2: - *value= EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum1))); - break; - case 3: - *value= EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum1))); - break; - case 4: - *value= EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum2))); - break; - case 5: - *value= EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum2))); - break; - case 6: - *value= EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum3))); - break; - case 7: - *value= EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_pause_quantum3))); - break; - } - - return EOK; -} - -void emacSetCopyPauseDisable(void *pD, uint8_t disable) -{ - uint32_t reg; - if (pD==NULL) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (disable) - EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetCopyPauseDisable(void *pD, uint8_t *disable) -{ - if ((pD==NULL)||(disable==NULL)) - return EINVAL; - *disable= EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -void emacSetPfcPriorityBasedPauseRx(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); -} - -uint32_t emacGetPfcPriorityBasedPauseRx(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable = EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - - return 0; -} - -uint32_t emacTxPfcPriorityBasedPause(void *pD) -{ - uint8_t fullDup = 1; - uint32_t reg; - - if (pD==NULL) - return EINVAL; - emacGetFullDuplex(pD, &fullDup); - if ((!fullDup) || !emacGetTxEnabled(pD)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacSetTxPfcPauseFrameFields(void *pD, uint8_t priEnVector, - uint8_t zeroQSelVector) -{ - uint32_t reg = 0; - if (pD==NULL) return EINVAL; - - EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MODIFY(reg, priEnVector); - EMAC_REGS__TX_PFC_PAUSE__VECTOR__MODIFY(reg, zeroQSelVector); - CPS_UncachedWrite32(CEDI_RegAddr(tx_pfc_pause), reg); - return 0; -} - -uint32_t emacGetTxPfcPauseFrameFields(void *pD, uint8_t *priEnVector, - uint8_t *zeroQSelVector) -{ - uint32_t reg = 0; - if ((pD==NULL) || (priEnVector==NULL) || (zeroQSelVector==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(tx_pfc_pause)); - *priEnVector = EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__READ(reg); - *zeroQSelVector = EMAC_REGS__TX_PFC_PAUSE__VECTOR__READ(reg); - return 0; -} - -uint32_t emacSetEnableMultiPfcPauseQuantum(void *pD, uint8_t enMultiPfcPause) -{ - uint32_t regVal = 0; - if (pD==NULL) return EINVAL; - if (enMultiPfcPause>1) return EINVAL; - - if ((CEDI_PdVar(hwCfg).pfc_multi_quantum==0) && (enMultiPfcPause==1)) - return ENOTSUP; - - regVal = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MODIFY(regVal,enMultiPfcPause); - - CPS_UncachedWrite32(CEDI_RegAddr(network_control), regVal); - return 0; -} - -uint32_t emacGetEnableMultiPfcPauseQuantum(void *pD, uint8_t *enMultiPfcPause) -{ - uint32_t regVal = 0; - if ((pD==NULL) || (enMultiPfcPause==NULL)) - return EINVAL; - - regVal = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - *enMultiPfcPause = EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__READ(regVal); - return 0; -} - - -/****************************** Loopback Control *****************************/ - -/** - * Enable or disable loop back mode in the EMAC. - * @param pD - driver private state info specific to this instance - * @param mode - enum selecting mode enable/disable: - * CEDI_SERDES_LOOPBACK :select loopback mode in PHY transceiver, if - * available - * CEDI_LOCAL_LOOPBACK :select internal loopback mode. Tx and Rx should be - * :disabled when enabling or disabling this mode. - * :Only available if int_loopback defined. - * CEDI_NO_LOOPBACK :disable loopback mode - * @return ENOTSUP if CEDI_SERDES_LOOPBACK selected and no_pcs defined, or - * if CEDI_LOCAL_LOOPBACK selected and either - * (no_int_loopback defined or PCS mode is selected) - * @return ENOTSUP if CEDI_LOCAL_LOOPBACK selected and no_int_loopback defined - * @return 0 otherwise. - */ -uint32_t emacSetLoopback(void *pD, uint8_t mode) -{ - uint32_t reg; - uint32_t reg2; - if (pD==NULL) return EINVAL; - if (mode>CEDI_SERDES_LOOPBACK) return EINVAL; - - if ((CEDI_PdVar(hwCfg).no_pcs && (mode==CEDI_SERDES_LOOPBACK)) || - (CEDI_PdVar(hwCfg).no_int_loopback && - (mode==CEDI_LOCAL_LOOPBACK))) - return ENOTSUP; - if ((EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config)))) && - (mode==CEDI_LOCAL_LOOPBACK)) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - reg2 = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - EMAC_REGS__NETWORK_CONTROL__LOOPBACK__CLR(reg); - if (mode==CEDI_LOCAL_LOOPBACK) { - EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SET(reg); - EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__CLR(reg2); - } - else if (mode==CEDI_SERDES_LOOPBACK) { - EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__CLR(reg); - EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SET(reg2); - } - else { /* CEDI_NO_LOOPBACK */ - EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__CLR(reg); - EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__CLR(reg2); - } - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), reg2); - - return 0; -} - -uint32_t emacGetLoopback(void *pD, uint8_t *mode) -{ - uint32_t reg; - uint32_t reg2; - if ((pD==NULL)||(mode==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - reg2 = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - if (EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__READ(reg2)) - *mode= CEDI_SERDES_LOOPBACK; - else - if (EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__READ(reg)) - *mode= CEDI_LOCAL_LOOPBACK; - else - *mode= CEDI_NO_LOOPBACK; - - return 0; -} - -/**************************** PTP/1588 Support *******************************/ - -void emacSetUnicastPtpDetect(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); -} - -uint32_t emacGetUnicastPtpDetect(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - - return 0; -} - -uint32_t emacSetPtpRxUnicastIpAddr(void *pD, uint32_t rxAddr) -{ - uint32_t reg = 0; - uint32_t ret = 0; - uint8_t enabled = 0; - ret = emacGetUnicastPtpDetect(pD, &enabled); - if (ret!=0) - return ret; - if (enabled) - return ENOTSUP; - EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MODIFY(reg, rxAddr); - CPS_UncachedWrite32(CEDI_RegAddr(rx_ptp_unicast), reg); - return 0; -} - -uint32_t emacGetPtpRxUnicastIpAddr(void *pD, uint32_t *rxAddr) -{ - if ((pD==NULL)||(rxAddr==NULL)) - return EINVAL; - *rxAddr= EMAC_REGS__RX_PTP_UNICAST__ADDRESS__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_ptp_unicast))); - - return 0; -} - -uint32_t emacSetPtpTxUnicastIpAddr(void *pD, uint32_t txAddr) -{ - uint32_t reg = 0; - uint32_t ret = 0; - uint8_t enabled = 0; - ret = emacGetUnicastPtpDetect(pD,&enabled); - if (ret!=0) - return ret; - if (enabled) - return ENOTSUP; - EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MODIFY(reg, txAddr); - CPS_UncachedWrite32(CEDI_RegAddr(tx_ptp_unicast), reg); - return 0; -} - -uint32_t emacGetPtpTxUnicastIpAddr(void *pD, uint32_t *txAddr) -{ - if ((pD==NULL)||(txAddr==NULL)) - return EINVAL; - *txAddr= EMAC_REGS__TX_PTP_UNICAST__ADDRESS__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_ptp_unicast))); - - return 0; -} - -uint32_t emacSet1588Timer(void *pD, CEDI_1588TimerVal *time) -{ - uint32_t reg; - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - if (time->nanosecs>0x3FFFFFFF) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_msb_sec)); - EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MODIFY(reg, time->secsUpper); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_msb_sec), reg); - /* write lower bits 2nd, for synchronised secs update */ - reg = 0; - EMAC_REGS__TSU_TIMER_SEC__TIMER__MODIFY(reg, time->secsLower); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_sec), reg); - reg = 0; - EMAC_REGS__TSU_TIMER_NSEC__TIMER__MODIFY(reg, time->nanosecs); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_nsec), reg); - return 0; -} - -uint32_t emacGet1588Timer(void *pD, CEDI_1588TimerVal *time) -{ - uint32_t reg, first; - if ((pD==NULL) || (time==NULL)) return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - first = EMAC_REGS__TSU_TIMER_NSEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_nsec))); - time->secsLower = EMAC_REGS__TSU_TIMER_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_sec))); - time->secsUpper = EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_msb_sec))); - /* test for nsec rollover */ - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_nsec)); - if (first>(EMAC_REGS__TSU_TIMER_NSEC__TIMER__READ(reg))) { - /* if so, use later read & re-read seconds - * (assume all done within 1s) */ - time->nanosecs = EMAC_REGS__TSU_TIMER_NSEC__TIMER__READ(reg); - time->secsLower = EMAC_REGS__TSU_TIMER_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_sec))); - time->secsUpper = EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_msb_sec))); - } - else - time->nanosecs = first; - - return 0; -} - -uint32_t emacAdjust1588Timer(void *pD, int32_t nSecAdjust) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - if ((nSecAdjust<(-0x3FFFFFFF)) || (nSecAdjust>0x3FFFFFFF)) - return EINVAL; - - reg = 0; - if (nSecAdjust<0) { - EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SET(reg); - nSecAdjust = -nSecAdjust; - } - - EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MODIFY(reg, nSecAdjust); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_adjust), reg); - return 0; -} - -uint32_t emacSet1588TimerInc(void *pD, CEDI_TimerIncrement *incSettings) -{ - uint32_t reg; - if ((pD==NULL) || (incSettings==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - -#ifdef EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MODIFY - reg = 0; - EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MODIFY(reg, - incSettings->subNsInc); - if (subNsTsuInc24bSupport(pD)) - EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MODIFY(reg, - incSettings->lsbSubNsInc); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_incr_sub_nsec), reg); - - reg = 0; - EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MODIFY(reg, - incSettings->nanoSecsInc); - EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MODIFY(reg, - incSettings->altNanoSInc); - EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MODIFY(reg, - incSettings->altIncCount); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_incr), reg); - -#else - reg = 0; - EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__TIMER__MODIFY(reg, - incSettings->subNsInc); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_incr_sub_nsec), reg); - - reg = 0; - EMAC_REGS__TSU_TIMER_INCR__COUNT__MODIFY(reg, incSettings->nanoSecsInc); - EMAC_REGS__TSU_TIMER_INCR__ALT_COUNT__MODIFY(reg, - incSettings->altNanoSInc); - EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MODIFY(reg, incSettings->altIncCount); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_timer_incr), reg); -#endif - - return 0; -} - -uint32_t emacGet1588TimerInc(void *pD, CEDI_TimerIncrement *incSettings) -{ - uint32_t reg; - if ((pD==NULL) || (incSettings==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - -#ifdef EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__READ - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_incr_sub_nsec)); - incSettings->subNsInc = - EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__READ(reg); - if (subNsTsuInc24bSupport(pD)) - incSettings->lsbSubNsInc = - EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__READ(reg); - else - incSettings->lsbSubNsInc = 0; - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_incr)); - incSettings->nanoSecsInc = - EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__READ(reg); - incSettings->altNanoSInc = - EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__READ(reg); - incSettings->altIncCount = EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__READ(reg); -#else - incSettings->subNsInc = EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_incr_sub_nsec))); - incSettings->lsbSubNsInc = 0; - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_incr)); - incSettings->nanoSecsInc = EMAC_REGS__TSU_TIMER_INCR__COUNT__READ(reg); - incSettings->altNanoSInc = EMAC_REGS__TSU_TIMER_INCR__ALT_COUNT__READ(reg); - incSettings->altIncCount = EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__READ(reg); -#endif - - return 0; -} - -uint32_t emacSetTsuTimerCompVal(void *pD, CEDI_TsuTimerVal *time) -{ - uint32_t reg; - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - if (time->nanosecs>0x003FFFFF) - return EINVAL; - - reg = 0; - EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MODIFY(reg, time->nanosecs); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_nsec_cmp), reg); - reg = 0; - EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MODIFY(reg, time->secsLower); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_sec_cmp), reg); - reg = 0; - EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MODIFY(reg, time->secsUpper); - CPS_UncachedWrite32(CEDI_RegAddr(tsu_msb_sec_cmp), reg); - return 0; -} - -uint32_t emacGetTsuTimerCompVal(void *pD, CEDI_TsuTimerVal *time) -{ - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - time->nanosecs = EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_nsec_cmp))); - time->secsLower = EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_sec_cmp))); - time->secsUpper = EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_msb_sec_cmp))); - return 0; -} - -uint32_t emacGetPtpFrameTxTime(void *pD, CEDI_1588TimerVal *time) -{ - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - time->nanosecs = EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_ptp_tx_nsec))); - time->secsLower = EMAC_REGS__TSU_PTP_TX_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_ptp_tx_sec))); - time->secsUpper = EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_ptp_tx_msb_sec))); - return 0; -} - -uint32_t emacGetPtpFrameRxTime(void *pD, CEDI_1588TimerVal *time) -{ - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - time->nanosecs = EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_ptp_rx_nsec))); - time->secsLower = EMAC_REGS__TSU_PTP_RX_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_ptp_rx_sec))); - time->secsUpper = EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_ptp_rx_msb_sec))); - return 0; -} - -uint32_t emacGetPtpPeerFrameTxTime(void *pD, CEDI_1588TimerVal *time) -{ - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - time->nanosecs = EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_peer_tx_nsec))); - time->secsLower = EMAC_REGS__TSU_PEER_TX_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_peer_tx_sec))); - time->secsUpper = EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_peer_tx_msb_sec))); - return 0; -} - -uint32_t emacGetPtpPeerFrameRxTime(void *pD, CEDI_1588TimerVal *time) -{ - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - time->nanosecs = EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_peer_rx_nsec))); - time->secsLower = EMAC_REGS__TSU_PEER_RX_SEC__TIMER__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_peer_rx_sec))); - time->secsUpper = EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_peer_rx_msb_sec))); - return 0; -} - -uint32_t emacGet1588SyncStrobeTime(void *pD, CEDI_1588TimerVal *time) -{ - if ((pD==NULL) || (time==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - time->nanosecs = EMAC_REGS__TSU_STROBE_NSEC__STROBE__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_strobe_nsec))); - time->secsLower = EMAC_REGS__TSU_STROBE_SEC__STROBE__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_strobe_sec))); - time->secsUpper = - EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__READ( - CPS_UncachedRead32(CEDI_RegAddr(tsu_strobe_msb_sec))); - return 0; -} - -uint32_t emacSetExtTsuPortEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (0==CEDI_PdVar(hwCfg).ext_tsu_timer) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - - return 0; -} - -uint32_t emacGetExtTsuPortEnable(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= 0; - - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - *enable = EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - return 0; -} - -uint32_t emacSet1588OneStepTxSyncEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - - return 0; -} - -uint32_t emacGet1588OneStepTxSyncEnable(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable = 0; - - if (CEDI_PdVar(hwCfg).tsu) - { - *enable = EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - } - return 0; -} - -/****************************** Time Stamping *********************************/ - -uint32_t emacSetDescTimeStampMode(void *pD, CEDI_TxTsMode txMode, - CEDI_RxTsMode rxMode) -{ - uint32_t regData; - CEDI_Config *config = &CEDI_PdVar(cfg); - - if (pD==NULL) - return EINVAL; - if ((txMode>CEDI_TX_TS_ALL) || (rxMode>CEDI_RX_TS_ALL)) - return EINVAL; - - if (((config->enTxExtBD==0) && (txMode!=0))|| - ((config->enRxExtBD==0) && (rxMode!=0))) - { - vDbgMsg(DBG_GEN_MSG, 5, "%s","ERROR: Time stamping not enabled in DMA config "); - return EINVAL; - } - - regData = CPS_UncachedRead32(CEDI_RegAddr(tx_bd_control)); - EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MODIFY(regData,txMode); - CPS_UncachedWrite32(CEDI_RegAddr(tx_bd_control),regData); - - regData = CPS_UncachedRead32(CEDI_RegAddr(rx_bd_control)); - EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MODIFY(regData,rxMode); - CPS_UncachedWrite32(CEDI_RegAddr(rx_bd_control),regData); - - return 0; -} - -uint32_t emacGetDescTimeStampMode(void *pD, CEDI_TxTsMode* txMode, - CEDI_RxTsMode* rxMode) -{ - uint32_t regData; - CEDI_Config *config = &CEDI_PdVar(cfg); - - if ((pD==NULL) || (txMode==NULL) || (rxMode==NULL)) - return EINVAL; - if ((config->enTxExtBD==0)||(config->enRxExtBD==0)) - return ENOTSUP; - - regData = CPS_UncachedRead32(CEDI_RegAddr(tx_bd_control)); - *txMode = (CEDI_TxTsMode)EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__READ(regData); - - regData = CPS_UncachedRead32(CEDI_RegAddr(rx_bd_control)); - *rxMode = (CEDI_RxTsMode)EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__READ(regData); - - return 0; -} - -uint32_t emacSetStoreRxTimeStamp(void *pD, uint8_t enable) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacGetStoreRxTimeStamp(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable = 0; - - if (0==CEDI_PdVar(hwCfg).tsu) - return ENOTSUP; - - *enable = EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - return 0; -} - -/********************** PCS Control/Auto-negotiation *************************/ - -uint32_t emacResetPcs(void *pD) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - vDbgMsg(DBG_GEN_MSG, 10, "%s entered (regBase %08X)\n", __func__, - (uint32_t)CEDI_PdVar(cfg).regBase); - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), reg); - - CEDI_PdVar(basePageExp) = 1; - CEDI_PdVar(autoNegActive) = 0; - - return 0; -} - -uint32_t emacGetPcsReady(void *pD, uint8_t *ready) -{ - if ((pD==NULL)||(ready==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - - *ready = (0==EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__READ( - CPS_UncachedRead32(CEDI_RegAddr(pcs_control)))); - return 0; -} - -uint32_t emacStartAutoNegotiation(void *pD, CEDI_AnAdvPage *advDat) -{ - uint32_t reg; - uint32_t event; - uint32_t ret; - - if ((pD==NULL)||(advDat==NULL)) - return EINVAL; - - if ((CEDI_PdVar(hwCfg).no_pcs) || - (EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))))) - return ENOTSUP; - if (CEDI_PdVar(autoNegActive)) - return EBUSY; - - //check if we have an event for auto negotiation complete: - ret=emacGetEventEnable(pD,0,&event); - if (ret!=0) - return ret; - if ((event & CEDI_EV_PCS_AN_COMPLETE) == 0) - return EINVAL; - - if ((advDat->fullDuplex>1) || (advDat->halfDuplex>1) || (advDat->nextPage>1) - || (advDat->pauseCap>CEDI_AN_PAUSE_CAP_BOTH) - || (advDat->remFlt>CEDI_AN_REM_FLT_AN_ERR)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), reg); - - emacSetAnAdvPage(pD, advDat); - - CEDI_PdVar(autoNegActive) = 1; - CEDI_PdVar(basePageExp) = 1; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), reg); - return 0; -} - -uint32_t emacSetAutoNegEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - - if (pD==NULL) - return EINVAL; - if (enable>1) return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs || - (EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))))) - return ENOTSUP; - if ((enable) && CEDI_PdVar(autoNegActive)) - return EBUSY; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - if (enable) { - EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SET(reg); - } - else - { - EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__CLR(reg); - CEDI_PdVar(autoNegActive) = 0; - } - CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), reg); - - return 0; -} - -uint32_t emacGetAutoNegEnable(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - - *enable = EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__READ( - CPS_UncachedRead32(CEDI_RegAddr(pcs_control))); - return 0; -} - -/* internal utility for reading PCS status & maintaining - * "read-once" functionality of link status & remote fault - */ -uint32_t readPcsStatus(void *pD) { - uint32_t reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_status)); - if (0==EMAC_REGS__PCS_STATUS__LINK_STATUS__READ(reg)) - CEDI_PdVar(anLinkStat) = 0; - if (1==EMAC_REGS__PCS_STATUS__REMOTE_FAULT__READ(reg)) - CEDI_PdVar(anRemFault) = 1; - return reg; -} - -uint32_t emacGetLinkStatus(void *pD, uint8_t *status) -{ - uint32_t reg; - - if ((pD==NULL)||(status==NULL)) - return EINVAL; - - reg = readPcsStatus(pD); - /* return low if this has not been done yet */ - *status = CEDI_PdVar(anLinkStat); - - CEDI_PdVar(anLinkStat) = - EMAC_REGS__PCS_STATUS__LINK_STATUS__READ(reg); - - return 0; -} - -uint32_t emacGetAnRemoteFault(void *pD, uint8_t *status) -{ - uint32_t reg; - - if ((pD==NULL)||(status==NULL)) - return EINVAL; - - reg = readPcsStatus(pD); - /* return high if this has not been done yet */ - *status = CEDI_PdVar(anRemFault); - - CEDI_PdVar(anRemFault) = - EMAC_REGS__PCS_STATUS__REMOTE_FAULT__READ(reg); - - return 0; -} - -uint32_t emacGetAnComplete(void *pD, uint8_t *status) -{ - if ((pD==NULL)||(status==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - - *status = EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__READ(readPcsStatus(pD)); - - return 0; -} - -uint32_t emacSetAnAdvPage(void *pD, CEDI_AnAdvPage *advDat) -{ - uint32_t reg; - - if ((pD==NULL)||(advDat==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - if ((advDat->fullDuplex>1) || (advDat->halfDuplex>1) || (advDat->nextPage>1) - || (advDat->pauseCap>CEDI_AN_PAUSE_CAP_BOTH) - || (advDat->remFlt>CEDI_AN_REM_FLT_AN_ERR)) - return EINVAL; - - reg = 0; - if (advDat->fullDuplex) - EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SET(reg); - if (advDat->halfDuplex) - EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SET(reg); - EMAC_REGS__PCS_AN_ADV__PAUSE__MODIFY(reg, advDat->pauseCap); - EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MODIFY(reg, advDat->remFlt); - if (advDat->nextPage) - EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_an_adv), reg); - - return 0; -} - -uint32_t emacGetAnAdvPage(void *pD, CEDI_AnAdvPage *advDat) -{ - uint32_t reg; - - if ((pD==NULL)||(advDat==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_an_adv)); - advDat->fullDuplex = EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__READ(reg); - advDat->halfDuplex = EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__READ(reg); - advDat->pauseCap = (CEDI_PauseCap)EMAC_REGS__PCS_AN_ADV__PAUSE__READ(reg); - advDat->remFlt = (CEDI_RemoteFault)EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__READ(reg); - advDat->nextPage = EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__READ(reg); - - return 0; -} - -uint32_t emacGetLpAbilityPage(void *pD, CEDI_LpAbilityPage *lpAbl) -{ - uint32_t reg; - - if ((pD==NULL) || (lpAbl==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_an_lp_base)); - - if (EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config)))) - { - /* SGMII mode format */ - lpAbl->sgmii = 1; - lpAbl->ablInfo.sgmLpAbl.speed = - (CEDI_IfSpeed)(EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__READ(reg)>>1); - lpAbl->ablInfo.sgmLpAbl.lpAck = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__READ(reg); - lpAbl->ablInfo.sgmLpAbl.linkStatus = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__READ(reg); - lpAbl->ablInfo.sgmLpAbl.duplex = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__READ(reg); - } - else - { - /* Default format */ - lpAbl->sgmii = 0; - lpAbl->ablInfo.defLpAbl.fullDuplex = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__READ(reg); - lpAbl->ablInfo.defLpAbl.halfDuplex = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__READ(reg); - lpAbl->ablInfo.defLpAbl.pauseCap = - (CEDI_PauseCap)EMAC_REGS__PCS_AN_LP_BASE__PAUSE__READ(reg); - lpAbl->ablInfo.defLpAbl.lpAck = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__READ(reg); - lpAbl->ablInfo.defLpAbl.remFlt = - (CEDI_RemoteFault)EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__READ(reg); - lpAbl->ablInfo.defLpAbl.lpNextPage = - EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__READ(reg); - } - - return 0; -} - -uint32_t emacGetPageRx(void *pD) -{ - if (pD==NULL) return 0; - if (CEDI_PdVar(hwCfg).no_pcs) - return 0; - - return EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__READ( - CPS_UncachedRead32(CEDI_RegAddr(pcs_an_exp))); -} - -uint32_t emacSetNextPageTx(void *pD, CEDI_AnNextPage *npDat) -{ - uint32_t reg; - - if ((pD==NULL)||(npDat==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - if ((npDat->message>0x7FF) || (npDat->ack2>1) || (npDat->msgPage>1) - || (npDat->np>1)) - return EINVAL; - - reg = 0; - EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MODIFY(reg, npDat->message); - if (npDat->ack2) - EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SET(reg); - if (npDat->msgPage) - EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SET(reg); - if (npDat->np) - EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_an_np_tx), reg); - - return 0; -} - -uint32_t emacGetNextPageTx(void *pD, CEDI_AnNextPage *npDat) -{ - uint32_t reg; - - if ((pD==NULL)||(npDat==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_an_np_tx)); - npDat->message = EMAC_REGS__PCS_AN_NP_TX__MESSAGE__READ(reg); - npDat->ack2 = EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__READ(reg); - npDat->msgPage = EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__READ(reg); - npDat->np = EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__READ(reg); - - return 0; -} - -uint32_t emacGetLpNextPage(void *pD, CEDI_LpNextPage *npDat) -{ - uint32_t reg; - - if ((pD==NULL)||(npDat==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_an_lp_np)); - npDat->message = EMAC_REGS__PCS_AN_LP_NP__MESSAGE__READ(reg); - npDat->toggle = EMAC_REGS__PCS_AN_LP_NP__TOGGLE__READ(reg); - npDat->ack2 = EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__READ(reg); - npDat->msgPage = EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__READ(reg); - npDat->ack = EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__READ(reg); - npDat->np = EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__READ(reg); - - return 0; -} - -/**************************** PHY Management *********************************/ - -uint32_t emacGetPhyId(void *pD, uint32_t *phyId) -{ - if ((pD==NULL)||(phyId==NULL)) - return EINVAL; - -#ifdef EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__READ - volatile uint32_t reg, retVal; - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_phy_top_id)); - retVal = EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__READ(reg)<<16; - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_phy_bot_id)); - retVal |= EMAC_REGS__PCS_PHY_BOT_ID__ID_CODE__READ(reg); - *phyId= retVal; - return 0; -#endif - return ENOTSUP; -} - -void emacSetMdioEnable(void *pD, uint8_t enable) -{ - uint32_t ncr; - if (pD==NULL) return; - if (enable>1) return; - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SET(ncr); - else - EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__CLR(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); -} - -uint32_t emacGetMdioEnable(void *pD) -{ - if (pD==NULL) return 0; - return EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); -} - -/* Initiate a write or set address operation on the MDIO interface. - * Clause 45 devices require a call to set the register address (if - * this is changing since last access), and then a write or read - * operation. - * The command writes to the shift register, which starts output on - * the MDIO interface. Write completion is signalled by the - * phyManComplete callback, or by polling getMdioIdle. - * @param pD - driver private state info specific to this instance - * @param flags - combination of 2 bit-flags: - * if CEDI_MDIO_FLG_CLAUSE_45 present, specifies clause 45 PHY - * (else clause 22). - * if CEDI_MDIO_FLG_SET_ADDR present, specifies a set address operation - * (else do a write operation) Ignored if not clause 45. - * @param phyAddr - PHY address - * @param devReg - device type (clause 45) or register address (clause 22) - * - enum CEDI_MdioDevType is available to specify the device type - * @param addrData - register address (if CEDI_MDIO_FLG_SET_ADDR) or data to write - */ -void emacPhyStartMdioWrite(void *pD, uint8_t flags, uint8_t phyAddr, - uint8_t devReg, uint16_t addrData) -{ - uint32_t reg; - if (pD==NULL) return; - reg = 0; - EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MODIFY(reg, addrData); - EMAC_REGS__PHY_MANAGEMENT__WRITE10__MODIFY(reg, 2); - EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MODIFY(reg, devReg); - EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MODIFY(reg, phyAddr); - if ((flags & CEDI_MDIO_FLG_CLAUSE_45) && (flags & CEDI_MDIO_FLG_SET_ADDR)) { - EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(reg, CEDI_PHY_ADDR_OP); - } - else - EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(reg, CEDI_PHY_WRITE_OP); - if ((flags & CEDI_MDIO_FLG_CLAUSE_45)==0) - EMAC_REGS__PHY_MANAGEMENT__WRITE1__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(phy_management), reg); -} - -/* Initiate a read operation on the MDIO interface. If clause 45, the - * register address will need to be set by a preceding phyStartMdioWrite - * call, unless same as for last operation. Completion is signalled by the - * phyManComplete callback, which will return the read data by a pointer - * parameter. Alternatively polling getMdioIdle will indicate when - * the operation completes, then getMdioReadDat will return the data. - * @param pD - driver private state info specific to this instance - * @param flags - combination of 2 bit-flags: - * if CEDI_MDIO_FLG_CLAUSE_45 present, specifies clause 45 PHY - * (else clause 22). - * if CEDI_MDIO_FLG_INC_ADDR present, and clause 45, then address will - * be incremented after the read operation. - * @param phyAddr - PHY address - * @param devReg - device type (clause 45) or register address (clause 22) - * - enum CEDI_MdioDevType is available to specify the device type - */ -void emacPhyStartMdioRead(void *pD, uint8_t flags, uint8_t phyAddr, - uint8_t devReg) -{ - uint32_t reg; - if (pD==NULL) return; - reg = 0; - EMAC_REGS__PHY_MANAGEMENT__WRITE10__MODIFY(reg, 2); - EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MODIFY(reg, devReg); - EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MODIFY(reg, phyAddr); - if (flags & CEDI_MDIO_FLG_CLAUSE_45) { - if (flags & CEDI_MDIO_FLG_INC_ADDR) { - EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(reg, - CEDI_PHY_CL45_READ_INC_OP); - } - else { - EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(reg, - CEDI_PHY_CL45_READ_OP); - } - } - else - EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(reg, CEDI_PHY_CL22_READ_OP); - if ((flags & CEDI_MDIO_FLG_CLAUSE_45)==0) - EMAC_REGS__PHY_MANAGEMENT__WRITE1__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(phy_management), reg); -} - -uint32_t emacGetMdioReadData(void *pD, uint16_t *readData) -{ - if ((pD==NULL)||(readData==NULL)) - return EINVAL; - *readData= EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__READ( - CPS_UncachedRead32(CEDI_RegAddr(phy_management))); - - return 0; -} - -uint32_t emacGetMdioIdle(void *pD) -{ - if (pD==NULL) return 0; - return EMAC_REGS__NETWORK_STATUS__MAN_DONE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_status))); -} - -/************************* Statistics Registers ******************************/ - -uint32_t emacReadStats(void *pD) -{ - CEDI_Statistics *stats; - - if (pD==NULL) - return EINVAL; - - stats = ((CEDI_Statistics *)(CEDI_PdVar(cfg).statsRegs)); - - if (CEDI_PdVar(hwCfg).no_stats) - return ENOTSUP; - - stats->octetsTxLo = CPS_UncachedRead32(CEDI_RegAddr(octets_txed_bottom)); - stats->octetsTxHi = EMAC_REGS__OCTETS_TXED_TOP__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(octets_txed_top))); - stats->framesTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_ok)); - stats->broadcastTx = CPS_UncachedRead32(CEDI_RegAddr(broadcast_txed)); - stats->multicastTx = CPS_UncachedRead32(CEDI_RegAddr(multicast_txed)); - stats->pauseFrTx = EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(pause_frames_txed))); - stats->fr64byteTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_64)); - stats->fr65_127byteTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_65)); - stats->fr128_255byteTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_128)); - stats->fr256_511byteTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_256)); - stats->fr512_1023byteTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_512)); - stats->fr1024_1518byteTx = - CPS_UncachedRead32(CEDI_RegAddr(frames_txed_1024)); - stats->fr1519_byteTx = CPS_UncachedRead32(CEDI_RegAddr(frames_txed_1519)); - stats->underrunFrTx = EMAC_REGS__TX_UNDERRUNS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_underruns))); - stats->singleCollFrTx = - CPS_UncachedRead32(CEDI_RegAddr(single_collisions)); - stats->multiCollFrTx = - CPS_UncachedRead32(CEDI_RegAddr(multiple_collisions)); - stats->excessCollFrTx = EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(excessive_collisions))); - stats->lateCollFrTx = EMAC_REGS__LATE_COLLISIONS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(late_collisions))); - stats->carrSensErrsTx = EMAC_REGS__CRS_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(crs_errors))); - stats->deferredFrTx = CPS_UncachedRead32(CEDI_RegAddr(deferred_frames)); - stats->alignErrsRx = EMAC_REGS__ALIGNMENT_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(alignment_errors))); - stats->octetsRxLo = CPS_UncachedRead32(CEDI_RegAddr(octets_rxed_bottom)); - stats->octetsRxHi = EMAC_REGS__OCTETS_RXED_TOP__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(octets_rxed_top))); - stats->framesRx = CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_ok)); - stats->broadcastRx = CPS_UncachedRead32(CEDI_RegAddr(broadcast_rxed)); - stats->multicastRx = CPS_UncachedRead32(CEDI_RegAddr(multicast_rxed)); - stats->pauseFrRx = EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(pause_frames_rxed))); - stats->fr64byteRx = CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_64)); - stats->fr65_127byteRx = CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_65)); - stats->fr128_255byteRx = CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_128)); - stats->fr256_511byteRx = CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_256)); - stats->fr512_1023byteRx = - CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_512)); - stats->fr1024_1518byteRx = - CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_1024)); - stats->fr1519_byteRx = - CPS_UncachedRead32(CEDI_RegAddr(frames_rxed_1519)); - stats->undersizeFrRx = EMAC_REGS__UNDERSIZE_FRAMES__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(undersize_frames))); - stats->oversizeFrRx = EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(excessive_rx_length))); - stats->jabbersRx = EMAC_REGS__RX_JABBERS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_jabbers))); - stats->fcsErrorsRx = EMAC_REGS__FCS_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(fcs_errors))); - stats->lenChkErrRx = EMAC_REGS__RX_LENGTH_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_length_errors))); - stats->rxSymbolErrs = EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_symbol_errors))); - stats->rxResourcErrs = - CPS_UncachedRead32(CEDI_RegAddr(rx_resource_errors)); - stats->overrunFrRx = EMAC_REGS__RX_OVERRUNS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_overruns))); - stats->ipChksumErrs = EMAC_REGS__RX_IP_CK_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_ip_ck_errors))); - stats->tcpChksumErrs = EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_tcp_ck_errors))); - stats->udpChksumErrs = EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_udp_ck_errors))); - stats->dmaRxPBufFlush = EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(auto_flushed_pkts))); - -/* - vDbgMsg(DBG_GEN_MSG, 10, "Non-zero Error Stats: %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u %s%u\n", - stats->underrunFrTx?"Tx underruns=":"", stats->underrunFrTx, - stats->singleCollFrTx?"Single coll=":"", stats->singleCollFrTx, - stats->multiCollFrTx?"Multiple coll=":"", stats->multiCollFrTx, - stats->excessCollFrTx?"Excessive coll=":"", stats->excessCollFrTx, - stats->lateCollFrTx?"Late coll=":"", stats->lateCollFrTx, - stats->deferredFrTx?"Deferred fr=":"", stats->deferredFrTx, - stats->carrSensErrsTx?"CarrSense errs=":"", stats->carrSensErrsTx, - stats->undersizeFrRx?"Undersize fr":"", stats->undersizeFrRx, - stats->oversizeFrRx?"Excess rx len=":"", stats->oversizeFrRx, - stats->jabbersRx?"Rx jabbers=":"", stats->jabbersRx, - stats->fcsErrorsRx?"FCS errs=":"", stats->fcsErrorsRx, - stats->lenChkErrRx?"Rx len errs=":"", stats->lenChkErrRx, - stats->rxSymbolErrs?"Rx sym errs=":"", stats->rxSymbolErrs, - stats->alignErrsRx?"Align errs=":"", stats->alignErrsRx, - stats->rxResourcErrs?"Rx res. errs=":"", stats->rxResourcErrs, - stats->overrunFrRx?"Rx overruns=":"", stats->overrunFrRx, - stats->ipChksumErrs?"Rx IP chk errs=":"", stats->ipChksumErrs, - stats->tcpChksumErrs?"Rx TCP chk errs=":"", stats->tcpChksumErrs, - stats->udpChksumErrs?"Rx UDP chk errs=":"", stats->udpChksumErrs, - stats->dmaRxPBufFlush?"Auto flushed pkts=":"", stats->dmaRxPBufFlush ); -*/ - - return 0; -} - -uint32_t emacClearStats(void *pD) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - - if (CEDI_PdVar(hwCfg).no_stats) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacTakeSnapshot(void *pD) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (CEDI_PdVar(hwCfg).no_snapshot || CEDI_PdVar(hwCfg).no_stats) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacSetReadSnapshot(void *pD, uint8_t enable) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (CEDI_PdVar(hwCfg).no_snapshot || CEDI_PdVar(hwCfg).no_stats) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacGetReadSnapshot(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).no_snapshot || CEDI_PdVar(hwCfg).no_stats) - return ENOTSUP; - - *enable = EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - return 0; -} - -/************************ WakeOnLAN/EEE Support ******************************/ - -uint32_t emacSetWakeOnLanReg(void *pD, CEDI_WakeOnLanReg *regVals) -{ - uint32_t reg = 0; - - if ((pD==NULL) || (regVals==NULL) || (regVals->magPktEn>1) || - (regVals->arpEn>1) || (regVals->specAd1En>1) || (regVals->multiHashEn>1)) - return EINVAL; - - EMAC_REGS__WOL_REGISTER__ADDR__MODIFY(reg, regVals->wolReqAddr); - if (regVals->magPktEn) - EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SET(reg); - if (regVals->arpEn) - EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SET(reg); - if (regVals->specAd1En) - EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SET(reg); - if (regVals->multiHashEn) - EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(wol_register), reg); - - return 0; -} - -uint32_t emacGetWakeOnLanReg(void *pD, CEDI_WakeOnLanReg *regVals) -{ - uint32_t reg = 0; - - if ((pD==NULL) || (regVals==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(wol_register)); - regVals->wolReqAddr = EMAC_REGS__WOL_REGISTER__ADDR__READ(reg); - regVals->magPktEn = EMAC_REGS__WOL_REGISTER__WOL_MASK_0__READ(reg); - regVals->arpEn = EMAC_REGS__WOL_REGISTER__WOL_MASK_1__READ(reg); - regVals->specAd1En = EMAC_REGS__WOL_REGISTER__WOL_MASK_2__READ(reg); - regVals->multiHashEn = EMAC_REGS__WOL_REGISTER__WOL_MASK_3__READ(reg); - - return 0; -} - -uint32_t emacSetLpiTxEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacGetLpiTxEnable(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - *enable = EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - return 0; -} - -uint32_t emacGetLpiStats(void *pD, CEDI_LpiStats *lpiStats) -{ - if ((pD==NULL) || (lpiStats==NULL)) - return EINVAL; - - lpiStats->rxLpiTrans = EMAC_REGS__RX_LPI__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_lpi))); - lpiStats->rxLpiTime = EMAC_REGS__RX_LPI_TIME__LPI_TIME__READ( - CPS_UncachedRead32(CEDI_RegAddr(rx_lpi_time))); - lpiStats->txLpiTrans = EMAC_REGS__TX_LPI__COUNT__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_lpi))); - lpiStats->txLpiTime = EMAC_REGS__TX_LPI_TIME__LPI_TIME__READ( - CPS_UncachedRead32(CEDI_RegAddr(tx_lpi_time))); - return 0; -} - -/**************************** Design Config **********************************/ - -uint32_t emacGetDesignConfig(void *pD, CEDI_DesignCfg *hwCfg) -{ - if ((pD==NULL) || (hwCfg==NULL)) - return EINVAL; - - /* Copy h/w config into user-supplied struct */ - *hwCfg = CEDI_PdVar(hwCfg); - return 0; -} - -/**************************** Debug Functionality ****************************/ - -uint32_t emacSetWriteStatsEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (CEDI_PdVar(hwCfg).no_stats) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SET(reg); - else - EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -uint32_t emacGetWriteStatsEnable(void *pD, uint8_t *enable) -{ - uint32_t reg; - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).no_stats) - return EINVAL; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - *enable = EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__READ(reg); - return 0; -} - -uint32_t emacIncStatsRegs(void *pD) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (CEDI_PdVar(hwCfg).no_stats) - return EINVAL; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); - return 0; -} - -void emacSetRxBackPressure(void *pD, uint8_t enable) -{ - uint32_t ncr; - if (pD==NULL) return; - if (enable>1) return; - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - if (enable) - EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SET(ncr); - else - EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__CLR(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); -} - -uint32_t emacGetRxBackPressure(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); - - return 0; -} - -uint32_t emacSetCollisionTest(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - if (CEDI_PdVar(hwCfg).no_pcs) - return ENOTSUP; - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - if (enable) - EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SET(reg); - else - EMAC_REGS__PCS_CONTROL__COLLISION_TEST__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(pcs_control), reg); - return 0; -} - -uint32_t emacGetCollisionTest(void *pD, uint8_t *enable) -{ - uint32_t reg; - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).no_pcs || (enable==NULL)) - return ENOTSUP; - reg = CPS_UncachedRead32(CEDI_RegAddr(pcs_control)); - *enable = EMAC_REGS__PCS_CONTROL__COLLISION_TEST__READ(reg); - return 0; -} - -void emacSetRetryTest(void *pD, uint8_t enable) -{ - uint32_t reg; - if (pD==NULL) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -uint32_t emacGetRetryTest(void *pD, uint8_t *enable) -{ - if ((pD==NULL)||(enable==NULL)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -uint32_t emacWriteUserOutputs(void *pD, uint16_t outVal) -{ - uint32_t tmp; - if (pD==NULL) return EINVAL; - if (0==CEDI_PdVar(hwCfg).user_io) - return ENOTSUP; - - tmp = 0; - EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MODIFY( - tmp, outVal); - CPS_UncachedWrite32(CEDI_RegAddr(user_io_register), tmp); - return 0; -} - -uint32_t emacReadUserOutputs(void *pD, uint16_t *outVal) -{ - uint32_t reg; - if ((pD==NULL) || (outVal==NULL)) - return EINVAL; - if (0==CEDI_PdVar(hwCfg).user_io) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(user_io_register)); - *outVal = EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__READ(reg); - return 0; -} - -uint32_t emacSetUserOutPin(void *pD, uint8_t pin, uint8_t state) -{ - uint32_t reg, val; - if (pD==NULL) return EINVAL; - if (0==CEDI_PdVar(hwCfg).user_io) - return ENOTSUP; - if (pin>=CEDI_PdVar(hwCfg).user_out_width) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(user_io_register)); - val = EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__READ(reg); - if (state) { - val |= (1<=CEDI_PdVar(hwCfg).user_in_width) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(user_io_register)); - val = EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__READ(reg); - *state = (val & (1<=sizeof(struct emac_regs))) - return EINVAL; - - *data = CPS_UncachedRead32((uint32_t *)(CEDI_PdVar(cfg).regBase + offs)); - return 0; -} - -uint32_t emacWriteReg(void *pD, uint32_t offs, uint32_t data) -{ - if ((pD==NULL) || (offs>=sizeof(struct emac_regs))) - return EINVAL; - - CPS_UncachedWrite32((uint32_t *)(CEDI_PdVar(cfg).regBase + offs), data); - return 0; -} - - -CEDI_OBJ EmacDrv = { - emacProbe, // probe - emacInit, // init - emacDestroy, // destroy - emacStart, // start - emacStop, // stop - emacIsr, // isr - emacSetEventEnable, - emacGetEventEnable, - emacSetIntrptModerate, - emacGetIntrptModerate, - emacSetIfSpeed, - emacGetIfSpeed, - emacSetJumboFramesRx, - emacGetJumboFramesRx, - emacSetJumboFrameRxMaxLen, - emacGetJumboFrameRxMaxLen, - emacSetUniDirEnable, - emacGetUniDirEnable, - emacSetTxChecksumOffload, - emacGetTxChecksumOffload, - emacSetRxBufOffset, - emacGetRxBufOffset, - emacSet1536ByteFramesRx, - emacGet1536ByteFramesRx, - emacSetRxChecksumOffload, - emacGetRxChecksumOffload, - emacSetFcsRemove, - emacGetFcsRemove, - emacSetTxPartialStFwd, - emacGetTxPartialStFwd, - emacSetRxPartialStFwd, - emacGetRxPartialStFwd, - emacSetRxDmaDataAddrMask, - emacGetRxDmaDataAddrMask, - emacSetRxBadPreamble, - emacGetRxBadPreamble, - emacSetFullDuplex, - emacGetFullDuplex, - emacSetIgnoreFcsRx, - emacGetIgnoreFcsRx, - emacSetRxHalfDuplexInTx, - emacGetRxHalfDuplexInTx, - emacGetIfCapabilities, - emacSetLoopback, - emacGetLoopback, - - emacCalcMaxTxFrameSize, - emacQueueTxBuf, - emacQTxBuf, - emacDeQTxBuf, - emacTxDescFree, - emacFreeTxDesc, - emacGetTxDescStat, - emacGetTxDescSize, - emacResetTxQ, - emacStartTx, - emacStopTx, - emacAbortTx, - emacTransmitting, - emacEnableTx, - emacGetTxEnabled, - emacGetTxStatus, - emacClearTxStatus, - emacEnableCbs, - emacDisableCbs, - emacGetCbsQSetting, - emacSetIpgStretch, - emacGetIpgStretch, - - emacCalcMaxRxFrameSize, - emacAddRxBuf, - emacNumRxBufs, - emacNumRxUsed, - emacReadRxBuf, - emacGetRxDescStat, - emacGetRxDescSize, - emacRxEnabled, - emacEnableRx, - emacDisableRx, - emacRemoveRxBuf, - emacResetRxQ, - emacGetRxStatus, - emacClearRxStatus, - emacSetHdrDataSplit, - emacGetHdrDataSplit, - emacSetRscEnable, - emacGetRscEnable, - emacSetRscClearMask, - emacSetSpecificAddr, - emacGetSpecificAddr, - emacSetSpecificAddr1Mask, - emacGetSpecificAddr1Mask, - emacDisableSpecAddr, - emacSetTypeIdMatch, - emacGetTypeIdMatch, - emacSetUnicastEnable, - emacGetUnicastEnable, - emacSetMulticastEnable, - emacGetMulticastEnable, - emacSetNoBroadcast, - emacGetNoBroadcast, - emacSetVlanOnly, - emacGetVlanOnly, - emacSetStackedVlanReg, - emacGetStackedVlanReg, - emacSetCopyAllFrames, - emacGetCopyAllFrames, - emacSetHashAddr, - emacGetHashAddr, - emacSetLenErrDiscard, - emacGetLenErrDiscard, - emacGetNumScreenRegs, - emacSetType1ScreenReg, - emacGetType1ScreenReg, - emacSetType2ScreenReg, - emacGetType2ScreenReg, - emacSetType2EthertypeReg, - emacGetType2EthertypeReg, - emacSetType2CompareReg, - emacGetType2CompareReg, - - emacSetPauseEnable, - emacGetPauseEnable, - emacTxPauseFrame, - emacTxZeroQPause, - emacGetRxPauseQuantum, - emacSetTxPauseQuantum, - emacGetTxPauseQuantum, - emacSetCopyPauseDisable, - emacGetCopyPauseDisable, - emacSetPfcPriorityBasedPauseRx, - emacGetPfcPriorityBasedPauseRx, - emacTxPfcPriorityBasedPause, - emacSetTxPfcPauseFrameFields, - emacGetTxPfcPauseFrameFields, - emacSetEnableMultiPfcPauseQuantum, - emacGetEnableMultiPfcPauseQuantum, - - emacSetUnicastPtpDetect, - emacGetUnicastPtpDetect, - emacSetPtpRxUnicastIpAddr, - emacGetPtpRxUnicastIpAddr, - emacSetPtpTxUnicastIpAddr, - emacGetPtpTxUnicastIpAddr, - emacSet1588Timer, - emacGet1588Timer, - emacAdjust1588Timer, - emacSet1588TimerInc, - emacGet1588TimerInc, - emacSetTsuTimerCompVal, - emacGetTsuTimerCompVal, - emacGetPtpFrameTxTime, - emacGetPtpFrameRxTime, - emacGetPtpPeerFrameTxTime, - emacGetPtpPeerFrameRxTime, - emacGet1588SyncStrobeTime, - emacSetExtTsuPortEnable, - emacGetExtTsuPortEnable, - emacSet1588OneStepTxSyncEnable, - emacGet1588OneStepTxSyncEnable, - emacSetDescTimeStampMode, - emacGetDescTimeStampMode, - emacSetStoreRxTimeStamp, - emacGetStoreRxTimeStamp, - - emacResetPcs, - emacGetPcsReady, - emacStartAutoNegotiation, - emacSetAutoNegEnable, - emacGetAutoNegEnable, - emacGetLinkStatus, - emacGetAnRemoteFault, - emacGetAnComplete, - emacSetAnAdvPage, - emacGetAnAdvPage, - emacGetLpAbilityPage, - emacGetPageRx, - emacSetNextPageTx, - emacGetNextPageTx, - emacGetLpNextPage, - - emacGetPhyId, - emacSetMdioEnable, - emacGetMdioEnable, - emacPhyStartMdioWrite, - emacPhyStartMdioRead, - emacGetMdioReadData, - emacGetMdioIdle, - - emacReadStats, - emacClearStats, - emacTakeSnapshot, - emacSetReadSnapshot, - emacGetReadSnapshot, - emacSetWakeOnLanReg, - emacGetWakeOnLanReg, - emacSetLpiTxEnable, - emacGetLpiTxEnable, - emacGetLpiStats, - emacGetDesignConfig, - - emacSetWriteStatsEnable, - emacGetWriteStatsEnable, - emacIncStatsRegs, - emacSetRxBackPressure, - emacGetRxBackPressure, - emacSetCollisionTest, - emacGetCollisionTest, - emacSetRetryTest, - emacGetRetryTest, - emacWriteUserOutputs, - emacReadUserOutputs, - emacSetUserOutPin, - emacReadUserInputs, - emacGetUserInPin, - emacGetMdioInState, - emacReadReg, - emacWriteReg, -}; - -CEDI_OBJ *CEDI_GetInstance(void) { - return &EmacDrv; -} - -#ifdef __cplusplus -} -#endif - -#endif /* CY_IP_MXETH */ - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd_rx.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd_rx.c deleted file mode 100644 index 13fbac944c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd_rx.c +++ /dev/null @@ -1,2190 +0,0 @@ -/****************************************************************************** - * copyright (C) 2014-2015 Cadence Design Systems - * All rights reserved. - ****************************************************************************** - * edd_rx.c - * Ethernet DMA MAC Driver - * - * Rx-related functions source file - *****************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXETH) - -#include "cdn_stdint.h" -#include "cdn_errno.h" -#include "log.h" -#include "cps_v2.h" -#include "emac_regs.h" -#include "cedi.h" -#include "edd_int.h" - -#ifdef __cplusplus -extern "C" { -#endif -/****************************************************************************** - * Driver API functions - *****************************************************************************/ - -/* Identify max Rx pkt size for queues - determined by size of Rx packet buffer - * (if using full store & forward mode), and the current maximum frame size, - * e.g. 1518, 1536 or jumbo frame. - * @param pD - driver private state info specific to this instance - * @param maxSize - pointer for returning max frame size, same for each Rx queue - * @return 0 if successful - * @return EINVAL if invalid parameters - */ -uint32_t emacCalcMaxRxFrameSize(void *pD, uint32_t *maxSize) { - uint16_t ram_word_size, ram_addr_bits; - uint32_t ram_size, max_size, tmp; - uint8_t enabled = 0; - uint16_t length; - - if ((pD==NULL) || (maxSize==NULL)) return EINVAL; - - if (0!=emacGetJumboFramesRx(pD,&enabled)) - return EINVAL; - - if (enabled) { - if (0!=emacGetJumboFrameRxMaxLen(pD, &length)) - return EINVAL; - max_size = length; - } else { - if (0!=emacGet1536ByteFramesRx(pD,&enabled)) - return EINVAL; - if (enabled) - max_size = 1536; - else - max_size = 1518; - } - - if (0!=emacGetRxPartialStFwd(pD, &tmp, &enabled)) - return EINVAL; - - if ((!enabled) && CEDI_PdVar(hwCfg).rx_pkt_buffer) - { - // What is word size of SRAM in bytes - ram_word_size = (CEDI_PdVar(hwCfg).rx_pbuf_data >> 1)+1; - //vDbgMsg(DBG_GEN_MSG, 10, "RAM word size = %u (x32 bits)\n", CEDI_PdVar(hwCfg).rx_pbuf_data); - ram_addr_bits = CEDI_PdVar(hwCfg).rx_pbuf_addr; - //vDbgMsg(DBG_GEN_MSG, 10, "RAM Rx addr bits = %u\n", ram_addr_bits); - - ram_size = (1<<(ram_addr_bits + ram_word_size + 1)) - 96; - vDbgMsg(DBG_GEN_MSG, 10, "RAM size = %u\n", ram_size); - - if (ram_size0 then initialise the buffer data to all zeros - * @return 0 if successful, EINVAL if invalid queueNum, buffer alignment, or - * bufStart pointer/addresses - */ -uint32_t emacAddRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf, uint8_t init) -{ - uint32_t tmp, bufLenWords; - rxQueue_t *rxQ; - - if (!pD) return EINVAL; - - if (queueNum>=(CEDI_PdVar(cfg)).rxQs) { - vDbgMsg(DBG_GEN_MSG, 5, "Error: Invalid Rx queue number: %u\n", queueNum); - return EINVAL; - } - - if ((buf==0) || (buf->vAddr==0) || (buf->pAddr==0)) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: NULL buf parameter"); - return EINVAL; - } -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered (regBase %08X) bufV=0x%08X bufP=0x%08X\n", __func__, -// CEDI_PdVar(cfg).regBase, buf->vAddr, buf->pAddr); - - rxQ = &(CEDI_PdVar(rxQueue[queueNum])); - - if (rxQ->numRxBufs>=((CEDI_PdVar(cfg)).rxQLen[queueNum])) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: Rx descriptor list full"); - return EINVAL; - } - - /* alignment checking */ - switch (CEDI_PdVar(cfg).dmaBusWidth) { - case CEDI_DMA_BUS_WIDTH_32: - tmp = 4; break; - case CEDI_DMA_BUS_WIDTH_64: - tmp = 8; break; - case CEDI_DMA_BUS_WIDTH_128: - tmp = 16; break; - default: tmp = 4; break; - } - if ((buf->pAddr)%tmp) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: Rx buffer not word-aligned"); - return EINVAL; - } - - /* save virtual address */ - *(rxQ->rxEndVA) = buf->vAddr; - - bufLenWords = (CEDI_PdVar(cfg).rxBufLength[queueNum])<<4; - if (init) - for (tmp=0; tmpvAddr)+tmp, 0); - - /* clear wrap & used on old end, add new buffer */ - CPS_UncachedWrite32(&(rxQ->rxDescEnd->word[0]), - buf->pAddr & CEDI_RXD_ADDR_MASK); - /* upper 32 bits if 64 bit addressing */ - if (CEDI_PdVar(cfg).dmaAddrBusWidth) { -#ifdef CEDI_64B_COMPILE - /* 64-bit addressing */ - CPS_UncachedWrite32(&(rxQ->rxDescEnd->word[2]), - (buf->pAddr & 0xFFFFFFFF00000000)>>32); -#else - /* 32-bit addressing */ - CPS_UncachedWrite32(&(rxQ->rxDescEnd->word[2]), 0x00000000); -#endif - } - - /* put known pattern into word[1] for debugging */ - CPS_UncachedWrite32(&(rxQ->rxDescEnd->word[1]), CEDI_RXD_EMPTY); - - /* inc end & stop pointer */ - rxQ->rxDescEnd = (rxDesc *)(((uintptr_t)rxQ->rxDescEnd) + - (CEDI_PdVar(rxDescriptorSize))); - rxQ->rxDescStop = rxQ->rxDescEnd; - - /* inc VA end & stop pointers & buffer count */ - rxQ->rxEndVA++; - rxQ->rxStopVA++; - *(rxQ->rxStopVA) = 0; - rxQ->numRxBufs++; - - /* write new end(-stop) descriptor */ - CPS_UncachedWrite32(&(rxQ->rxDescEnd->word[0]), - CEDI_RXD_WRAP | CEDI_RXD_USED ); - - return 0; -} - -/* Get the number of useable buffers/descriptors present in the specified - * Rx queue, excluding the end-stop descriptor. - * @param pD - driver private state info specific to this instance - * @param queueNum - number of the Rx queue (range 0 to rxQs-1) - * @param numBufs - pointer for returning number of descriptors - * @return 0 if successful - * @return EINVAL if invalid parameter - */ -uint32_t emacNumRxBufs(void *pD, uint8_t queueNum, uint16_t *numBufs) -{ - if ((pD==NULL) || (numBufs==NULL) || (queueNum>=(CEDI_PdVar(cfg)).rxQs)) - return EINVAL; - - *numBufs = (CEDI_PdVar(rxQueue[queueNum])).numRxBufs; - return 0; -} - -/* Get the number of buffers/descriptors marked "used" in the specified Rx - * queue (excluding unuseable end-stop), i.e. those holding unread data. - * @param pD - driver private state info specific to this instance - * @param queueNum - number of the Rx queue (range 0 to rxQs-1) - * @return number of used buffers - * @return 0 if invalid parameter - */ -uint32_t emacNumRxUsed(void *pD, uint8_t queueNum) -{ - uint32_t tmp, thisWd, count=0; - rxDesc *thisDesc; - rxQueue_t *rxQ; - - if ((pD==NULL) || (queueNum>=(CEDI_PdVar(cfg)).rxQs)) - return 0; - - rxQ = &(CEDI_PdVar(rxQueue[queueNum])); - /* count forward from tail, until used not set */ - thisDesc = rxQ->rxDescTail; - for (tmp = 0; tmpnumRxBufs; tmp++) - { - thisWd = CPS_UncachedRead32(&(thisDesc->word[0])); - if (thisWd & CEDI_RXD_USED) - count++; - else - break; - if (thisWd & CEDI_RXD_WRAP) - thisDesc = rxQ->rxDescStart; - else - thisDesc = (rxDesc *)(((uintptr_t)(thisDesc)) - + (CEDI_PdVar(rxDescriptorSize))); - } - return count; -} - -/** - * Read first unread descriptor (at tail of queue): if new data is available - * it swaps out the buffer and replaces it with a new one, clears the - * descriptor for re-use, then updates the driver queue-pointer. - * Checks for Start Of Frame (SOF) and End Of Frame (EOF) flags in the - * descriptors, passing back in return value. - * If EOF set, the descriptor status is returned via rxDescStat. - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum - * number of the Rx queue - * @param[in,out] buf pointer to address of memory for new buffer to add to Rx - * descriptor queue, if data is available the buffer addresses for this are - * returned in buf, else if no data available the new buffer can be re-used. - * Physical address of buffer is checked for word-alignment in 64/128-bit - * width cases. - * @param[in] init if >0 then initialise the (new) buffer data to all zeros. - * Ignored if no data available. - * @param[out] descData pointer for returning status & descriptor data - * Struct fields: - * - * uint32_t rxDescStat - Rx descriptor status word - * - * uint8_t status - Rx data status, one of the following values: - * CEDI_RXDATA_SOF_EOF :data available, single-buffer frame (SOF & EOF - * set) - * CEDI_RXDATA_SOF_ONLY :data available, start of multi-buffer frame - * CEDI_RXDATA_NO_FLAG :data available, intermediate buffer of multi- - * buffer frame - * CEDI_RXDATA_EOF_ONLY :data available, end of multi-buffer frame - * CEDI_RXDATA_NODATA :no data available - * - * CEDI_TimeStampData rxTsData - Rx descriptor timestamp when valid - * (rxTsData->tsValid will be set to 1) - * - * @return 0 if successful, - * @return EINVAL if invalid queueNum, buf, rxDescStat or - * status parameters - */ -uint32_t emacReadRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf, - uint8_t init, CEDI_RxDescData *descData) -{ - uint32_t tmp, bufLenWords, descWd0; - CEDI_BuffAddr oldbuf; - uint8_t wdNum, tailWrap; - uint32_t tsLowerWd, tsUpperWd; - rxQueue_t *rxQ; - - if (!pD) return EINVAL; - -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered (regBase %08lX)\n", __func__, -// CEDI_PdVar(cfg).regBase); - - if (buf==NULL) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: NULL buf parameter"); - return EINVAL; - } - - if (descData==NULL) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: NULL descData parameter"); - return EINVAL; - } - - if (queueNum>=(CEDI_PdVar(cfg)).rxQs) { - vDbgMsg(DBG_GEN_MSG, 5, "Error: Invalid Rx queue number - %u\n", queueNum); - return EINVAL; - } - - if ((buf->vAddr==0) || (buf->pAddr==0)) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: NULL buf address"); - return EINVAL; - } - - /* alignment checking for new buffer */ - switch (CEDI_PdVar(cfg).dmaBusWidth) { - case CEDI_DMA_BUS_WIDTH_32: - tmp = 4; break; - case CEDI_DMA_BUS_WIDTH_64: - tmp = 8; break; - case CEDI_DMA_BUS_WIDTH_128: - tmp = 16; break; - default: tmp = 4; break; - } - if ((buf->pAddr)%tmp) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: Rx buffer not word-aligned"); - return EINVAL; - } - - rxQ = &(CEDI_PdVar(rxQueue[queueNum])); - - /* get first descriptor & test used bit */ - descWd0 = CPS_UncachedRead32(&(rxQ->rxDescTail->word[0])); - - if (descWd0 & CEDI_RXD_USED) { - /* new data received - read & process descriptor */ - - /* get old physical address */ - oldbuf.pAddr = descWd0 & CEDI_RXD_ADDR_MASK; - -#ifdef CEDI_64B_COMPILE - /* upper 32 bits if 64 bit addressing */ - if (CEDI_PdVar(cfg).dmaAddrBusWidth) - oldbuf.pAddr |= ((uint64_t)CPS_UncachedRead32( - &(rxQ->rxDescTail->word[2])))<<32; -#endif - - /* get old virtual address & clear from list */ - oldbuf.vAddr = *(rxQ->rxTailVA); - *(rxQ->rxTailVA) = 0; - - /* save new virtual address */ - *(rxQ->rxStopVA) = buf->vAddr; - - bufLenWords = (CEDI_PdVar(cfg).rxBufLength[queueNum])<<4; - if (init) - for (tmp=0; tmpvAddr+4*tmp), 0); - - /* read Rx status */ - descData->rxDescStat = CPS_UncachedRead32(&(rxQ->rxDescTail->word[1])); - - /* extract timestamp if available */ - if ((CEDI_PdVar(cfg).enRxExtBD) && (descWd0 & CEDI_RXD_TS_VALID)) { - uint32_t reg; - descData->rxTsData.tsValid = 1; - // position depends on 32/64 bit addr - wdNum = (CEDI_PdVar(cfg).dmaAddrBusWidth)?4:2; - - tsLowerWd = CPS_UncachedRead32(&(rxQ->rxDescTail->word[wdNum])); - tsUpperWd = CPS_UncachedRead32(&(rxQ->rxDescTail->word[wdNum+1])); - - descData->rxTsData.tsNanoSec = tsLowerWd & CEDI_TS_NANO_SEC_MASK; - descData->rxTsData.tsSecs = - (((tsUpperWd & CEDI_TS_SEC1_MASK)<> CEDI_TS_SEC0_SHIFT)); - - /* The timestamp only contains lower few bits of seconds, so add value from 1588 timer */ - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_sec)); - /* If the top bit is set in the timestamp, but not in 1588 timer, it has rolled over, so subtract max size */ - if ((descData->rxTsData.tsSecs & (CEDI_TS_SEC_TOP>>1)) && !(reg & (CEDI_TS_SEC_TOP>>1))) { - descData->rxTsData.tsSecs -= (CEDI_TS_SEC_TOP<<1); - - } - descData->rxTsData.tsSecs += ((~CEDI_TS_SEC_MASK) & EMAC_REGS__TSU_TIMER_SEC__TIMER__READ(reg)); - } - else - { - descData->rxTsData.tsValid = 0; - } - - /* save this for later */ - tailWrap = descWd0 & CEDI_RXD_WRAP; - - /* write back to descriptors */ - CPS_UncachedWrite32(&(rxQ->rxDescTail->word[1]), CEDI_RXD_EMPTY); - /* zero buf physical address & set used - this will be new end-stop */ - CPS_UncachedWrite32(&(rxQ->rxDescTail->word[0]), - CEDI_RXD_USED | (tailWrap?CEDI_RXD_WRAP:0)); - - /* handle old "stop" descriptor now */ - /* insert new buf physical address & clear used */ - descWd0 = CPS_UncachedRead32(&(rxQ->rxDescStop->word[0])); - descWd0 = ((buf->pAddr) & CEDI_RXD_ADDR_MASK) | - (descWd0 & CEDI_RXD_WRAP); - CPS_UncachedWrite32(&(rxQ->rxDescStop->word[0]), descWd0); - /* upper 32 bits if 64 bit addressing */ - if (CEDI_PdVar(cfg).dmaAddrBusWidth) { -#ifdef CEDI_64B_COMPILE - /* 64-bit addressing */ - CPS_UncachedWrite32(&(rxQ->rxDescStop->word[2]), - (buf->pAddr & 0xFFFFFFFF00000000)>>32); -#else - /* 32-bit addressing */ - CPS_UncachedWrite32(&(rxQ->rxDescStop->word[2]), 0x00000000); -#endif - } - - /* update pointers */ - rxQ->rxDescStop = rxQ->rxDescTail; - rxQ->rxStopVA = rxQ->rxTailVA; - if (tailWrap) { - rxQ->rxDescTail = rxQ->rxDescStart; - rxQ->rxTailVA = rxQ->rxBufVAddr; - } - else { - rxQ->rxDescTail = (rxDesc *)(((uintptr_t)(rxQ->rxDescTail)) - + (CEDI_PdVar(rxDescriptorSize))); - rxQ->rxTailVA++; - } - - /* return old buffer addresses */ - buf->pAddr = oldbuf.pAddr; - buf->vAddr = oldbuf.vAddr; -/* vDbgMsg(DBG_GEN_MSG, 10, "%s vAddr=%p pAddr=%p\n", - __func__, (void *)buf->vAddr, (void *)buf->pAddr);*/ - - - /* work out read frame status */ - if ((descData->rxDescStat) & CEDI_RXD_SOF) { - if ((descData->rxDescStat) & CEDI_RXD_EOF) - descData->status = CEDI_RXDATA_SOF_EOF; - else - descData->status = CEDI_RXDATA_SOF_ONLY; - } - else - { - if ((descData->rxDescStat) & CEDI_RXD_EOF) - descData->status = CEDI_RXDATA_EOF_ONLY; - else - descData->status = CEDI_RXDATA_NO_FLAG; - } - } - else - descData->status = CEDI_RXDATA_NODATA; - - return 0; -} - -/* Decode the Rx descriptor status into a bit-field struct - * @param pD - driver private state info specific to this instance - * @param rxDStatWord - Rx descriptor status word - * @param rxDStat - pointer to bit-field struct for decoded status fields - */ -void emacGetRxDescStat(void *pD, uint32_t rxDStatWord, CEDI_RxDescStat *rxDStat) -{ - uint32_t reg, wd1; - - if ((NULL==pD) || (NULL==rxDStat)) return; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - - wd1 = rxDStatWord; - rxDStat->bufLen = wd1 & CEDI_RXD_LEN_MASK; - if (EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__READ(reg) || - (EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__READ(reg)==0)) { - rxDStat->bufLen |= wd1 & CEDI_RXD_LEN13_FCS_STAT; - rxDStat->fcsStatus = 0; - } - else - rxDStat->fcsStatus = (wd1 & CEDI_RXD_LEN13_FCS_STAT)?1:0; - - rxDStat->sof = (wd1 & CEDI_RXD_SOF)?1:0; - rxDStat->eof = (wd1 & CEDI_RXD_EOF)?1:0; - rxDStat->header = (!rxDStat->eof && (wd1 & CEDI_RXD_HDR))?1:0; - rxDStat->eoh = (!rxDStat->eof && (wd1 & CEDI_RXD_EOH))?1:0; - rxDStat->vlanTagDet = (wd1 & CEDI_RXD_VLAN_TAG)?1:0; - rxDStat->cfi = ((wd1 & CEDI_RXD_CFI) && rxDStat->vlanTagDet)?1:0; - if (rxDStat->vlanTagDet) - rxDStat->vlanPri = - (wd1 & CEDI_RXD_VLAN_PRI_MASK)>>CEDI_RXD_VLAN_PRI_SHIFT; - else - rxDStat->vlanPri = 0; - rxDStat->priTagDet = (wd1 & CEDI_RXD_PRI_TAG)?1:0; - if (EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__READ(reg)) { - rxDStat->chkOffStat = (wd1 & CEDI_RXD_TYP_IDR_CHK_STA_MASK)\ - >>CEDI_RXD_TYP_IDR_CHK_STA_SHIFT; - rxDStat->snapNoVlanCfi = (wd1 & CEDI_RXD_TYP_MAT_SNP_NCFI)?1:0; - rxDStat->typeMatchReg = 0; - rxDStat->typeIdMatch = 0; - } - else { - rxDStat->chkOffStat = 0; - rxDStat->snapNoVlanCfi = 0; - rxDStat->typeMatchReg = (wd1 & CEDI_RXD_TYP_IDR_CHK_STA_MASK)\ - >>CEDI_RXD_TYP_IDR_CHK_STA_SHIFT; - rxDStat->typeIdMatch = (wd1 & CEDI_RXD_TYP_MAT_SNP_NCFI)?1:0; - } - - rxDStat->specAddReg = (wd1 & CEDI_RXD_SPEC_REG_MASK)\ - >>CEDI_RXD_SPEC_REG_SHIFT; - if (CEDI_PdVar(hwCfg).rx_pkt_buffer && - (CEDI_PdVar(hwCfg).num_spec_add_filters>4)) - { /* extra spec. addr matching variation */ - rxDStat->specAddReg += ((wd1 & CEDI_RXD_SPEC_ADD_MAT)?1:0) << 2; - rxDStat->specAddMatch = (wd1 & CEDI_RXD_EXT_ADD_MAT)?1:0; - rxDStat->extAddrMatch = 0; - } - else - { - rxDStat->specAddMatch = (wd1 & CEDI_RXD_SPEC_ADD_MAT)?1:0; - rxDStat->extAddrMatch = (wd1 & CEDI_RXD_EXT_ADD_MAT)?1:0; - } - rxDStat->uniHashMatch = (wd1 & CEDI_RXD_UNI_HASH_MAT)?1:0; - rxDStat->multiHashMatch = (wd1 & CEDI_RXD_MULTI_HASH_MAT)?1:0; - rxDStat->broadcast = (wd1 & (uint32_t)CEDI_RXD_BROADCAST_DET)?1:0; -} - -/* Provide the size of descriptor calculated for the current configuration. - * @param pD - driver private state info specific to this instance - * @param rxDescSize - pointer to Rx descriptor Size - */ -void emacGetRxDescSize(void *pD, uint32_t *rxDescSize) -{ - if ((pD==NULL)||(rxDescSize==NULL)) - return; - *rxDescSize = CEDI_PdVar(rxDescriptorSize); -} - -/* Get state of receiver - * @param pD - driver private state info specific to this instance - * @return 1 if enabled - * @return 0 if disabled or pD==NULL - */ -uint32_t emacRxEnabled(void *pD) -{ - uint32_t reg; - if (pD==NULL) return 0; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - return EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__READ(reg); -} - -/* Enable the receive circuit. - * @param pD - driver private state info specific to this instance - */ -void emacEnableRx(void *pD) -{ - uint32_t reg; - if (!pD) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); -} - -/* Disable the receive circuit. - * @param pD - driver private state info specific to this instance - */ -void emacDisableRx(void *pD) -{ - uint32_t reg; - if (!pD) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), reg); -} - -/* Remove a buffer from the end of the receive buffer queue. This function is - * intended to be used when shutting down the driver, prior to deallocating the - * receive buffers, and should not be called while Rx is enabled or unread - * data remains in the queue. - * @param pD - driver private state info specific to this instance - * @param queueNum - number of the Rx queue (range 0 to rxQs-1) - * @param buf - pointer to struct for returning virtual and physical addresses - * of buffer. - * @return 0 if successful - * @return EINVAL if invalid queueNum, ENOENT if no buffers left to free - */ -uint32_t emacRemoveRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf) -{ - uint32_t tmp; - rxQueue_t *rxQ; - - if (!pD) return EINVAL; - - if (queueNum>=(CEDI_PdVar(cfg)).rxQs) { - vDbgMsg(DBG_GEN_MSG, 5, "Error: Invalid Rx queue number: %u\n", queueNum); - return EINVAL; - } - - if (buf==0) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: NULL buf parameter"); - return EINVAL; - } - - rxQ = &(CEDI_PdVar(rxQueue[queueNum])); - - if (0==rxQ->numRxBufs) - return ENOENT; - - /* skip "stop" descriptor since no buffer there */ - if ((rxQ->rxDescEnd==rxQ->rxDescStop) && (rxQ->rxDescEnd!=rxQ->rxDescStart)) - { - rxQ->rxDescEnd = (rxDesc*) - ((uintptr_t)(rxQ->rxDescEnd) - CEDI_PdVar(rxDescriptorSize)); - rxQ->rxEndVA--; - } - - /* get physical address */ - buf->pAddr = CPS_UncachedRead32(&(rxQ->rxDescEnd->word[0])) - & CEDI_RXD_ADDR_MASK; - /* get virtual address */ - buf->vAddr = *(rxQ->rxEndVA); - - /* dec end/tail pointers unless already at start of list */ - if (rxQ->rxDescEnd!=rxQ->rxDescStart) { - rxQ->rxDescEnd = (rxDesc*) - ((uintptr_t)(rxQ->rxDescEnd) - CEDI_PdVar(rxDescriptorSize)); - rxQ->rxEndVA--; - - /* set wrap on new end descriptor */ - tmp = CPS_UncachedRead32(&(rxQ->rxDescEnd->word[0])); - CPS_UncachedWrite32(&(rxQ->rxDescEnd->word[0]), tmp | CEDI_RXD_WRAP); - } - rxQ->numRxBufs--; - - return 0; -} - -void emacFindQBaseAddr(void *pD, uint8_t queueNum, rxQueue_t *rxQ, - uint32_t *pAddr, uintptr_t *vAddr) { - uint8_t q = 0; - /* find start addresses for this rxQ */ - *vAddr = CEDI_PdVar(cfg).rxQAddr; - *pAddr = CEDI_PdVar(cfg).rxQPhyAddr; - - if (queueNum>0) - rxQ->rxBufVAddr = (CEDI_PdVar(rxQueue[0]).rxBufVAddr); - while (qnumRxDesc)*(CEDI_PdVar(rxDescriptorSize));//sizeof(rxDesc); - *pAddr += (rxQ->numRxDesc)*(CEDI_PdVar(rxDescriptorSize));//sizeof(rxDesc); - rxQ->rxBufVAddr += rxQ->numRxDesc; - q++; - } - vDbgMsg(DBG_GEN_MSG, 10, "%s: base address Q%u virt=%08lX phys=%08X vAddrList=%p\n", - __func__, queueNum, *vAddr, *pAddr, rxQ->rxBufVAddr); -} -/* Reset Rx buffer descriptor list/ buffer virtual address list to initial - * empty state, clearing all descriptors. For use by init or after a fatal - * error. Disables receive circuit. - * @param pD - driver private state info specific to this instance - * @param queueNum - number of the Rx queue (range 0 to rxQs-1) - * @param ptrsOnly - if =1, then reset pointers and clearing used bits only - * after a link down/up event (assume buffers already assigned) - * if =0, initialise all list fields for this queue, including - * clearing buffer addresses - * @return 0 if successful - * @return EINVAL if invalid parameter - */ -uint32_t emacResetRxQ(void *pD, uint8_t queueNum, uint8_t ptrsOnly) -{ -#define CEDI_WR_RXQ_PTR_REG_N_CASE(Q) case Q:\ - CPS_UncachedWrite32(CEDI_RegAddr(receive_q##Q##_ptr), regTmp);\ - break; - - uint32_t regTmp; - uint16_t i; - uint32_t pAddr; - uintptr_t vAddr; - rxDesc* descPtr; - rxQueue_t *rxQ; - - if ((pD==NULL) || (queueNum>=CEDI_PdVar(cfg).rxQs) || (ptrsOnly>1)) - return EINVAL; - - emacDisableRx(pD); - - rxQ = &(CEDI_PdVar(rxQueue[queueNum])); - emacFindQBaseAddr(pD, queueNum, rxQ, &pAddr, &vAddr); - - /* want the virtual addresses here: */ - if (ptrsOnly) { - if (rxQ->rxDescStop!=rxQ->rxDescEnd) { - /* copy buffer addresses from new "stop" descriptor to old one, - * before reset pointers */ - CPS_UncachedWrite32((uint32_t *)&(rxQ->rxDescStop->word[0]), - CPS_UncachedRead32((uint32_t *)&(rxQ->rxDescEnd->word[0]))); - *(rxQ->rxStopVA) = *(rxQ->rxEndVA); - } - } - else - { - rxQ->rxDescStart = (rxDesc *)vAddr; - rxQ->rxDescEnd = (rxDesc *)vAddr; - } - rxQ->rxDescStop = (rxDesc *)vAddr; - rxQ->rxDescTail = (rxDesc *)vAddr; - rxQ->rxTailVA = rxQ->rxBufVAddr; - rxQ->rxStopVA = rxQ->rxBufVAddr; - if (!ptrsOnly) { - rxQ->rxEndVA = rxQ->rxBufVAddr; - *(rxQ->rxStopVA) = 0; - rxQ->numRxBufs = 0; - } - - /* full reset: clear used flags except stop & set wrap flag, only expand - * available size as buffers are added - if ptrsOnly, then buffers already - * in ring, preserve addresses & only clear used bits/wd1 */ - descPtr = rxQ->rxDescStart; - for (i = 0; inumRxDesc; i++) { - if (ptrsOnly) { - if (rxQ->rxDescStop==rxQ->rxDescEnd) { - CPS_UncachedWrite32((uint32_t *)&(rxQ->rxDescStop->word[0]), - CEDI_RXD_WRAP|CEDI_RXD_USED ); - CPS_UncachedWrite32(&(rxQ->rxDescStop->word[1]), CEDI_RXD_EMPTY); - *(rxQ->rxStopVA) = 0; - } - else - { - pAddr = CPS_UncachedRead32((uint32_t *)&(rxQ->rxDescStop->word[0])); - CPS_UncachedWrite32((uint32_t *)&(rxQ->rxDescStop->word[0]), - pAddr & ~(CEDI_RXD_WRAP|CEDI_RXD_USED)); - CPS_UncachedWrite32(&(rxQ->rxDescStop->word[1]), CEDI_RXD_EMPTY); - /* inc stop pointer */ - rxQ->rxDescStop = (rxDesc *)(((uintptr_t)rxQ->rxDescStop) + - (CEDI_PdVar(rxDescriptorSize))); - /* inc VA stop pointer */ - rxQ->rxStopVA++; - } - } - else { - CPS_UncachedWrite32((uint32_t *) - &(descPtr->word[0]), i?0:CEDI_RXD_WRAP|CEDI_RXD_USED); - CPS_UncachedWrite32((uint32_t *) - &(descPtr->word[1]), CEDI_RXD_EMPTY); - descPtr = (rxDesc*) (((uintptr_t)(descPtr)) + - (CEDI_PdVar(rxDescriptorSize))); - } - } - - if (!ptrsOnly) { - /* write hardware base address register */ - regTmp = 0; - EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MODIFY(regTmp, pAddr>>2); - switch (queueNum) { - case 0: - CPS_UncachedWrite32(CEDI_RegAddr(receive_q_ptr), regTmp); - break; - CEDI_WR_RXQ_PTR_REG_N_CASE(1); - CEDI_WR_RXQ_PTR_REG_N_CASE(2); - CEDI_WR_RXQ_PTR_REG_N_CASE(3); - CEDI_WR_RXQ_PTR_REG_N_CASE(4); - CEDI_WR_RXQ_PTR_REG_N_CASE(5); - CEDI_WR_RXQ_PTR_REG_N_CASE(6); - CEDI_WR_RXQ_PTR_REG_N_CASE(7); - CEDI_WR_RXQ_PTR_REG_N_CASE(8); - CEDI_WR_RXQ_PTR_REG_N_CASE(9); - CEDI_WR_RXQ_PTR_REG_N_CASE(10); - CEDI_WR_RXQ_PTR_REG_N_CASE(11); - CEDI_WR_RXQ_PTR_REG_N_CASE(12); - CEDI_WR_RXQ_PTR_REG_N_CASE(13); - CEDI_WR_RXQ_PTR_REG_N_CASE(14); - CEDI_WR_RXQ_PTR_REG_N_CASE(15); - } - } - return 0; -} - -/* Return the content of EMAC receive status register - * @param pD - driver private state info specific to this instance - * @param status - pointer to struct with fields for each flag - * @return =1 if any flags set, =0 if not or status=NULL. - */ -uint32_t emacGetRxStatus(void *pD, CEDI_RxStatus *status) -{ - uint32_t reg; - if ((pD==NULL)||(status==NULL)) - return 0; - - reg = CPS_UncachedRead32(CEDI_RegAddr(receive_status)); - - status->buffNotAvail = - EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__READ(reg); - status->frameRx = - EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__READ(reg); - status->rxOverrun = - EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__READ(reg); - status->hRespNotOk = - EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__READ(reg); - - return reg?1:0; -} - -/* Reset the bits of EMAC receive status register as selected in resetStatus - * @param pD - driver private state info specific to this instance - * @param resetStatus - OR'd combination of CEDI_RXS_ bit-fields - */ -void emacClearRxStatus(void *pD, uint32_t resetStatus) -{ - uint32_t reg = 0; - if (!pD) return; - - if (resetStatus & CEDI_RXS_NO_BUFF) - reg |= CEDI_RXS_NO_BUFF; - - if (resetStatus & CEDI_RXS_FRAME_RX) - reg |= CEDI_RXS_FRAME_RX; - - if (resetStatus & CEDI_RXS_OVERRUN) - reg |= CEDI_RXS_OVERRUN; - - if (resetStatus & CEDI_RXS_HRESP_ERR) - reg |= CEDI_RXS_HRESP_ERR; - - CPS_UncachedWrite32(CEDI_RegAddr(receive_status), reg); -} - -/** - * Enable/disable header-data split feature. - * When enabled, frame L2/L3/L4 headers will written to separate - * buffer, before data starts in a second buffer (if not zero payload) - */ -uint32_t emacSetHdrDataSplit(void *pD, uint8_t enable) { - - uint32_t reg; - if ((pD==NULL) || (enable>1)) - return EINVAL; - if (CEDI_PdVar(hwCfg).hdr_split==0) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(dma_config)); - if (enable) - EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SET(reg); - else - EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__CLR(reg); - - CPS_UncachedWrite32(CEDI_RegAddr(dma_config), reg); - return EOK; -} - -/** - * Read enable/disable status for header-data split feature - */ -uint32_t emacGetHdrDataSplit(void *pD, uint8_t *enable) { - - if ((pD==NULL) || (enable==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).hdr_split==0) - return ENOTSUP; - - *enable = EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__READ( - CPS_UncachedRead32(CEDI_RegAddr(dma_config))); - - return EOK; -} - -/** - * Enable/disable Receive Segment Coalescing function. - * When enabled, consecutive TCP/IP frames on a priority queue - * will be combined to form a single large frame - */ -uint32_t emacSetRscEnable(void *pD, uint8_t queue, uint8_t enable) { - - uint32_t reg, enableField; - if (pD==NULL) - return EINVAL; - if (CEDI_PdVar(hwCfg).pbuf_rsc==0) - return ENOTSUP; - if ((queue<1) || (queue>=(CEDI_PdVar(cfg)).rxQs) || (enable>1)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(rsc_control)); - enableField = EMAC_REGS__RSC_CONTROL__RSC_CONTROL__READ(reg); - - if (enable) - enableField |= (1 << (queue-1)); - else - enableField &= ~(1 << (queue-1)); - - EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MODIFY(reg, enableField); - CPS_UncachedWrite32(CEDI_RegAddr(rsc_control), reg); - - return EOK; -} - -/** - * Read enabled status of RSC on a specified priority queue - */ -uint32_t emacGetRscEnable(void *pD, uint8_t queue, uint8_t *enable) { - - uint32_t reg; - if ((pD==NULL) || (enable==NULL)) - return EINVAL; - if ((queue<1)||(queue>=(CEDI_PdVar(cfg)).rxQs)) - return EINVAL; - if (CEDI_PdVar(hwCfg).pbuf_rsc==0) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(rsc_control)); - *enable = (EMAC_REGS__RSC_CONTROL__RSC_CONTROL__READ(reg) - & (1<<(queue-1)))?1:0; - - return EOK; -} - -/** - * Set/Clear Mask of Receive Segment Coalescing disabling. - * When mask is set and RSC is enabled, the RSC operation is not - * disabled by receipt of frame with an end-coalesce flag set - * (SYN/FIN/RST/URG) - */ -uint32_t emacSetRscClearMask(void *pD, uint8_t setMask) { - - uint32_t reg; - if ((pD==NULL) || (setMask>1)) - return EINVAL; - if (CEDI_PdVar(hwCfg).pbuf_rsc==0) - return ENOTSUP; - - reg = CPS_UncachedRead32(CEDI_RegAddr(rsc_control)); - if (setMask) - reg |= (1<<16); - else - reg &= ~(1<<16); - CPS_UncachedWrite32(CEDI_RegAddr(rsc_control), reg); - - return EOK; -} - -uint32_t emacSetRxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable) -{ - uint32_t reg; - if (!pD) return EINVAL; - if (CEDI_PdVar(hwCfg).rx_pkt_buffer==0) - return ENOTSUP; - if (enable>1) return EINVAL; -// if ((enable) && (!CEDI_PdVar(hwCfg).rx_pkt_buffer)) -// return EINVAL; - if (watermark>((1<byte[0] + (addr->byte[1]<<8) + \ - (addr->byte[2]<<16) + (addr->byte[3]<<24));\ - CPS_UncachedWrite32((CEDI_RegAddr(spec_add##reg##_bottom)),\ - regVal);\ - regVal = 0;\ - if (reg==1) {\ - EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MODIFY(regVal,\ - addr->byte[4] + (addr->byte[5]<<8));\ - EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MODIFY( \ - regVal,specFilterType);\ - } else {\ - EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MODIFY(regVal,\ - addr->byte[4] + (addr->byte[5]<<8));\ - EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MODIFY( \ - regVal,specFilterType);\ - EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MODIFY( \ - regVal,byteMask);\ - }\ - CPS_UncachedWrite32((CEDI_RegAddr(spec_add##reg##_top)),\ - regVal); break; - - uint32_t regVal; - if ((!pD)||(addr==NULL)) return EINVAL; - if ((!addrNum) || (addrNum>(CEDI_PdVar(hwCfg).num_spec_add_filters))) - return EINVAL; - if ((specFilterType>1) || (byteMask>0x3F)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).num_spec_add_filters==0) - return ENOTSUP; - - regVal = 0; - switch(addrNum) { - CEDI_WR_SPEC_ADDR_CASE(1) - CEDI_WR_SPEC_ADDR_CASE(2) - CEDI_WR_SPEC_ADDR_CASE(3) - CEDI_WR_SPEC_ADDR_CASE(4) - CEDI_WR_SPEC_ADDR_CASE(5) - CEDI_WR_SPEC_ADDR_CASE(6) - CEDI_WR_SPEC_ADDR_CASE(7) - CEDI_WR_SPEC_ADDR_CASE(8) - CEDI_WR_SPEC_ADDR_CASE(9) - CEDI_WR_SPEC_ADDR_CASE(10) - CEDI_WR_SPEC_ADDR_CASE(11) - CEDI_WR_SPEC_ADDR_CASE(12) - CEDI_WR_SPEC_ADDR_CASE(13) - CEDI_WR_SPEC_ADDR_CASE(14) - CEDI_WR_SPEC_ADDR_CASE(15) - CEDI_WR_SPEC_ADDR_CASE(16) - CEDI_WR_SPEC_ADDR_CASE(17) - CEDI_WR_SPEC_ADDR_CASE(18) - CEDI_WR_SPEC_ADDR_CASE(19) - CEDI_WR_SPEC_ADDR_CASE(20) - CEDI_WR_SPEC_ADDR_CASE(21) - CEDI_WR_SPEC_ADDR_CASE(22) - CEDI_WR_SPEC_ADDR_CASE(23) - CEDI_WR_SPEC_ADDR_CASE(24) - CEDI_WR_SPEC_ADDR_CASE(25) - CEDI_WR_SPEC_ADDR_CASE(26) - CEDI_WR_SPEC_ADDR_CASE(27) - CEDI_WR_SPEC_ADDR_CASE(28) - CEDI_WR_SPEC_ADDR_CASE(29) - CEDI_WR_SPEC_ADDR_CASE(30) - CEDI_WR_SPEC_ADDR_CASE(31) - CEDI_WR_SPEC_ADDR_CASE(32) -} - - return EOK; -} - - /** - * Get the value of a specific address register - * @param[in] pD driver private state info specific to this instance - * @param[in] addrNum number of specific address filters, in - * range 1 - num_spec_add_filters - * @param[out] specFilterType flag specifying whether to use MAC source or - * destination address for filtering. When set to 1 use source address. - * @param[out] byteMask Bits masking out bytes of specific address from - * comparison. When high, the associated address byte will be ignored. - * e.g. LSB of byteMask=1 implies first byte received should not be compared - * Ignored if addrNum=1, full bit masking available (SpecificAddr1Mask) - * @param[out] addr pointer to a 6-byte MAC address struct for returning the - * address value - * @return 0 if successful - * @return EINVAL if pD, addrNum, specFilterType or byteMask invalid - * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 - */ -uint32_t emacGetSpecificAddr(void *pD, uint8_t addrNum, CEDI_MacAddress *addr, - uint8_t *specFilterType, uint8_t *byteMask) -{ - -#define CEDI_RD_SPEC_ADDR_CASE(reg) \ - case(reg):\ - regAddrBottom = EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__READ(\ - CPS_UncachedRead32(CEDI_RegAddr(spec_add##reg##_bottom)));\ - regTopVal= CPS_UncachedRead32(CEDI_RegAddr(spec_add##reg##_top));\ - if (reg==1) {\ - regAddrTop = EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__READ(\ - regTopVal);\ - *specFilterType = \ - EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__READ(regTopVal);\ - *byteMask = 0;\ - } else {\ - regAddrTop = EMAC_REGS__SPEC_ADD_TOP__ADDRESS__READ(regTopVal);\ - *specFilterType = \ - EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__READ(regTopVal);\ - *byteMask = \ - EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__READ(regTopVal);}\ - break; - - uint32_t regAddrTop, regAddrBottom, regTopVal; - if ((pD==NULL)||(addr==NULL)) - return EINVAL; - - if ((specFilterType==NULL)||(byteMask==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).num_spec_add_filters==0) - return ENOTSUP; - if ((!addrNum) || (addrNum>(CEDI_PdVar(hwCfg).num_spec_add_filters))) - return EINVAL; - regAddrTop = 0; - regAddrBottom = 0; - switch(addrNum) { - CEDI_RD_SPEC_ADDR_CASE(1) - CEDI_RD_SPEC_ADDR_CASE(2) - CEDI_RD_SPEC_ADDR_CASE(3) - CEDI_RD_SPEC_ADDR_CASE(4) - CEDI_RD_SPEC_ADDR_CASE(5) - CEDI_RD_SPEC_ADDR_CASE(6) - CEDI_RD_SPEC_ADDR_CASE(7) - CEDI_RD_SPEC_ADDR_CASE(8) - CEDI_RD_SPEC_ADDR_CASE(9) - CEDI_RD_SPEC_ADDR_CASE(10) - CEDI_RD_SPEC_ADDR_CASE(11) - CEDI_RD_SPEC_ADDR_CASE(12) - CEDI_RD_SPEC_ADDR_CASE(13) - CEDI_RD_SPEC_ADDR_CASE(14) - CEDI_RD_SPEC_ADDR_CASE(15) - CEDI_RD_SPEC_ADDR_CASE(16) - CEDI_RD_SPEC_ADDR_CASE(17) - CEDI_RD_SPEC_ADDR_CASE(18) - CEDI_RD_SPEC_ADDR_CASE(19) - CEDI_RD_SPEC_ADDR_CASE(20) - CEDI_RD_SPEC_ADDR_CASE(21) - CEDI_RD_SPEC_ADDR_CASE(22) - CEDI_RD_SPEC_ADDR_CASE(23) - CEDI_RD_SPEC_ADDR_CASE(24) - CEDI_RD_SPEC_ADDR_CASE(25) - CEDI_RD_SPEC_ADDR_CASE(26) - CEDI_RD_SPEC_ADDR_CASE(27) - CEDI_RD_SPEC_ADDR_CASE(28) - CEDI_RD_SPEC_ADDR_CASE(29) - CEDI_RD_SPEC_ADDR_CASE(30) - CEDI_RD_SPEC_ADDR_CASE(31) - CEDI_RD_SPEC_ADDR_CASE(32) - } - -// vDbgMsg(DBG_GEN_MSG, 10, "top=%08X bottom=%08X\n", -// regAddrTop, regAddrBottom); - addr->byte[0] = (regAddrBottom & 0xFF); - addr->byte[1] = ((regAddrBottom>>8) & 0xFF); - addr->byte[2] = ((regAddrBottom>>16) & 0xFF); - addr->byte[3] = ((regAddrBottom>>24) & 0xFF); - addr->byte[4] = (regAddrTop & 0xFF); - addr->byte[5] = ((regAddrTop>>8) & 0xFF); - return EOK; -} - -/* Set the specific address 1 mask register to the given value, allowing - * address matching against a portion of the specific address 1 register - * @param pD - driver private state info specific to this instance - * @param mask - pointer to the address mask value to write - * @return 0 if successful - * @return EINVAL if mask=NULL - * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 - */ -uint32_t emacSetSpecificAddr1Mask(void *pD, CEDI_MacAddress *mask) -{ - uint32_t reg; - - if ((pD==NULL) || (mask==NULL)) - return EINVAL; - if (CEDI_PdVar(hwCfg).num_spec_add_filters==0) - return ENOTSUP; - - reg = 0; - EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MODIFY(reg, - mask->byte[0] + (mask->byte[1]<<8) + (mask->byte[2]<<16) - + (mask->byte[3]<<24)); - CPS_UncachedWrite32((CEDI_RegAddr(mask_add1_bottom)), reg); - reg = 0; - EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MODIFY(reg, - mask->byte[4] + (mask->byte[5]<<8)); - CPS_UncachedWrite32((CEDI_RegAddr(mask_add1_top)), reg); - return EOK; -} - -/* Get the value of the specific address 1 mask register - * @param pD - driver private state info specific to this instance - * @param mask - pointer to a 6-byte MAC address struct for returning the - * mask value - * @return 0 if successful, EINVAL if addrNum invalid - * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 - */ -uint32_t emacGetSpecificAddr1Mask(void *pD, CEDI_MacAddress *mask) -{ - int reg1, reg2; - if ((pD==NULL)||(mask==NULL)) return EINVAL; - if (CEDI_PdVar(hwCfg).num_spec_add_filters==0) - return ENOTSUP; - - reg1 = EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__READ( - CPS_UncachedRead32(CEDI_RegAddr(mask_add1_bottom))); - reg2 = EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__READ( - CPS_UncachedRead32(CEDI_RegAddr(mask_add1_top))); - -// vDbgMsg(DBG_GEN_MSG, 10, "top=%08X bottom=%08X\n", reg2, reg1); - mask->byte[0] = (reg1 & 0xFF); - mask->byte[1] = ((reg1>>8) & 0xFF); - mask->byte[2] = ((reg1>>16) & 0xFF); - mask->byte[3] = ((reg1>>24) & 0xFF); - mask->byte[4] = (reg2 & 0xFF); - mask->byte[5] = ((reg2>>8) & 0xFF); - return EOK; -} - -/* Disable the specific address match stored at given register, by writing 0 - * to lower address register - * @param pD - driver private state info specific to this instance - * @param addrNum - - * number of specific address filters, in range 1 - num_spec_add_filters - * $RANGE $FROM 1 $TO CEDI_DesignCfg.num_spec_add_filters$ - * @return 0 if successful - * @return EINVAL if invalid parameter - * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 - */ -uint32_t emacDisableSpecAddr(void *pD, uint8_t addrNum) -{ -#define CEDI_DIS_SPEC_ADDR_CASE(reg) \ - case(reg): \ - CPS_UncachedWrite32((CEDI_RegAddr(spec_add##reg##_bottom)), 0); break; - - if (!pD) return EINVAL; - if (CEDI_PdVar(hwCfg).num_spec_add_filters==0) - return ENOTSUP; - if ((!addrNum) || (addrNum>(CEDI_PdVar(hwCfg).num_spec_add_filters))) - return EINVAL; - - switch(addrNum) { - CEDI_DIS_SPEC_ADDR_CASE(1) - CEDI_DIS_SPEC_ADDR_CASE(2) - CEDI_DIS_SPEC_ADDR_CASE(3) - CEDI_DIS_SPEC_ADDR_CASE(4) - CEDI_DIS_SPEC_ADDR_CASE(5) - CEDI_DIS_SPEC_ADDR_CASE(6) - CEDI_DIS_SPEC_ADDR_CASE(7) - CEDI_DIS_SPEC_ADDR_CASE(8) - CEDI_DIS_SPEC_ADDR_CASE(9) - CEDI_DIS_SPEC_ADDR_CASE(10) - CEDI_DIS_SPEC_ADDR_CASE(11) - CEDI_DIS_SPEC_ADDR_CASE(12) - CEDI_DIS_SPEC_ADDR_CASE(13) - CEDI_DIS_SPEC_ADDR_CASE(14) - CEDI_DIS_SPEC_ADDR_CASE(15) - CEDI_DIS_SPEC_ADDR_CASE(16) - CEDI_DIS_SPEC_ADDR_CASE(17) - CEDI_DIS_SPEC_ADDR_CASE(18) - CEDI_DIS_SPEC_ADDR_CASE(19) - CEDI_DIS_SPEC_ADDR_CASE(20) - CEDI_DIS_SPEC_ADDR_CASE(21) - CEDI_DIS_SPEC_ADDR_CASE(22) - CEDI_DIS_SPEC_ADDR_CASE(23) - CEDI_DIS_SPEC_ADDR_CASE(24) - CEDI_DIS_SPEC_ADDR_CASE(25) - CEDI_DIS_SPEC_ADDR_CASE(26) - CEDI_DIS_SPEC_ADDR_CASE(27) - CEDI_DIS_SPEC_ADDR_CASE(28) - CEDI_DIS_SPEC_ADDR_CASE(29) - CEDI_DIS_SPEC_ADDR_CASE(30) - CEDI_DIS_SPEC_ADDR_CASE(31) - CEDI_DIS_SPEC_ADDR_CASE(32) - } - - return 0; -} - -/** - * En/Disable Type ID match field of the specified register, and set - * type Id value if enabling - * @param[in] pD driver private state info specific to this instance - * @param[in] matchSel number of TypeID Match register, range 1 - 4 - * $RANGE $FROM 1 $TO 4$ - * @param[in] typeId the Type ID match value to write, - * ignored if enable equal 0 - * @param[in] enable if equal 1 enables the type matching for this ID, - * if 0 then disables type matching for this ID - * $RANGE $FROM 0 $TO 1$ - * @return 0 if successful, - * @return EINVAL if matchSel invalid - * $VALIDFAIL if ((enable==0)&&((matchSel<1)||(matchSel>4))) - * $EXPECT_RETURN EINVAL $ - */ -uint32_t emacSetTypeIdMatch(void *pD, uint8_t matchSel, uint16_t typeId, - uint8_t enable) -{ - uint32_t regVal = 0; - if ((pD==NULL) || (matchSel<1) || (matchSel>4)) return EINVAL; - if (enable>1) return EINVAL; - - switch (matchSel) { - case 1: - if (enable) { - EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SET(regVal); - EMAC_REGS__SPEC_TYPE1__MATCH__MODIFY(regVal, typeId); - } - CPS_UncachedWrite32(CEDI_RegAddr(spec_type1),regVal); - break; - case 2: - if (enable) { - EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SET(regVal); - EMAC_REGS__SPEC_TYPE2__MATCH__MODIFY(regVal, typeId); - } - CPS_UncachedWrite32(CEDI_RegAddr(spec_type2),regVal); - break; - case 3: - if (enable) { - EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SET(regVal); - EMAC_REGS__SPEC_TYPE3__MATCH__MODIFY(regVal, typeId); - } - CPS_UncachedWrite32(CEDI_RegAddr(spec_type3),regVal); - break; - case 4: - if (enable) { - EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SET(regVal); - EMAC_REGS__SPEC_TYPE4__MATCH__MODIFY(regVal, typeId); - } - CPS_UncachedWrite32(CEDI_RegAddr(spec_type4),regVal); - break; - } - - return 0; -} - -/* Read the specified Type ID match register settings - * @param pD - driver private state info specific to this instance - * @param matchSel - number of TypeID Match register, range 1 - 4 - * @param typeId - pointer for returning the Type ID match value read, - * ignored if disabled - * @param enabled - pointer for returning enabled status: if value returned <>0 - * then typeId matching is enabled for this register, else disabled - * @return 0 if successful, EINVAL if invalid parameter - */ -uint32_t emacGetTypeIdMatch(void *pD, uint8_t matchSel, uint16_t *typeId, - uint8_t *enabled) -{ - uint32_t regVal = 0; - if (pD==NULL) return EINVAL; - if ((matchSel<1) || (matchSel>4) || (enabled==NULL)) return EINVAL; - if (*enabled && (typeId==NULL)) return EINVAL; - - switch (matchSel) { - case 1: - regVal = CPS_UncachedRead32(CEDI_RegAddr(spec_type1)); - *enabled = EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__READ(regVal); - *typeId = EMAC_REGS__SPEC_TYPE1__MATCH__READ(regVal); - break; - case 2: - regVal = CPS_UncachedRead32(CEDI_RegAddr(spec_type2)); - *enabled = EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__READ(regVal); - *typeId = EMAC_REGS__SPEC_TYPE2__MATCH__READ(regVal); - break; - case 3: - regVal = CPS_UncachedRead32(CEDI_RegAddr(spec_type3)); - *enabled = EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__READ(regVal); - *typeId = EMAC_REGS__SPEC_TYPE3__MATCH__READ(regVal); - break; - case 4: - regVal = CPS_UncachedRead32(CEDI_RegAddr(spec_type4)); - *enabled = EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__READ(regVal); - *typeId = EMAC_REGS__SPEC_TYPE4__MATCH__READ(regVal); - break; - } - - return 0; -} - -/* En/disable reception of unicast frames when hash register matched - * @param pD - driver private state info specific to this instance - * @param enable if<>0, enables reception, else disables - */ -void emacSetUnicastEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - if (!pD) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -/* Return state of unicast frame matching - * @param pD - driver private state info specific to this instance - * @return =0 if disabled, =1 if enabled - */ -uint32_t emacGetUnicastEnable(void *pD, uint8_t *enable) -{ - if ((pD==0)||(enable==0)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -/* En/disable reception of multicast frames when hash register matched - * @param pD - driver private state info specific to this instance - * @param enable if<>0, enables, else disables - */ -void emacSetMulticastEnable(void *pD, uint8_t enable) -{ - uint32_t reg; - if (!pD) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -/* Return state of multicast frame matching - * @param pD - driver private state info specific to this instance - * @return =0 if disabled, =1 if enabled - */ -uint32_t emacGetMulticastEnable(void *pD, uint8_t *enable) -{ - if ((pD==0)||(enable==0)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -/* Dis/Enable receipt of broadcast frames - * @param pD - driver private state info specific to this instance - * @param reject if =0 broadcasts are accepted, else they are rejected. - */ -void emacSetNoBroadcast(void *pD, uint8_t reject) -{ - uint32_t reg; - if (!pD) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (reject) - EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -/* Return broadcast rejection setting - * @param pD - driver private state info specific to this instance - * @return if =0, broadcasts being accepted, else rejected - */ -uint32_t emacGetNoBroadcast(void *pD, uint8_t *reject) -{ - if ((pD==0)||(reject==0)) - return EINVAL; - *reject= EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -/* En/Disable receipt of only frames which have been VLAN tagged - * @param pD - driver private state info specific to this instance - * @param enable<>0 to reject non-VLAN-tagged frames. - */ -void emacSetVlanOnly(void *pD, uint8_t enable) -{ - uint32_t reg; - if (!pD) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -/* Return VLAN-tagged filter setting - * @param pD - driver private state info specific to this instance - * @return <>0 if VLAN-only, else accept non-VLAN tagged frames - */ -uint32_t emacGetVlanOnly(void *pD, uint8_t *enable) -{ - if ((pD==0)||(enable==0)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -/* En/Disable stacked VLAN processing mode. - * @param pD - driver private state info specific to this instance - * @param enable - if <>0 enables stacked VLAN processing, if =0 disables it - * @param vlanType - sets user defined VLAN type for matching first VLAN tag. - * Ignored if enable =0. - */ -void emacSetStackedVlanReg(void *pD, uint8_t enable, uint16_t vlanType) -{ - uint32_t reg; - if (!pD) return; - if (enable>1) return; - - reg = CPS_UncachedRead32(CEDI_RegAddr(stacked_vlan)); - if (enable) { - EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SET(reg); - EMAC_REGS__STACKED_VLAN__MATCH__MODIFY(reg, vlanType); - } - else - EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(stacked_vlan), reg); -} - -/* Reads stacked VLAN register settings. - * @param pD - driver private state info specific to this instance - * @param enable - pointer for returning Enabled field: =1 if enabled, =0 if - * disabled. - * @param vlanType - pointer for returning VLAN type field - * - */ -void emacGetStackedVlanReg(void *pD, uint8_t *enable, uint16_t *vlanType) -{ - uint32_t reg; - if ((pD==NULL)||(enable==NULL) || (vlanType==NULL)) return; - - reg = CPS_UncachedRead32(CEDI_RegAddr(stacked_vlan)); - *enable = EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__READ(reg); - *vlanType = EMAC_REGS__STACKED_VLAN__MATCH__READ(reg); -} - -/* En/Disable copy all frames mode - * @param pD - driver private state info specific to this instance - * @param enable - if <>0, enables copy all frames mode, else this is - * disabled - */ -void emacSetCopyAllFrames(void *pD, uint8_t enable) -{ - uint32_t reg; - if (!pD) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -/* Get "copy all" setting - * @param pD - driver private state info specific to this instance - * @return =0 if disabled, =1 if enabled - */ -uint32_t emacGetCopyAllFrames(void *pD, uint8_t *enable) -{ - if ((pD==0)||(enable==0)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -/* Set the hash address register. - * @param pD - driver private state info specific to this instance - * @param hAddrTop - most significant 32 bits of hash register - * @param hAddrBot - least significant 32 bits of hash register - * @return EINVAL if pD=NULL, else 0. - */ -uint32_t emacSetHashAddr(void *pD, uint32_t hAddrTop, uint32_t hAddrBot) -{ - if (pD==NULL) return EINVAL; - CPS_UncachedWrite32(CEDI_RegAddr(hash_bottom), - EMAC_REGS__HASH_BOTTOM__ADDRESS__WRITE(hAddrBot)); - CPS_UncachedWrite32(CEDI_RegAddr(hash_top), - EMAC_REGS__HASH_TOP__ADDRESS__WRITE(hAddrTop)); - return 0; -} - -/* Read the hash address register. - * @param pD - driver private state info specific to this instance - * @param hAddrTop - pointer for returning most significant 32 bits of - * hash register - * @param hAddrBot - pointer for returning least significant 32 bits of - * hash register - * @return EINVAL if any parameter =NULL, else 0. - */ -uint32_t emacGetHashAddr(void *pD, uint32_t *hAddrTop, uint32_t *hAddrBot) -{ - if ((pD==NULL) || (hAddrTop==NULL) || (hAddrBot==NULL)) return EINVAL; - *hAddrBot = EMAC_REGS__HASH_BOTTOM__ADDRESS__READ( - CPS_UncachedRead32(CEDI_RegAddr(hash_bottom))); - *hAddrTop = EMAC_REGS__HASH_TOP__ADDRESS__READ( - CPS_UncachedRead32(CEDI_RegAddr(hash_top))); - return 0; -} - -/* Enable/disable discard of frames with length shorter than given in length - * field - * @param pD - driver private state info specific to this instance - * @param enable - if <>1 then enable, else disable. - */ -void emacSetLenErrDiscard(void *pD, uint8_t enable) -{ - uint32_t reg; - if (!pD) return; - if (enable>1) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) - EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SET(reg); - else - EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); -} - -/* Read enable/disable status for discard of frames with length shorter than - * given in length field. - * @param pD - driver private state info specific to this instance - * @return 1 if enabled, 0 if disabled. - */ -uint32_t emacGetLenErrDiscard(void *pD, uint8_t *enable) -{ - if ((pD==0)||(enable==0)) - return EINVAL; - *enable= EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_config))); - - return 0; -} - -/******************************** Rx Priority Queues ******************************/ - -/* Return the numbers of screener, ethtype & compare registers present - * @param pD - driver private state info specific to this instance - * @param regNums - points to a CEDI_NumScreeners struct with the match parameters - * to be written - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacGetNumScreenRegs(void *pD, CEDI_NumScreeners *regNums) -{ - if ((pD==NULL) || (regNums==NULL)) - return EINVAL; - - regNums->type1ScrRegs = CEDI_PdVar(hwCfg).num_type1_screeners; - regNums->type2ScrRegs = CEDI_PdVar(hwCfg).num_type2_screeners; - regNums->ethtypeRegs = CEDI_PdVar(hwCfg).num_scr2_ethtype_regs; - regNums->compareRegs = CEDI_PdVar(hwCfg).num_scr2_compare_regs; - return 0; -} - - -/* Write Rx frame matching values to a Type 1 screening register, for allocating - * to a priority queue. - * @param pD - driver private state info specific to this instance - * @param regNum - the Type 1 register number, range 0 to num_type1_screeners-1 - * @param regVals - points to a CEDI_T1Screen struct with the match parameters - * to be written - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacSetType1ScreenReg(void *pD, uint8_t regNum, CEDI_T1Screen *regVals) -{ -#define CEDI_WR_SCRN_TYPE1_REG_CASE(rNum) \ - case(rNum):\ - CPS_UncachedWrite32(CEDI_RegAddr(screening_type_1_register_##rNum),reg);\ - break; - - uint32_t reg; - if ((pD==NULL) || (regVals==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).num_type1_screeners==0) - return ENOTSUP; - - if ((regNum>=CEDI_PdVar(hwCfg).num_type1_screeners) || - (regVals->qNum>=CEDI_PdVar(cfg).rxQs) || - (regVals->udpEnable>1) || (regVals->dstcEnable>1)) - return EINVAL; - - reg = 0; - EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MODIFY(reg, - regVals->qNum); - EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MODIFY(reg, - regVals->dstcEnable); - EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MODIFY(reg, - regVals->dstcMatch); - EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MODIFY(reg, - regVals->udpEnable); - EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MODIFY(reg, - regVals->udpPort); - - switch (regNum) { - CEDI_WR_SCRN_TYPE1_REG_CASE(0) - CEDI_WR_SCRN_TYPE1_REG_CASE(1) - CEDI_WR_SCRN_TYPE1_REG_CASE(2) - CEDI_WR_SCRN_TYPE1_REG_CASE(3) - CEDI_WR_SCRN_TYPE1_REG_CASE(4) - CEDI_WR_SCRN_TYPE1_REG_CASE(5) - CEDI_WR_SCRN_TYPE1_REG_CASE(6) - CEDI_WR_SCRN_TYPE1_REG_CASE(7) - CEDI_WR_SCRN_TYPE1_REG_CASE(8) - CEDI_WR_SCRN_TYPE1_REG_CASE(9) - CEDI_WR_SCRN_TYPE1_REG_CASE(10) - CEDI_WR_SCRN_TYPE1_REG_CASE(11) - CEDI_WR_SCRN_TYPE1_REG_CASE(12) - CEDI_WR_SCRN_TYPE1_REG_CASE(13) - CEDI_WR_SCRN_TYPE1_REG_CASE(14) - CEDI_WR_SCRN_TYPE1_REG_CASE(15) - } - return 0; -} - -/* Read Rx frame matching values from a Type1 screening register - * @param pD - driver private state info specific to this instance - * @param regNum - the Type 1 register number, range 0 to num_type1_screeners-1 - * @param regVals - points to a CEDI_T1Screen struct for returning the match - * parameters - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacGetType1ScreenReg(void *pD, uint8_t regNum, CEDI_T1Screen *regVals) -{ -#define CEDI_RD_SCRN_TYPE1_REG_CASE(rNum) \ - case(rNum):\ - reg=CPS_UncachedRead32(CEDI_RegAddr(screening_type_1_register_##rNum));\ - break; - - uint32_t reg = 0; - - if ((pD==NULL) || (regVals==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).num_type1_screeners==0) - return ENOTSUP; - - if (regNum>=CEDI_PdVar(hwCfg).num_type1_screeners) - return EINVAL; - - switch (regNum) { - CEDI_RD_SCRN_TYPE1_REG_CASE(0) - CEDI_RD_SCRN_TYPE1_REG_CASE(1) - CEDI_RD_SCRN_TYPE1_REG_CASE(2) - CEDI_RD_SCRN_TYPE1_REG_CASE(3) - CEDI_RD_SCRN_TYPE1_REG_CASE(4) - CEDI_RD_SCRN_TYPE1_REG_CASE(5) - CEDI_RD_SCRN_TYPE1_REG_CASE(6) - CEDI_RD_SCRN_TYPE1_REG_CASE(7) - CEDI_RD_SCRN_TYPE1_REG_CASE(8) - CEDI_RD_SCRN_TYPE1_REG_CASE(9) - CEDI_RD_SCRN_TYPE1_REG_CASE(10) - CEDI_RD_SCRN_TYPE1_REG_CASE(11) - CEDI_RD_SCRN_TYPE1_REG_CASE(12) - CEDI_RD_SCRN_TYPE1_REG_CASE(13) - CEDI_RD_SCRN_TYPE1_REG_CASE(14) - CEDI_RD_SCRN_TYPE1_REG_CASE(15) - } - regVals->qNum = - EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__READ(reg); - regVals->dstcMatch = - EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__READ(reg); - regVals->udpPort = - EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__READ(reg); - regVals->dstcEnable = - EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__READ(reg); - regVals->udpEnable = - EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__READ( - reg); - return 0; -} - -/* Write Rx frame matching values to a Type 2 screening register, for - * allocating to a priority queue. - * @param pD - driver private state info specific to this instance - * @param regNum - the Type 2 register number, range 0 to num_type2_screeners-1 - * @param regVals - points to a CEDI_T2Screen struct with the match - * parameters to be written - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacSetType2ScreenReg(void *pD, uint8_t regNum, CEDI_T2Screen *regVals) -{ -#define CEDI_WR_SCRN_TYPE2_REG_CASE(rNum) \ - case(rNum):\ - CPS_UncachedWrite32(CEDI_RegAddr(screening_type_2_register_##rNum),\ - reg); break; - - uint32_t reg; - - if ((pD==NULL) || (regVals==NULL)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).num_type2_screeners==0) - return ENOTSUP; - - if ((regNum>=CEDI_PdVar(hwCfg).num_type2_screeners) || - (regVals->qNum>=CEDI_PdVar(cfg).rxQs) || - (regVals->vlanEnable>1) || - (regVals->vlanEnable && (regVals->vlanPriority>=8)) || - (regVals->eTypeEnable>1) || - ((regVals->eTypeEnable) && (regVals->ethTypeIndex>=8)) || - ((regVals->eTypeEnable) && - (regVals->ethTypeIndex>=CEDI_PdVar(hwCfg).num_scr2_ethtype_regs)) || - (regVals->compAEnable>1) || - ((regVals->compAEnable) && (regVals->compAIndex>=32)) || - ((regVals->compAEnable) && - (regVals->compAIndex>=CEDI_PdVar(hwCfg).num_scr2_compare_regs)) || - (regVals->compBEnable>1) || - ((regVals->compBEnable) && (regVals->compBIndex>=32)) || - ((regVals->compBEnable) && - (regVals->compBIndex>=CEDI_PdVar(hwCfg).num_scr2_compare_regs)) || - (regVals->compCEnable>1) || - ((regVals->compCEnable) && (regVals->compCIndex>=32)) || - ((regVals->compCEnable) && - (regVals->compCIndex>=CEDI_PdVar(hwCfg).num_scr2_compare_regs))) - return EINVAL; - - reg = 0; - EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MODIFY(reg, - regVals->qNum); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MODIFY(reg, - regVals->vlanEnable); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MODIFY(reg, - regVals->vlanPriority); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MODIFY(reg, - regVals->eTypeEnable); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__MODIFY(reg, - regVals->ethTypeIndex); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MODIFY(reg, - regVals->compAEnable); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MODIFY(reg, - regVals->compAIndex); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MODIFY(reg, - regVals->compBEnable); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MODIFY(reg, - regVals->compBIndex); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MODIFY(reg, - regVals->compCEnable); - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MODIFY(reg, - regVals->compCIndex); - - switch (regNum) { - CEDI_WR_SCRN_TYPE2_REG_CASE(0) - CEDI_WR_SCRN_TYPE2_REG_CASE(1) - CEDI_WR_SCRN_TYPE2_REG_CASE(2) - CEDI_WR_SCRN_TYPE2_REG_CASE(3) - CEDI_WR_SCRN_TYPE2_REG_CASE(4) - CEDI_WR_SCRN_TYPE2_REG_CASE(5) - CEDI_WR_SCRN_TYPE2_REG_CASE(6) - CEDI_WR_SCRN_TYPE2_REG_CASE(7) - CEDI_WR_SCRN_TYPE2_REG_CASE(8) - CEDI_WR_SCRN_TYPE2_REG_CASE(9) - CEDI_WR_SCRN_TYPE2_REG_CASE(10) - CEDI_WR_SCRN_TYPE2_REG_CASE(11) - CEDI_WR_SCRN_TYPE2_REG_CASE(12) - CEDI_WR_SCRN_TYPE2_REG_CASE(13) - CEDI_WR_SCRN_TYPE2_REG_CASE(14) - CEDI_WR_SCRN_TYPE2_REG_CASE(15) - } - return 0; -} - -/* Read Rx frame matching values from a Type 2 screening register - * @param pD - driver private state info specific to this instance - * @param regNum - the Type 2 register number, range 0 to num_type2_screeners-1 - * @param regVals - points to a CEDI_T2Screen struct for returning the match - * parameters - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacGetType2ScreenReg(void *pD, uint8_t regNum, CEDI_T2Screen *regVals) -{ -#define CEDI_RD_SCRN_TYPE2_REG_CASE(rNum) \ - case(rNum):\ - reg=CPS_UncachedRead32(CEDI_RegAddr(screening_type_2_register_##rNum));\ - break; - - uint32_t reg = 0; - - if ((pD==0)||(regVals==0)) - return EINVAL; - - if (CEDI_PdVar(hwCfg).num_type2_screeners==0) - return ENOTSUP; - - if (regNum>=CEDI_PdVar(hwCfg).num_type2_screeners) - return EINVAL; - - switch (regNum) { - CEDI_RD_SCRN_TYPE2_REG_CASE(0) - CEDI_RD_SCRN_TYPE2_REG_CASE(1) - CEDI_RD_SCRN_TYPE2_REG_CASE(2) - CEDI_RD_SCRN_TYPE2_REG_CASE(3) - CEDI_RD_SCRN_TYPE2_REG_CASE(4) - CEDI_RD_SCRN_TYPE2_REG_CASE(5) - CEDI_RD_SCRN_TYPE2_REG_CASE(6) - CEDI_RD_SCRN_TYPE2_REG_CASE(7) - CEDI_RD_SCRN_TYPE2_REG_CASE(8) - CEDI_RD_SCRN_TYPE2_REG_CASE(9) - CEDI_RD_SCRN_TYPE2_REG_CASE(10) - CEDI_RD_SCRN_TYPE2_REG_CASE(11) - CEDI_RD_SCRN_TYPE2_REG_CASE(12) - CEDI_RD_SCRN_TYPE2_REG_CASE(13) - CEDI_RD_SCRN_TYPE2_REG_CASE(14) - CEDI_RD_SCRN_TYPE2_REG_CASE(15) - } - regVals->qNum = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__READ(reg); - regVals->vlanPriority = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__READ(reg); - regVals->vlanEnable = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__READ(reg); - regVals->ethTypeIndex = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__READ(reg); - regVals->eTypeEnable = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__READ(reg); - regVals->compAIndex = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__READ(reg); - regVals->compAEnable = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__READ(reg); - regVals->compBIndex = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__READ(reg); - regVals->compBEnable = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__READ(reg); - regVals->compCIndex = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__READ(reg); - regVals->compCEnable = - EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__READ(reg); - return 0; -} - -/* Write the ethertype compare value at the given index in the Ethertype - * registers - * @param pD - driver private state info specific to this instance - * @param index - number of screener Type 2 Ethertype compare register to - * write, range 0 to num_scr2_ethtype_regs-1 - * @param eTypeVal - Ethertype compare value to write - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacSetType2EthertypeReg(void *pD, uint8_t index, uint16_t eTypeVal) -{ -#define CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(rNum) \ - case(rNum):\ - CPS_UncachedWrite32(CEDI_RegAddr(screening_type_2_ethertype_reg_##rNum),reg);\ - break; - - uint32_t reg; - - if (pD==NULL) - return EINVAL; - - if ((CEDI_PdVar(hwCfg).num_type2_screeners==0) || - (CEDI_PdVar(hwCfg).num_scr2_ethtype_regs==0)) - return ENOTSUP; - - if (index>=CEDI_PdVar(hwCfg).num_scr2_ethtype_regs) - return EINVAL; - - reg = 0; - EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MODIFY(reg, - eTypeVal); - switch (index) { - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(0) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(1) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(2) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(3) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(4) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(5) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(6) - CEDI_WR_SCRN_TYPE2_ETHTYPE_REG_CASE(7) - } - return 0; -} - -/* Read the ethertype compare value at the given index in the Ethertype - * registers - * @param pD - driver private state info specific to this instance - * @param index - number of screener Type 2 Ethertype compare register to - * read, range 0 to num_scr2_ethtype_regs-1 - * @param eTypeVal - pointer for returning the Ethertype compare value - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacGetType2EthertypeReg(void *pD, uint8_t index, uint16_t *eTypeVal) -{ -#define CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(rNum) \ - case(rNum):\ - reg = CPS_UncachedRead32(CEDI_RegAddr(screening_type_2_ethertype_reg_##rNum));\ - break; - - uint32_t reg = 0; - - if ((pD==NULL)||(eTypeVal==NULL)) - return EINVAL; - - if ((CEDI_PdVar(hwCfg).num_type2_screeners==0) || - (CEDI_PdVar(hwCfg).num_scr2_ethtype_regs==0)) - return ENOTSUP; - - if (index>=CEDI_PdVar(hwCfg).num_scr2_ethtype_regs) - return EINVAL; - - switch (index) { - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(0) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(1) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(2) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(3) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(4) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(5) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(6) - CEDI_RD_SCRN_TYPE2_ETHTYPE_REG_CASE(7) - } - *eTypeVal = (uint16_t)( - EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__READ(reg)); - return 0; -} - -/* Write the compare value at the given index in the Type 2 compare register - * @param pD - driver private state info specific to this instance - * @param index - number of the Type 2 compare register to write, range 0 to - * num_scr2_compare_regs-1 - * @param regVals - points to a CEDI_T2Compare struct with the compare - * parameters to be written - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacSetType2CompareReg(void *pD, uint8_t index, CEDI_T2Compare *regVals) -{ -#define CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(rNum) \ - case(rNum):\ - CPS_UncachedWrite32(CEDI_RegAddr(type2_compare_##rNum##_word_0),reg0);\ - CPS_UncachedWrite32(CEDI_RegAddr(type2_compare_##rNum##_word_1),reg1);\ - break; - - uint32_t reg0, reg1; - - if ((pD==NULL)||(regVals==NULL)) - return EINVAL; - - if ((CEDI_PdVar(hwCfg).num_type2_screeners==0) || - (CEDI_PdVar(hwCfg).num_scr2_compare_regs==0)) - return ENOTSUP; - - if ((index>=CEDI_PdVar(hwCfg).num_scr2_compare_regs) - || (regVals->offsetVal>0x3F) - || (regVals->offsetPosition>CEDI_T2COMP_OFF_TCPUDP) - || (regVals->disableMask>1)) - return EINVAL; - - reg0 = 0; - reg1 = 0; - EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MODIFY(reg0, - regVals->compMask); - EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MODIFY(reg0, - regVals->compValue); - EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MODIFY(reg1, - regVals->offsetVal); - EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MODIFY(reg1, - regVals->offsetPosition); - EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MODIFY(reg1, - regVals->disableMask); - - switch (index) { - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(0) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(1) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(2) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(3) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(4) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(5) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(6) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(7) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(8) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(9) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(10) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(11) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(12) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(13) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(14) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(15) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(16) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(17) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(18) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(19) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(20) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(21) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(22) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(23) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(24) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(25) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(26) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(27) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(28) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(29) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(30) - CEDI_WR_SCRN_TYPE2_COMPARE_REG_CASE(31) - } - return 0; -} - -/* Read the compare value at the given index in the Type 2 compare register - * @param pD - driver private state info specific to this instance - * @param index - number of the Type 2 compare register to read, range 0 to - * num_scr2_compare_regs-1 - * @param regVals - points to a CEDI_T2Compare struct for returning the - * compare parameters - * @return 0 if successful, EINVAL if parameter invalid - */ -uint32_t emacGetType2CompareReg(void *pD, uint8_t index, CEDI_T2Compare *regVals) -{ -#define CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(rNum) \ - case(rNum):\ - reg0=CPS_UncachedRead32(CEDI_RegAddr(type2_compare_##rNum##_word_0));\ - reg1=CPS_UncachedRead32(CEDI_RegAddr(type2_compare_##rNum##_word_1));\ - break; - - uint32_t reg0 = 0, reg1 = 0; - - if ((pD==0)||(regVals==0)) - return EINVAL; - - if ((CEDI_PdVar(hwCfg).num_type2_screeners==0) || - (CEDI_PdVar(hwCfg).num_scr2_compare_regs==0)) - return ENOTSUP; - - if (index>=CEDI_PdVar(hwCfg).num_scr2_compare_regs) - return EINVAL; - - switch (index) { - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(0) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(1) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(2) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(3) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(4) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(5) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(6) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(7) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(8) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(9) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(10) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(11) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(12) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(13) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(14) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(15) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(16) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(17) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(18) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(19) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(20) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(21) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(22) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(23) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(24) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(25) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(26) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(27) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(28) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(29) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(30) - CEDI_RD_SCRN_TYPE2_COMPARE_REG_CASE(31) - } - - regVals->compMask =(uint16_t)( - EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__READ(reg0)); - regVals->compValue =(uint16_t)( - EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__READ(reg0)); - regVals->offsetVal =(uint8_t)( - EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__READ(reg1)); - regVals->offsetPosition =(CEDI_T2Offset)( - EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__READ(reg1)); - regVals->disableMask = (uint8_t)( - EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__READ(reg1)); - - return 0; -} - -#ifdef __cplusplus -} -#endif - -#endif /* CY_IP_MXETH */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd_tx.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd_tx.c deleted file mode 100644 index 07c7ef4998..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/edd_tx.c +++ /dev/null @@ -1,1182 +0,0 @@ -/****************************************************************************** - * copyright (C) 2014-2015 Cadence Design Systems - * All rights reserved. - ****************************************************************************** - * edd_tx.c - * Ethernet DMA MAC Driver - * - * Tx-related functions source file - *****************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXETH) - -#include "cdn_stdint.h" -#include "cdn_errno.h" -#include "log.h" -#include "cps_v2.h" -#include "emac_regs.h" -#include "cedi.h" -#include "edd_int.h" - -#ifdef __cplusplus -extern "C" { -#endif -/****************************************************************************** - * Private Driver functions - *****************************************************************************/ - -/* move descriptor pointer bd and virtual address pointer vp on to next in ring. - * stat should be the status (word 1) of current descriptor */ -static void inc_txbd(void *pD, uint32_t stat, txDesc **bd, uintptr_t **vp, - txQueue_t *txQ) { - if (stat & CEDI_TXD_WRAP) { - *bd = txQ->bdBase; - *vp = txQ->vAddrList; - } else { - *bd = (txDesc *) (((uintptr_t)(*bd))+(CEDI_PdVar(txDescriptorSize))); - ++(*vp); - } -} - -/* move descriptor and virtual address pointers back to previous in ring */ -static void dec_txbd(void *pD, txDesc **bd, uintptr_t **vp, txQueue_t *txQ) { - if (*bd==txQ->bdBase) { - *bd = (txDesc *)(((uintptr_t)(*bd))+ - (txQ->descMax-1)*(CEDI_PdVar(txDescriptorSize))); - *vp += (txQ->descMax-1); - } else { - *bd = (txDesc *)(((uintptr_t)(*bd))-(CEDI_PdVar(txDescriptorSize))); - --(*vp); - } -} - -/****************************************************************************** - * Driver API functions - *****************************************************************************/ - -/** - * Identify max Tx pkt size for queues. When using full store & forward packet - * buffering, this is based on the sram size for each queue, otherwise it is - * limited by an internal counter to 16kB. - * @param pD - driver private state info specific to this instance - * @param maxTxSize - pointer for returning array of sizes for queues - * @return 0 if successful - * @return EINVAL if any parameter =NULL - */ -uint32_t emacCalcMaxTxFrameSize(void *pD, CEDI_FrameSize *maxTxSize) { - uint32_t i, watermark; - uint16_t ram_word_size, ram_addr_bits, burst_len; - uint16_t ram_size, num_segments, size_per_segment, tx_overhead; - uint16_t num_segments_q[CEDI_MAX_TX_QUEUES]; - uint8_t enabled = 0; - uint32_t ret; - - if ((pD==NULL) || (maxTxSize==NULL)) return EINVAL; - - if (0!=(ret = emacGetTxPartialStFwd(pD, &watermark, &enabled))) - return ret; - - if (!(enabled) && CEDI_PdVar(hwCfg).tx_pkt_buffer) - { - // What is word size of SRAM in bytes - ram_word_size = (CEDI_PdVar(hwCfg).tx_pbuf_data >> 1)+1; - //vDbgMsg(DBG_GEN_MSG, 10, "RAM word size = %u (x32 bits)\n", CEDI_PdVar(hwCfg).tx_pbuf_data); - ram_addr_bits = CEDI_PdVar(hwCfg).tx_pbuf_addr; - //vDbgMsg(DBG_GEN_MSG, 10, "RAM Tx addr bits = %u\n", ram_addr_bits); - - ram_size = ram_addr_bits + ram_word_size + 1; - vDbgMsg(DBG_GEN_MSG, 10, "RAM size = %u\n", 1<FrameSize[i] = - (1 << (num_segments_q[i] + size_per_segment)) - tx_overhead; - /* add in some extra overhead */ - maxTxSize->FrameSize[i] = (maxTxSize->FrameSize[i]*9)/10; - } - else - maxTxSize->FrameSize[i] = 0; - } - } - else - for (i=0; iFrameSize[i] = CEDI_TXD_LMASK; - else - maxTxSize->FrameSize[i] = 0; - - vDbgMsg(DBG_GEN_MSG, 10, - "max_frm_size_Q0 = %u, Q1 = %u, Q2 = %u, Q3 = %u,\n", - maxTxSize->FrameSize[0], maxTxSize->FrameSize[1], - maxTxSize->FrameSize[2], maxTxSize->FrameSize[3]); - vDbgMsg(DBG_GEN_MSG, 10, - "max_frm_size_Q4 = %u, Q5 = %u, Q6 = %u, Q7 = %u,\n", - maxTxSize->FrameSize[4], maxTxSize->FrameSize[5], - maxTxSize->FrameSize[6], maxTxSize->FrameSize[7]); - return 0; -} - - -/* Add a buffer containing Tx data to the end of the transmit queue. - * Use repeated calls for multi-buffer frames, setting lastBuffer on the - * last call, to indicate the end of the frame. - * @param pD - driver private state info specific to this instance - * @param queueNum - number of Tx queue - * @param bufAdd - pointer to struct for virtual and physical addresses of - * start of data buffer - * @param length - length of data in buffer - * @param flags - bit-flags specifying last buffer/auto CRC/auto-start - * @return 0 if successful - * @return EINVAL if invalid queueNum, length or buffer alignment, NULL - * pointers or buffer addresses - * @return ENOENT if no available descriptors - */ -uint32_t emacQueueTxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *bufAdd, - uint32_t length, uint8_t flags) -{ - txQueue_t *txQ; - txDesc *freeDesc; - txDesc *bd1stBuf; - uint32_t stat, ncr; - uint16_t nFree; - - if ((pD==NULL) || (queueNum>=CEDI_PdVar(cfg).txQs) || (bufAdd==NULL) - || (bufAdd->pAddr==0)) - return EINVAL; - -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered\n", __func__); - - txQ = &CEDI_PdVar(txQueue)[queueNum]; - freeDesc = txQ->bdHead; - bd1stBuf = txQ->bd1stBuf; - - if (!length || (length > CEDI_TXD_LMASK)) { - vDbgMsg(DBG_GEN_MSG, 5, "Error: bad length specified: %u\n", length); - return EINVAL; - } - - if (emacTxDescFree(pD, queueNum, &nFree)) return EINVAL; - if (!nFree) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: insufficient buffer descriptors"); - return ENOENT; - } - - /* preserve wrap bit if present in status word */ - stat = CPS_UncachedRead32(&freeDesc->word[1]) & CEDI_TXD_WRAP; - stat |= ((flags & CEDI_TXB_LAST_BUFF)?CEDI_TXD_LAST_BUF:0) - | ((flags & CEDI_TXB_NO_AUTO_CRC)?CEDI_TXD_NO_AUTO_CRC:0) | length; - - /* Handle a multi-buffer frame */ - if (!(flags & CEDI_TXB_LAST_BUFF) && (NULL == bd1stBuf)) { - /* This is the 1st buf of several; prevent it from going and remember its BD. */ - stat |= (uint32_t)CEDI_TXD_USED; - txQ->bd1stBuf = freeDesc; - } - - *txQ->vHead = bufAdd->vAddr; - CPS_UncachedWrite32(&freeDesc->word[0], bufAdd->pAddr & 0xFFFFFFFF); - /* upper 32 bits if 64 bit addressing */ - if (CEDI_PdVar(cfg).dmaAddrBusWidth) { -#ifdef CEDI_64B_COMPILE - /* 64-bit addressing */ - CPS_UncachedWrite32(&freeDesc->word[2], - (bufAdd->pAddr & 0xFFFFFFFF00000000)>>32); -#else - /* 32-bit addressing */ -#endif - } - CPS_UncachedWrite32(&freeDesc->word[1], stat); - - if ((flags & CEDI_TXB_LAST_BUFF) && (NULL != bd1stBuf)) { - /* Last buffer of a multibuffer frame is in place, 1st buffer can go. */ - CPS_UncachedWrite32(&bd1stBuf->word[1], - CPS_UncachedRead32(&bd1stBuf->word[1]) & ~CEDI_TXD_USED); - txQ->bd1stBuf = NULL; - } - - --txQ->descFree; - if (emacTxDescFree(pD, queueNum, &nFree)) return EINVAL; - vDbgMsg(DBG_GEN_MSG, 15, "len=%u, queue=%u, txbdHead=%p, buffV=%p, buffP=%p, descFree=%u\n", - length, queueNum, freeDesc, (void *)bufAdd->vAddr, (void *)bufAdd->pAddr, nFree); - inc_txbd(pD, stat, &freeDesc, &txQ->vHead, txQ); - txQ->bdHead = freeDesc; - - /* set going if complete frame queued */ - if ((flags & CEDI_TXB_LAST_BUFF) && !(flags & CEDI_TXB_NO_AUTO_START)) { - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SET(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); - } - - return 0; -} - -/* Add a buffer containing Tx data to the end of the transmit queue. - * Use repeated calls for multi-buffer frames, setting lastBuffer on the - * last call, to indicate the end of the frame. - * @param pD - driver private state info specific to this instance - * @param prm - pointer to struct of parameters - * @return 0 if successful - * @return EINVAL if invalid queueNum, length or buffer alignment, NULL - * pointers or buffer addresses, or prm->flags specifies - * CEDI_TXB_LAST_BUFF as well as CEDI_TXB_TCP_ENCAP or CEDI_TXB_UDP_ENCAP - * @return ENOENT if no available descriptors - */ -uint32_t emacQTxBuf(void *pD, CEDI_qTxBufParams *prm) -{ - txQueue_t *txQ; - txDesc *freeDesc; - txDesc *bd1stBuf; - uint32_t stat, ncr; - uint16_t nFree; - - if ((pD==NULL) || (prm->queueNum>=CEDI_PdVar(cfg).txQs) - || (prm->bufAdd==NULL) - || (prm->bufAdd->pAddr==0)) - return EINVAL; - -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered\n", __func__); - - txQ = &CEDI_PdVar(txQueue)[prm->queueNum]; - freeDesc = txQ->bdHead; - bd1stBuf = txQ->bd1stBuf; - - if (!prm->length || (prm->length > CEDI_TXD_LMASK)) { - vDbgMsg(DBG_GEN_MSG, 5, "Error: bad length specified: %u\n", - prm->length); - return EINVAL; - } - - if (emacTxDescFree(pD, prm->queueNum, &nFree)) return EINVAL; - if (!nFree) { - vDbgMsg(DBG_GEN_MSG, 5, "%s\n", "Error: insufficient buffer descriptors"); - return ENOENT; - } - - if (NULL!=bd1stBuf) { /* inc counter after 1st in frame */ - txQ->descNum++; - } - - /* preserve wrap bit if present in status word */ - stat = CPS_UncachedRead32(&freeDesc->word[1]) & CEDI_TXD_WRAP; - stat |= ((prm->flags & CEDI_TXB_LAST_BUFF)?CEDI_TXD_LAST_BUF:0) - | ((prm->flags & CEDI_TXB_NO_AUTO_CRC)?CEDI_TXD_NO_AUTO_CRC:0) - | prm->length - | ((txQ->descNum>=1)? - ((prm->mssMfs << CEDI_TXD_MSSMFS_SHIFT) & CEDI_TXD_MSSMFS_MASK):0); - // only set MSS/MFS on second or later descriptor -// vDbgMsg(DBG_GEN_MSG, 10, "descNum = %u, desc wd1 = 0x%08X, mss = %u\n", -// txQ->descNum, stat, (stat>>16) & 0x3FFF); - - /* Handle a multi-buffer frame */ - if (!(prm->flags & CEDI_TXB_LAST_BUFF) && (NULL==bd1stBuf)) { - /* This is the 1st buf of several; prevent it from going and remember its BD. */ - stat |= CEDI_TXD_USED - /* Also use this condition to set encapsulation flags & TCP stream - - * must not set stream if TSO bit clear */ - | ((prm->flags & CEDI_TXB_TCP_ENCAP)? - /* TSO settings */ - (CEDI_TXD_TSO_ENABLE| - (((prm->tcpStream)<flags & CEDI_TXB_TSO_AUTO_SEQ)?CEDI_TXD_AUTOSEQ_SEL:0)) : - /* UFO bit only */ - ((prm->flags & CEDI_TXB_UDP_ENCAP)?CEDI_TXD_UFO_ENABLE:0)); - txQ->bd1stBuf = freeDesc; - } - - *txQ->vHead = prm->bufAdd->vAddr; - CPS_UncachedWrite32(&freeDesc->word[0], prm->bufAdd->pAddr & 0xFFFFFFFF); - - /* upper 32 bits if 64 bit addressing */ - if (CEDI_PdVar(cfg).dmaAddrBusWidth) { -#ifdef CEDI_64B_COMPILE - /* 64-bit addressing */ - CPS_UncachedWrite32(&freeDesc->word[2], - (prm->bufAdd->pAddr & 0xFFFFFFFF00000000)>>32); -#else -#endif - } - CPS_UncachedWrite32(&freeDesc->word[1], stat); - - - if ((prm->flags & CEDI_TXB_LAST_BUFF) && (NULL!=bd1stBuf)) { - /* Last buffer of a multibuffer frame is in place, 1st buffer can go. */ - CPS_UncachedWrite32(&bd1stBuf->word[1], - CPS_UncachedRead32(&bd1stBuf->word[1]) & ~CEDI_TXD_USED); - /* vDbgMsg(DBG_GEN_MSG, 10, - "set multi-buffer go: 1stBuf=%p, wd1=%08X, transmit queue ptr=%08X\n", - bd1stBuf, CPS_UncachedRead32(&bd1stBuf->word[1]), - CPS_UncachedRead32(CEDI_RegAddr(transmit_q_ptr)));*/ - txQ->bd1stBuf = NULL; - txQ->descNum = 0; - } - - --txQ->descFree; - /* if (emacTxDescFree(pD, prm->queueNum, &nFree)) return EINVAL; - vDbgMsg(DBG_GEN_MSG, 10, - "len=%u, queue=%u, txbdHead=%p, buffV=%p, buffP=%p, wd1=%08X, descFree=%u\n", - prm->length, prm->queueNum, freeDesc, - (void *)prm->bufAdd->vAddr, - (void *)prm->bufAdd->pAddr, - CPS_UncachedRead32(&freeDesc->word[1]), nFree);*/ - inc_txbd(pD, stat, &freeDesc, &txQ->vHead, txQ); - txQ->bdHead = freeDesc; - - /* set going if complete frame queued */ - if ((prm->flags & CEDI_TXB_LAST_BUFF) && !(prm->flags & CEDI_TXB_NO_AUTO_START)) { - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SET(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); - } - - return 0; -} - -/* Remove buffer from head of transmit queue in case of error during queueing - * and free the corresponding descriptor. - * Caller must have knowledge of queueing status, i.e. that frame has not been - * completed for transmission (first used bit still set) and how many - * descriptors have been queued for untransmitted frame. - * @param pD - driver private state info specific to this instance - * @param prm - pointer to struct of parameters to return - * @return 0 if successful - * @return EINVAL if invalid queueNum or NULL parameters - * @return ENOENT if no unfree descriptors in queue - */ -uint32_t emacDeQTxBuf(void *pD, CEDI_qTxBufParams *prm) -{ - txQueue_t *txQ; - txDesc *descToFree; - uint32_t stat; - - if ((pD==NULL) || (prm==NULL) || (prm->bufAdd==NULL) || - (prm->queueNum>=CEDI_PdVar(cfg).txQs)) - return EINVAL; - -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered\n", __func__); - - txQ = &CEDI_PdVar(txQueue)[prm->queueNum]; - descToFree = txQ->bdHead; - - /* Check if any in queue */ - if (txQ->bdTail==txQ->bdHead) - return ENOENT; - - /* unwind head pointers */ - dec_txbd(pD, &descToFree, &txQ->vHead, txQ); - txQ->bdHead = descToFree; - - /* get virtual address */ - prm->bufAdd->vAddr = *txQ->vHead; - - /* get phys address */ - prm->bufAdd->pAddr = CPS_UncachedRead32(&descToFree->word[0]); -#ifdef CEDI_64B_COMPILE - /* upper 32 bits if 64 bit addressing */ - if (CEDI_PdVar(cfg).dmaAddrBusWidth) { - prm->bufAdd->pAddr |= (CPS_UncachedRead32(&descToFree->word[2])<<32); - } -#endif - - /* get length */ - stat = CPS_UncachedRead32(&descToFree->word[1]); - prm->length = stat & CEDI_TXD_LEN_MASK; - /* set used bit */ - CPS_UncachedWrite32(&descToFree->word[1], stat | (uint32_t)CEDI_TXD_USED); - - if (txQ->descNum>0) - txQ->descNum--; - - ++txQ->descFree; - - return 0; -} - -/* Get number of free descriptors in specified Tx queue - * @param pD - driver private state info specific to this instance - * @param queueNum - number of Tx queue - * @param numFree - pointer for returning number of free descriptors - * @return 0 if successful - * @return EINVAL if invalid parameter - */ -uint32_t emacTxDescFree(void *pD, uint8_t queueNum, uint16_t *numFree) -{ - if ((pD==NULL) || (numFree==NULL) || (queueNum>=CEDI_PdVar(cfg).txQs)) - return EINVAL; - *numFree = CEDI_PdVar(txQueue)[queueNum].descFree; - return 0; -} - -/* - * Read Tx descriptor queue and free used descriptor. - * - * @param[in] pD driver private state info specific to this instance - * @param[in] queueNum number of Tx queue - * $RANGE $FROM 0 $TO CEDI_Config.txQs-1$ - * @param[out] descData pointer for returning status & descriptor data - * Struct fields: - * - * CEDI_BuffAddr bufAdd - addresses of buffer freed up - * - * uint32_t txDescStat - descriptor status word. Only valid if first - * buffer of frame. - * - * uint8_t status - descriptor queue status, one of the following values: - * CEDI_TXDATA_1ST_NOT_LAST :a first descriptor was freed, - * frame not finished: - * bufAdd & txDescStat are valid - * CEDI_TXDATA_1ST_AND_LAST :a first descriptor was freed, - * frame is finished: - * bufAdd & txDescStat are valid - * CEDI_TXDATA_MID_BUFFER :a descriptor was freed, - * (not first in frame), - * frame not finished: bufAdd valid, - * txDescStat not valid - * CEDI_TXDATA_LAST_BUFFER :a descriptor was freed, frame is finished: - * bufAdd valid, txDescStat not valid - * CEDI_TXDATA_NONE_FREED :no used descriptor to free: - * bufAdd & txDescStat not valid - * - * CEDI_TimeStampData txTsData - Tx descriptor timestamp when valid - * (txTsData->tsValid will be set to 1). - * @return 0 if successful (and status is set), - * @return ENOENT if the queue is empty (status = CEDI_TXDATA_NONE_FREED), or - * @return EIO if an incomplete frame was detected (no lastBuffer flag in - * queue) - * @return EINVAL if any parameter invalid - */ -uint32_t emacFreeTxDesc(void *pD, uint8_t queueNum, CEDI_TxDescData *descData) -{ - txQueue_t *txQ; -// uint16_t nFree = 0; -// txDesc *freedDesc; - uint8_t wdNum; - uint32_t tsLowerWd, tsUpperWd; -// uintptr_t *nextV; -// txDesc *nextD; -// uint32_t wd1_1, wd1_2, wd1_3, wd1_4, wd1_5; - - if ((pD==NULL) || (descData==NULL)) - return EINVAL; - if (queueNum>=CEDI_PdVar(cfg).txQs) - return EINVAL; - -// vDbgMsg(DBG_GEN_MSG, 10, "%s entered\n", __func__); - txQ = &CEDI_PdVar(txQueue)[queueNum]; - - /* Check if any to free */ - if (txQ->bdTail == txQ->bdHead) - { - descData->status = CEDI_TXDATA_NONE_FREED; - return ENOENT; - } - - /* Free next used descriptor in this frame */ - descData->txDescStat = CPS_UncachedRead32(&(txQ->bdTail->word[1])); - if (txQ->firstToFree) - { - /* look ahead to next desc */ - /* nextD = txQ->bdTail; - nextV = txQ->vTail; - inc_txbd(pD, descData->txDescStat, &nextD, &nextV, txQ); - wd1_1 = CPS_UncachedRead32(&(nextD->word[1])); - inc_txbd(pD, descData->txDescStat, &nextD, &nextV, txQ); - wd1_2 = CPS_UncachedRead32(&(nextD->word[1])); - inc_txbd(pD, descData->txDescStat, &nextD, &nextV, txQ); - wd1_3 = CPS_UncachedRead32(&(nextD->word[1])); - inc_txbd(pD, descData->txDescStat, &nextD, &nextV, txQ); - wd1_4 = CPS_UncachedRead32(&(nextD->word[1])); - inc_txbd(pD, descData->txDescStat, &nextD, &nextV, txQ); - wd1_5 = CPS_UncachedRead32(&(nextD->word[1])); - vDbgMsg(DBG_GEN_MSG, 10, - " testing desc: queue=%u, txBdTail=%p, wd1(0)=%08X,"\ - " wd1(1)=%08X, wd1(2)=%08X, wd1(3)=%08X, wd1(4)=%08X, wd1(5)=%08X\n", - queueNum, txQ->bdTail, descData->txDescStat, wd1_1, wd1_2, - wd1_3, wd1_4, wd1_5);*/ - - /* Only test used bit state for first buffer in frame. */ - if(!(descData->txDescStat & (uint32_t)CEDI_TXD_USED)) { - descData->status = CEDI_TXDATA_NONE_FREED; - return 0; - } - - /* extract timestamp if available */ - if ((CEDI_PdVar(cfg).enTxExtBD) && - (descData->txDescStat & CEDI_TXD_TS_VALID)) - { - uint32_t reg; - descData->txTsData.tsValid = 1; - // position depends on 32/64 bit addr - wdNum = (CEDI_PdVar(cfg).dmaAddrBusWidth)?4:2; - tsLowerWd = CPS_UncachedRead32(&(txQ->bdTail->word[wdNum])); - tsUpperWd = CPS_UncachedRead32(&(txQ->bdTail->word[wdNum+1])); - - descData->txTsData.tsNanoSec = tsLowerWd & CEDI_TS_NANO_SEC_MASK; - descData->txTsData.tsSecs = ((tsUpperWd & CEDI_TS_SEC1_MASK) - <> CEDI_TS_SEC0_SHIFT); - - /* The timestamp only contains lower few bits of seconds, so add value from 1588 timer */ - reg = CPS_UncachedRead32(CEDI_RegAddr(tsu_timer_sec)); - /* If the top bit is set in the timestamp, but not in 1588 timer, it has rolled over, so subtract max size */ - if ((descData->txTsData.tsSecs & (CEDI_TS_SEC_TOP>>1)) && !(reg & (CEDI_TS_SEC_TOP>>1))) { - descData->txTsData.tsSecs -= CEDI_TS_SEC_TOP; - } - descData->txTsData.tsSecs += ((~CEDI_TS_SEC_MASK) & EMAC_REGS__TSU_TIMER_SEC__TIMER__READ(reg)); - } - else{ - descData->txTsData.tsValid = 0; - - } - - if (descData->txDescStat & CEDI_TXD_LAST_BUF) - descData->status = CEDI_TXDATA_1ST_AND_LAST; - else { - txQ->firstToFree = 0; - descData->status = CEDI_TXDATA_1ST_NOT_LAST; - } - } - else - { - /* set later used bits in frame, for consistency */ - CPS_UncachedWrite32(&(txQ->bdTail->word[1]), - descData->txDescStat | (uint32_t)CEDI_TXD_USED); - if (descData->txDescStat & CEDI_TXD_LAST_BUF) { - descData->status = CEDI_TXDATA_LAST_BUFFER; - txQ->firstToFree = 1; - } - else - descData->status = CEDI_TXDATA_MID_BUFFER; - } - - descData->bufAdd.pAddr = CPS_UncachedRead32(&(txQ->bdTail->word[0])); - -#ifdef CEDI_64B_COMPILE - /* upper 32 bits if 64 bit addressing */ - if ((CEDI_PdVar(cfg).dmaAddrBusWidth) && - (sizeof(descData->bufAdd.pAddr)==sizeof(uint64_t))) - descData->bufAdd.pAddr |= - ((uint64_t)CPS_UncachedRead32(&(txQ->bdTail->word[2])))<<32; - -#endif - - descData->bufAdd.vAddr = *txQ->vTail; -// freedDesc = txQ->bdTail; - - /* move queue pointers on */ - inc_txbd(pD, descData->txDescStat, &txQ->bdTail, &txQ->vTail, txQ); - ++txQ->descFree; - /*if (0==emacTxDescFree(pD, queueNum, &nFree)) - vDbgMsg(DBG_GEN_MSG, 15, - " free desc: queue=%u, txBdTail=%p, buffV=%p, buffP=%p, length=%u, descFree=%u\n", - queueNum, freedDesc, (void *)descData->bufAdd.vAddr, - (void *)descData->bufAdd.pAddr, descData->txDescStat & CEDI_TXD_LMASK, nFree);*/ - - /* paranoid - empty and no last buffer flag (on last freed)? */ - if ((0==(descData->txDescStat & CEDI_TXD_LAST_BUF)) && - (txQ->descFree==txQ->descMax-CEDI_MIN_TXBD)) { - vDbgMsg(DBG_GEN_MSG, 5, - "Error: txQueue %u: LAST bit of frame not found!\n", queueNum); - txQ->firstToFree = 1; - return EIO; - } - - return 0; -} - -/* Decode the Tx descriptor status into a bit-field struct - * @param pD - driver private state info specific to this instance - * @param txDStatWord - Tx descriptor status word - * @param txDStat - pointer to bit-field struct for decoded status fields - */ -void emacGetTxDescStat(void *pD, uint32_t txDStatWord, CEDI_TxDescStat *txDStat) -{ - uint32_t wd1; - - if ((NULL==pD) || (NULL==txDStat)) - return; - - wd1 = txDStatWord; - txDStat->chkOffErr = (wd1 & CEDI_TXD_CHKOFF_MASK) >> CEDI_TXD_CHKOFF_SHIFT; - txDStat->lateColl = (wd1 & CEDI_TXD_LATE_COLL)?1:0; - txDStat->frameCorr = (wd1 & CEDI_TXD_FR_CORR)?1:0; - txDStat->txUnderrun = (wd1 & CEDI_TXD_UNDERRUN)?1:0; - txDStat->retryExc = (wd1 & CEDI_TXD_RETRY_EXC)?1:0; -} - -/* Provide the size of descriptor calculated for the current configuration. - * @param pD - driver private state info specific to this instance - * @param txDescSize - pointer to Tx descriptor Size - */ -void emacGetTxDescSize(void *pD, uint32_t *txDescSize) -{ - if ((pD==NULL)||(txDescSize==NULL)) return; - *txDescSize = CEDI_PdVar(txDescriptorSize); -} - -/* Reset transmit buffer queue. Any untransmitted buffer data will be - * discarded and must be re-queued. Transmission must be disabled - * before calling this function. - * @param pD - driver private state info specific to this instance - * @param queueNum - number of Tx queue - * @return 0 if successful - * @return EINVAL if invalid parameter - */ -uint32_t emacResetTxQ(void *pD, uint8_t queueNum) -{ -#define CEDI_WR_TXQ_PTR_REG_N_CASE(Q) case Q:\ - regTmp = CPS_UncachedRead32(CEDI_RegAddr(transmit_q##Q##_ptr));\ - EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MODIFY(regTmp, pAddr>>2);\ - CPS_UncachedWrite32(CEDI_RegAddr(transmit_q##Q##_ptr), regTmp);\ - break; - - uint32_t result = 0, regTmp; - txQueue_t *txQ; - txDesc *descStartPerQ; - uint32_t pAddr; - uintptr_t vAddr; - uint16_t q, i; - - if ((pD==NULL) || (queueNum>=CEDI_PdVar(cfg).txQs)) - return EINVAL; - - txQ = &CEDI_PdVar(txQueue)[queueNum]; - txQ->descFree = CEDI_PdVar(cfg).txQLen[queueNum]; - txQ->descMax = txQ->descFree + CEDI_MIN_TXBD; - vAddr = CEDI_PdVar(cfg).txQAddr; - pAddr = CEDI_PdVar(cfg).txQPhyAddr; - q = 0; - /* find start addresses for this txQ */ - if (queueNum>0) - txQ->vAddrList = CEDI_PdVar(txQueue)[0].vAddrList; - while (qdescMax * (CEDI_PdVar(txDescriptorSize)); //sizeof(txDesc); - pAddr += txQ->descMax * (CEDI_PdVar(txDescriptorSize)); //sizeof(txDesc); - txQ->vAddrList += txQ->descMax; - q++; - } - vDbgMsg(DBG_GEN_MSG, 10, "%s: base address Q%u virt=%08lX phys=%08X vAddrList=%p\n", - __func__, queueNum, vAddr, pAddr, txQ->vAddrList); - txQ->bdBase = (txDesc *)vAddr; - - txQ->bdTail = txQ->bdBase; - txQ->bdHead = txQ->bdBase; - txQ->bd1stBuf = NULL; - txQ->vHead = txQ->vAddrList; - txQ->vTail = txQ->vAddrList; - txQ->firstToFree = 1; - txQ->descNum = 0; - - /* set used flags & last wrap flag */ - descStartPerQ = txQ->bdBase; - for (i = 0; idescMax; i++) { - CPS_UncachedWrite32((uint32_t *)&(descStartPerQ->word[0]), 0); - CPS_UncachedWrite32((uint32_t *)&(descStartPerQ->word[1]), - CEDI_TXD_USED | (i==(txQ->descMax-1)?CEDI_TXD_WRAP:0)); - - descStartPerQ = (txDesc*) (((uintptr_t)(descStartPerQ)) + - (CEDI_PdVar(txDescriptorSize))); - } - - switch (q) { - case 0: - regTmp = CPS_UncachedRead32(CEDI_RegAddr(transmit_q_ptr));\ - EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MODIFY(regTmp, pAddr>>2); - CPS_UncachedWrite32(CEDI_RegAddr(transmit_q_ptr), regTmp); - break; - CEDI_WR_TXQ_PTR_REG_N_CASE(1); - CEDI_WR_TXQ_PTR_REG_N_CASE(2); - CEDI_WR_TXQ_PTR_REG_N_CASE(3); - CEDI_WR_TXQ_PTR_REG_N_CASE(4); - CEDI_WR_TXQ_PTR_REG_N_CASE(5); - CEDI_WR_TXQ_PTR_REG_N_CASE(6); - CEDI_WR_TXQ_PTR_REG_N_CASE(7); - CEDI_WR_TXQ_PTR_REG_N_CASE(8); - CEDI_WR_TXQ_PTR_REG_N_CASE(9); - CEDI_WR_TXQ_PTR_REG_N_CASE(10); - CEDI_WR_TXQ_PTR_REG_N_CASE(11); - CEDI_WR_TXQ_PTR_REG_N_CASE(12); - CEDI_WR_TXQ_PTR_REG_N_CASE(13); - CEDI_WR_TXQ_PTR_REG_N_CASE(14); - CEDI_WR_TXQ_PTR_REG_N_CASE(15); - } - - return result; -} - -/* Enable & start the transmit circuit. Not required during normal - * operation, as queueTxBuf will automatically start Tx when complete frame - * has been queued, but may be used to restart after a Tx error. - * @param pD - driver private state info specific to this instance - * @return 0 if successful - * @return ECANCELED if no entries in buffer - * @return EINVAL if invalid parameter - */ -uint32_t emacStartTx(void *pD) -{ - const CEDI_Config *cfg; - uint32_t qNum; - uint8_t ok = 0; - txQueue_t *txQ; - uint32_t ncr; - - if (pD==NULL) return EINVAL; - - vDbgMsg(DBG_GEN_MSG, 10, "%s entered\n", __func__); - - cfg = &((CEDI_PrivateData *)pD)->cfg; - - if (!emacGetTxEnabled(pD)) - emacEnableTx(pD); - - /* if anything to transmit, start transmission */ - for (qNum = 0; qNum < cfg->txQs; ++qNum) { - txQ = &CEDI_PdVar(txQueue)[qNum]; - if (txQ->bdHead != txQ->bdTail) { - ok = 1; - break; - } - } - if (!ok) - return ECANCELED; - else - { - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SET(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); - } - return 0; -} - -/* Halt transmission as soon as current frame Tx has finished - * @param pD - driver private state info specific to this instance - */ -void emacStopTx(void *pD) -{ - uint32_t ncr; - - if (!pD) return; - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__SET(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); - return; -} - -/* Immediately disable transmission without waiting for completion. - * Since the EMAC will reset to point to the start of transmit descriptor - * list, the buffer queues may have to be reset after this call. - * @param pD - driver private state info specific to this instance - */ -void emacAbortTx(void *pD) -{ - uint32_t ncr; - - if (!pD) return; - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__CLR(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); - return; -} - -/* Get state of transmitter - * @param pD - driver private state info specific to this instance - * @return 1 if active - * @return 0 if idle or pD==NULL - */ -uint32_t emacTransmitting(void *pD) -{ - if (pD==NULL) return 0; - - return EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__READ( - CPS_UncachedRead32(CEDI_RegAddr(transmit_status))); -} - -/** - * Enable the transmit circuit. This will be done automatically - * when call startTx, but it may be desirable to call this earlier, - * since some functionality depends on transmit being enabled. - * @param[in] pD driver private state info specific to this instance - */ -void emacEnableTx(void *pD) -{ - uint32_t ncr; - if (pD==NULL) return; - - /* Enable the transmitter */ - ncr = CPS_UncachedRead32(CEDI_RegAddr(network_control)); - EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SET(ncr); - CPS_UncachedWrite32(CEDI_RegAddr(network_control), ncr); -} - -/** - * Get state of transmision enabled - * @param pD - driver private state info specific to this instance - * @return 1 if transmission enabled - * @return 0 if transmission disabled or pD==NULL - */ -uint32_t emacGetTxEnabled(void *pD) -{ - if (pD==NULL) return 0; - - return EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__READ( - CPS_UncachedRead32(CEDI_RegAddr(network_control))); -} - -/* Get the content of EMAC transmit status register - * @param pD - driver private state info specific to this instance - * @param status - pointer to struct with fields for each flag - * @return raw status register value, !=0 if any flags set - */ -uint32_t emacGetTxStatus(void *pD, CEDI_TxStatus *status) -{ - uint32_t reg; - if ((pD==NULL)||(status==NULL)) - return 0; - - reg = CPS_UncachedRead32(CEDI_RegAddr(transmit_status)); -// vDbgMsg(DBG_GEN_MSG, 10, "-----getTxStatus reads 0x%08X ------\n", reg); - - status->txComplete = - EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__READ(reg); - status->usedBitRead = - EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__READ(reg); - status->collisionOcc = - EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__READ(reg); - status->retryLimExc = - EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__READ(reg); - status->lateCollision = - EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__READ(reg); - status->txActive = - EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__READ(reg); - status->txFrameErr = - EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__READ(reg); - status->txUnderRun = - EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__READ(reg); - status->hRespNotOk = - EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__READ(reg); - - return reg; -} - -/* Reset the bits of EMAC transmit status register as selected in resetStatus - * @param pD - driver private state info specific to this instance - * @param resetStatus - OR'd combination of CEDI_TXS_ bit-fields - */ -void emacClearTxStatus(void *pD, uint32_t resetStatus) -{ - uint32_t dst = 0; - - if (!pD) return; - if (resetStatus & CEDI_TXS_USED_READ) - EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MODIFY(dst, 1); - if (resetStatus & CEDI_TXS_COLLISION) - EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MODIFY(dst, 1); - if (resetStatus & CEDI_TXS_RETRY_EXC) - EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MODIFY(dst, 1); - if (resetStatus & CEDI_TXS_LATE_COLL) - EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MODIFY(dst, 1); - /* txActive not resettable */ - if (resetStatus & CEDI_TXS_FRAME_ERR) - EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MODIFY(dst, 1); - if (resetStatus & CEDI_TXS_TX_COMPLETE) - EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, 1); - if (resetStatus & CEDI_TXS_UNDERRUN) - EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, 1); - if (resetStatus & CEDI_TXS_HRESP_ERR) - EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MODIFY(dst, 1); - if (dst) - CPS_UncachedWrite32(CEDI_RegAddr(transmit_status), dst); -} - -uint32_t emacSetTxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable) -{ - uint32_t reg; - if (!pD) return EINVAL; - if (CEDI_PdVar(hwCfg).tx_pkt_buffer==0) - return ENOTSUP; - if (enable>1) return EINVAL; - - if ((enable==1) && - ((watermark<0x14) || (watermark>=(1<1) || CEDI_PdVar(hwCfg).exclude_cbs) return; - reg = CPS_UncachedRead32(CEDI_RegAddr(cbs_control)); - if (qSel) /* i.e. queue B */ - EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MODIFY(reg, 0); - else - EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MODIFY(reg, 0); - CPS_UncachedWrite32(CEDI_RegAddr(cbs_control), reg); -} - -/** - * Read CBS setting for the specified queue. - * @param[in] pD driver private state info specific to this instance - * @param[in] qSel if equal 0 selects highest priority queue (queue A), - * if equal 1 selects next-highest priority queue (queue B) - * $RANGE $FROM 0 $TO 1$ - * @param[out] enable returns: 1 if CBS enabled for the specified queue, - * 0 if not enabled - * @param[out] idleSlope pointer for returning the idleSlope value - * for selected queue. - * @return 0 for success. - * @return EINVAL for invalid pointer. - * @return ENOTSUP if CBS has been excluded from h/w config - */ -uint32_t emacGetCbsQSetting(void *pD, uint8_t qSel, - uint8_t *enable, uint32_t *idleSlope) -{ - uint32_t reg, enabled; - - if ((pD==0)||(enable==0)||(idleSlope==0)) - return EINVAL; - if (CEDI_PdVar(hwCfg).exclude_cbs==1) - return ENOTSUP; - if (qSel>1) return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(cbs_control)); - if (qSel) { /* i.e. queue B */ - enabled = EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__READ(reg); - if (enabled && (idleSlope!=NULL)) { - reg = CPS_UncachedRead32(CEDI_RegAddr(cbs_idleslope_q_b)); - *idleSlope = EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__READ(reg); - } - } - else { - enabled = EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__READ(reg); - if (enabled && (idleSlope!=NULL)) { - reg = CPS_UncachedRead32(CEDI_RegAddr(cbs_idleslope_q_a)); - *idleSlope = EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__READ(reg); - } - } - - *enable=enabled; - return 0; -} - -/** - * Enable/disable the inter-packet gap (IPG) stretch function. - * @param[in] pD driver private state info specific to this instance - * @param[in] enable if equal 1 then enable IPG stretch, if 0 then disable. - * $RANGE $FROM 0 $TO 1$ - * @param[in] multiplier multiplying factor applied to previous Tx frame - * length. Ignored if enable equal 0. - * @param[in] divisor after multiplying previous frame length, divide by - * (divisor+1) - if result>96 bits, this is used for the Tx IPG. - * Ignored if enable equal 0. - * @return EINVAL if pD equal NULL - * @return 0 if successful. - */ -uint32_t emacSetIpgStretch(void *pD, uint8_t enable, uint8_t multiplier, - uint8_t divisor) -{ - uint32_t reg; - - if (pD==NULL) return EINVAL; - if (enable>1) return EINVAL; - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (enable) { - EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SET(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); - reg = CPS_UncachedRead32(CEDI_RegAddr(stretch_ratio)); - EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MODIFY(reg, - (divisor << 8) | multiplier); - CPS_UncachedWrite32(CEDI_RegAddr(stretch_ratio), reg); - } - else { - EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__CLR(reg); - CPS_UncachedWrite32(CEDI_RegAddr(network_config), reg); - } - return 0; -} - -/* Read the inter-packet gap (IPG) stretch settings. - * @param pD - driver private state info specific to this instance - * @param enabled - pointer for returning enabled state: returns 1 if - * IPG stretch enabled, 0 if disabled. - * @param multiplier - pointer for returning IPG multiplying factor. - * @param divisor - pointer for returning IPG divisor. - * @return =0 if successful, EINVAL if any parameter =NULL - */ -uint32_t emacGetIpgStretch(void *pD, uint8_t *enabled, uint8_t *multiplier, - uint8_t *divisor) -{ - uint32_t reg, stretch; - - if ((pD==NULL) || (enabled==NULL) || (multiplier==NULL) || (divisor==NULL)) - return EINVAL; - - reg = CPS_UncachedRead32(CEDI_RegAddr(network_config)); - if (EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__READ(reg)) { - *enabled = 1; - reg = CPS_UncachedRead32(CEDI_RegAddr(stretch_ratio)); - stretch = EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__READ(reg); - *multiplier = (stretch & 0xFF); - *divisor = (stretch >> 8) & 0xFF; - } - else { - *enabled = 0; - *multiplier = 0; - *divisor = 0; - } - return 0; -} - -#ifdef __cplusplus -} -#endif - -#endif /* CY_IP_MXETH */ - -/* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/ppu_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/ppu_v1.c deleted file mode 100644 index 28e790d074..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mtb-pdl-cat1/drivers/source/ppu_v1.c +++ /dev/null @@ -1,380 +0,0 @@ -/***************************************************************************//** -* \file ppu_v1.c -* \version 1.0 -* -* This file provides the source code for ARM PPU driver -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cy_device.h" - -#if defined (CY_IP_MXS28SRSS) - -#include -#include - -void ppu_v1_init(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - /* Set edge sensitivity to masked for all input edges */ - ppu->IESR = 0; - - /* Mask all interrupts */ - ppu->IMR = PPU_V1_IMR_MASK; - - /* Acknowledge any interrupt left pending */ - ppu->ISR = PPU_V1_ISR_MASK; -} - -/* - * PWPR and PWSR registers - */ -int ppu_v1_request_power_mode(struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode) -{ - uint32_t power_policy; - CY_ASSERT(ppu != NULL); - CY_ASSERT(ppu_mode < PPU_V1_MODE_COUNT); - - power_policy = ppu->PWPR & ~(PPU_V1_PWPR_POLICY | PPU_V1_PWPR_DYNAMIC_EN); - ppu->PWPR = power_policy | ppu_mode; - - return CY_RET_SUCCESS; -} - -int ppu_v1_set_power_mode(struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode) -{ - int status; - - status = ppu_v1_request_power_mode(ppu, ppu_mode); - if (status != CY_RET_SUCCESS) - return status; - - while ((ppu->PWSR & (PPU_V1_PWSR_PWR_STATUS | PPU_V1_PWSR_PWR_DYN_STATUS)) - != ppu_mode) - continue; - - return CY_RET_SUCCESS; -} - -int ppu_v1_request_operating_mode(struct ppu_v1_reg *ppu, - enum ppu_v1_opmode op_mode) -{ - uint32_t power_policy; - CY_ASSERT(ppu != NULL); - CY_ASSERT(op_mode < PPU_V1_OPMODE_COUNT); - - power_policy = ppu->PWPR & ~(PPU_V1_PWPR_OP_POLICY | PPU_V1_PWPR_OP_DYN_EN); - ppu->PWPR = power_policy | (op_mode << PPU_V1_PWPR_OP_POLICY_POS); - - return CY_RET_SUCCESS; -} - -void ppu_v1_opmode_dynamic_enable(struct ppu_v1_reg *ppu, - enum ppu_v1_opmode min_dyn_mode) -{ - uint32_t power_policy; - - CY_ASSERT(ppu != NULL); - CY_ASSERT(min_dyn_mode < PPU_V1_OPMODE_COUNT); - - power_policy = ppu->PWPR & ~PPU_V1_PWPR_OP_POLICY; - ppu->PWPR = power_policy | - PPU_V1_PWPR_OP_DYN_EN | - (min_dyn_mode << PPU_V1_PWPR_OP_POLICY_POS); - while ((ppu->PWSR & PPU_V1_PWSR_OP_DYN_STATUS) == 0) - continue; -} - -void ppu_v1_dynamic_enable(struct ppu_v1_reg *ppu, - enum ppu_v1_mode min_dyn_state) -{ - uint32_t power_policy; - - CY_ASSERT(ppu != NULL); - CY_ASSERT(min_dyn_state < PPU_V1_MODE_COUNT); - - power_policy = ppu->PWPR & ~PPU_V1_PWPR_POLICY; - ppu->PWPR = power_policy | PPU_V1_PWPR_DYNAMIC_EN | min_dyn_state; - while ((ppu->PWSR & PPU_V1_PWSR_PWR_DYN_STATUS) == 0) - continue; -} - -void ppu_v1_lock_off_enable(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - ppu->PWPR |= PPU_V1_PWPR_OFF_LOCK_EN; -} - -void ppu_v1_lock_off_disable(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - ppu->PWPR &= ~PPU_V1_PWPR_OFF_LOCK_EN; -} - -enum ppu_v1_mode ppu_v1_get_power_mode(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return (enum ppu_v1_mode)(ppu->PWSR & PPU_V1_PWSR_PWR_STATUS); -} - -enum ppu_v1_mode ppu_v1_get_programmed_power_mode(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return (enum ppu_v1_mode)(ppu->PWPR & PPU_V1_PWPR_POLICY); -} - -enum ppu_v1_opmode ppu_v1_get_operating_mode(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return (enum ppu_v1_opmode) - ((ppu->PWSR & PPU_V1_PWSR_OP_STATUS) >> PPU_V1_PWSR_OP_STATUS_POS); -} - -enum ppu_v1_opmode ppu_v1_get_programmed_operating_mode(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return (enum ppu_v1_opmode) - ((ppu->PWPR & PPU_V1_PWPR_OP_POLICY) >> PPU_V1_PWPR_OP_POLICY_POS); -} - -bool ppu_v1_is_dynamic_enabled(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return ((ppu->PWSR & PPU_V1_PWSR_PWR_DYN_STATUS) != 0); -} - -bool ppu_v1_is_locked(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return ((ppu->PWSR & PPU_V1_PWSR_OFF_LOCK_STATUS) != 0); -} - -/* - * DISR register - */ -bool ppu_v1_is_power_devactive_high(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode) -{ - CY_ASSERT(ppu != NULL); - - return (ppu->DISR & - (1 << (ppu_mode + PPU_V1_DISR_PWR_DEVACTIVE_STATUS_POS))) != 0; -} - -bool ppu_v1_is_op_devactive_high(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive) -{ - CY_ASSERT(ppu != NULL); - - return (ppu->DISR & - (1 << (op_devactive + PPU_V1_DISR_OP_DEVACTIVE_STATUS_POS))) != 0; -} - -/* - * UNLK register - */ -void ppu_v1_off_unlock(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - ppu->UNLK = PPU_V1_UNLK_OFF_UNLOCK; -} - -/* - * PWCR register - */ -void ppu_v1_disable_devactive(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - ppu->PWCR &= ~PPU_V1_PWCR_DEV_ACTIVE_EN; -} - -void ppu_v1_disable_handshake(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - ppu->PWCR &= ~PPU_V1_PWCR_DEV_REQ_EN; -} - -/* - * Interrupt registers: IMR, AIMR, ISR, AISR, IESR, OPSR - */ -void ppu_v1_interrupt_mask(struct ppu_v1_reg *ppu, unsigned int mask) -{ - CY_ASSERT(ppu != NULL); - - ppu->IMR |= mask & PPU_V1_IMR_MASK; -} - -void ppu_v1_additional_interrupt_mask(struct ppu_v1_reg *ppu, unsigned int mask) -{ - CY_ASSERT(ppu != NULL); - - ppu->AIMR |= mask & PPU_V1_AIMR_MASK; -} - -void ppu_v1_interrupt_unmask(struct ppu_v1_reg *ppu, unsigned int mask) -{ - CY_ASSERT(ppu != NULL); - - ppu->IMR &= ~(mask & PPU_V1_IMR_MASK); -} - -void ppu_v1_additional_interrupt_unmask(struct ppu_v1_reg *ppu, - unsigned int mask) -{ - CY_ASSERT(ppu != NULL); - - ppu->AIMR &= ~(mask & PPU_V1_AIMR_MASK); -} - -bool ppu_v1_is_additional_interrupt_pending(struct ppu_v1_reg *ppu, - unsigned int mask) -{ - return (ppu->AISR & (mask & PPU_V1_AISR_MASK)) != 0; -} - -void ppu_v1_ack_interrupt(struct ppu_v1_reg *ppu, unsigned int mask) -{ - CY_ASSERT(ppu != NULL); - - ppu->ISR &= mask & PPU_V1_IMR_MASK; -} - -void ppu_v1_ack_additional_interrupt(struct ppu_v1_reg *ppu, unsigned int mask) -{ - CY_ASSERT(ppu != NULL); - - ppu->AISR &= mask & PPU_V1_AIMR_MASK; -} - -void ppu_v1_set_input_edge_sensitivity(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode, enum ppu_v1_edge_sensitivity edge_sensitivity) -{ - CY_ASSERT(ppu != NULL); - CY_ASSERT(ppu_mode < PPU_V1_MODE_COUNT); - CY_ASSERT((edge_sensitivity & ~PPU_V1_EDGE_SENSITIVITY_MASK) == 0); - - /* Clear current settings */ - ppu->IESR &= ~(PPU_V1_EDGE_SENSITIVITY_MASK << - (ppu_mode * PPU_V1_BITS_PER_EDGE_SENSITIVITY)); - - /* Update settings */ - ppu->IESR |= edge_sensitivity << - (ppu_mode * PPU_V1_BITS_PER_EDGE_SENSITIVITY); -} - -enum ppu_v1_edge_sensitivity ppu_v1_get_input_edge_sensitivity( - struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode) -{ - CY_ASSERT(ppu != NULL); - CY_ASSERT(ppu_mode < PPU_V1_MODE_COUNT); - - return (enum ppu_v1_edge_sensitivity)( - (ppu->IESR >> (ppu_mode * PPU_V1_BITS_PER_EDGE_SENSITIVITY)) & - PPU_V1_EDGE_SENSITIVITY_MASK); -} - -void ppu_v1_ack_power_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode) -{ - ppu->ISR = 1 << (ppu_mode + PPU_V1_ISR_ACTIVE_EDGE_POS); -} - -bool ppu_v1_is_power_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_mode ppu_mode) -{ - return ppu->ISR & (1 << (ppu_mode + PPU_V1_ISR_ACTIVE_EDGE_POS)); -} - -void ppu_v1_set_op_active_edge_sensitivity(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive, - enum ppu_v1_edge_sensitivity edge_sensitivity) -{ - CY_ASSERT(ppu != NULL); - CY_ASSERT(op_devactive < PPU_V1_OP_DEVACTIVE_COUNT); - CY_ASSERT((edge_sensitivity & ~PPU_V1_EDGE_SENSITIVITY_MASK) == 0); - - /* Clear current settings */ - ppu->OPSR &= ~(PPU_V1_EDGE_SENSITIVITY_MASK << - (op_devactive * PPU_V1_BITS_PER_EDGE_SENSITIVITY)); - - /* Update settings */ - ppu->OPSR |= edge_sensitivity << - (op_devactive * PPU_V1_BITS_PER_EDGE_SENSITIVITY); -} - -enum ppu_v1_edge_sensitivity ppu_v1_get_op_active_edge_sensitivity( - struct ppu_v1_reg *ppu, enum ppu_v1_op_devactive op_devactive) -{ - CY_ASSERT(ppu != NULL); - CY_ASSERT(op_devactive < PPU_V1_OP_DEVACTIVE_COUNT); - - return (enum ppu_v1_edge_sensitivity)( - (ppu->OPSR >> (op_devactive * PPU_V1_BITS_PER_EDGE_SENSITIVITY)) & - PPU_V1_EDGE_SENSITIVITY_MASK); -} - -void ppu_v1_ack_op_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive) -{ - ppu->ISR = 1 << (op_devactive + PPU_V1_ISR_OP_ACTIVE_EDGE_POS); -} - -bool ppu_v1_is_op_active_edge_interrupt(struct ppu_v1_reg *ppu, - enum ppu_v1_op_devactive op_devactive) -{ - return ppu->ISR & (1 << (op_devactive + PPU_V1_ISR_OP_ACTIVE_EDGE_POS)); -} - -bool ppu_v1_is_dyn_policy_min_interrupt(struct ppu_v1_reg *ppu) -{ - return ppu->ISR & PPU_V1_ISR_DYN_POLICY_MIN_IRQ; -} - -/* - * IDR0 register - */ -unsigned int ppu_v1_get_num_opmode(struct ppu_v1_reg *ppu) -{ - return ((ppu->IDR0 & PPU_V1_IDR0_NUM_OPMODE) - >> PPU_V1_IDR0_NUM_OPMODE_POS) + 1; -} - -/* - * AIDR register - */ -unsigned int ppu_v1_get_arch_id(struct ppu_v1_reg *ppu) -{ - CY_ASSERT(ppu != NULL); - - return (ppu->AIDR & (PPU_V1_AIDR_ARCH_REV_MINOR | - PPU_V1_AIDR_ARCH_REV_MAJOR)); -} -#endif /* CY_IP_MXS28SRSS */